Display device

Abstract

A display device is disclosed. The display device includes a display panel, which includes a plurality of pixels. At least one of the pixels includes a light-emitting diode, a first transistor connected between a power line receiving a power supply voltage and an anode of the light-emitting diode, a second transistor connected between a data line and a first reference node, a first capacitor connected between the power line and the first reference node, a second capacitor connected between the first reference node and a second reference node, a third transistor connected between the first reference node and a reference voltage line receiving a reference voltage, a fourth transistor connected between an initialization voltage line receiving an initialization voltage and a drain of the first transistor, and a fifth transistor connected between the drain of the first transistor and the anode of the light-emitting diode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0065837, filed on June 1, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device that prevents degradation of its display quality. Background Art

[0004] Various display devices that can be used in electronic devices such as televisions, mobile phones, tablet computers, navigation units, and game units are being developed. In particular, since portable display devices use batteries, various studies are being conducted to reduce power consumption in portable display devices.

[0005] One of the researches on reducing power consumption is to reduce the operating frequency of the display device. For example, when the operating frequency is reduced in a specific operating environment such as still image display, the power consumption of the display device is reduced.

[0006] In recent years, there has been a demand for a technology that reduces power consumption of a display device while preventing degradation of display quality. Summary of the Invention

[0007] The present disclosure provides a display device capable of preventing display quality from being deteriorated at each frequency.

[0008] Embodiments of the present inventive concept provide a display device including a display panel, the display panel including a plurality of pixels. At least one of the pixels includes a light-emitting diode, a first transistor connected between a power line receiving a power supply voltage and an anode of the light-emitting diode, a second transistor connected between a data line and a first reference node, a first capacitor connected between the power line and the first reference node, a second capacitor connected between the first reference node and a second reference node, a third transistor connected between the first reference node and a reference voltage line receiving a reference voltage, a fourth transistor connected between an initialization voltage line receiving an initialization voltage and a drain of the first transistor, and a fifth transistor connected between the drain of the first transistor and the anode of the light-emitting diode. The first transistor includes a source connected to the power line and a gate connected to the second reference node.

[0009] The second transistor includes a gate for receiving a data write signal, a source connected to the data line, and a drain connected to a first reference node. The third transistor includes a gate for receiving a compensation scan signal, a source connected to a reference voltage line, and a drain connected to the first reference node. In a frame, a compensation period during which a compensation scan signal having an on-level is applied to the gate of the third transistor precedes a write period during which a data write signal having an on-level is applied to the gate of the second transistor.

[0010] The display device further includes a sixth transistor connected between the second reference node and the drain of the first transistor. The sixth transistor includes a gate receiving the compensation scan signal, a source connected to the second reference node, and a drain connected to the drain of the first transistor.

[0011] The display device further includes a seventh transistor connected between the second reference node and the initialization voltage line. The seventh transistor includes a gate receiving an initialization scan signal, a source connected to the initialization voltage line, and a drain connected to the second reference node.

[0012] The fourth transistor includes a gate receiving a black scan signal, a source connected to the source of the seventh transistor, and a drain connected to the drain of the first transistor.

[0013] The fifth transistor includes a gate for receiving a light emitting signal, a source connected to the drain of the fourth transistor, and a drain connected to the anode of the light emitting diode. In a frame, an initialization scan signal having a conductive level is applied to the gate of the seventh transistor during an initialization period before a compensation period and a write period. In a frame, a black scan signal having a conductive level is applied to the gate of the fourth transistor during a black period between the compensation period and the write period.

[0014] In one frame, the initialization period, the compensation period, the black period, and the writing period are in the non-light emitting period of the light emitting signal.

[0015] In one frame, the initialization period, compensation period and black period are in the non-light emitting period of the light emitting signal, the black period overlaps with the non-light emitting period and light emitting period of the light emitting signal, and the writing period overlaps with the light emitting period.

[0016] In one frame, the initialization period and the compensation period are in the non-light emitting period of the light emitting signal, the black period overlaps with the light emitting period of the light emitting signal, and the writing period overlaps with the light emitting period.

[0017] Embodiments of the present inventive concept provide a display device including a display panel having a drive circuit and a light-emitting diode connected to the drive circuit. The drive circuit includes a drive transistor, a first transistor, and a second transistor. The drive transistor has a gate for receiving a data signal from a data line, a source for receiving a power supply voltage, and a drain electrically connected to an anode of the light-emitting diode. The first transistor has a source connected to the drain of the drive transistor and a drain connected to the anode of the light-emitting diode. The second transistor has a source connected to an initialization voltage line, a drain connected to the drain of the drive transistor and the source of the first transistor, and a gate for receiving a black scan signal.

[0018] According to the above, the difference in brightness of the display device for each operating frequency can be reduced, thereby preventing degradation of the display quality of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other advantages of the present disclosure will become readily apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0021] Figure 2 is an equivalent circuit diagram showing a pixel according to an embodiment of the present disclosure;

[0022] Figure 3 is shown for driving Figure 2 : a waveform diagram of a driving signal of a pixel shown in ;

[0023] Figure 4 is shown for driving Figure 2 : a waveform diagram of a driving signal of a pixel shown in ;

[0024] Figure 5 is shown for driving Figure 2 : a waveform diagram of a driving signal of a pixel shown in ;

[0025] Figure 6 is shown for driving Figure 2 : a waveform diagram of a driving signal of a pixel shown in ;

[0026] Figure 7 is shown for driving Figure 2 : a waveform diagram of a driving signal of a pixel shown in ;

[0027] Figure 8A is an equivalent circuit diagram showing an initialization operation of the drain voltage of the driving transistor;

[0028] Figure 8Bis an equivalent circuit diagram showing an initialization operation of an anode voltage of a light emitting diode;

[0029] Figure 9 is an equivalent circuit diagram showing a pixel according to an embodiment of the present disclosure;

[0030] Figure 10 is shown for driving Figure 9 A waveform diagram of a driving signal for a pixel shown in FIG; and

[0031] Figure 11 is a waveform diagram showing the luminance of a pixel at each driving frequency according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In the present disclosure, it will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0033] The same reference numerals throughout the text indicate the same elements. In the drawings, the thickness, proportion and size of components are exaggerated for effective description of technical contents.

[0034] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It will be understood that although the terms first, second, etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Unless otherwise clearly indicated in the context, the singular forms "a", "an", and "the" as used herein are also intended to include plural forms.

[0036] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” etc., may be used herein for descriptive convenience to describe the relationship of one element or feature to another element or feature as shown in the figures.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It should also be understood that, unless expressly defined otherwise herein, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0038] It should also be understood that the terms “include” and / or “including” when used in this specification indicate the presence of stated features, integers, steps, operations, elements and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0039] Hereinafter, the present disclosure will be explained in detail with reference to the accompanying drawings.

[0040] Figure 1 is a block diagram illustrating a display device DD according to an embodiment of the present disclosure.

[0041] Reference Figure 1 The display device DD includes a timing controller TC, a scan drive circuit SDC, a data drive circuit DDC, and a display panel DP. In this embodiment, a self-luminous display panel will be described as the display panel DP. The self-luminous display panel can be an organic light-emitting display panel or a quantum dot light-emitting display panel.

[0042] The timing controller TC receives an input image signal and converts the input image signal into a data format suitable for the interface between the data driver circuit DDC and the timing controller TC to generate image data D-RGB. The timing controller TC outputs the image data D-RGB and various control signals DCS and SCS.

[0043] The scan drive circuit SDC receives scan control signals SCS from the timing controller TC. The scan control signals SCS include a vertical start signal that initiates the operation of the scan drive circuit SDC and a clock signal that determines the output timing of the signals. The scan drive circuit SDC generates a plurality of signals GW1 to GWn, GC1 to GCn, GB1 to GBn, and GI1 to GIn, and outputs the signals GW1 to GWn, GC1 to GCn, GB1 to GBn, and GI1 to GIn to corresponding signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, and GIL1 to GILn, respectively. Furthermore, the scan drive circuit SDC generates a plurality of emission signals EM1 to EMn in response to the scan control signals SCS, and outputs the emission signals EM1 to EMn to corresponding emission lines EML1 to EMLn.

[0044] exist Figure 1 In the embodiment of the present invention, the signals GW1 to GWn, GC1 to GCn, GB1 to GBn, and GI1 to GIn, as well as the emission signals EM1 to EMn, are output from a single scan driving circuit SDC. However, the present disclosure should not be limited thereto or thereby. According to another embodiment of the present disclosure, the display device DD may include a plurality of scan driving circuits SDC that respectively generate and output portions of the signals GW1 to GWn, GC1 to GCn, GB1 to GBn, and GI1 to GIn. Furthermore, according to another embodiment of the present disclosure, the driving circuits that generate and output the signals GW1 to GWn, GC1 to GCn, GB1 to GBn, and GI1 to GIn, and the driving circuit that generates and outputs the emission signals EM1 to EMn may be provided separately from each other.

[0045] The data drive circuit DDC receives a data control signal DCS and image data D-RGB from the timing controller TC. The data drive circuit DDC converts the image data D-RGB into data signals Vdata and outputs the data signals Vdata to data lines DL1 to DLm, described later. The data signals Vdata are analog voltages corresponding to the grayscale values ​​of the image data D-RGB and, therefore, may also be referred to as data voltages Vdata below.

[0046] The display panel DP includes write scan lines GWL1 to GWLn, compensation scan lines GCL1 to GCLn, black scan lines GBL1 to GBLn, initialization scan lines GIL1 to GILn, emission lines EML1 to EMLn, data lines DL1 to DLm, a power line PL, a reference voltage line QL, an initialization voltage line RL, and a plurality of pixels PX11 to PXnm. The write scan lines GWL1 to GWLn, the compensation scan lines GCL1 to GCLn, the black scan lines GBL1 to GBLn, the initialization scan lines GIL1 to GILn, and the emission lines EML1 to EMLn extend in a first direction DR1 and are arranged in a second direction DR2 that intersects the first direction DR1.

[0047] Data lines DL1 to DLm intersect the write scan lines GWL1 to GWLn, the compensation scan lines GCL1 to GCLn, the black scan lines GBL1 to GBLn, the initialization scan lines GIL1 to GILn, and the emission lines EML1 to EMLn, while being insulated from the write scan lines GWL1 to GWLn, the compensation scan lines GCL1 to GCLn, the black scan lines GBL1 to GBLn, the initialization scan lines GIL1 to GILn, and the emission lines EML1 to EMLn. Each of pixels PX11 to PXnm is connected to a corresponding signal line among the signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, and GIL1 to GILn. The connection structure between pixels PX11 to PXnm and the signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, and GIL1 to GILn can vary depending on the configuration of the driving circuit of each pixel PX11 to PXnm.

[0048] A power line PL receives a power voltage ELVDD. An initialization voltage line RL receives an initialization voltage Vint. A reference voltage line QL receives a reference voltage Vref. The reference voltage line QL may receive the power voltage ELVDD. The initialization voltage Vint has a voltage level lower than that of the power voltage ELVDD. A common voltage ELVSS is applied to the display panel DP. The common voltage ELVSS has a voltage level lower than that of the power voltage ELVDD.

[0049] In the above description, reference is made to Figure 1 The display device DD has been described above; however, the display device of the present disclosure should not be limited thereto or thereby. Depending on the configuration of the pixels PX11 to PXnm, the signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, and GIL1 to GILn may be added or omitted. Furthermore, the connection structure between a pixel and the signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, and GIL1 to GILn may be changed as desired.

[0050] Pixels PX11 to PXnm can be categorized into several groups based on the color of light emitted by pixels PX11 to PXnm. For example, pixels PX11 to PXnm include red pixels that generate red light, green pixels that generate green light, and blue pixels that generate blue light. The light-emitting diodes of the red pixels, the light-emitting diodes of the green pixels, and the light-emitting diodes of the blue pixels include light-emitting layers of different materials.

[0051] At least one of the pixels PX11 to PXnm includes a plurality of transistors and capacitors connected to the transistors. At least one of the scan driving circuit SDC and the data driving circuit DDC may include a plurality of transistors formed by the same process as the pixel driving circuit.

[0052] The signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, and GIL1 to GILn, the pixels PX11 to PXnm, the scan driving circuit SDC, and the data driving circuit DDC may be formed on the base substrate through multiple photolithography processes.

[0053] Figure 2 is an equivalent circuit diagram showing a pixel PXij according to an embodiment of the present disclosure, and Figures 3 to 5 is shown for driving Figure 2 : FIG. 1 is a waveform diagram of a driving signal of a pixel PXij shown in FIG.

[0054] Figure 2 A pixel PXij connected to an i-th write scan line GWLi among the write scan lines GWL1 to GWLn and a j-th data line DLj among the data lines DL1 to DLm is shown.

[0055] In this embodiment, the pixel PXij includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a first capacitor Cst1 and a second capacitor Cst2, and a light-emitting diode OLED. In this embodiment, each of the first transistor T1 to the seventh transistor T7 is described as a P-type transistor, however, they should not be limited to P-type transistors. Each of the first transistor T1 to the seventh transistor T7 can be implemented by one of a P-type transistor and an N-type transistor. As another way, some of the first transistor T1 to the seventh transistor T7 can be implemented by P-type transistors, and the other transistors of the first transistor T1 to the seventh transistor T7 can be implemented by N-type transistors. In addition, the number of transistors included in the pixel PXij should not be limited to seven. That is, at least one of the first transistor T1 to the seventh transistor T7 can be omitted or added to the pixel PXij.

[0056] In this embodiment, the first transistor T1 is a driving transistor, and the second transistor T2 is a switching transistor. The first capacitor Cst1 is connected between a power line PL receiving a power supply voltage ELVDD and a first reference node RN1. The first capacitor Cst1 includes a first electrode Cst1_1 connected to the first reference node RN1 and a second electrode Cst1_2 connected to the power line PL. The second capacitor Cst2 is connected between the first reference node RN1 and a second reference node RN2. The second capacitor Cst2 includes a first electrode Cst2_1 connected to the first reference node RN1 and a second electrode Cst2_2 connected to the second reference node RN2.

[0057] The first transistor T1 is connected between a power line PL and one electrode of the light-emitting diode OLED. A source S1 of the first transistor T1 is electrically connected to the power line PL. In this disclosure, the phrase "a transistor is electrically connected to a signal line, or a transistor is electrically connected to a transistor" means "any of the source, drain, and gate of the transistor is integral with the signal line, or any of the source, drain, and gate of the transistor is connected to another transistor via a connecting electrode." Another transistor may be arranged between the source S1 of the first transistor T1 and the power line PL.

[0058] The drain D1 of the first transistor T1 is electrically connected to the anode of the light emitting diode OLED. Another transistor may be arranged between the drain D1 of the first transistor T1 and the anode of the light emitting diode OLED. The gate G1 of the first transistor T1 is electrically connected to the second reference node RN2.

[0059] The second transistor T2 is connected between the j-th data line DLj and the first reference node RN1. A source S2 of the second transistor T2 is electrically connected to the j-th data line DLj, and a drain D2 of the second transistor T2 is electrically connected to the first reference node RN1. In this embodiment, a gate G2 of the second transistor T2 is electrically connected to the i-th write scan line GWLi.

[0060] The third transistor T3 is connected between the first reference node RN1 and the reference voltage line QL. The drain D3 of the third transistor T3 is electrically connected to the first reference node RN1, and the source S3 of the third transistor T3 is electrically connected to the reference voltage line QL. In this embodiment, the gate G3 of the third transistor T3 is electrically connected to the i-th compensation scan line GCLi.

[0061] The sixth transistor T6 is connected between the drain D1 of the first transistor T1 and the second reference node RN2. The source S6 of the sixth transistor T6 is electrically connected to the second reference node RN2, and the drain D6 of the sixth transistor T6 is electrically connected to the drain D1 of the first transistor T1. The gate G6 of the sixth transistor T6 is electrically connected to the i-th compensation scan line GCLi. Figure 2 In the embodiment, the gate G3 of the third transistor T3 and the gate G6 of the sixth transistor T6 are commonly connected to the i-th compensation scan line GCLi, however, the present disclosure should not be limited thereto or thereby. According to another embodiment, the gate G6 of the sixth transistor T6 may be connected to a signal line different from the signal line to which the gate G3 of the third transistor T3 is connected. According to an embodiment, the sixth transistor T6 may include a plurality of gates.

[0062] The seventh transistor T7 is connected between the source S6 of the sixth transistor T6 and the initialization voltage line RL. The source S7 of the seventh transistor T7 is electrically connected to the initialization voltage line RL, and the drain D7 of the seventh transistor T7 is electrically connected to the source S6 of the sixth transistor T6. In an embodiment, the gate G7 of the seventh transistor T7 is connected to the i-th initialization scan line GILi. Depending on the embodiment, the seventh transistor T7 may include multiple gates.

[0063] Since the sixth transistor T6 and the seventh transistor T7 include a plurality of gates, leakage current of the pixel PXij generated when the sixth transistor T6 and the seventh transistor T7 are turned off may be reduced.

[0064] The fourth transistor T4 is connected between the drain D1 of the first transistor T1 and the source S7 of the seventh transistor T7. The drain D4 of the fourth transistor T4 is electrically connected to the drain D1 of the first transistor T1, and the source S4 of the fourth transistor T4 is electrically connected to the source S7 of the seventh transistor T7. In an embodiment of the present disclosure, the gate G4 of the fourth transistor T4 is electrically connected to the i-th black scan line GBLi.

[0065] The fifth transistor T5 is connected between the drain D1 of the first transistor T1 and the light-emitting diode OLED. The source S5 of the fifth transistor T5 is electrically connected to the drain D1 of the first transistor T1 and the drain D4 of the fourth transistor T4, and the drain D5 of the fifth transistor T5 is electrically connected to the anode of the light-emitting diode OLED. The gate G5 of the fifth transistor T5 is electrically connected to the i-th emission line EMLi.

[0066] The light emitting diode OLED is connected between the common electrode and the fifth transistor T5. A cathode of the light emitting diode OLED is electrically connected to the common electrode, and an anode of the light emitting diode OLED is electrically connected to a drain electrode D5 of the fifth transistor T5.

[0067] Figure 3 A waveform diagram showing a portion of a frame period is shown. Figure 1 and Figure 3 , the display device DD displays an image in each frame period. During one frame period, each of the write scan lines GWL1 to GWLn, the compensation scan lines GCL1 to GCLn, the black scan lines GBL1 to GBLn, the initialization scan lines GIL1 to GILn, and the emission lines EML1 to EMLn is sequentially scanned. Figure 2 and Figure 3Each of the signals GIi, GCi, GBi, and GWi, and the emission signal EMi, has a high level and a low level. Because the signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, and GIL1 to GILn, and the emission lines EML1 to EMLn are electrically connected to the gates of the transistors, when the signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, and GIL1 to GILn, and the emission lines EML1 to EMLn have a high level, the N-type transistors are turned on, and when the signal lines GWL1 to GWLn, GCL1 to GCLn, GBL1 to GBLn, GIL1 to GILn, and the emission lines EML1 to EMLn have a low level, the P-type transistors are turned on.

[0068] Among the initialization scan signals GI1 to GIn, the initialization scan signal supplied to the i-th initialization scan line GILi is referred to as an i-th initialization scan signal GIi.

[0069] Among the compensation scan signals GC1 to GCn, the compensation scan signal supplied to the i-th compensation scan line GCLi is referred to as an i-th compensation scan signal GCi.

[0070] Among the black scan signals GB1 to GBn, the black scan signal supplied to the i-th black scan line GBLi is referred to as an i-th black scan signal GBi.

[0071] Among the data write signals GW1 to GWn, the data write signal supplied to the i-th write scan line GWLi is referred to as an i-th data write signal GWi.

[0072] Among the light emitting signals EM1 to EMn, a light emitting signal supplied to the i-th light emitting line EMLi is referred to as an i-th light emitting signal EMi.

[0073] In this embodiment, the i-th light emitting signal EMi includes a non-light emitting period EMW_1 having a high level and a light emitting period EMW_2 having a low level.

[0074] In the non-light-emitting period EMW_1 of one frame (1 frame), during the "initialization period GIW," the i-th initialization scan signal GIi having a conduction level (low level) is provided to the gate G7 of the seventh transistor T7 for initialization. The initialization period GIW is included in the non-light-emitting period EMW_1. When the seventh transistor T7 is turned on during the initialization period GIW, the initialization voltage Vint is applied to the gate G1 of the first transistor T1 through the seventh transistor T7. Therefore, the second reference node RN2 connected to the gate G1 of the first transistor T1 is initialized to the initialization voltage Vint.

[0075] Then, during the "compensation period GCW," an i-th compensation scan signal GCi having a conduction level (low level) is supplied to the gate G3 of the third transistor T3 and the gate G6 of the sixth transistor T6. During the compensation period GCW, the third transistor T3 and the sixth transistor T6 are turned on. In this case, the first transistor T1 is diode-connected and forward-biased by the turned-on sixth transistor T6. Therefore, a compensation voltage ELVDD-Vth is applied to the gate G1 of the first transistor T1. The compensation voltage ELVDD-Vth is calculated by subtracting the threshold voltage Vth of the first transistor T1 from the power supply voltage ELVDD supplied from the power line PL. That is, the voltage of the second reference node RN2 may be the compensation voltage ELVDD-Vth. Simultaneously, when the third transistor T3 is turned on during the compensation period GCW, the reference voltage Vref is applied to the drain D2 of the second transistor T2 via the third transistor T3. Therefore, the voltage of the first reference node RN1, which is connected to the drain D2 of the second transistor T2, may be the reference voltage Vref.

[0076] During the "write period GWW," an i-th data write signal GWi having a turn-on level (low level) is supplied to the gate G2 of the second transistor T2. When the second transistor T2 is turned on during the write period GWW, a data voltage Vdata corresponding to the data is applied to the drain D3 of the third transistor T3 through the second transistor T2. Therefore, the voltage of the first reference node RN1 connected to the drain D3 of the third transistor T3 may have the data voltage Vdata.

[0077] The power voltage ELVDD and the data voltage Vdata are respectively applied to both electrodes of the first capacitor Cst1 , and the first capacitor Cst1 is charged with a voltage difference (ELVDD−Vdata) between both electrodes of the first capacitor Cst1 .

[0078] The data voltage Vdata and the compensation voltage ELVDD-Vth are applied to both electrodes of the second capacitor Cst2, and the second capacitor Cst2 is charged with a voltage difference (ELVDD-Vth-Vdata) between both electrodes of the second capacitor Cst2.

[0079] In this case, the voltage of the first reference node RN1 changes from the reference voltage Vref, which is the voltage when the third transistor T3 is turned on, to the data voltage Vdata, which is the voltage when the second transistor T2 is turned on. Due to the coupling effect of the second capacitor Cst2, the voltage change (Vdata-Vref) of the first reference node RN1 is transmitted to the second reference node RN2. In other words, the voltage of the second reference node RN2 can be the value (Vdata+ELVDD-Vth-Vref) obtained by adding the voltage change (Vdata-Vref) of the first reference node RN1 when the second transistor T2 is turned on to the compensation voltage ELVDD-Vth when the sixth transistor T6 is turned on.

[0080] Then, the fifth transistor T5 is turned on during the light emitting period EMW_2. Therefore, due to the voltage difference between the gate voltage of the gate G1 of the first transistor T1 and the source voltage of the source S1 of the first transistor T1, a driving current Id is generated, and the driving current Id is provided to the light emitting diode OLED through the fifth transistor T5. As a result, current flows through the light emitting diode OLED. During the light emitting period EMW_2, the gate-source voltage Vgs of the first transistor T1 is maintained at a value ELVDD-(Vdata+ELVDD-Vth-Vref) by the second capacitor Cst2, and according to the current-voltage relationship of the first transistor T1, the driving current Id of the first transistor T1 is equal to the square of the value obtained by subtracting the threshold voltage Vth of the first transistor T1 from the gate-source voltage Vgs of the first transistor T1, that is, (Vdata-Vref). 2 Therefore, the driving current Id can be determined regardless of the threshold voltage Vth of the first transistor T1.

[0081] The data signal Vdata output from the data driver circuit DDC is written into the display panel DP of the display device DD, thereby causing the light-emitting diode OLED to emit light. The frequency at which the data signal Vdata is written is referred to as the operating frequency. The frequency of the write period GWW during which the second transistor T2 electrically connected to the j-th data line DLj is turned on to write the data signal Vdata is substantially the same as the operating frequency.

[0082] The gate G6 of the sixth transistor T6 and the gate G2 of the second transistor T2 are connected to different signal lines. In this way, the gate G1 and the drain D1 of the first transistor T1 are connected in the form of a diode, and therefore, the timing for applying the compensation voltage ELVDD-Vth to the gate G1 of the first transistor T1 and the timing for applying the data voltage Vdata of the j-th data line DLj to the first reference node RN1 through the second transistor T2 can be independently controlled. That is, the compensation period GCW and the write period GWW do not overlap with each other. Since the operation of compensating for the threshold voltage Vth of the first transistor T1 through the sixth transistor T6 and the operation of writing data in the first reference node RN1 through the second transistor T2 are performed in different periods from each other, each operation is not affected by the other operation. Although the write period GWW of the i-th data write signal GWi is determined by the display device DD (refer to Figure 1 ), but the compensation period GCW of the i-th compensation scan signal GCi may be determined independently of the write period GWW. The compensation period GCW may have substantially the same width as that of the write period GWW determined by the operating frequency.

[0083] As another example, refer to Figure 4 The compensation period GCW may be wider than the writing period GWW. Therefore, although the display device DD has a high operating frequency, the operation of compensating the threshold voltage Vth of the first transistor T1 can be completed by a sufficient compensation period GCW.

[0084] Then, during the "black period GBW," an i-th black scan signal GBi having a turn-on level (low level) is supplied to the gate electrode G4 of the fourth transistor T4 to initialize the drain electrode D1 of the first transistor T1. When the fourth transistor T4 is turned on during the black period GBW, the initialization voltage Vint is supplied to the drain electrode D1 of the first transistor T1 via the fourth transistor T4. Therefore, the voltage of the drain electrode D1 of the first transistor T1 may have the initialization voltage Vint. When the fifth transistor T5 is turned on and the drive current Id flows through the light-emitting diode OLED, the light-emitting diode OLED may be prevented from transiently emitting light due to the voltage remaining in the drain electrode D1 of the first transistor T1 and flowing into the anode electrode of the light-emitting diode OLED.

[0085] During the non-emission period EMW_1, after the third transistor T3 and the sixth transistor T6 are turned on in response to the compensation period GCW, the fourth transistor T4 is turned on during the black period GBW. When the sixth transistor T6 is turned on, the drain D1 of the first transistor T1 is connected to the gate G1 of the first transistor T1 in a diode configuration, and the compensation voltage ELVDD-Vth is applied to the drain D1. When the fourth transistor T4 is turned on, the initialization voltage Vint is applied to the drain D1 of the first transistor T1 through the fourth transistor T4, and thus the compensation voltage ELVDD-Vth is initialized to the initialization voltage Vint.

[0086] Before the second transistor T2 is turned on during the write period GWW, the fourth transistor T4 is turned on during the black period GBW. When the second transistor T2 is turned on, the voltage (Vdata+ELVDD-Vth-Vref) is applied to the gate G1 of the first transistor T1, which is electrically connected to the second reference node RN2. Therefore, the first transistor T1 is turned on, and the on-state of the first transistor T1 is maintained by the charge stored in the second capacitor Cst2. When the first transistor T1 is turned on, the power supply voltage ELVDD provided by the power line PL electrically connected to the source S1 is applied to the drain D1.

[0087] When the fourth transistor T4 is turned on, the initialization voltage Vint is applied to the drain D1 of the first transistor T1 through the fourth transistor T4. Therefore, the fourth transistor T4 is turned on before the power supply voltage ELVDD is applied to the drain D1 of the first transistor T1.

[0088] Figure 4 and Figure 5 Is shown driving Figure 2 : The waveform diagram of the pixel driving signal is shown in FIG.

[0089] Reference Figure 4 The initialization period GIW is wider than the black period GBW and the writing period GWW. The compensation period GCW is wider than the black period GBW and the writing period GWW. By extending the initialization period GIW and the compensation period GCW during which the voltage of the gate G1 of the first transistor T1 is initialized and the compensation voltage ELVDD-Vth is applied, the influence of previous data can be reduced.

[0090] Reference Figure 5 The initialization periods GIW1 to GIWn and the compensation periods GCW1 to GCWn are repeated multiple times in one frame. The influence of previous data can be reduced by repeating the initialization periods GIW1 to GIWn and the compensation periods GCW1 to GCWn during which the voltage of the gate G1 of the first transistor T1 is initialized and the compensation voltage ELVDD-Vth is applied.

[0091] Figure 6 and Figure 7 Is shown driving Figure 2 : The waveform diagram of the pixel driving signal is shown in FIG. Figure 8A is an equivalent circuit diagram showing an initialization operation of the drain voltage of the driving transistor. Figure 8B is an equivalent circuit diagram showing an initialization operation of an anode voltage of a light emitting diode.

[0092] Reference Figure 6 、 Figure 8A and Figure 8B The black period GBW overlaps with the non-emission period EMW_1 and the emission period EMW_2. The fourth transistor T4 is turned on during the black period GBW_1 that overlaps with the non-emission period EMW_1, and forms a path PH1 for applying the initialization voltage Vint to the drain electrode D1 of the first transistor T1 through the fourth transistor T4. As a result, the voltage of the drain electrode D1 of the first transistor T1 is initialized.

[0093] The fourth transistor T4 and the fifth transistor T5 are simultaneously turned on during the black period GBW_2, which overlaps with the light-emitting period EMW_2. This forms a path PH2, in which the initialization voltage Vint is applied to the drain D1 of the first transistor T1 via the fourth transistor T4 and to the drain D5 of the fifth transistor T5 via the fourth transistor T4 and the fifth transistor T5. Consequently, the voltage at the drain D1 of the first transistor T1 and the voltage at the anode of the light-emitting diode OLED are initialized. Therefore, when the fifth transistor T5 is turned on, the light-emitting diode OLED is prevented from transiently emitting light due to the current flowing through the light-emitting diode OLED caused by the residual voltage in the drain D1 of the first transistor T1. Furthermore, even when the first transistor T1 is turned off, leakage current flowing through the first transistor T1 can be discharged through the fourth transistor T4, resulting in improved contrast of the display panel DP by achieving a true black image. The ratio of the black period GBW_1, which overlaps with the non-light-emitting period EMW_1, to the black period GBW_2, which overlaps with the light-emitting period EMW_2, is not limited to the ratio shown in the figure. Before the second transistor T2 is turned on in response to the i-th data write signal GWi in the write period GWW, the fourth transistor T4 is turned on in the black period GBW. The write period GWW may overlap with the light emission period EMW_2.

[0094] As an example of the present disclosure, refer to Figure 7 , the black period GBW completely overlaps with the light emitting period EMW_2. In this case, the voltage of the drain electrode D1 of the first transistor T1 and the voltage of the anode electrode of the light emitting diode OLED are initialized in the black period GBW completely overlapping with the light emitting period EMW_2.

[0095] Figure 9 is an equivalent circuit diagram illustrating a pixel PXij according to an embodiment of the present disclosure. Figure 10 is shown for driving Figure 9 : FIG. 1 is a waveform diagram of a driving signal of a pixel PXij shown in FIG.

[0096] Figure 9 A pixel PXij connected to an i-th scan line SLi among the scan lines and a j-th data line DLj among the data lines is shown as a representative example.

[0097] In this embodiment, pixel PXij includes a first transistor Ta, a second transistor Tb, a third transistor Tc, a fourth transistor Td, a fifth transistor Te, a sixth transistor Tf, and a seventh transistor Tg, as well as a light-emitting diode (OLED). In this embodiment, each of the first to seventh transistors Tg is described as a P-type transistor, however, they should not be limited to P-type transistors. Each of the first to seventh transistors Tg can be implemented as either a P-type transistor or an N-type transistor. Alternatively, some of the first to seventh transistors Tg can be implemented as P-type transistors, and the rest of the first to seventh transistors Tg can be implemented as N-type transistors. Furthermore, the number of transistors included in pixel PXij should not be limited to seven. That is, at least one of the first to seventh transistors Tg can be omitted, and alternatively, one or more transistors can be added to pixel PXij. In this embodiment, the first transistor Ta is a drive transistor, and the second transistor Tb is a switching transistor. A capacitor Cst is connected between a power line PL receiving a power supply voltage ELVDD and a reference node RN. The capacitor Cst includes a first electrode Cst_1 connected to the reference node RN and a second electrode Cst_2 connected to the power line PL.

[0098] The first transistor Ta is connected between the power line PL and one electrode of the light-emitting diode OLED. The source electrode Sa of the first transistor Ta is electrically connected to the power line PL. In this disclosure, the expression "a transistor is electrically connected to a signal line, or a transistor is electrically connected to a transistor" means "any of the source, drain, and gate of the transistor is integral with the signal line, or any of the source, drain, and gate of the transistor is connected to another transistor via a connecting electrode." Another transistor may be arranged between the source electrode Sa of the first transistor Ta and the power line PL.

[0099] The drain electrode Da of the first transistor Ta is electrically connected to the anode of the light emitting diode OLED. Another transistor may be arranged between the drain electrode Da of the first transistor Ta and the anode of the light emitting diode OLED. The gate electrode Ga of the first transistor Ta is electrically connected to the reference node RN.

[0100] The second transistor Tb is connected between the j-th data line DLj and the source Sa of the first transistor Ta. The source Sb of the second transistor Tb is electrically connected to the j-th data line DLj, and the drain Db of the second transistor Tb is electrically connected to the source Sa of the first transistor Ta. In this embodiment, the gate Gb of the second transistor Tb is electrically connected to the i-th scan line SLi.

[0101] The third transistor Tc is connected between the power line PL and the source Sa of the first transistor Ta. The source Sc of the third transistor Tc is electrically connected to the power line PL, and the drain Dc of the third transistor Tc is electrically connected to the source Sa of the first transistor Ta. In this embodiment, the gate Gc of the third transistor Tc is electrically connected to the i-th emission line EML'i.

[0102] The sixth transistor Tf is connected between the reference node RN and the drain Da of the first transistor Ta. The source Sf of the sixth transistor Tf is electrically connected to the reference node RN, and the drain Df of the sixth transistor Tf is electrically connected to the drain Da of the first transistor Ta. In this embodiment, the gate Gf of the sixth transistor Tf is electrically connected to the i-th scan line SLi. The sixth transistor Tf may include multiple gates.

[0103] The seventh transistor Tg is connected between the reference node RN and the initialization voltage line RL. The drain Dg of the seventh transistor Tg is electrically connected to the reference node RN, and the source Sg of the seventh transistor Tg is electrically connected to the initialization voltage line RL. In this embodiment, the gate Gg of the seventh transistor Tg is electrically connected to the (i-1)th scan line SLi-1. The seventh transistor Tg may include multiple gate electrodes.

[0104] Since the sixth transistor Tf and the seventh transistor Tg include a plurality of gates, leakage current generated when the sixth transistor Tf and the seventh transistor Tg are turned off may be reduced.

[0105] The fourth transistor Td is connected between the drain Da of the first transistor Ta and the source Sg of the seventh transistor Tg. The source Sd of the fourth transistor Td is electrically connected to the source Sg of the seventh transistor Tg, and the drain Dd of the fourth transistor Td is electrically connected to the drain Da of the first transistor Ta. The gate Gd of the fourth transistor Td is electrically connected to the i-th initialization scan line ISLi.

[0106] The fifth transistor Te is connected between the drain Da of the first transistor Ta and the light-emitting diode OLED. The source Se of the fifth transistor Te is electrically connected to the drain Da of the first transistor Ta and the drain Dd of the fourth transistor Td, and the drain De of the fifth transistor Te is electrically connected to the anode of the light-emitting diode OLED. The gate Ge of the fifth transistor Te is electrically connected to the i-th emission line EML'i. According to another embodiment, the gate Gc of the third transistor Tc can be connected to a signal line different from the signal line to which the gate Ge of the fifth transistor Te is connected.

[0107] The light emitting diode OLED is connected between the common electrode and the fifth transistor Te. A cathode of the light emitting diode OLED is electrically connected to the common electrode, and an anode of the light emitting diode OLED is electrically connected to a drain De of the fifth transistor Te.

[0108] Figure 10 A portion of a frame period is shown. Figure 9 and Figure 10 , the display device DD displays an image in each frame period. For one frame period, each of the scanning line, the initialization scanning line, and the light emitting line is sequentially scanned.

[0109] Reference Figure 9 and Figure 10 Each of the signals SCi-1, SCi, and ISCi, as well as the emission signal EM'i, has a high level and a low level. Because the scan lines SLi and SLi-1, the initialization scan line ISLi, and the emission line EML'i are electrically connected to the gates of the transistors, when the scan lines SLi and SLi-1, the initialization scan line ISLi, and the emission line EML'i are high, the N-type transistor is turned on, and when the scan lines SLi and SLi-1, the initialization scan line ISLi, and the emission line EML'i are low, the P-type transistor is turned on. The emission signal EM'i includes a non-emission period EMW_1a and an emission period EMW_2a.

[0110] During the non-light-emission period EMW_1a of one frame (1 frame), during the "previous scanning period AP1," the previous scanning signal SCi-1 having a turn-on level (low level) is supplied to the gate Gg of the seventh transistor Tg. When the seventh transistor Tg is turned on during the previous scanning period AP1, the initialization voltage Vint is applied to the gate Ga of the first transistor Ta through the seventh transistor Tg. Therefore, the reference node RN connected to the gate Ga of the first transistor Ta is initialized to the initialization voltage Vint.

[0111] Then, during the "scan period AP2", a scan signal SCi having a turn-on level (low level) is provided to the gate Gb of the second transistor Tb and the gate Gf of the sixth transistor Tf. The second transistor Tb and the sixth transistor Tf are turned on in the scan period AP2. The data voltage Vdata corresponding to the data is applied to the source Sa of the first transistor Ta through the second transistor Tb. In this case, the first transistor Ta is connected in the form of a diode and is forward biased by the turned-on sixth transistor Tf. Therefore, a compensation voltage Vdata-Vth obtained by subtracting the threshold voltage Vth of the first transistor Ta from the data voltage Vdata applied to the source Sa of the first transistor Ta is applied to the gate Ga of the first transistor Ta. That is, the voltage of the reference node RN may have the compensation voltage Vdata-Vth. Therefore, the first transistor Ta is turned on, and the conduction state of the first transistor Ta is maintained by the charge stored in the capacitor Cst.

[0112] Next, during the "initialization period AP3," an initialization scan signal ISCi having a turn-on level (low level) is supplied to the gate Gd of the fourth transistor Td. The fourth transistor Td is turned on during the initialization period AP3. The initialization voltage Vint is applied to the drain Da of the first transistor Ta through the fourth transistor Td, and the voltage of the drain Da of the first transistor Ta is initialized from the compensation voltage Vdata-Vth to the initialization voltage Vint.

[0113] Then, during the "emission period EMW_2a", the emission signal EM'i having a turn-on level (low level) is supplied to the gate Gc of the third transistor Tc and the gate Ge of the fifth transistor Te. The third transistor Tc and the fifth transistor Te are turned on during the emission period EMW_2a, and the driving current Id flows through the light emitting diode OLED.

[0114] Figure 11 is a waveform diagram showing the luminance of a pixel at each driving frequency according to an embodiment of the present disclosure.

[0115] Reference Figure 2 、 Figure 10 、 Figure 11 , the operation of initializing the anode of the light emitting diode OLED is called “first drive AA”, the operation of not initializing the anode of the light emitting diode OLED is called “second drive BB”, and the operation of not initializing the anode of the light emitting diode OLED but initializing the drain D1 of the first transistor T1 and the drain Da of the first transistor Ta is called “third drive CC”.

[0116] The light emitting diode OLED emits light with a specific amount of brightness LU corresponding to the data voltage Vdata applied thereto. The amount of light emitted by the light emitting diode OLED in a specific time period is referred to as the light emission amount LUM. In the case of the first drive AA, since the anode of the light emitting diode OLED is initialized, a specific time period is required until the light emitting diode OLED emits light with a specific amount of brightness LU, and this is called "light emission delay LD". In the case of the second drive BB, since the anode of the light emitting diode OLED is not initialized, the light emission delay LD does not occur. However, when the voltage remaining in the drain D1 of the driving transistor T1 flows into the light emitting diode OLED, the light emitting diode OLED instantaneously emits light with high brightness at the beginning of the second drive BB, and this is called "instantaneous light emission IL". In the display device DD (refer to Figure 1 ), in the first drive AA, when the operating frequency of the display device DD is changed from approximately 60 Hz to approximately 120 Hz, the influence of the light emission delay LD at the operating frequency of approximately 120 Hz is greater than the influence of the light emission delay LD at the operating frequency of approximately 60 Hz. Therefore, the light emission amount LUM of the display device DD when the display device DD is driven at approximately 120 Hz is less than the light emission amount LUM of the display device DD when the display device DD is driven at approximately 60 Hz, and therefore, the difference in the light emission amount LUM when the operating frequency is changed is recognized by the observer.

[0117] In the case of the second drive BB, the influence of the instantaneous light emission IL at an operating frequency of approximately 120 Hz is greater than the influence of the instantaneous light emission IL at an operating frequency of approximately 60 Hz. Therefore, the light emission amount LUM of the display device DD when the display device DD is driven at approximately 120 Hz is greater than the light emission amount LUM of the display device DD when the display device DD is driven at approximately 60 Hz. Therefore, the difference in the light emission amount LUM when the operating frequency changes is recognized by the observer.

[0118] In the third drive CC, the light emission delay LD and instantaneous light emission IL have little effect on the light-emitting diode OLED. Consequently, the difference between the light emission delay LD and instantaneous light emission IL is small between operating frequencies of approximately 60 Hz and approximately 120 Hz. Consequently, the difference in light emission quantity LUM when the operating frequency changes is not noticeable to an observer. That is, since the transistor transmitting the initialization voltage Vint is not connected to the anode of the light-emitting diode OLED, the occurrence of light emission delay LD is prevented. Furthermore, since the fourth transistor T4 and the fourth transistor Td transmitting the initialization voltage Vint are connected to the drain D1 of the first transistor T1 and the drain Da of the first transistor Ta, respectively, the occurrence of instantaneous light emission IL is prevented. Therefore, when the light-emitting diode OLED emits light, the difference in light emission quantity LUM, i.e., flickering, which is noticeable to an observer and is caused by voltage remaining in the drain D1 of the first transistor T1 and the drain Da of the first transistor Ta and flowing into the light-emitting diode OLED, is prevented.

[0119] like Figure 11 As shown in FIG, driving without initializing the anode of the light emitting diode OLED and driving with initializing the drain D1 of the first transistor T1 and the drain Da of the first transistor Ta can prevent the display quality of the display device DD from being deteriorated due to a change in the light emission amount LUM of the light emitting diode OLED according to the operating frequency of the display device DD. To this end, the connection structure of the fourth transistor T4 or the fourth transistor Td electrically connected between the anode of the light emitting diode OLED and the initialization voltage line RL in the conventional display device DD can be changed to a connection structure in which the fourth transistor T4 or the fourth transistor Td is electrically connected between the drain D1 of the first transistor T1 or the drain Da of the first transistor Ta and the initialization voltage line RL.

[0120] Although the embodiments of the present disclosure have been described, it should be understood that the disclosure should not be limited to these embodiments, but one skilled in the art can make various changes and modifications within the spirit and scope of the disclosure as hereinafter claimed.

[0121] Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined in accordance with the following claims.

Claims

1. A display device, comprising: The display panel includes a plurality of pixels, at least one of the plurality of pixels includes: light-emitting diodes; a first transistor connected between a power line receiving a power supply voltage and an anode of the light emitting diode; a second transistor connected between the data line and the first reference node; a first capacitor connected between the power line and the first reference node; a second capacitor connected between the first reference node and a second reference node; a third transistor connected between the first reference node and a reference voltage line receiving a reference voltage; a fourth transistor connected between an initialization voltage line receiving an initialization voltage and a drain of the first transistor; and a fifth transistor connected between the drain of the first transistor and the anode of the light emitting diode, Wherein, the first transistor includes: a source electrode connected to the power supply line; and a gate connected to the second reference node, Wherein, the second transistor includes a gate for receiving a data write signal; Wherein, the third transistor includes a gate for receiving a compensation scanning signal; Wherein, the fourth transistor includes a gate for receiving a black scan signal.

2. The display device according to claim 1, wherein The second transistor includes: a source electrode connected to the data line; and a drain connected to the first reference node, Wherein, the third transistor includes: a source electrode connected to the reference voltage line; and a drain connected to the first reference node, In one frame, a compensation period in which the compensation scan signal having an on level is applied to the gate of the third transistor precedes a writing period in which the data write signal having an on level is applied to the gate of the second transistor.

3. The display device according to claim 2, further comprising: a sixth transistor connected between the second reference node and the drain of the first transistor, Wherein, the sixth transistor includes: a gate, the gate receiving the compensation scanning signal; a source connected to the second reference node; and A drain electrode is connected to the drain electrode of the first transistor.

4. The display device according to claim 2, further comprising: a seventh transistor connected between the second reference node and the initialization voltage line, Wherein, the seventh transistor includes: a gate, the gate receiving an initialization scan signal; a source electrode connected to the initialization voltage line; and A drain is connected to the second reference node.

5. The display device according to claim 4, wherein The fourth transistor includes: a source connected to the source of the seventh transistor; and A drain electrode is connected to the drain electrode of the first transistor. The display device according to claim 5 , wherein: The fifth transistor includes: a gate, the gate receiving a light emitting signal; a source connected to the drain of the fourth transistor; and a drain electrode connected to the anode of the light emitting diode, wherein, in the one frame, an initialization period in which the initialization scan signal having a turn-on level is applied to the gate of the seventh transistor is before the compensation period and the writing period, In the one frame, a black period in which the black scan signal having an on level is applied to the gate electrode of the fourth transistor is between the compensation period and the writing period.

7. The display device according to claim 6, wherein: In the one frame, the initialization period, the compensation period, the black period, and the writing period are in a non-light emitting period of the light emitting signal.

8. The display device according to claim 6, wherein: In the one frame, the initialization period, the compensation period, and the black period are in the non-luminescence period of the luminescence signal, the black period overlaps with the non-luminescence period and the luminescence period of the luminescence signal, and the writing period overlaps with the luminescence period.

9. The display device according to claim 6, wherein: In the one frame, the initialization period and the compensation period are in a non-light emitting period of the light emitting signal, the black period overlaps with a light emitting period of the light emitting signal, and the writing period overlaps with the light emitting period.

10. A display device comprising: A display panel, the display panel comprising a drive circuit and a light-emitting diode connected to the drive circuit, the drive circuit comprising: Driver transistors, including: a gate electrode receiving a data signal from a data line, a source receiving a power supply voltage, and a drain electrode electrically connected to an anode of the light emitting diode, A first transistor comprising: a source connected to the drain of the driving transistor, and a drain electrode connected to the anode of the light emitting diode; A second transistor comprising: source, the source being connected to an initialization voltage line, a drain connected to the drain of the driving transistor and the source of the first transistor, and a gate, the gate receiving a black scanning signal; A third transistor includes: a gate, the gate receiving a compensation scanning signal, a source connected to a reference voltage line, and a drain connected to a first reference node; and a fourth transistor comprising: a gate, the gate receiving the compensation scanning signal, a source connected to a second reference node, and A drain electrode is connected to the drain electrode of the driving transistor.

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