Transient Enhancement Circuit

Abstract

This application is applicable to the field of power supply technology, and provides a transient enhancement circuit, including a direction detection unit, a slope detection unit, and a compensation unit. The direction detection unit collects first information on the change in the output voltage, and outputs a first logic signal and a second logic signal according to the first information. The first information reflects whether the output voltage increases or decreases. The slope detection unit collects slope information on the change in the output voltage, and outputs a third logic signal and a fourth logic signal according to the slope information. The slope information reflects the slope of the increase or decrease in the output voltage. The compensation unit provides a compensation current for the compensation capacitor when the compensation capacitor is charged or discharged according to the first logic signal, the second logic signal, the third logic signal, and the fourth logic signal. The transient enhancement circuit according to the embodiment of this application determines the intervention moment and the intervention duration by detecting the first information and the slope information on the change in the output voltage, improves the accuracy of intervention, and enables the output voltage to quickly return to stability.

Description

Technical Field

[0001] This application belongs to the technical field of power supplies, and particularly relates to a transient enhancement circuit. Background Art

[0002] A DC-DC converter can convert a DC voltage within a range or of a fixed value into another DC voltage that is variable or of a fixed value. Due to the presence of right-half plane zeros in the DC-DC converter, the design of the loop bandwidth is restricted. Therefore, it is necessary to design a transient enhancement circuit to improve the transient response process of the DC-DC converter. Traditional transient enhancement circuits have the problem of inaccurate intervention, resulting in the output voltage of the DC-DC converter being unable to quickly recover to stability. Summary of the Invention

[0003] Embodiments of this application provide a transient enhancement circuit, which can solve the problem of inaccurate intervention of traditional transient enhancement circuits.

[0004] Embodiments of this application provide a transient enhancement circuit, including:

[0005] A direction detection unit, configured to collect first information on the change in the output voltage of the DC-DC converter, and configured to output a first logic signal and a second logic signal according to the first information; wherein, the first information is used to reflect an increase or a decrease in the output voltage;

[0006] A slope detection unit, configured to collect slope information on the change in the output voltage, and configured to output a third logic signal and a fourth logic signal according to the slope information; wherein, the slope information is used to reflect the slope of the increase or the slope of the decrease in the output voltage; and

[0007] A compensation unit, configured to provide a compensation current for a compensation capacitor when the compensation capacitor is charging or discharging according to the first logic signal, the second logic signal, the third logic signal, and the fourth logic signal, where the compensation capacitor is a capacitor connected to the output end of an error amplifier.

[0008] In a possible implementation, the direction detection unit includes:

[0009] A first bias current source, configured to provide a first static bias current;

[0010] A first mirror unit, configured to receive the first static bias current, and configured to output a first current signal and a second current signal according to the first static bias current;

[0011] A second mirror unit, configured to receive the output voltage, and configured to output a third current signal and a fourth current signal according to the output voltage; and

[0012] A first logic unit is configured to receive the first current signal, the second current signal, the third current signal, and the fourth current signal; when the output voltage increases beyond a first preset voltage, the first logic unit is configured to output the first logic signal according to the first current signal and the third current signal; when the output voltage decreases below a second preset voltage, the first logic unit is configured to output the second logic signal according to the second current signal and the fourth current signal.

[0013] In a possible implementation, the second mirror unit includes a first resistor, a second resistor, a third resistor, a first capacitor, a first switch transistor, a first transistor, a second transistor, and a third transistor;

[0014] A first end of the first resistor, a source electrode of the second transistor, and a first end of the third resistor are all configured to receive the output voltage; a source electrode of the first transistor is electrically connected to a second end of the first resistor, and a drain electrode of the first transistor is respectively electrically connected to a gate electrode of the first transistor, a first end of the second resistor, a drain electrode of the first switch transistor, and the second mirror unit; a gate electrode of the second transistor is respectively electrically connected to a first end of the first capacitor, a second end of the second resistor, a source electrode of the first switch transistor, and a gate electrode of the third transistor, and a drain electrode of the second transistor is respectively electrically connected to a first input terminal of the first logic unit and the second mirror unit; a drain electrode of the third transistor is respectively electrically connected to a second input terminal of the first logic unit and the second mirror unit, a second end of the first capacitor is grounded, and a gate electrode of the first switch transistor is configured to receive a control signal.

[0015] In a possible implementation, the first mirror unit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0016] A gate electrode of the fourth transistor is respectively electrically connected to a drain electrode of the fourth transistor, a first bias current source, a gate electrode of the fifth transistor, a gate electrode of the sixth transistor, and a gate electrode of the seventh transistor, and a source electrode of the fourth transistor, a source electrode of the fifth transistor, a source electrode of the sixth transistor, and a source electrode of the seventh transistor are all grounded; a drain electrode of the fifth transistor is electrically connected to a drain electrode of the first transistor, a drain electrode of the sixth transistor is respectively electrically connected to a drain electrode of the second transistor and a first input terminal unit of the first logic unit, and a drain electrode of the seventh transistor is respectively electrically connected to a drain electrode of the third transistor and a second input terminal of the first logic unit.

[0017] In a possible implementation, the first logic unit includes a first Schmitt trigger, a second Schmitt trigger, a first inverter, a second inverter, and a third inverter;

[0018] The input terminals of the first Schmitt trigger are electrically connected to the drain of the sixth transistor and the drain of the second transistor respectively, and the output terminal of the first Schmitt trigger is electrically connected to the input terminal of the first inverter; the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the output terminal of the second inverter is electrically connected to the compensation unit; the input terminals of the second Schmitt trigger are electrically connected to the drain of the third transistor and the drain of the seventh transistor respectively, and the output terminal of the second Schmitt trigger is electrically connected to the input terminal of the third inverter; the output terminal of the third inverter is electrically connected to the compensation unit.

[0019] In a possible implementation, the slope detection unit includes:

[0020] A second bias current source for providing a second static bias current;

[0021] A third mirror unit for receiving the second static bias current and for outputting a fifth current signal and a sixth current signal according to the second static bias current;

[0022] A fourth mirror unit for receiving the output voltage and for outputting a seventh current signal and an eighth current signal according to the output voltage; and

[0023] A second logic unit for receiving the fifth current signal, the sixth current signal, the seventh current signal and the eighth current signal; when the slope of the increasing output voltage exceeds a first preset slope, the second logic unit is used for outputting the third logic signal according to the fifth current signal and the seventh current signal; when the slope of the decreasing output voltage is lower than a second preset slope, the second logic unit is used for outputting the fourth logic signal according to the sixth current signal and the eighth current signal.

[0024] In a possible implementation, the third mirror unit includes an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor;

[0025] The gate of the eighth transistor is electrically connected to the drain of the eighth transistor, the second bias current source, the gate of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor respectively; the source of the eighth transistor, the source of the ninth transistor, the source of the tenth transistor, and the source of the eleventh transistor are all electrically connected to a voltage source; the drain of the ninth transistor is electrically connected to the fourth mirror unit, the drain of the tenth transistor is electrically connected to the fourth mirror unit and the first input terminal of the second logic unit respectively, and the drain of the eleventh transistor is electrically connected to the fourth mirror unit and the second input terminal of the second logic unit respectively.

[0026] In a possible implementation, the fourth mirror unit includes a fourth resistor, a second capacitor, a third capacitor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;

[0027] The first end of the fourth resistor is used to receive the output voltage, the first end of the third capacitor is electrically connected to the first end of the second capacitor and the second end of the fourth resistor respectively, and the second end of the second capacitor is grounded; the gate of the twelfth transistor is electrically connected to the drain of the twelfth transistor, the second end of the third capacitor, the drain of the ninth transistor, the gate of the thirteenth transistor, and the gate of the fourteenth transistor respectively, and the source of the twelfth transistor, the source of the thirteenth transistor, and the source of the fourteenth transistor are all grounded; the drain of the thirteenth transistor is electrically connected to the first input terminal of the second logic unit and the drain of the tenth transistor respectively, and the drain of the fourteenth transistor is electrically connected to the second input terminal of the second logic unit and the drain of the eleventh transistor respectively.

[0028] In a possible implementation, the second logic unit includes a third Schmitt trigger, a fourth Schmitt trigger, a fourth inverter, a fifth inverter, and a sixth inverter;

[0029] The input terminals of the third Schmitt trigger are electrically connected to the drain of the tenth transistor and the drain of the thirteenth transistor respectively, and the output terminal of the third Schmitt trigger is electrically connected to the input terminal of the fourth inverter; the input terminal of the fifth inverter is electrically connected to the output terminal of the fourth inverter, and the output terminal of the fifth inverter is electrically connected to the compensation unit; the input terminals of the fourth Schmitt trigger are electrically connected to the drain of the eleventh transistor and the drain of the fourteenth transistor respectively, and the output terminal of the fourth Schmitt trigger is electrically connected to the input terminal of the sixth inverter; the output terminal of the sixth inverter is electrically connected to the compensation unit.

[0030] In a possible implementation, the compensation unit includes an AND gate, a NAND gate, a seventh inverter, an eighth inverter, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, and a current source;

[0031] The input terminal of the NAND gate is used to receive the first logic signal and the third logic signal, and the output terminal of the NAND gate is electrically connected to the input terminal of the seventh inverter and the gate of the third switching transistor respectively; the input terminal of the AND gate is used to receive the second logic signal and the fourth logic signal, and the output terminal of the AND gate is electrically connected to the input terminal of the eighth inverter and the gate of the fifth switching transistor respectively; the source of the second switching transistor is electrically connected to the current source, and the drain of the second switching transistor is electrically connected to the drain of the fourth switching transistor and the first end of the compensation capacitor respectively; the source of the third switching transistor is electrically connected to the current source, and the drain of the third switching transistor is electrically connected to the drain of the fifth switching transistor and the second end of the compensation capacitor respectively; the sources of the fourth switching transistor and the fifth switching transistor are both electrically connected to the current source.

[0032] The beneficial effects of the embodiments of the present application compared with the prior art are as follows:

[0033] The direction detection unit is used to collect the first information on the change of the output voltage of the DC-DC converter, and to output a first logic signal and a second logic signal according to the first information, where the first information is used to reflect an increase or a decrease in the output voltage. The slope detection unit is used to collect the slope information on the change of the output voltage, and to output a third logic signal and a fourth logic signal according to the slope information, where the slope information is used to reflect the slope of the increase or the slope of the decrease in the output voltage. The compensation unit is used to provide a compensation current for the compensation capacitor when the compensation capacitor is charged or discharged according to the first logic signal, the second logic signal, the third logic signal, and the fourth logic signal, and the compensation capacitor is a capacitor connected to the output terminal of the error amplifier.

[0034] The transient enhancement circuit provided by the embodiments of the present application determines the intervention moment and the intervention duration by detecting the first information and the slope information of the output voltage change when the output voltage of the DC-DC converter changes suddenly, improves the accuracy of the intervention, and enables the output voltage to quickly return to stability. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 It is a structural block diagram of a transient enhancement circuit provided by an embodiment of the present application;

[0037] Figure 2 It is a schematic circuit connection diagram of a direction detection unit provided by an embodiment of the present application;

[0038] Figure 3 It is a schematic circuit connection diagram of a slope detection unit provided by an embodiment of the present application;

[0039] Figure 4 It is a schematic circuit connection diagram of a compensation unit provided by an embodiment of the present application;

[0040] Figure 5 It is a schematic circuit connection diagram of a transient enhancement circuit provided by an embodiment of the present application;

[0041] Figure 6 It is a timing diagram of a transient enhancement circuit provided by an embodiment of the present application. Detailed implementation manners

[0042] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system architectures, technologies, etc. are proposed to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0043] It should be understood that when used in the specification and the appended claims of the present application, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0044] It should also be understood that the term "and / or" used in the specification and the appended claims of the present application refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0045] As used in the specification and the appended claims of the present application, the term "if" can be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" according to the context. Similarly, the phrase "if determined" or "if [the described condition or event] is detected" can be interpreted as meaning "once determined" or "in response to determining" or "once [the described condition or event] is detected" or "in response to detecting [the described condition or event]" according to the context.

[0046] In addition, in the description of the specification and the appended claims of the present application, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0047] The reference to "one embodiment" or "some embodiments" etc. described in the specification of the present application means that a specific feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.

[0048] Figure 1 The structural block diagram of a transient enhancement circuit provided by an embodiment of the present application is shown. Refer to Figure 1 As shown, the transient enhancement circuit includes a direction detection unit 100, a slope detection unit 200, and a compensation unit 300.

[0049] Specifically, the input end of the direction detection unit 100 is electrically connected to the output end of the DC-DC converter. The first output end and the second output end of the direction detection unit 100 are respectively electrically connected to the two input ends of the compensation unit 300. The direction detection unit 100 is configured to collect the first information of the output voltage change of the DC-DC converter through the input end, and is configured to output a first logic signal and a second logic signal according to the first information of the output voltage. Among them, the first output end of the direction detection unit 100 outputs the first logic signal, and the second output end of the direction detection unit 100 outputs the second logic signal. The first information of the output voltage is used to reflect whether the output voltage increases or decreases. When the output voltage increases or decreases, the first logic signal and the second logic signal output by the direction detection unit 100 will change.

[0050] Exemplarily, when the output voltage is within a preset range, both the first logic signal and the second logic signal are low-level signals; when the output voltage increases beyond the first preset voltage, the first logic signal is a low-level signal and the second logic signal becomes a high-level signal; when the output voltage decreases below the second preset voltage, the first logic signal becomes a high-level signal and the second logic signal is a low-level signal. Through the above technical means, the direction detection unit 100 realizes the detection of the first information of the output voltage change.

[0051] The input end of the slope detection unit 200 is electrically connected to the output end of the DC-DC converter. The first output end and the second output end of the slope detection unit 200 are respectively electrically connected to the two input ends of the compensation unit 300. The slope detection unit 200 is configured to collect the slope information of the output voltage change of the DC-DC converter through the input end, and is configured to output a third logic signal and a fourth logic signal according to the slope information of the output voltage change. Among them, the third logic signal is output from the first output end of the slope detection unit, and the fourth logic signal is output from the second output end of the slope detection unit. The slope information of the output voltage change is used to reflect the slope of the output voltage increase or the slope of the output voltage decrease, and the slope information can characterize the speed of the output voltage change. When the slope of the output voltage increase or the slope of the output voltage decrease exceeds a preset value, the third logic signal and the fourth logic signal output by the slope detection unit 200 will change.

[0052] Exemplarily, when the slopes of the output voltage increase and decrease are within a preset range, both the third logic signal and the fourth logic signal are low-level signals; when the slope of the output voltage increase exceeds the first preset slope, the fourth logic signal becomes a high-level signal, and the third logic signal is a low-level signal; when the slope of the output voltage decrease is lower than the second preset slope, the fourth logic signal is a low-level signal, and the third logic signal becomes a high-level signal. Through the above technical means, the slope detection unit 200 realizes the detection of the slope information of the output voltage.

[0053] The compensation unit 300 includes four input ends, which are respectively connected to the two output ends of the direction detection unit 100 and the two output ends of the slope detection unit 200 in a corresponding manner. The output end of the compensation unit 300 is electrically connected to a compensation capacitor. Among them, the compensation capacitor is a capacitor connected to the output end of the error amplifier. The compensation unit 300 is configured to receive the first logic signal, the second logic signal, the third logic signal, and the fourth logic signal, and is configured to output a compensation signal according to the first logic signal, the second logic signal, the third logic signal, and the fourth logic signal. The compensation signal is used to provide a compensation current for the compensation capacitor when the compensation capacitor is charged or discharged, which can enable the output end of the error amplifier to quickly reach the corresponding voltage, and further enable the regulation unit to quickly regulate the output voltage of the DC-DC converter, so that the output voltage of the DC-DC converter quickly returns to stability.

[0054] The transient enhancement circuit provided by the embodiment of the present application can improve the accuracy of the transient enhancement circuit intervention by detecting the first information and the slope information of the output voltage, and can accelerate the speed of the output voltage regulation by outputting a compensation signal.

[0055] Figure 2 The circuit connection diagram of the direction detection unit 100 provided by an embodiment of the present application is shown. Refer to Figure 2As shown, the direction detection unit 100 includes a first bias current source I BIAS1 , a first mirror unit 102, a second mirror unit 101, and a first logic unit 103.

[0056] Specifically, the first bias current source I BIAS1 is used to provide a first static bias current.

[0057] The first mirror unit 102 is electrically connected to the first bias current source I BIAS1 . The first mirror unit 102 is configured to output a first current signal and a second current signal according to the first static bias current. Among them, the first current signal and the second current signal are equal, and the first static bias current may or may not be equal to the first current signal. Since the first static bias current is a fixed value, the first current signal and the second current signal are both fixed values.

[0058] The second mirror unit 101 is electrically connected to the output terminal of the DC-DC converter. The second mirror unit 101 is configured to receive the output voltage and output a third current signal and a fourth current signal according to the output voltage. Among them, when the output voltage changes, the third current signal and the fourth current signal also change.

[0059] The first logic unit 103 is electrically connected to the first mirror unit 102 and the second mirror unit 101 respectively. The first logic unit 103 is configured to output a first logic signal US according to the first current signal and the third current signal. The first logic unit 103 is further configured to output a second logic signal OS according to the second current signal and the fourth current signal.

[0060] Exemplarily, as Figure 2 shown, the second mirror unit 101 includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a first transistor M1, a second transistor M2, a third transistor M3, and a first switch tube Q1. The first end of the first resistor R1, the source electrode of the second transistor M2, and the first end of the third resistor R3 are all configured to receive the output voltage. The source electrode of the first transistor M1 is electrically connected to the second end of the first resistor R1. The drain electrode of the first transistor M1 is electrically connected to the gate of the first transistor M1, the first end of the second resistor R2, the drain electrode of the first switch tube Q1, and the second mirror unit 101 respectively. The gate of the second transistor M2 is electrically connected to the first end of the first capacitor C1, the second end of the second resistor R2, the source electrode of the first switch tube Q1, and the gate of the third transistor M3 respectively. The drain electrode of the second transistor M2 is electrically connected to the first input terminal of the first logic unit 103 and the second mirror unit 101 respectively. The drain electrode of the third transistor M3 is electrically connected to the second input terminal of the first logic unit 103 and the second mirror unit 101 respectively. The second end of the first capacitor C1 is grounded. The gate of the first switch tube Q1 is configured to receive a control signal SS_OK.

[0061] The second resistor R2 and the first capacitor C1 form a low-pass filter, which can filter out high-frequency impurity signals. The first transistor M1, the second transistor M2, and the third transistor M3 form a current mirror structure. The width-to-length ratios of the first transistor M1, the second transistor M2, and the third transistor M3 are equal, and the branch bias currents of the first transistor M1, the second transistor M2, and the third transistor M3 are the same. The resistance value of the first resistor R1 is greater than that of the third resistor R3. Preferably, the resistance value of the first resistor R1 is twice that of the third resistor R3. The voltage between the source and the gate of the second transistor M2 is greater than the voltage between the source and the gate of the first transistor M1, and the voltage between the source and the gate of the third transistor M3 is less than the voltage between the source and the gate of the first transistor M1. The drain current of the second transistor M2 is the first current signal, and the drain current of the third transistor M3 is the second current signal.

[0062] The first mirror unit 102 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The gate of the fourth transistor M4 is electrically connected to the drain of the fourth transistor M4, the first bias current source I BIAS1 , the gate of the fifth transistor M5, the gate of the sixth transistor M6, and the gate of the seventh transistor M7. The sources of the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all grounded. The drain of the fifth transistor M5 is electrically connected to the drain of the first transistor M1. The drain of the sixth transistor M6 is electrically connected to the drain of the second transistor M2 and the first input terminal unit of the first logic unit 103. The drain of the seventh transistor M7 is electrically connected to the drain of the third transistor M3 and the second input terminal of the first logic unit 103.

[0063] The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 form a current mirror structure. The drain current of the sixth transistor M6 is the third current signal, and the drain current of the seventh transistor M7 is the fourth current signal. The width-to-length ratios of the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are equal, and the width-to-length ratio of the fifth transistor M5 is m times that of the fourth transistor M4.

[0064] The first logic unit 103 includes a first Schmitt trigger X1, a second Schmitt trigger X2, a first inverter I1, a second inverter I2, and a third inverter I3. The input terminal of the first Schmitt trigger X1 is electrically connected to the drain of the sixth transistor M6 and the drain of the second transistor M2 respectively, and the output terminal of the first Schmitt trigger X1 is electrically connected to the input terminal of the first inverter I1. The input terminal of the second inverter I2 is electrically connected to the output terminal of the first inverter I1, and the output terminal of the second inverter I2 is electrically connected to the compensation unit 300. The input terminal of the second Schmitt trigger X2 is electrically connected to the drain of the third transistor M3 and the drain of the seventh transistor M7 respectively, and the output terminal of the second Schmitt trigger X2 is electrically connected to the input terminal of the third inverter I3. The output terminal of the third inverter I3 is electrically connected to the compensation unit 300.

[0065] Specifically, when the DC-DC converter is in the startup process, the control signal SS_OK controls the first switching transistor Q1 to be in the conducting state. At this time, the second resistor R2 is short-circuited, and the transient enhancement circuit does not work. When the DC-DC converter completes startup, the control signal SS_OK controls the first switching transistor Q1 to be in the off state. At this time, the transient enhancement circuit can work normally.

[0066] When the output voltage increases, the gate voltage of the first transistor M1 increases with the increase of the output voltage. Under the action of the second resistor R2 and the first capacitor C1, the gate voltages of the second transistor M2 and the third transistor M3 remain unchanged. The voltage between the gate and source of the second transistor M2 increases. At this time, the first logic signal US remains at a low level signal. The voltage between the gate and source of the third transistor M3 increases with the increase of the output voltage. When the output voltage increases beyond the first preset voltage, the current capacity of the second transistor M2 is greater than the bias current of the seventh transistor M7, and the potential at the input terminal of the second Schmitt trigger X2 becomes high level. After passing through the second Schmitt trigger X2 and the third inverter I3, the output second logic signal OS becomes a high level signal. When the output voltage decreases below the first preset voltage, the second logic signal OS becomes a low level signal.

[0067] When the output voltage decreases, the voltage between the gate and source of the second transistor M2 decreases. When the output voltage decreases below the second preset voltage, the sixth transistor M6 pulls down the drain potential, and the first logic signal US becomes a high level signal. When the output voltage increases beyond the second preset voltage, the first logic signal US becomes a low level signal. During this process, the second logic signal OS remains at a low level signal.

[0068] Figure 3 The circuit connection diagram of the slope detection unit 200 provided by an embodiment of the present application is shown. Refer to Figure 3As shown, the slope detection unit 200 includes a second bias current source, a third mirror unit 201, a fourth mirror unit 202, and a second logic unit 203.

[0069] Specifically, the second bias current source is used to provide a second static bias current.

[0070] The third mirror unit 201 is electrically connected to the second bias current source. The third mirror unit 201 is configured to output a fifth current signal and a sixth current signal according to the second static bias current. The fifth current signal and the sixth current signal are equal. The second static bias current may or may not be equal to the fifth current signal. Since the second static bias current is a fixed value, the fifth current signal and the sixth current signal are both fixed values.

[0071] The fourth mirror unit 202 is electrically connected to the output terminal of the DC-DC converter. The fourth mirror unit 202 is configured to receive the output voltage and output a seventh current signal and an eighth current signal according to the output voltage. Wherein, when the output voltage changes, the seventh current signal and the eighth current signal also change.

[0072] The second logic unit 203 is electrically connected to the third mirror unit 201 and the fourth mirror unit 202 respectively. The second logic unit 203 is configured to output a third logic signal TRAN_US according to the fifth current signal and the seventh current signal. The second logic unit 203 is further configured to output a fourth logic signal TRAN_OS according to the sixth current signal and the eighth current signal. For example, when the slope of the increasing output voltage and the slope of the decreasing output voltage are within a preset range, both the third logic signal TRAN_US and the fourth logic signal TRAN_OS are low-level signals; when the slope of the increasing output voltage exceeds a first preset slope, the third logic signal TRAN_US remains a low-level signal, and the fourth logic signal TRAN_OS becomes a high-level signal; when the slope of the decreasing output voltage is lower than a second preset slope, the third logic signal TRAN_US becomes a high-level signal, and the fourth logic signal TRAN_OS remains a low-level signal. Through the above technical means, the slope detection unit 200 realizes the detection of the slope information of the output voltage.

[0073] Exemplarily, such as Figure 3As shown, the third mirror unit 201 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The gate of the eighth transistor M8 is electrically connected to the drain of the eighth transistor M8, a second bias current source, the gate of the ninth transistor M9, the gate of the tenth transistor M10, and the gate of the eleventh transistor M11. The source of the eighth transistor M8, the source of the ninth transistor M9, the source of the tenth transistor M10, and the source of the eleventh transistor M11 are all electrically connected to a voltage source. The drain of the ninth transistor M9 is electrically connected to the fourth mirror unit 202, the drain of the tenth transistor M10 is electrically connected to the fourth mirror unit 202 and the first input terminal of the second logic unit 203, and the drain of the eleventh transistor M11 is electrically connected to the fourth mirror unit 202 and the second input terminal of the second logic unit 203.

[0074] The fourth mirror unit 202 includes a fourth resistor R4, a second capacitor C2, a third capacitor C3, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14. The first end of the fourth resistor R4 is used to receive an output voltage. The first end of the third capacitor C3 is electrically connected to the first end of the second capacitor C2 and the second end of the fourth resistor R4, and the second end of the second capacitor C2 is grounded. The gate of the twelfth transistor M12 is electrically connected to the drain of the twelfth transistor M12, the second end of the third capacitor C3, the drain of the ninth transistor M9, the gate of the thirteenth transistor M13, and the gate of the fourteenth transistor M14. The source of the twelfth transistor M12, the source of the thirteenth transistor M13, and the source of the fourteenth transistor M14 are all grounded. The drain of the thirteenth transistor M13 is electrically connected to the first input terminal of the second logic unit 203 and the drain of the tenth transistor M10, and the drain of the fourteenth transistor M14 is electrically connected to the second input terminal of the second logic unit 203 and the drain of the eleventh transistor M11.

[0075] The second logic unit 203 includes a third Schmitt trigger X3, a fourth Schmitt trigger X4, a fourth inverter I4, a fifth inverter I5, and a sixth inverter I6. The input terminal of the third Schmitt trigger X3 is electrically connected to the drain of the tenth transistor M10 and the drain of the thirteenth transistor M13, and the output terminal of the third Schmitt trigger X3 is electrically connected to the input terminal of the fourth inverter I4; the input terminal of the fifth inverter I5 is electrically connected to the output terminal of the fourth inverter I4, and the output terminal of the fifth inverter I5 is electrically connected to the compensation unit 300. The input terminal of the fourth Schmitt trigger X4 is electrically connected to the drain of the eleventh transistor M11 and the drain of the fourteenth transistor M14, and the output terminal of the fourth Schmitt trigger X4 is electrically connected to the input terminal of the sixth inverter I6; the output terminal of the sixth inverter I6 is electrically connected to the compensation unit 300.

[0076] Specifically, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 form a current mirror structure, and the aspect ratios of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are 1:2:3:1. The twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 form a current mirror structure, and the aspect ratios of the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are the same. The fourth resistor R4 and the second capacitor C2 form a low-pass filter to filter out the high-frequency components of the output voltage.

[0077] Assume that the current of the third capacitor C3 is I c , and the voltage between the gate and the source of the twelfth transistor M12 is V GS，M12 , V OUT is the output voltage, C3 is the capacitance value of the third capacitor C3, I BIAS2 is the second static bias current, (W / L) M12 is the aspect ratio of the twelfth transistor M12, μ n is the electron mobility, C OX is the gate oxide capacitance per unit area, then there is:

[0078]

[0079]

[0080] From the above formula, it can be obtained that the change in the voltage V GS，M12 between the gate and the source of the twelfth transistor M12 will affect the current I c of the third capacitor C3. Therefore, by selecting the twelfth transistor M12 with a larger aspect ratio, the voltage V GS，M12 will reduce the influence on the current I c of the third capacitor C3. Thus, the current I c of the third capacitor C3 is mainly affected by the output voltage V OUT . Then, simplifying the above formula (1) can obtain:

[0081]

[0082] When the current I c flowing into the third capacitor C3 is greater than the second static bias current I BIAS2 , it indicates that the slope of the output voltage increase is too large (greater than the first preset slope). At this time, the third logic signal TRAN_US maintains a low-level signal, and the fourth logic signal TRAN_OS becomes a high-level signal. When the current I c flowing into the third capacitor C3 is less than the second static bias current I BIAS2When the fourth logic signal TRAN_OS becomes a low-level signal, it indicates that the increase of the output voltage ends at this time.

[0083] When the current I flowing out of the third capacitor C3 c is greater than the second static bias current I BIAS2 it indicates that the decreasing slope of the output voltage is too large (lower than the second preset slope). At this time, the third logic signal TRAN_US becomes a high-level signal, and the fourth logic signal TRAN_OS remains a low-level signal. When the current I flowing out of the third capacitor C3 c is less than the second static bias current I BIAS2 the third logic signal TRAN_US becomes a low-level signal, indicating that the increase of the output voltage ends at this time.

[0084] By setting the parameters of the second static bias current I BIAS2 and the third capacitor C3, the change slopes of the corresponding output voltage when the transient enhancement circuit intervenes and exits can be adjusted.

[0085] Figure 4 FIG. shows a schematic circuit connection diagram of a compensation unit 300 provided in an embodiment of the present application. Refer to Figure 4 As shown, the compensation unit 300 includes an AND gate Z1, a NAND gate K1, a seventh inverter I7, an eighth inverter I8, a second switching transistor Q2, a third switching transistor Q3, a fourth switching transistor Q4, a fifth switching transistor Q5, and a current source ID. The input terminal of the NAND gate K1 is used to receive the first logic signal US and the third logic signal TRAN_US. The output terminal of the NAND gate K1 is electrically connected to the input terminal of the seventh inverter I7 and the gate of the third switching transistor Q3 respectively. The input terminal of the AND gate Z1 is used to receive the second logic signal OS and the fourth logic signal TRAN_OS. The output terminal of the AND gate Z1 is electrically connected to the input terminal of the eighth inverter I8 and the gate of the fifth switching transistor Q5 respectively. The source of the second switching transistor Q2 is electrically connected to the current source ID. The drain of the second switching transistor Q2 is electrically connected to the drain of the fourth switching transistor Q4 and the first end of the compensation capacitor Cc respectively. The source of the third switching transistor Q3 is electrically connected to the current source ID. The drain of the third switching transistor Q3 is electrically connected to the drain of the fifth switching transistor Q5 and the second end of the compensation capacitor Cc respectively. The sources of the fourth switching transistor Q4 and the fifth switching transistor Q5 are both electrically connected to the current source ID.

[0086] Specifically, when the output voltage increases beyond a first preset voltage, the second logic signal OS becomes a high-level signal; when the slope of the increase in the output voltage exceeds a first preset slope, the fourth logic signal TRAN_OS becomes a high-level signal. When the output voltage increases beyond the first preset voltage and the slope of the increase in the output voltage exceeds the first preset slope, the second logic signal OS becomes a high-level signal and the fourth logic signal TRAN_OS becomes a high-level signal. The AND gate Z1 outputs a high-level signal based on the second logic signal OS and the fourth logic signal TRAN_OS, driving the second switching transistor Q2 and the fifth switching transistor Q5 to conduct. The current source ID provides a compensation current to discharge the compensation capacitor Cc, accelerating the rate of decrease of the potential at the output terminal of the error amplifier, and thus accelerating the rate of decrease of the control voltage, causing the output voltage to decrease rapidly.

[0087] When the output voltage decreases below a second preset voltage, the first logic signal US becomes a high-level signal; when the slope of the decrease in the output voltage is lower than a second preset slope, the third logic signal TRAN_US becomes a high-level signal. When the output voltage decreases below the second preset voltage and the slope of the decrease in the output voltage is lower than the second preset slope, the first logic signal US becomes a high-level signal and the third logic signal TRAN_US becomes a high-level signal. The NAND gate K1 outputs a low-level signal based on the first logic signal US and the third logic signal TRAN_US, driving the third switching transistor Q3 and the fourth switching transistor Q4 to conduct. The current source ID provides a compensation current to charge the compensation capacitor Cc, accelerating the rate of increase of the potential at the output terminal of the error amplifier, and thus accelerating the rate of increase of the control voltage, causing the output voltage to increase rapidly.

[0088] To clearly illustrate the working principle of the transient enhancement circuit in the embodiments of the present application, the following is combined with Figure 5 and Figure 6 for illustration.

[0089] Before time t1, the output voltage is stable, and the first logic signal US, the second logic signal OS, the third logic signal TRAN_US, and the fourth logic signal TRAN_OS are all low-level signals, and the transient enhancement circuit does not operate.

[0090] At time t1 - t2, the output voltage exceeds the first preset voltage V OUT,OS_TH , and the slope of the increase in the output voltage exceeds the first preset slope. The second logic signal OS and the fourth logic signal TRAN_OS are high-level signals, the first logic signal US and the third logic signal TRAN_US are low-level signals, the drive signal EN_TRAN_OS is a high-level signal, the second switching transistor Q2 and the fifth switching transistor Q5 conduct, and the current source ID provides a compensation current to discharge the compensation capacitor Cc, accelerating the rate of decrease of the potential at the output terminal of the error amplifier, and thus accelerating the rate of decrease of the control voltage, causing the output voltage to decrease rapidly.

[0091] At time t2 - t3, the output voltage exceeds the first preset voltage V OUT,OS_TH , and the slope of the decreasing output voltage is lower than the second preset slope. The second logic signal OS and the third logic signal TRAN_US are high - level signals, the first logic signal US and the fourth logic signal TRAN_OS are low - level signals, and the transient enhancement circuit does not operate.

[0092] At time t4 - t5, the output voltage is lower than the second preset voltage V OUT,US_TH , and the slope of the decreasing output voltage is lower than the second preset slope. The first logic signal US and the third logic signal TRAN_US are high - level signals, the second logic signal OS and the fourth logic signal TRAN_OS are low - level signals, the drive signal EN_TRAN_US is a high - level signal, the third switch Q3 and the fourth switch Q4 are turned on, and the current source ID provides a compensation current to charge the compensation capacitor Cc, accelerating the rising speed of the potential at the output end of the error amplifier, and further accelerating the rising speed of the control voltage, so that the output voltage rises rapidly.

[0093] At time t5 - t6, the output voltage is lower than the second preset voltage V OUT,US_TH , and the slope of the increasing output voltage exceeds the first preset slope. The first logic signal US and the fourth logic signal TRAN_OS are high - level signals, the second logic signal OS and the third logic signal TRAN_US are high - level signals, and the transient enhancement circuit does not operate.

[0094] From the above analysis of the working state of the transient enhancement circuit, it can be seen that when the output voltage changes suddenly, the transient enhancement circuit can improve the accuracy of intervention and make the output voltage quickly return to stability.

[0095] The above - described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A transient enhancement circuit, characterized in that, it includes: A direction detection unit, configured to collect first information on the change in the output voltage of a DC-DC converter, and configured to output a first logic signal and a second logic signal according to the first information; wherein, the first information is used to reflect an increase or a decrease in the output voltage; A slope detection unit, configured to collect slope information on the change in the output voltage, and configured to output a third logic signal and a fourth logic signal according to the slope information; wherein, the slope information is used to reflect the slope of an increase or the slope of a decrease in the output voltage; and A compensation unit, configured to provide a compensation current for a compensation capacitor when the compensation capacitor is charged or discharged according to the first logic signal, the second logic signal, the third logic signal, and the fourth logic signal, and the compensation capacitor is a capacitor connected to the output end of an error amplifier; The direction detection unit includes: A first bias current source, configured to provide a first static bias current; A first mirror unit, configured to receive the first static bias current, and configured to output a first current signal and a second current signal according to the first static bias current; A second mirror unit, configured to receive the output voltage, and configured to output a third current signal and a fourth current signal according to the output voltage; and A first logic unit, configured to receive the first current signal, the second current signal, the third current signal, and the fourth current signal; when the output voltage increases beyond a first preset voltage, the first logic unit is configured to output the first logic signal according to the first current signal and the third current signal; when the output voltage decreases below a second preset voltage, the first logic unit is configured to output the second logic signal according to the second current signal and the fourth current signal.

2. The transient enhancement circuit according to claim 1, characterized in that, the second mirror unit includes a first resistor, a second resistor, a third resistor, a first capacitor, a first switching tube, a first transistor, a second transistor, and a third transistor; The first end of the first resistor, the source electrode of the second transistor, and the first end of the third resistor are all configured to receive the output voltage; the source electrode of the first transistor is electrically connected to the second end of the first resistor, and the drain electrode of the first transistor is respectively electrically connected to the gate electrode of the first transistor, the first end of the second resistor, the drain electrode of the first switching tube, and the second mirror unit; the gate electrode of the second transistor is respectively electrically connected to the first end of the first capacitor, the second end of the second resistor, the source electrode of the first switching tube, and the gate electrode of the third transistor, and the drain electrode of the second transistor is respectively electrically connected to the first input end of the first logic unit and the second mirror unit; the drain electrode of the third transistor is respectively electrically connected to the second input end of the first logic unit and the second mirror unit, the second end of the first capacitor is grounded, and the gate electrode of the first switching tube is configured to receive a control signal.

3. The transient enhancement circuit according to claim 2, characterized in that, The first mirror unit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate of the fourth transistor is electrically connected to the drain of the fourth transistor, the first bias current source, the gate of the fifth transistor, the gate of the sixth transistor, and the gate of the seventh transistor. The source of the fourth transistor, the source of the fifth transistor, the source of the sixth transistor, and the source of the seventh transistor are all grounded. The drain of the fifth transistor is electrically connected to the drain of the first transistor. The drain of the sixth transistor is electrically connected to the drain of the second transistor and the first input terminal unit of the first logic unit. The drain of the seventh transistor is electrically connected to the drain of the third transistor and the second input terminal of the first logic unit.

4. The transient enhancement circuit according to claim 3, wherein, The first logic unit includes a first Schmitt trigger, a second Schmitt trigger, a first inverter, a second inverter, and a third inverter; The input terminal of the first Schmitt trigger is electrically connected to the drain of the sixth transistor and the drain of the second transistor. The output terminal of the first Schmitt trigger is electrically connected to the input terminal of the first inverter. The input terminal of the second inverter is electrically connected to the output terminal of the first inverter. The output terminal of the second inverter is electrically connected to the compensation unit. The input terminal of the second Schmitt trigger is electrically connected to the drain of the third transistor and the drain of the seventh transistor. The output terminal of the second Schmitt trigger is electrically connected to the input terminal of the third inverter. The output terminal of the third inverter is electrically connected to the compensation unit.

5. The transient enhancement circuit according to claim 1, wherein, The slope detection unit includes: A second bias current source for providing a second static bias current; A third mirror unit for receiving the second static bias current and outputting a fifth current signal and a sixth current signal according to the second static bias current; A fourth mirror unit for receiving the output voltage and outputting a seventh current signal and an eighth current signal according to the output voltage; and A second logic unit for receiving the fifth current signal, the sixth current signal, the seventh current signal, and the eighth current signal. When the slope of the increasing output voltage exceeds a first preset slope, the second logic unit is configured to output the third logic signal according to the fifth current signal and the seventh current signal. When the slope of the decreasing output voltage is lower than a second preset slope, the second logic unit is configured to output the fourth logic signal according to the sixth current signal and the eighth current signal.

6. The transient enhancement circuit according to claim 5, wherein, The third mirror unit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The gate of the eighth transistor is electrically connected to the drain of the eighth transistor, the second bias current source, the gate of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor respectively; the source of the eighth transistor, the source of the ninth transistor, the source of the tenth transistor, and the source of the eleventh transistor are all electrically connected to a voltage source; the drain of the ninth transistor is electrically connected to the fourth mirror unit, the drain of the tenth transistor is electrically connected to the fourth mirror unit and the first input terminal of the second logic unit respectively, and the drain of the eleventh transistor is electrically connected to the fourth mirror unit and the second input terminal of the second logic unit respectively.

7. The transient enhancement circuit according to claim 6, wherein, the fourth mirror unit includes a fourth resistor, a second capacitor, a third capacitor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; the first end of the fourth resistor is used to receive the output voltage, the first end of the third capacitor is electrically connected to the first end of the second capacitor and the second end of the fourth resistor respectively, and the second end of the second capacitor is grounded; the gate of the twelfth transistor is electrically connected to the drain of the twelfth transistor, the second end of the third capacitor, the drain of the ninth transistor, the gate of the thirteenth transistor, and the gate of the fourteenth transistor respectively, and the source of the twelfth transistor, the source of the thirteenth transistor, and the source of the fourteenth transistor are all grounded; the drain of the thirteenth transistor is electrically connected to the first input terminal of the second logic unit and the drain of the tenth transistor respectively, and the drain of the fourteenth transistor is electrically connected to the second input terminal of the second logic unit and the drain of the eleventh transistor respectively.

8. The transient enhancement circuit according to claim 7, wherein, the second logic unit includes a third Schmitt trigger, a fourth Schmitt trigger, a fourth inverter, a fifth inverter, and a sixth inverter; the input terminals of the third Schmitt trigger are electrically connected to the drain of the tenth transistor and the drain of the thirteenth transistor respectively, and the output terminal of the third Schmitt trigger is electrically connected to the input terminal of the fourth inverter; the input terminal of the fifth inverter is electrically connected to the output terminal of the fourth inverter, and the output terminal of the fifth inverter is electrically connected to the compensation unit; the input terminals of the fourth Schmitt trigger are electrically connected to the drain of the eleventh transistor and the drain of the fourteenth transistor respectively, and the output terminal of the fourth Schmitt trigger is electrically connected to the input terminal of the sixth inverter; the output terminal of the sixth inverter is electrically connected to the compensation unit.

9. The transient enhancement circuit according to any one of claims 1 to 8, wherein, the compensation unit includes an AND gate, a NAND gate, a seventh inverter, an eighth inverter, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, and a current source; The input terminals of the NAND gate are used to receive the first logic signal and the third logic signal, and the output terminal of the NAND gate is electrically connected to the input terminal of the seventh inverter and the gate of the third switching transistor respectively; the input terminals of the AND gate are used to receive the second logic signal and the fourth logic signal, and the output terminal of the AND gate is electrically connected to the input terminal of the eighth inverter and the gate of the fifth switching transistor respectively; the source of the second switching transistor is electrically connected to the current source, and the drain of the second switching transistor is electrically connected to the drain of the fourth switching transistor and the first end of the compensation capacitor respectively; the source of the third switching transistor is electrically connected to the current source, and the drain of the third switching transistor is electrically connected to the drain of the fifth switching transistor and the second end of the compensation capacitor respectively; the sources of the fourth switching transistor and the fifth switching transistor are both electrically connected to the current source.

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