A superconducting quantum circuit and its preparation method, and a quantum computer

Abstract

The application discloses a superconducting quantum circuit and a preparation method thereof and a quantum computer, and belongs to the technical field of quantum computing. The superconducting quantum circuit comprises a first superconducting element, a second superconducting element and a superconducting quantum interference device formed on a substrate. The superconducting quantum interference device comprises a bottom electrode integrally connected with the second superconducting element, a barrier layer located on the bottom electrode and a top electrode electrically connected with the first superconducting element at one end, and the top electrode and the barrier layer form partial overlap to obtain a Josephson junction at the overlapping position. The structure of the superconducting quantum circuit provided by the application is convenient for preparation, and is helpful to shorten the process flow and improve the preparation efficiency.

Description

Technical Field

[0001] The present application belongs to the field of quantum information, especially the field of quantum computing technology. In particular, the present application relates to a superconducting quantum circuit and a preparation method thereof, and a quantum computer. Background Art

[0002] Quantum computing, a new computing method that combines quantum mechanics with computer science, performs calculations by following the laws of quantum mechanics and manipulating quantum information units. It uses qubits, composed of microscopic particles, as its basic unit and exhibits the properties of quantum superposition and entanglement. Furthermore, through the controlled evolution of quantum states, quantum computing enables information encoding and computational storage, offering enormous information capacity and superb parallel processing capabilities unmatched by classical computing techniques. As the number of qubits increases, computational storage capabilities will expand exponentially. This is currently one of the key development areas in the field of quantum information technology.

[0003] Internationally, physical systems being explored for quantum computing include ion traps, superconductors, ultracold atoms, polarized molecules, linear optics, diamond color centers, and electron or nuclear spins in silicon 28. In recent years, superconducting technology has attracted considerable attention from commercial companies for two reasons: first, the desire to leverage existing, highly advanced technologies, including semiconductor integrated circuit processes and techniques, to advance quantum computing; and second, the advantage of superconducting systems is their exceptional scalability.

[0004] Currently, the superconducting quantum circuit structures used in related technologies present numerous inconveniences in their fabrication. For example, in one superconducting quantum circuit structure, the superconducting quantum interference device (SQUID) and other superconducting elements are relatively independent, often requiring the fabrication of one structure before the other. For example, it is often necessary to first fabricate the superconducting element to be connected to the SQUID, then perform a process of oblique evaporation coating, oxidation, and then oblique evaporation coating to fabricate the SQUID connected to the superconducting element, and finally form the structure electrically connecting the two. This lengthy process significantly hinders shortening fabrication cycles and improving process efficiency.

[0005] There is an urgent need to propose a new superconducting quantum circuit structure to facilitate efficient process preparation. Invention content

[0006] In response to the deficiencies in the prior art, the present application provides a superconducting quantum circuit and a method for preparing the same, as well as a quantum computer, which can be prepared efficiently.

[0007] One embodiment of the present application provides a superconducting quantum circuit, comprising a first superconducting element, a second superconducting element, and a superconducting quantum interference device between the first superconducting element and the second superconducting element, wherein the superconducting quantum interference device comprises:

[0008] a bottom electrode integrally connected with the second superconducting element;

[0009] a barrier layer on the bottom electrode; and

[0010] a top electrode electrically connected with the first superconducting element, and the top electrode partially overlaps with the barrier layer to form a Josephson junction at the overlapping part.

[0011] Optionally, the first superconducting element is a ground layer, and the second superconducting element is a capacitor plate having a capacitive effect relative to the ground layer. Illustratively, the capacitor plate comprises at least two sub-capacitor plates, and one of the at least two sub-capacitor plates is integrally connected with the bottom electrode.

[0012] Optionally, a ground layer is formed on the substrate, and the first superconducting element and the second superconducting element are both capacitor plates having a capacitive effect relative to the ground layer. Illustratively, the capacitor plates both comprise at least two sub-capacitor plates, and one of the at least two sub-capacitor plates is integrally connected with the bottom electrode or the top electrode.

[0013] Optionally, the at least two sub-capacitor plates are separated from each other.

[0014] Optionally, the superconducting quantum interference device comprises at least two top electrodes.

[0015] Optionally, the at least two top electrodes are parallel to each other or not parallel to each other.

[0016] Optionally, the Josephson junction is a tunnel junction or other structure exhibiting Josephson effect.

[0017] Optionally, the superconducting quantum circuit further comprises a third superconducting element, and the third superconducting element is on the same surface as the first superconducting element and the second superconducting element.

[0018] Optionally, the third superconducting element is at least one of a read resonant cavity, a pulse control line, a magnetic flux modulation signal line, and a read signal line.

[0019] A second embodiment of the present application provides a method for fabricating a superconducting quantum circuit, the superconducting quantum circuit comprising a first superconducting element and a second superconducting element formed on a substrate, and a superconducting quantum interference device located between the first superconducting element and the second superconducting element. The fabrication method comprises:

[0020] patterning a superconducting material layer formed on a substrate to obtain the first superconducting element, the second superconducting element, and a first electrode integrally connected to the second superconducting element;

[0021] oxidizing the surface of the first electrode to obtain a bottom electrode and a barrier layer located on the bottom electrode; and

[0022] A top electrode is formed, one end of which is electrically connected to the first superconducting element, and the top electrode partially overlaps with the barrier layer to obtain a Josephson junction at the overlap.

[0023] Optionally, the step of patterning the superconducting material layer formed on the substrate to obtain the first superconducting element, the second superconducting element, and the first electrode integrally connected to the second superconducting element includes:

[0024] forming a mask layer having a resist pattern on the superconducting material layer, wherein the resist pattern includes a first resist pattern for defining the first superconducting element, a second resist pattern for defining the second superconducting element, and a third resist pattern for defining the first electrode, wherein the third resist pattern is connected to the second resist pattern;

[0025] The superconducting material layer not covered by the resist pattern is etched to obtain the first superconducting element, the second superconducting element and the first electrode, wherein the first electrode is integrally connected to the second superconducting element.

[0026] Optionally, the step of forming a top electrode having one end electrically connected to the first superconducting element, wherein the top electrode partially overlaps with the barrier layer, includes:

[0027] forming a mask layer having deposition windows on the superconducting material layer, wherein the deposition windows include a first window for limiting the deposited superconducting material to form the top electrode, and the first window exposes a portion of the first superconducting element and a portion of the barrier layer;

[0028] A superconducting material is deposited and the mask layer is peeled off to obtain a top electrode having one end electrically connected to the first superconducting element, wherein the top electrode partially overlaps with the barrier layer.

[0029] A third embodiment of the present application provides a quantum computer, comprising the superconducting quantum circuit, or comprising a superconducting quantum circuit prepared by the preparation method.

[0030] Compared with the prior art, the superconducting quantum circuit provided by the present application includes a first superconducting element and a second superconducting element formed on a substrate, and a superconducting quantum interference device located between the first superconducting element and the second superconducting element, and the superconducting quantum interference device includes: a bottom electrode integrally connected to the second superconducting element; a barrier layer located on the bottom electrode; and a top electrode electrically connected to the first superconducting element at one end, and the top electrode and the barrier layer partially overlap to obtain a Josephson junction at the overlap. Integrated connection of Bottom electrode and the second superconducting element Only one patterning process is required for preparation. After a barrier layer is formed on the surface of the bottom electrode, an evaporation coating process or the like is then performed to obtain a top electrode that partially overlaps with the barrier layer and is electrically connected to the first superconducting element at one end. Compared with the problems of lengthy preparation steps, long preparation cycles, and low process efficiency caused by the relatively independent structural form of the superconducting quantum interference device and other superconducting elements in the prior art, the structure of the superconducting quantum circuit provided in the present application is easy to prepare, helps shorten the process flow, and improves preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of the structure of quantum bits on a superconducting quantum chip in related technologies;

[0032] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D A schematic diagram of the preparation process of a superconducting quantum circuit provided in this application;

[0033] Figure 3A This is a schematic diagram of the structure of the first superconducting quantum circuit provided by this application;

[0034] Figure 3B A schematic diagram of the structure of the second superconducting quantum circuit provided in this application;

[0035] Figure 3C A schematic diagram of the structure of the second superconducting quantum circuit provided in this application;

[0036] Figure 4 This is a flow chart of a method for preparing a superconducting quantum circuit provided in this application.

[0037] Description of reference numerals:

[0038] 1-substrate, 2-superconducting material layer;

[0039] 21 - ground layer, 22 - capacitor plate, 221 - first sub-capacitor plate, 222 - second sub-capacitor plate, 223 - third sub-capacitor plate, 23 - electrical connection portion, 24 - first electrode, 241 - bottom electrode, 242 - barrier layer, 25 - first region, 26 - second region, 27 - third region, 28 - fourth region, 291 - first capacitor plate, 292 - second capacitor plate;

[0040] 31 - top electrode, 32 - pulse signal line, 33 - flux modulation signal line, 34 - reading resonant cavity, 35 - coupling structure. DETAILED DESCRIPTION

[0041] The following detailed description is illustrative only and is not intended to limit the application or uses of the embodiments and / or embodiments. In addition, there is no intention to be bound by any express or implied information presented in the previous "Background Technology" or "Summary of the Invention" section or "Detailed Description of the Invention" section.

[0042] To make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it is obvious that in various cases, one or more embodiments can be practiced without these specific details, and the various embodiments can be combined and referenced with each other without contradiction.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] In addition, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. In addition, references to being "on" and "under" various layers can be made based on the accompanying drawings.

[0045] Depending on the different physical systems used to construct quantum bits, the physical implementation methods of quantum bits include superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quantum, photons, etc.

[0046] Superconducting quantum computing is currently the fastest-growing and most advanced approach to implementing solid-state quantum computing. Because the energy level structure of superconducting quantum circuits can be controlled by external electromagnetic signals, the circuits' design and customization are highly controllable. Furthermore, thanks to the mature technology of existing integrated circuits, superconducting quantum circuits possess scalability unmatched by most quantum physics systems. Currently, the structure of qubits in superconducting quantum computing often utilizes a single grounded capacitor and a superconducting quantum interference device (SQUID) with one end grounded and the other connected to the capacitor. This capacitor is often a cross-shaped parallel plate capacitor.

[0047] Figure 1 This is a schematic diagram of the structure of quantum bits on a superconducting quantum chip in related technology.

[0048] See also Figure 1 As shown, the capacitor plate C q is surrounded by a ground plane (GND), and the capacitor plate C q There is a gap between the ground plane (GND) and one end of the superconducting quantum interference device Squid is connected to the capacitor plate C q , and the other end is connected to the ground plane (GND). Capacitor plate C q The first end is usually used to connect to the superconducting quantum interference device Squid, and the second end is used to couple with the reading resonant cavity. A certain amount of space needs to be reserved near the first and second ends for wiring. For example, space needs to be reserved near the first end for arranging the pulse control line (also known as the XY signal line) and the flux modulation signal line (also known as the Z signal line). The cross-shaped capacitor plate C q The other two ends are used to couple with adjacent qubits. In this type of superconducting quantum circuit, the superconducting quantum interference device and other superconducting elements are relatively independent, which often requires the preparation of one of the two structures first and then the other when preparing the superconducting quantum circuit. This brings many inconveniences to the preparation of the superconducting quantum circuit. For example, it is often necessary to first prepare the capacitor plate C to be connected to the superconducting quantum interference device Squid. q (or other superconducting components), and then the process of oblique evaporation coating-oxidation-oblique evaporation coating is carried out to prepare the capacitor plate C q The connected superconducting quantum interference device Squid is finally formed into a structure in which the two are electrically connected. This process is lengthy and has brought great obstacles to shortening the preparation cycle and improving process efficiency.

[0049] To this end, the present application provides a superconducting quantum circuit and its preparation method, and a quantum computer to solve the deficiencies in the prior art. Integrated connection of The bottom electrode and the second superconducting element are During the process preparation, it can be prepared simultaneously through a single patterning process. After a barrier layer is formed on the surface of the obtained bottom electrode, an evaporation coating process or the like is performed to obtain a top electrode that partially overlaps with the barrier layer and is electrically connected to the first superconducting element at one end. Compared with the problems of lengthy preparation steps, long preparation cycles, and low process efficiency caused by the relatively independent structural forms of superconducting quantum interference devices and other superconducting elements in the prior art, the solution provided in this application helps to shorten the preparation process flow of superconducting quantum circuits and achieve more efficient process preparation.

[0050] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D This is a schematic diagram of the preparation process of a superconducting quantum circuit provided by this application, wherein: Figure 2D To better illustrate the structure of a superconducting quantum circuit provided by the present application, M, N, and P are schematically enlarged in the accompanying drawings of the present application for ease of understanding and comparison.

[0051] See also Figure 2D As shown, combined with Figure 2A 、 Figure 2B and Figure 2C As shown, the present application provides a superconducting quantum circuit, which includes a first superconducting element and a second superconducting element formed on a substrate 1, and a superconducting quantum interference device located between the first superconducting element and the second superconducting element, wherein the superconducting quantum interference device includes:

[0052] a bottom electrode 241 integrally connected to the second superconducting element;

[0053] a barrier layer 242 located on the bottom electrode 241; and

[0054] A top electrode 31 is electrically connected to the first superconducting element at one end, and the top electrode 31 partially overlaps with the barrier layer 242 to form a Josephson junction at the overlap, wherein the Josephson junction is a tunnel junction or other structure exhibiting the Josephson effect.

[0055] Compared with the prior art, the superconducting quantum interference device in the superconducting quantum circuit provided by this application Bottom electrode 241 Integrally connected to the second superconducting element , The bottom electrode 241 and the second superconducting element are connected integrally It is easy to prepare through a single patterning process, and this form The bottom electrode 241 has good electrical connection with the second superconducting element. Connection performanceAfter forming the barrier layer 242 on the surface of the bottom electrode 241, a process such as evaporation coating is performed to obtain a top electrode 31 that partially overlaps with the barrier layer 242 and is electrically connected to the first superconducting element at one end. Compared with the superconducting quantum interference device and other superconducting elements (for example, the attached superconducting quantum circuit) used in the related art, Figure 1 The capacitor plate C shown in q ) The relatively independent structure requires a process of first etching to obtain a superconducting element, then performing oblique evaporation coating-oxidation-oblique evaporation coating to obtain a superconducting quantum interference device, and finally forming a structure electrically connecting the superconducting element and the superconducting quantum interference device. The structure of the superconducting quantum circuit provided in this application is easy to prepare, and helps to shorten the process flow and improve preparation efficiency.

[0056] Exemplarily, the bottom electrode 241 and the second superconducting element may be directly connected, or may be integrally connected via an electrical connection portion 23 formed simultaneously with the second superconducting element and the bottom electrode 241 .

[0057] In some embodiments of this application, see Figure 2D As shown, combined with Figure 2A 、 Figure 2B and Figure 2C As shown, the first superconducting element is a ground layer 21, and the second superconducting element is a capacitor plate 22 having a capacitive effect relative to the ground layer 21. The capacitor plate 22 is not directly connected to the ground layer 21, but has a suitable gap with the ground layer 21. The physical size of the gap is designed and determined according to the performance parameters of the quantum computing circuit. It should be noted that a capacitor C is formed between the capacitor plate 21 and the ground layer 21, thereby forming a circuit structure of a quantum bit in the form of a single superconducting island, namely: ground plane (GND)-superconducting quantum interference device-capacitor plate. In this embodiment, the capacitor plate 22 is surrounded by the ground layer 21 and is separated from the ground layer 21 by a gap that exposes the surface of the substrate 1. The substrate 1 can be a dielectric substrate such as silicon or sapphire. Exemplarily, the ground layer 21, the capacitor plate 22, and the superconducting quantum interference device are formed on a silicon substrate. The capacitor plate 22 and the ground layer 21 can be formed of a superconducting material that exhibits superconducting properties at a temperature equal to or lower than a critical temperature, such as aluminum, niobium or titanium nitride, etc. In specific implementation, it is not limited to these materials. Any material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature can be used to form the ground layer 21, the capacitor plate 22 and other structures.

[0058] Figure 3A This is a schematic structural diagram of the first superconducting quantum circuit provided in this application.

[0059] As an example, see Figure 3AAs shown, and contrasting combination Figures 2A to 2D As shown, the capacitor plate 22 includes at least two sub-capacitor plates, and one of the at least two sub-capacitor plates is integrally connected to the bottom electrode 241. In this embodiment, the capacitor plate 22 is divided into a first sub-capacitor plate 221, a second sub-capacitor plate 222 and a third sub-capacitor plate 223 to form multiple capacitance effects, and the first sub-capacitor plate 221 connected to the bottom electrode 241 adopts a structure integrally formed with the bottom electrode 241. In the structure of the thin film limit, the contribution of thickness to the capacitance effect can be ignored. The capacitor plate 22 in the qubit structure is divided and arranged into multiple sub-capacitor plates, so that the capacitance size in the qubit changes with the change of the area of ​​the sub-capacitor plate and the change of the number of sub-capacitor plates. The change in the capacitance in the qubit then affects the resonant frequency of the qubit. Due to the need to couple with pulse control lines, flux modulation signal lines, read resonant cavities or other circuit structures or to avoid crosstalk, when the area covered by the capacitor plate 22 on the substrate 1 is limited, the capacitance value of the quantum bit can be reduced by dividing the capacitor plate 22. For example, when the capacitor plate 22 is divided into multiple independent sub-capacitor plates, it corresponds to multiple capacitors connected in series, and the capacitance size of the quantum bit is determined by these capacitors connected in series.

[0060] The superconducting quantum circuit provided in the present application is not limited to the embodiment in which the first superconducting element is the ground layer 21 and the second superconducting element is the capacitor plate 22 having a capacitive effect relative to the ground layer 21. Some other embodiments of the superconducting quantum circuit provided in the present application are described below with reference to the accompanying drawings.

[0061] Figure 3B This is a schematic diagram of the structure of the second superconducting quantum circuit provided in this application.

[0062] In other embodiments of the present application, see Figure 3B As shown, and contrasting combination Figures 2A to 2D As shown, a grounding layer 21 is formed on the substrate 1, and the first superconducting element and the second superconducting element are both capacitor plates 22 with a capacitive effect relative to the grounding layer 21. Figure 3B As shown, the first superconducting element is a first capacitor plate 291 having a capacitive effect relative to the ground layer 21, and the second superconducting element is a second capacitor plate 292 having a capacitive effect relative to the ground layer 21, thereby forming a circuit structure having two quantum bits in the form of superconducting islands, namely: capacitor plate-superconducting quantum interference device-capacitor plate.

[0063] Figure 3C This is a schematic diagram of the structure of the third superconducting quantum circuit provided in this application.

[0064] As an example, see Figure 3CAs shown, and contrasting combination Figures 2A to 2D As shown, the first capacitor plate 291 and the second capacitor plate 292 each include at least two sub-capacitor plates, and one of the at least two sub-capacitor plates is integrally connected to the bottom electrode 241 or the top electrode 31. Schematically, for distinction, see Figure 3C As shown, the second capacitor plate 292 is divided into multiple sub-capacitor plates to form multiple capacitance effects. Similarly, the first capacitor plate 291 can also be divided into multiple sub-capacitor plates (not shown in the figure). The sub-capacitor plate connected to the top electrode 31 adopts a structure integrally formed with the top electrode 31, and the sub-capacitor plate connected to the bottom electrode 241 adopts a structure integrally formed with the bottom electrode 241.

[0065] It should be noted that the at least two sub-capacitor plates forming the same capacitor plate may be separated from each other or may be electrically connected to each other.

[0066] In some embodiments of the present application, the superconducting quantum interference device includes at least two top electrodes 31. Different numbers of top electrodes 31 result in different numbers of Josephson junctions included in the superconducting quantum interference device. By adjusting the number of top electrodes 31, superconducting quantum interference devices with different structural forms and different magnetic flux sensitivities can be prepared. The at least two top electrodes 31 can be parallel or non-parallel to each other. Exemplarily, at least two of the top electrodes 31 form at least two partial overlaps with the barrier layer 242, and the overlapping areas are different from each other. The different overlapping areas result in different critical currents of the formed Josephson junctions, thereby obtaining a superconducting quantum interference device including an asymmetric Josephson junction, thereby making the spectrum of the superconducting quantum circuit have at least two magnetic flux insensitive points. Exemplarily, the number of top electrodes 31 included in the superconducting quantum interference device is an odd number, and the overlapping areas of each top electrode 31 and the barrier layer 242 are the same. This structural form can also make the spectrum of the superconducting quantum circuit have at least two magnetic flux insensitive points.

[0067] In some embodiments of the present application, the superconducting quantum circuit further includes a third superconducting element fabricated simultaneously with the first superconducting element. The third superconducting element is located on the same surface as the first superconducting element and the second superconducting element, that is, all are located on the surface of the substrate 1. Exemplarily, the third superconducting element is at least one of the read resonant cavity 34, the pulse control line 32, the flux modulation signal line 33, and the read signal line.

[0068] Figure 4 This is a flow chart of a method for preparing a superconducting quantum circuit provided in this application.

[0069] See also Figure 4 , and combined with Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D As shown, in an embodiment of the present application, a method for preparing a superconducting quantum circuit is further provided. The superconducting quantum circuit includes a first superconducting element and a second superconducting element formed on a substrate 1, and a superconducting quantum interference device located between the first superconducting element and the second superconducting element. The preparation method includes steps S301 to S303, wherein:

[0070] Step S401: In this step, a patterning process is performed on the superconducting material layer 2 formed on the substrate 1, that is, the superconducting material layer 2 formed on the substrate 1 is patterned to obtain the first superconducting element, the second superconducting element, and the first electrode 24 integrally connected to the second superconducting element.

[0071] Step S402: Oxidize the surface of the first electrode 24 to obtain a bottom electrode 241 and a barrier layer 242 located on the bottom electrode 241. It can be understood that in this step, the unoxidized portion of the first electrode 24 forms the bottom electrode 241, and the oxide layer generated by surface oxidation forms the barrier layer 242. It should be noted that in this step, a mask can be formed using photoresist or the like to cover areas where oxidation is not desired to occur, so as to avoid oxidation of structures such as the first superconducting element and the second superconducting element.

[0072] Step S403 : forming a top electrode 31 , one end of which is electrically connected to the first superconducting element, and partially overlapping the top electrode 31 and the barrier layer 242 to obtain a Josephson junction at the overlapping portion.

[0073] The method for preparing a superconducting quantum circuit provided by the present application firstly prepares a first superconducting element, a second superconducting element and a first electrode simultaneously through a graphic process, and the first The electrode is integrally connected to the second superconducting element After the surface of the first electrode is oxidized to form a bottom electrode and a barrier layer, an evaporation coating process is performed again to obtain a top electrode that partially overlaps with the barrier layer and has one end electrically connected to the first superconducting element. Compared with the prior art method of first etching to obtain a superconducting element, then performing an oblique evaporation coating-oxidation-oblique evaporation coating process to obtain a superconducting quantum interference device, and finally forming a structure in which the two are electrically connected, the present application shortens the process flow and improves the preparation efficiency.

[0074] It should be emphasized that the method for preparing a superconducting quantum circuit provided in the present application does not require the angle of the evaporation coating during the preparation of the Josephson junction. In specific implementation, an oblique evaporation method or a perpendicular evaporation method relative to the surface to be evaporated can be used; and in the preparation process of the superconducting quantum circuit, multiple Josephson junctions or multiple superconducting quantum circuits provided in this embodiment can be prepared simultaneously, and the bottom electrodes of the multiple Josephson junctions and the top electrodes of the multiple Josephson junctions are not limited to parallel structures.

[0075] In some embodiments of the present application, step S401, patterning the superconducting material layer 2 formed on the substrate 1 to obtain the first superconducting element, the second superconducting element, and an implementation of the first electrode 24 integrally connected to the second superconducting element, specifically includes steps S3011 to S3012, wherein:

[0076] Step S4011: Form a mask layer having a resist pattern on the superconducting material layer 2, wherein the resist pattern includes a first resist pattern for defining the first superconducting element, a second resist pattern for defining the second superconducting element, and a third resist pattern for defining the first electrode 24, wherein the third resist pattern is connected to the second resist pattern. Exemplarily, the step of forming the mask layer having the resist pattern includes: first coating a photoresist on the superconducting material layer 2 to form a photoresist layer, and then performing processes such as exposure and development on the photoresist layer. The pattern formed by the photoresist layer not dissolved by the developer is the resist pattern, and the portion dissolved by the developer is the etched pattern. The etched pattern exposes the area to be etched on the superconducting material layer 2. It is understood that the first resist pattern is consistent with the shape of the first superconducting element to be obtained, the second resist pattern is consistent with the shape of the second superconducting element to be obtained, and the third resist pattern is consistent with the shape of the first electrode 24 to be obtained.

[0077] Step S4012: Etch the superconducting material layer 2 not covered by the resist pattern, and obtain the first superconducting element, the second superconducting element and the first electrode 24 through the protection and limitation of the first resist pattern, the second resist pattern and the third resist pattern, and the first electrode 24 is integrally connected to the second superconducting element.

[0078] In some embodiments of the present application, step S303, forming a top electrode 31 having one end electrically connected to the first superconducting element, wherein the top electrode 31 partially overlaps with the barrier layer 242 to obtain a Josephson junction at the overlap, specifically includes steps S3031 to S3032, wherein:

[0079] Step S4031: forming a mask layer having a deposition window on the superconducting material layer 2, wherein the deposition window includes a first window for limiting the deposited superconducting material to form the top electrode 31, and the first window exposes a portion of the first superconducting element and a portion of the barrier layer 242;

[0080] Step S4032 : depositing superconducting material by vertical evaporation coating process, peeling off the mask layer to obtain a top electrode 31 having one end electrically connected to the first superconducting element, and the top electrode 31 partially overlaps with the barrier layer 242 .

[0081] When the superconducting material layer 2 formed on the substrate 1 is patterned, a first region 25 for preparing a resonant cavity, a second region 26 for preparing a pulse signal line, a third region 27 for preparing a flux modulation signal line, and a fourth region 28 for preparing a coupling structure between adjacent bits can be obtained synchronously by etching; and when forming the top electrode 31, a deposition coating (which can be in the form of vertical evaporation coating) can also be used to synchronously obtain a resonant cavity 34, a pulse signal line 32, a flux modulation signal line 33 and a coupling structure 35 on the first region 25, the second region 26, the third region 27 and the fourth region 28 respectively. It should be noted that the coupling structure can be a capacitive coupling structure or a resonant cavity coupling structure, and is not limited to this in specific implementation. In some embodiments, when the superconducting material layer 2 formed on the substrate 1 is patterned, the resonant cavity 34, the pulse signal line 32, the flux modulation signal line 33 and the coupling structure 35 can also be obtained synchronously with the first superconducting element and the second superconducting element by etching.

[0082] In an embodiment of the present application, a quantum computer is further provided, comprising the superconducting quantum circuit in the embodiment of the present application, or comprising the superconducting quantum circuit prepared by the preparation method in the embodiment of the present application.

[0083] It should be noted that the superconducting quantum circuit in the aforementioned quantum computer is similar to the aforementioned structure and has the same beneficial effects as the aforementioned superconducting quantum circuit embodiment, so a detailed description thereof will not be given here. For technical details not disclosed in the quantum computer embodiment of this application, those skilled in the art are referred to the description of the aforementioned superconducting quantum circuit for understanding, and to save space, a detailed description thereof will not be given here.

[0084] A method for preparing a superconducting quantum circuit provided in an embodiment of the present application may require the deposition of one or more materials, such as superconductors, dielectrics and / or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering) or epitaxial techniques and other deposition processes. A method for preparing a superconducting quantum circuit described in an embodiment of the present application may require the removal of one or more materials from the device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching technology, dry etching technology or lift-off process. Known exposure (lithographic) techniques (e.g., photolithography or electron beam exposure) can be used to pattern the material forming the circuit elements described herein.

[0085] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the scope of protection of the present application.

Claims

1. A superconducting quantum circuit, characterized in that: The superconducting quantum circuit includes a first superconducting element and a second superconducting element formed on a substrate, and a superconducting quantum interference device located between the first superconducting element and the second superconducting element, wherein the superconducting quantum interference device includes: a bottom electrode integrally connected to the second superconducting element; a barrier layer located on the bottom electrode; and a top electrode having one end electrically connected to the first superconducting element, wherein the top electrode partially overlaps with the barrier layer to form a Josephson junction at the overlap; A grounding layer is formed on the substrate, the second superconducting element is a capacitor plate having a capacitance effect relative to the grounding layer, the capacitor plate includes at least two sub-capacitor plates, and the at least two sub-capacitor plates are separated from each other.

2. The superconducting quantum circuit according to claim 1, characterized in that The first superconducting element is the ground layer.

3. The superconducting quantum circuit according to claim 1, characterized in that One of the at least two sub-capacitor plates is integrally connected to the bottom electrode.

4. The superconducting quantum circuit according to claim 1, characterized in that The first superconducting element is a capacitor plate having a capacitive effect relative to the ground layer.

5. The superconducting quantum circuit according to claim 4, characterized in that Each of the capacitor plates includes at least two sub-capacitor plates, and one of the at least two sub-capacitor plates is integrally connected to the bottom electrode or integrally connected to the top electrode.

6. The superconducting quantum circuit according to claim 1, characterized in that The superconducting quantum interference device includes at least two top electrodes.

7. The superconducting quantum circuit according to claim 6, characterized in that The at least two top electrodes are parallel or non-parallel to each other.

8. The superconducting quantum circuit according to any one of claims 1 to 5 and 6 to 7, characterized in that: The Josephson junction is a tunnel junction or other structures exhibiting the Josephson effect.

9. The superconducting quantum circuit according to any one of claims 1 to 5 and 6 to 7, characterized in that: The superconducting quantum circuit further includes a third superconducting element, which is located on the same surface as the first superconducting element and the second superconducting element.

10. The superconducting quantum circuit according to claim 9, characterized in that: The third superconducting element is at least one of a read resonant cavity, a pulse control line, a flux modulation signal line, and a read signal line.

11. A method for preparing a superconducting quantum circuit, characterized in that: The superconducting quantum circuit includes a first superconducting element and a second superconducting element formed on a substrate, and a superconducting quantum interference device located between the first superconducting element and the second superconducting element, wherein a ground layer is formed on the substrate, the second superconducting element is a capacitor plate having a capacitive effect relative to the ground layer, the capacitor plate includes at least two sub-capacitor plates, and the at least two sub-capacitor plates are separated from each other. The preparation method includes: patterning a superconducting material layer formed on a substrate to obtain the first superconducting element, the second superconducting element, and a first electrode integrally connected to the second superconducting element; oxidizing the surface of the first electrode to obtain a bottom electrode and a barrier layer located on the bottom electrode; and A top electrode is formed, one end of which is electrically connected to the first superconducting element, and the top electrode partially overlaps with the barrier layer to obtain a Josephson junction at the overlap.

12. The preparation method according to claim 11, characterized in that The step of patterning the superconducting material layer formed on the substrate to obtain the first superconducting element, the second superconducting element, and the first electrode integrally connected to the second superconducting element comprises: forming a mask layer having a resist pattern on the superconducting material layer, wherein the resist pattern includes a first resist pattern for defining the first superconducting element, a second resist pattern for defining the second superconducting element, and a third resist pattern for defining the first electrode, wherein the third resist pattern is connected to the second resist pattern; The superconducting material layer not covered by the resist pattern is etched to obtain the first superconducting element, the second superconducting element and the first electrode, wherein the first electrode is integrally connected to the second superconducting element.

13. The preparation method according to claim 11, characterized in that The step of forming a top electrode having one end electrically connected to the first superconducting element, wherein the top electrode partially overlaps with the barrier layer, comprises: forming a mask layer having deposition windows on the superconducting material layer, wherein the deposition windows include a first window for limiting the deposited superconducting material to form the top electrode, and the first window exposes a portion of the first superconducting element and a portion of the barrier layer; A superconducting material is deposited and the mask layer is peeled off to obtain a top electrode having one end electrically connected to the first superconducting element, wherein the top electrode partially overlaps with the barrier layer.

14. A quantum computer, characterized in that The invention comprises the superconducting quantum circuit according to any one of claims 1 to 10, or comprises a superconducting quantum circuit prepared by the preparation method according to any one of claims 11 to 13.

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