Display device

Abstract

A display device capable of suppressing breakage caused by constituent members is provided. A display device according to an embodiment includes: a substrate; a plurality of pixels each including a plurality of light emitting elements, the plurality of light emitting elements being disposed on the substrate and having mutually different light emitting colors; a resin layer filling a gap portion between the plurality of light emitting elements provided in each of the pixels; and a common electrode formed of a transparent conductive material covering the resin layer, the resin layer being provided in an island shape for each of the pixels.

Description

[0001] This application is based on Japanese Patent Application 2020-103083 (filed on 6 / 15 / 2020) and claims priority to that application. The entire contents of that application are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to display devices. Background Technology

[0003] LED displays are generally known to use light-emitting diodes (LEDs) as self-emissive elements, but in recent years, as a more sophisticated display device, display devices using tiny diode elements called microLEDs (hereinafter referred to as microLED displays) have been developed.

[0004] Unlike previous liquid crystal displays and organic EL displays, this micro-LED display is formed by mounting multiple chip-shaped micro-LEDs in the display area. Therefore, it is easy to achieve both high precision and large size, and it has attracted attention as a next-generation display.

[0005] A micro-LED has a light-emitting layer and upper and lower electrodes disposed above and below the light-emitting layer. The upper and lower electrodes of the micro-LED are electrically connected to the driving circuit formed on the substrate of the micro-LED display via electrodes respectively disposed on the upper and lower sides of the upper and lower electrodes. However, depending on the components constituting the micro-LED display, internal stress may sometimes concentrate at the interface between the upper and lower electrodes of the micro-LED and the electrodes respectively disposed on the upper and lower sides of the upper and lower electrodes. As a result, the electrodes respectively disposed on the upper and lower sides of the upper and lower electrodes of the micro-LED may peel off or break from the upper and lower electrodes. Summary of the Invention

[0006] One of the purposes of this disclosure is to provide a miniature LED display (display device) that can suppress breakage caused by its constituent components.

[0007] One embodiment of the display device includes: a substrate; a plurality of pixels, each having a plurality of light-emitting elements, the plurality of light-emitting elements being disposed on the substrate and having different light-emitting colors; a resin layer filling the gaps between the plurality of light-emitting elements disposed in each of the pixels; and a common electrode formed of a transparent conductive material covering the resin layer, the resin layer being disposed in an island shape for each of the pixels.

[0008] One embodiment of the display device includes: an insulating substrate; a first organic insulating layer disposed on the insulating substrate; a second organic insulating layer disposed on the first organic insulating layer; a resin layer disposed on the second organic insulating layer; a common electrode disposed on the resin layer; and a plurality of pixels, each having a plurality of light-emitting elements, the plurality of light-emitting elements being disposed between the second organic insulating layer and the common electrode and surrounded by the resin layer, the common electrode being in contact with the second organic insulating layer between two adjacent pixels. Attached Figure Description

[0009] Figure 1 This is a perspective view that briefly illustrates the configuration of the display device according to the embodiment.

[0010] Figure 2 This is a diagram that briefly illustrates the circuit configuration of the display device according to the embodiment.

[0011] Figure 3 This is a simplified diagram illustrating the equivalent circuit of the sub-pixel involved in the implementation.

[0012] Figure 4 This is a top view that briefly illustrates the configuration of the display panel involved in the embodiment.

[0013] Figure 5 This is a cross-sectional view that briefly illustrates the configuration of the display panel according to the embodiment.

[0014] Figure 6 This is another cross-sectional view that briefly illustrates the configuration of the display panel involved in the embodiment.

[0015] Figure 7 This is a top view that briefly illustrates the configuration of a pixel of the display panel involved in the embodiment.

[0016] Figure 8 This is a top view that briefly shows the configuration of the display panel involved in the comparative example.

[0017] Figure 9 This is a cross-sectional view that briefly shows the configuration of the display panel involved in the comparative example.

[0018] Figure 10 This is another cross-sectional view that briefly illustrates the configuration of the display panel involved in the embodiment.

[0019] Figure 11 This is another cross-sectional view that briefly illustrates the configuration of the display panel according to the embodiment. Detailed Implementation

[0020] Several implementation methods are described with reference to the accompanying drawings.

[0021] It should be noted that the disclosure is merely an example, and appropriate modifications that would be readily conceived by those skilled in the art within the scope of the invention are of course included within the scope of the invention. Furthermore, the accompanying drawings are sometimes schematically illustrated compared to the actual embodiments for the purpose of clarity, and are merely examples, not limiting interpretations of the invention. Additionally, in this specification and the figures, the same reference numerals are used for parts that are the same as or have similar functions to those described in previously presented figures, and repeated detailed descriptions are sometimes appropriately omitted.

[0022] Figure 1 This is a perspective view that briefly shows the configuration of a display device 1 according to one embodiment. Figure 1 The diagram illustrates a three-dimensional space defined by a first direction X, a second direction Y perpendicular to the first direction X, and a third direction Z perpendicular to both the first and second directions Y. It should be noted that the first direction X and the second direction Y are orthogonal to each other, but they may intersect at angles other than 90 degrees. In this specification, viewing the display device 1 from a direction parallel to the third direction Z is referred to as a top-down view.

[0023] In this embodiment, we will mainly describe the case where the display device 1 is a microLED display that uses microLEDs as self-emissive elements.

[0024] like Figure 1 As shown, the display device 1 includes a display panel 2, a first circuit board 3, and a second circuit board 4.

[0025] In one example, the display panel 2 is rectangular. In the illustrated example, the short side EX of the display panel 2 is parallel to the first direction X, and the long side EY of the display panel 2 is parallel to the second direction Y. The third direction Z corresponds to the thickness direction of the display panel 2. The first direction X can also be referred to as a direction parallel to the short side of the display device 1, the second direction Y can also be referred to as a direction parallel to the long side of the display device 1, and the third direction Z can also be referred to as the thickness direction of the display device 1. The main surface of the display panel 2 is parallel to the XY plane defined by the first direction X and the second direction Y. The display panel 2 has a display area DA (display portion) and a non-display area NDA (non-display portion) outside the display area DA. The non-display area NDA has a terminal area MT. In the illustrated example, the non-display area NDA surrounds the display area DA.

[0026] The display area DA is the area where an image is displayed, for example, having multiple pixels PX arranged in a matrix. Pixel PX includes light-emitting elements (micro-LEDs) and switching elements (driving transistors) for driving the light-emitting elements.

[0027] The terminal area MT is located along the short side EX of the display panel 2 and includes terminals for electrical connection of the display panel 2 to external devices, etc.

[0028] The first circuit board 3 is mounted on the terminal area MT and is electrically connected to the display panel 2. The first circuit board 3 is, for example, a flexible printed circuit board. The first circuit board 3 includes a driver IC chip (hereinafter referred to as a panel driver) 5 for driving the display panel 2. It should be noted that in the illustrated example, the panel driver 5 is disposed on the first circuit board 3, but it can also be disposed below the first circuit board 3. Alternatively, the panel driver 5 can be mounted outside the first circuit board 3. In this case, the panel driver 5 can be mounted on the non-display area NDA of the display panel 2, or it can be mounted on the second circuit board 4. The second circuit board 4 is, for example, a rigid printed circuit board. The second circuit board 4 is connected to the first circuit board 3, for example, below it.

[0029] The panel driver 5 is connected to a control board (not shown) via, for example, a second circuit board 4. The panel driver 5 drives a plurality of pixels PX based on an image signal output from the control board, thereby performing control over the display of an image on the display panel 2.

[0030] It should be noted that the display panel 2 may also have a bent area BA as indicated by the diagonal lines. The bent area BA is the area that is bent when the display device 1 is housed in the housing of an electronic device or the like. The bent area BA is located on the terminal area MT side in the non-display area NDA. When the bent area BA is bent, the first circuit board 3 and the second circuit board 4 are configured to face the display panel 2.

[0031] Figure 2 This is a diagram showing the circuit configuration of display device 1. Figure 3 This is the equivalent circuit diagram of the sub-pixels SP included in pixel PX. It should be noted that... Figure 2 For ease of explanation, not all wiring diagrams are shown; some are omitted.

[0032] like Figure 2 and Figure 3 As shown, the display panel 2 includes: an insulating substrate (insulating substrate) 20 that is transparent to light, a plurality of pixels PX arranged in a matrix on the insulating substrate 20 in the display area DA, various wiring, scan line driving circuits YDR1 and YDR2, and signal line driving circuits XDR, etc.

[0033] The various wiring configurations include: multiple first scan lines Sga, multiple second scan lines Sgb, multiple third scan lines Sgc, multiple fourth scan lines Sgd, multiple image signal lines VL, multiple first power lines SLa, multiple reset wirings Sgr, and multiple initialization wirings Sgi.

[0034] In this embodiment, the first scan line Sga, the third scan line Sgc, and the fourth scan line Sgd are connected to the scan line drive circuit YDR1 and extend in the first direction X. The second scan line Sgb is connected to the scan line drive circuit YDR2 and extends in the first direction X. The image signal line VL is connected to the signal line drive circuit XDR and extends in the second direction Y. The first power line SLa, the reset wiring Sgr, and the initialization wiring Sgi extend in the second direction Y.

[0035] For example, multiple first power lines SLa are located in the display area DA and arranged at intervals in the first direction X. The display panel 2 not only has the first power lines SLa, but also a second power line SLb set to a different potential than the first power lines SLa. In this embodiment, the first power line SLa is a high-potential power line fixed at a high potential Pvdd, and the second power line SLb is a low-potential power line fixed at a low potential Pvss. The first power line SLa is connected to the high-potential power supply, and the second power line SLb is connected to the low-potential power supply.

[0036] The scan line driving circuit YDR1 is configured to drive the first scan line Sga, the third scan line Sgc, and the fourth scan line Sgd. The scan line driving circuit YDR2 is configured to drive the second scan line Sgb. The signal line driving circuit XDR is configured to drive the image signal line VL. The scan line driving circuits YDR1 and YDR2, along with the signal line driving circuit XDR, are formed on the insulating substrate 20 in the non-display area NDA, and together with the panel driver 5, constitute the driving unit 7.

[0037] Each pixel PX has multiple sub-pixels SP. Each sub-pixel SP includes a light-emitting element 10 and a pixel circuit that provides driving current to the light-emitting element 10. The light-emitting element 10 is, for example, a self-emissive element, and in this embodiment, a micro LED. The display device 1 of this embodiment is a micro LED display.

[0038] Each sub-pixel SP's pixel circuit is a voltage signal-based pixel circuit that controls the light emission of the light-emitting element 10 based on an image signal Vsig composed of a voltage signal. It includes a reset switch RST, a pixel switch SST, an initialization switch IST, an output switch BCT, a drive transistor DRT, a holding capacitor Cs, and an auxiliary capacitor Cad. The holding capacitor Cs and the auxiliary capacitor Cad are capacitors. The auxiliary capacitor Cad is a component used to adjust the amount of light emission current; sometimes, the auxiliary capacitor Cad is not needed.

[0039] The reset switch RST, pixel switch SST, initialization switch IST, output switch BCT, and driving transistor DRT are all constructed from TFTs (thin-film transistors). In this embodiment, the reset switch RST, pixel switch SST, initialization switch IST, output switch BCT, and driving transistor DRT are all constructed from TFTs of the same conductivity type, such as N-channel TFTs. It should be noted that the reset switch RST, pixel switch SST, initialization switch IST, output switch BCT, and driving transistor DRT can also be constructed from P-channel TFTs. In this case, both N-channel and P-channel TFTs can be formed simultaneously. The reset switch RST, pixel switch SST, initialization switch IST, and output switch BCT only need to function as switches, and may not necessarily be constructed from TFTs.

[0040] In the display device 1 according to this embodiment, the TFTs constituting the driving transistor DRT and each switch are all thin-film transistors with a top-gate structure formed using the same process and the same structure, and using polycrystalline silicon as the semiconductor layer. It should be noted that the semiconductor layer may also use semiconductors other than polycrystalline silicon, such as amorphous silicon or oxide semiconductors.

[0041] The reset switch RST, pixel switch SST, initialization switch IST, output switch BCT, and drive transistor DRT each have a first terminal, a second terminal, and a control terminal. In this embodiment, the first terminal is designated as the source electrode, the second terminal as the drain electrode, and the control terminal as the gate electrode.

[0042] In the pixel circuit of pixel PX, the driving transistor DRT and the output switch BCT are connected in series with the light-emitting element 10 between the first power line SLa and the second power line SLb. The first power line SLa (high potential Pvdd) is set to a potential of 10V for example, and the second power line SLb (low potential Pvss) is set to a potential of 1.5V for example.

[0043] In the output switch BCT, the drain electrode is connected to the first power supply line SLa, the source electrode is connected to the drain electrode of the driving transistor DRT, and the gate electrode is connected to the second scan line Sgb. Thus, the output switch BCT is controlled by the control signal BG provided to the second scan line Sgb to be either on (conducting) or off (non-conducting). The output switch BCT responds to the control signal BG to control the emission time of the light-emitting element 10.

[0044] In the driving transistor DRT, the drain electrode is connected to the source electrode of the output switch BCT, and the source electrode is connected to one electrode (the anode in this case) of the light-emitting element 10. The other electrode (the cathode in this case) of the light-emitting element 10 is connected to the second power supply line SLb. The driving transistor DRT outputs a driving current corresponding to the image signal Vsig to the light-emitting element 10.

[0045] In the pixel switch SST, the source electrode is connected to the image signal line VL, the drain electrode is connected to the gate electrode of the driving transistor DRT, and the gate electrode is connected to the third scan line Sgc, which functions as a gate wiring for signal write control. The pixel switch SST is controlled to be turned on and off by a control signal SG supplied from the third scan line Sgc. The pixel switch SST responds to the control signal SG to control the connection or disconnection between the pixel circuit and the image signal line VL, and draws the image signal Vsig from the image signal line VL into the pixel circuit.

[0046] In the initialization switch IST, the source electrode is connected to the initialization wiring Sgi, the drain electrode is connected to the gate electrode of the driving transistor DRT, and the gate electrode is connected to the first scan line Sga. The initialization switch IST is controlled to be turned on and off by a control signal IG supplied from the first scan line Sga. The initialization switch IST responds to the control signal IG to control the connection or disconnection of the pixel circuit and the initialization wiring Sgi. By connecting the pixel circuit and the initialization wiring Sgi with the initialization switch IST, the initial potential (initialization voltage) Vini can be taken from the initialization wiring Sgi into the pixel circuit.

[0047] The reset switch RST is connected between the source electrode of the drive transistor DRT and the reset wiring Sgr. The gate electrode of the reset switch RST is connected to the fourth scan line Sgd, which functions as a gate wiring for reset control. As described above, the reset wiring Sgr is connected to the reset power supply and fixed at the reset potential Vrst, which is a constant potential. The reset switch RST is controlled to be turned on and off by the control signal RG provided through the fourth scan line Sgd. By switching the reset switch RST to the on state, the potential of the source electrode of the drive transistor DRT can be reset to the reset potential Vrst.

[0048] The retaining capacitor Cs is connected between the gate and source electrodes of the driving transistor DRT. The auxiliary capacitor Cad is connected between the source electrode of the driving transistor DRT and the first power supply line SLa, which is a constant potential wiring.

[0049] on the other hand, Figure 2 The panel driver 5 shown controls the scan line drive circuits YDR1 and YDR2, as well as the signal line drive circuit XDR. The panel driver 5 receives digital image signals and synchronization signals supplied from the outside, and generates a vertical scan control signal to control the vertical scan timing and a horizontal scan control signal to control the horizontal scan timing based on the synchronization signal.

[0050] The panel driver 5 provides these vertical scan control signals and horizontal scan control signals to the scan line drive circuits YDR1 and YDR2 and the signal line drive circuit XDR, respectively, and provides digital image signals and initialization signals to the signal line drive circuit XDR in sync with the horizontal scan timing and vertical scan timing.

[0051] The signal line drive circuit XDR converts the image signals obtained sequentially during each horizontal scan under the control of the horizontal scan control signal into analog format and provides the grayscale-corresponding image signal Vsig to multiple image signal lines VL. The panel driver 5 fixes the first power line SLa at a high potential Pvdd, the reset wiring Sgr at a reset potential Vrst, and the initialization wiring Sgi at an initialization potential Vini. It should be noted that the potentials of the first power line SLa, the reset wiring Sgr, and the initialization wiring Sgi can also be set via the signal line drive circuit XDR.

[0052] The panel driver 5 provides the start pulse signal STV, clock signal CKV, etc. to the scan line drive circuits YDR1 and YDR2.

[0053] The scan line drive circuits YDR1 and YDR2 include shift registers (not shown), output buffers, etc., which sequentially forward the start pulse signal STV to the next-stage shift register and supply four control signals (IG, BG, SG, and RG) to the sub-pixels SP of each row via the output buffer. Thus, the first scan line Sga, the second scan line Sgb, the third scan line Sgc, and the fourth scan line Sgd are driven by the control signals IG, BG, SG, and RG, respectively.

[0054] It should be noted that, in Figure 3 The circuit configuration of the sub-pixel SP described herein is an example. As long as it includes at least the driving transistor DRT and the light-emitting element 10, the circuit configuration of the sub-pixel SP can also be other configurations. For example, it can be omitted in... Figure 3The circuit configuration of the sub-pixel SP described herein is a part of the components, and other components may be added.

[0055] Next, refer to Figure 4 The multiple pixels PX, multiple wiring WLa, and multiple resin layers 31 are described.

[0056] like Figure 4 As shown, the second power line SLb is located in the non-display area NDA. The second power line SLb is formed in a Π shape. The second power line SLb is located at the top, left, and right sides of the non-display area NDA, but not below the signal line drive circuit XDR. However, the second power line SLb can also be located at the bottom of the non-display area NDA, forming a shape that surrounds the display area DA on all four sides.

[0057] Multiple wirings WLa are located in the display area DA and the non-display area NDA, respectively. The multiple wirings WLa are electrically connected to the second power line SLb in the non-display area NDA. The multiple wirings WLa extend in the first direction X and are arranged at intervals in the second direction Y, and are electrically connected to the contact electrodes CON of the multiple pixels PX arranged in the first direction X. In this embodiment, wiring WLa functions as the first wiring.

[0058] It should be noted that multiple wirings WLa can also extend in the second direction Y and be arranged at intervals in the first direction X, electrically connected to the contact electrodes CON of multiple pixels PX arranged in the second direction Y.

[0059] In the display area DA, multiple pixels PX arranged in a matrix each have multiple light-emitting elements 10. The multiple light-emitting elements 10 have different emission colors, for example, red (R), green (G), and blue (B).

[0060] Details regarding resin layer 31 will be discussed in conjunction with... Figure 5 The explanation will be described later, such as Figure 4 As shown, each of the multiple pixels PX has a resin layer 31 arranged in an island shape on a per-pixel basis. The resin layer 31 is configured to surround the multiple light-emitting elements 10 disposed in each pixel PX. When viewed from above, the area of ​​the resin layer 31 of each pixel is smaller than the area of ​​a single pixel (pixel PX) when viewed from above. Figure 4As shown, there is a region where a resin layer 31 is not provided between a pixel PX and its adjacent pixel PX in the first direction X. The resin layer 31 of the pixel PX is separate (not connected) from the resin layer 31 of its adjacent pixel PX in the first direction X. Additionally, there is also a region where a resin layer 31 is not provided between a pixel PX and its adjacent pixel PX in the second direction Y. The resin layer 31 of the pixel PX is also separate (not connected) from the resin layer 31 of its adjacent pixel PX in the second direction Y.

[0061] It should be noted that, in Figure 4 The illustration shows a configuration where multiple wirings WLa extend at positions overlapping with the resin layer 31 of each pixel PX when viewed from above. However, this is not a limitation; the multiple wirings WLa can also extend at positions where they do not overlap with the resin layer 31 of each pixel PX when viewed from above. Nevertheless, when considering wiring resistance, it is ideal for the multiple light-emitting elements 10 to be configured close to the wirings WLa.

[0062] Figure 5 It schematically shows along Figure 4 A cross-sectional view of a display panel 2 after the AB line has been cut off. It should be noted that... Figure 5 In the diagram, the display surface, i.e. the light-emitting surface, of the display panel 2 is depicted facing upwards, and the back surface is depicted facing downwards.

[0063] like Figure 5 As shown, the display panel 2 includes an insulating substrate 20, insulating layers 21 to 26 disposed on the insulating substrate 20, and a plurality of pixels PX. The plurality of pixels PX are disposed on the insulating substrate 20, located in the display area DA, and have a plurality of light-emitting elements 10.

[0064] The insulating substrate 20 can primarily be a glass substrate such as quartz or alkali-free glass, or a resin substrate such as polyimide. The material of the insulating substrate 20 only needs to be able to withstand the processing temperatures during TFT manufacturing. When the insulating substrate 20 is a flexible resin substrate, the display device 1 can be configured as a thin-film display. The resin substrate is not limited to polyimide; other resin materials can also be used. It should be noted that when polyimide or similar materials are used as the insulating substrate 20, it may be more appropriate to refer to the insulating substrate 20 as an organic insulating layer or a resin layer.

[0065] An insulating layer 21 is disposed on an insulating substrate 20. Various TFTs are formed on the insulating layer 21. In the display area DA, a driving transistor DRT and the like are formed on the insulating layer 21. The TFT such as the driving transistor DRT has a semiconductor layer SC, a gate electrode GE, a first electrode E1, and a second electrode E2.

[0066] A semiconductor layer SC is disposed on an insulating layer 21. An insulating layer 22 is disposed on the insulating layer 21 and the semiconductor layer SC. A gate electrode GE is disposed on the insulating layer 22, opposite to the channel region of the semiconductor layer SC. An insulating layer 23 is disposed on the insulating layer 22 and the gate electrode GE. A first electrode E1 and a second electrode E2 are disposed on the insulating layer 23. The first electrode E1 and the second electrode E2 are electrically connected to the corresponding semiconductor layer SC through contact holes formed in the insulating layers 22 and 23, respectively. In this embodiment, a first power line SLa is also disposed on the insulating layer 23.

[0067] In addition, the gate electrode GE is not limited to this example; for example, it can also be disposed between the insulating layer 22 and the insulating substrate 20.

[0068] An insulating layer 24 is disposed on the insulating layer 23, the first electrode E1, the second electrode E2, and the first power line SLa. The insulating layer 24 covers multiple TFTs, including multiple driving transistors DRT. Multiple contact holes h1 and h2 are formed on the insulating layer 24. Contact hole h1 exposes the upper surface of the first electrode E1. Contact hole h2 exposes the upper surface of the first power line SLa.

[0069] A conductive layer CL1 is disposed on the insulating layer 24. The conductive layer CL1 is connected to the first power line Sla through the contact hole h2 and is electrically connected to the first power line SLa.

[0070] An insulating layer 25 is disposed on top of the insulating layer 24 and the conductive layer CL1. The insulating layer 25 has a contact hole h3 surrounded by a contact hole h1, which, together with the contact hole h1, exposes the upper surface of the first electrode E1. The conductive layer CL2 is disposed on the insulating layer 25. The conductive layer CL2 is connected to the first electrode E1 through the contact hole h3 formed in the insulating layer 25 and is electrically connected to the first electrode E1.

[0071] An insulating layer 26 is disposed on the insulating layer 25 and the conductive layer CL2. A contact hole h4 is formed on the insulating layer 26, which exposes the upper surface of the conductive layer CL2.

[0072] The pixel electrode PE is disposed on the insulating layer 26. The pixel electrode PE is connected to and electrically connected to the conductive layer CL2 through a contact hole h4 formed in the insulating layer 26. The pixel electrode PE is electrically connected to the first electrode E1 of the driving transistor DRT via the conductive layer CL2. The driving transistor DRT provides a signal to the pixel electrode PE to control the current value.

[0073] In this embodiment, the display panel 2 has a contact electrode CON, a connecting layer LA1, and a connecting layer LA2. The contact electrode CON is disposed on the insulating layer 26 and positioned with an insulating distance between it and the pixel electrode PE. The connecting layer LA1 is disposed on the pixel electrode PE. When viewed from above, the connecting layer LA1 does not overlap with the contact hole h4. The connecting layer LA2 is disposed on the contact electrode CON.

[0074] Here, insulating layers 21 to 26 are formed of inorganic or organic insulating materials. In this embodiment, insulating layers 21, 22, 23, and 25 are formed of inorganic insulating materials such as silicon oxide (SiO2) or silicon nitride (SiN).

[0075] Insulating layers 24 and 26 are formed of a resin material such as a photosensitive acrylic resin, which serves as an organic insulating material. Insulating layers 24 and 26 each have a flat surface on the side opposite to the light-emitting element 10, functioning as planarization layers. In this embodiment, the insulating layer 24 disposed above the insulating substrate 20 functions as a first organic insulating layer, and the insulating layer 26 disposed above the insulating layer 24 functions as a second organic insulating layer.

[0076] The semiconductor layer SC is formed from low-temperature polycrystalline silicon, which is polycrystalline silicon. However, the semiconductor layer SC can also be formed from semiconductors other than polycrystalline silicon, such as amorphous silicon and oxide semiconductors. The gate electrode GE is formed from a metal that is a conductive material. For example, the gate electrode GE is formed from MoW (molybdenum tungsten).

[0077] The first electrode E1, the second electrode E2, and the first power line SLa are located in the same layer and are formed of a metal that is the same conductive material. For example, the first electrode E1, the second electrode E2, and the first power line SLa each adopt a three-layer stacked structure (Ti-based / Al-based / Ti-based), having: a lower layer, which is composed of Ti (titanium), Ti-containing alloys, or other metal materials with Ti as the main component; a middle layer, which is composed of Al (aluminum), Al-containing alloys, or other metal materials with Al as the main component; and an upper layer, which is composed of Ti, Ti-containing alloys, or other metal materials with Ti as the main component.

[0078] Switches such as driving transistors (DRTs) are positioned above the insulating substrate 20 and covered by the insulating layer 24. Here, a top-gate TFT is used as an example, but the TFT can also be a bottom-gate TFT.

[0079] The conductive layer CL1 is formed of transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0080] The conductive layer CL2, pixel electrode PE, and contact electrode CON are formed of a metal that is a conductive material. For example, the conductive layer CL2, pixel electrode PE, and contact electrode CON have a double-layer stacked structure, comprising: a lower layer, which is composed of a Ti-based metal material such as Ti or a Ti-containing alloy; and an upper layer, which is composed of an Al-based metal material such as Al or an Al-containing alloy. The upper layer, formed of Al or an Al alloy, is the topmost layer among the conductive layer CL2, pixel electrode PE, and contact electrode CON. For example, the topmost layer of the contact electrode CON is located on the side opposite to the common electrode CE. The connecting layer LA1 is connected to the topmost layer of the pixel electrode PE, and the connecting layer LA2 is connected to the topmost layer of the contact electrode CON. Ideally, the pixel electrode PE and the contact electrode CON are located in the same layer and formed of a metal that is the same conductive material.

[0081] It should be noted that the conductive layer CL2, the pixel electrode PE, and the contact electrode CON can each have a single conductive layer, a three-layer stacked structure, or a two-layer stacked structure, respectively.

[0082] In the three-layer stacked structure, the conductive layer CL2, the pixel electrode PE, and the contact electrode CON are not limited to Ti-based / Al-based / Ti-based structures, but can also be Mo-based / Al-based / Mo-based structures. In the Mo-based / Al-based / Mo-based structure, for example, the pixel electrode PE has: a lower layer composed of a Mo-based metallic material, such as Mo (molybdenum) or Mo-containing alloys; a middle layer composed of an Al-based metallic material, such as Al or Al-containing alloys; and an upper layer composed of a Mo-based metallic material, such as Mo or Mo-containing alloys.

[0083] In a two-layer stacked structure, such as the pixel electrode PE, it can also have: a lower layer composed of a Mo-based metallic material, such as Mo or a Mo-containing alloy; and an upper layer composed of an Al-based metallic material, such as Al or an Al-containing alloy. It should be noted that the conductive layer CL2 and the pixel electrode PE can also be formed of transparent conductive materials.

[0084] The connecting layers LA1 and LA2 are formed using solder.

[0085] In the display area DA, a light-emitting element 10 is mounted above the pixel electrode PE. Specifically, the light-emitting element 10 is mounted on the connecting layer LA1. The light-emitting element 10 has an anode AN as a first polarity electrode, a cathode CA as a second polarity electrode, and a light-emitting layer LI that emits light. The anode AN and cathode CA can also be collectively referred to as the upper and lower electrodes. Furthermore, the anode AN can also be referred to as the lower electrode, and the cathode CA can also be referred to as the upper electrode.

[0086] In each light-emitting element 10, the anode AN is located on the side opposite to one of the pixel electrodes PE among the plurality of pixel electrodes PE, and is electrically connected to the pixel electrode PE. In this embodiment, the anode AN is located on and connected to the connecting layer LA1. In each light-emitting element 10, the cathode CA is located on the side opposite to the side where the anode AN is located. In each light-emitting element 10, the light-emitting layer LI is located between the anode AN and the cathode CA.

[0087] A resin layer 31 is disposed on the insulating layer 26, the pixel electrode PE, the contact electrode CON, the connecting layer LA1, the connecting layer LA2, and the light-emitting element 10. The resin layer 31 fills the gaps between the multiple light-emitting elements 10. The resin layer 31 is used to suppress the entry of moisture from the outside and can also be called a sealing film. The resin layer 31 has a flat surface on the side opposite to the side opposite to the insulating layer 26. Therefore, the resin layer 31 also functions as a planarization layer. The resin layer 31 exposes the surface of the cathode CA in the light-emitting element 10.

[0088] It should be noted that the resin layer 31 may also have a thickness that does not reach the cathode CA of the light-emitting element 10. Although some unevenness remains on the surface forming the common electrode CE due to the installation of the light-emitting element 10, it is acceptable as long as the material forming the common electrode CE can be continuously covered without interruption.

[0089] A common electrode CE is located at least in the display area DA, disposed above the resin layer 31 and the plurality of light-emitting elements 10, and covering the resin layer 31 and the plurality of light-emitting elements 10. The common electrode CE is in contact with and electrically connected to the cathodes CA of the plurality of light-emitting elements 10. The common electrode CE is shared by the plurality of pixels PX, and continuously covers the plurality of resin layers 31 arranged in an island-like manner on a unit of one pixel.

[0090] In order to extract the emitted light from the light-emitting element 10, the common electrode CE needs to be formed as a transparent electrode, and ITO, as a transparent conductive material, is used to form the common electrode CE.

[0091] The common electrode CE is electrically connected to the contact electrodes CON of the multiple pixels PX through multiple contact holes h5 formed in the multiple resin layers 31. In this embodiment, the common electrode CE is connected to the connection layer LA2 of the multiple pixels PX through the multiple contact holes h5. The common electrode CE is connected to the connection layer LA2 but not to the contact electrodes CON, thus forming an ohmic contact between the common electrode CE and the connection layer LA2.

[0092] like Figure 5As shown, the common electrode CE contacts the insulating layer 26 between pixel PX1 and the pixel PX2 adjacent to pixel PX1. That is, as described above, no resin layer 31 is provided between pixel PX1 and pixel PX2. The resin layer 31a filling the gaps between the plurality of light-emitting elements 10 arranged in pixel PX1 and the resin layer 31b filling the gaps between the plurality of light-emitting elements 10 arranged in pixel PX2 are separated and sealed by the common electrode CE.

[0093] It should be noted that, in Figure 5 The example shown illustrates a configuration where a common electrode CE is provided covering the entire surface of the display area DA, but the configuration is not limited to this one; for example, [examples would be inserted here]. Figure 6 As shown, the common electrode CE can also be set on a unit of one pixel. That is, the common electrode CE may not be shared by multiple pixels PX. In this case, the resin layer 31 and the common electrode CE are not set between pixels PX1 and PX2. However, even in this case, the resin layer 31a filling the gaps between the multiple light-emitting elements 10 arranged in pixel PX1 and the resin layer 31b filling the gaps between the multiple light-emitting elements 10 arranged in pixel PX2 are separated and sealed by the common electrodes CEa and CEb set on a unit of one pixel. It should be noted that as long as the resin layer 31a of pixel PX1 and the resin layer 31b of pixel PX2 are separated, the common electrodes CEa and CEb may not be set on the sides of the resin layers 31a and 31b.

[0094] As described above, the display panel 2 has a structure extending from the insulating substrate 20 to the common electrode CE. It should be noted that cover components such as a cover glass, optical layers such as a polarizing plate, and a touch panel substrate may also be provided above the common electrode CE.

[0095] Figure 7 This is a top view showing a pixel (pixel PX) of the display panel 2, which shows a plurality of pixel electrodes PE, a plurality of connection layers LA1, contact electrodes CON, connection layers LA2 and wiring WLa corresponding to the plurality of light-emitting elements 10 disposed on the pixel PX.

[0096] like Figure 7As shown, pixel PX has sub-pixels Spa, SPb, and SPc. Sub-pixels Spa, SPb, and SPc are arranged at intervals in the first direction X. Sub-pixel Spa has a pixel electrode PEa, a connecting layer LA1a, and a light-emitting element 10a. The light-emitting element 10a is, for example, a red light-emitting element. Sub-pixel SPb has a pixel electrode PEb, a connecting layer LA1b, and a light-emitting element 10b. The light-emitting element 10b is, for example, a green light-emitting element. Furthermore, sub-pixel SPc has a pixel electrode PEc, a connecting layer LA1c, and a light-emitting element 10c. The light-emitting element 10c is, for example, a blue light-emitting element.

[0097] Multiple pixel electrodes PEa, PEb, PEc, contact electrodes CON, and wiring WLa are disposed between the insulating layer 26 and the resin layer 31; in other words, they are disposed in the same layer and formed of the same metal. In this embodiment, wiring WLa is integrally formed with the multiple contact electrodes CON arranged in the first direction X.

[0098] Multiple pixel electrodes PEa, PEb, and PEc are electrically connected to a conductive layer CL2 located below the insulating layer 26 through multiple contact holes h4 formed in the insulating layer 26. A common electrode CE located above the resin layer 31 is connected to the connecting layer LA2 through a contact hole h5 formed in the resin layer 31.

[0099] The spacing between two adjacent sub-pixels SP in the first direction X is, for example, shorter than the length of the region without resin layer 31 in the first direction X.

[0100] Here, comparative examples are used to illustrate the effects of the display device 1 (display panel 2) according to this embodiment. It should be noted that the comparative examples are used to illustrate part of the effects that the display device 1 (display panel 2) according to this embodiment can achieve, and are not intended to exclude the common effects between the comparative examples and this embodiment from the scope of this application.

[0101] Figure 8 This is a top view of the display device 1A (display panel 2A) involved in the comparative example. Figure 9 This is a cross-sectional view of the display device 1A (display panel 2A) involved in the comparative example. On the other hand, Figure 10 This is a cross-sectional view of the display device 1 (display panel 2) according to this embodiment. It should be noted that... Figure 10 It is Figure 5 The simplified diagram omits elements unnecessary for illustrating the differences from the comparative example. For example... Figure 8 and Figure 9 As shown, the display device 1A (display panel 2A) involved in the comparative example differs from this embodiment in that a resin layer 31 is provided on the entire surface covering the display area DA.

[0102] Generally, the organic insulating material forming the resin layer 31 has a large coefficient of linear expansion and is prone to thermal shrinkage. Therefore, internal stress caused by thermal shrinkage is applied to the interface between the resin layer 31 and the common electrode CE. When internal stress is applied to the interface between the resin layer 31 and the common electrode CE, the common electrode CE may peel off from the resin layer 31. When the common electrode CE peels off from the resin layer 31, the common electrode CE may also peel off from the cathode CA of the light-emitting element 10. When the common electrode CE peels off from the cathode CA of the light-emitting element 10, since the common electrode CE and the light-emitting element 10 are not electrically connected, there is a problem that the driving current cannot be supplied to the light-emitting element 10. On the other hand, when the resin layer 31 is not provided in the gaps between the multiple light-emitting elements 10, there is a problem that moisture and other substances cannot be prevented from entering from the outside.

[0103] In contrast, according to the configuration of the display panel 2 in this embodiment, as follows: Figure 10 As shown, the resin layer 31 is arranged in an island shape for each pixel PX, and no resin layer 31 is provided between two adjacent pixels PX. Therefore, the aforementioned internal stress can be dispersed on a per-pixel basis. Thus, it is possible to suppress the peeling of the common electrode CE from the resin layer 31, and further suppress the peeling of the common electrode CE from the cathode CA of the light-emitting element 10 (it is possible to suppress interlayer cracks). Accordingly, a display device 1 can be obtained that improves the connection reliability between the common electrode CE and the cathode CA of the light-emitting element 10 and suppresses damage caused by the constituent components.

[0104] Furthermore, in the configuration of this embodiment, the common electrode CE is electrically connected to the contact electrode CON for each pixel. The contact electrode CON is electrically connected to the wiring WLa formed of metal. Therefore, compared to the case where the common electrode CE is in contact with the second power line SLb in the non-display area NDA, the wiring resistance between the light-emitting element 10 and the second power line SLb can be reduced. Accordingly, a display device 1 capable of achieving high brightness can be obtained. Alternatively, a display device 1 capable of achieving low power consumption can be obtained. Alternatively, a display device 1 capable of achieving both high brightness and low power consumption can be obtained.

[0105] It should be noted that in this embodiment, the resin layer 31 is described as being configured in an island shape on a unit of one pixel, but this configuration is not limited to this one. For example, the resin layer 31 may also be configured in an island shape on a unit of several pixels. Even in this case, the internal stress described above can be dispersed on a unit of several pixels. Therefore, compared with the configuration involved in the comparative example, it is possible to suppress the peeling of the common electrode CE from the resin layer 31, and further suppress the peeling of the common electrode CE from the cathode CA of the light-emitting element 10.

[0106] It should be noted that in this embodiment, the resin layer 31 is described as an island not provided between two adjacent pixels PX. However, the resin layer 31 may also be formed as a thin layer remaining between two adjacent pixels PX. In this case, for example, it becomes a structure in which the resin layer 31 formed island-like in pixel PX is connected to the resin layer 31 formed island-like in different pixels PX by using a thinner resin layer 31. For example, in Figure 4 In the example shown, a portion of the wiring WLa is exposed from the resin layer 31 between two adjacent pixels PX. However, to protect the wiring WLa from the influence of the external environment, it is also possible to have a structure in which the wiring WLa is covered by a thinner resin layer 31 without being exposed from the resin layer 31. Here, a thinner resin layer 31 means, for example, a film thickness thinner than the island-shaped resin layer 31 in the pixel PX, preferably less than half the film thickness of the island-shaped resin layer 31. Therefore, even when a thin resin layer 31 is formed between two adjacent pixels PX, it can be said that the resin layer 31 formed in the pixel PX is formed as an island.

[0107] Moreover, the structure involved in this embodiment, in addition to Figure 10 In addition to the internal stress of the dispersed resin layer 31 shown, there are also... Figure 11 It plays a particularly good role in flexible display devices like the one shown. Figure 11 The insulating substrate 20 is a flexible resin substrate 20 with flexibility, and the display device 1 is a flexible display device 1 that can be bent. For example... Figure 11 As shown, the resin layers 31 formed in an island-like pattern on each pixel PX are connected by thinner resin layers 31. This can be left as described above to protect the wiring WLa, or it can focus on protecting curved surfaces where stress is easily applied. Of course, to improve flexibility, a structure in which no resin layer 31 is formed between two adjacent pixels PX can also be used. Figure 11 The structure, and Figure 8 and Figure 9 Compared to the structure where the resin layer 31 is formed on the front surface, the flexibility of the flexible display device 1 can be further improved.

[0108] According to one embodiment described above, a miniature LED display (display device) that can suppress damage caused by constituent components can be provided.

[0109] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can also be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are all included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A display device comprising: substrate; Multiple pixels, each having multiple light-emitting elements, the multiple light-emitting elements being disposed on the substrate and having different light-emitting colors; A resin layer is used to fill the gaps between the plurality of light-emitting elements disposed in each of the pixels; as well as The common electrode is formed of a transparent conductive material covering the resin layer. The resin layer is arranged in an island shape for each pixel. The plurality of light-emitting elements are chip-shaped micro-LEDs, each having a light-emitting layer and upper and lower electrodes. The light-emitting layer emits light, and the upper and lower electrodes are arranged above and below the light-emitting layer, separated by the light-emitting layer. The common electrode is electrically connected to the upper electrode of each of the light-emitting elements. The resin layer has a flat surface on one side of the upper electrode. The resin layer is divided and sealed by the common electrode between two adjacent pixels, according to each pixel.

2. The display device according to claim 1, wherein, When viewed from above, the area of ​​the resin layer of each pixel is smaller than the area of ​​the pixel when viewed from above.

3. The display device according to claim 2, wherein, The common electrode is continuously covered with multiple resin layers arranged for each pixel.

4. The display device according to claim 2, wherein, The common electrode is arranged in an island shape for each pixel and is not located between two adjacent pixels.

5. The display device according to claim 4, wherein, The common electrode is electrically connected to the contact electrode provided for each pixel through contact holes formed in the resin layer.

6. The display device according to claim 5, wherein, The substrate has a first wiring, which is electrically connected to the contact electrode disposed for each pixel. The first wiring extends at the position where it overlaps with the resin layer when viewed from above.

7. The display device according to claim 5, wherein, The common electrode is electrically connected to the contact electrode provided for each pixel. The substrate has a first wiring, which is electrically connected to the contact electrode disposed for each pixel. The first wiring extends at a position where it does not overlap with the resin layer when viewed from above.

8. A display device comprising: Insulating substrate; A first organic insulating layer is disposed on the insulating substrate; A second organic insulating layer is disposed on top of the first organic insulating layer; A resin layer is disposed on top of the second organic insulating layer; A common electrode is disposed on the resin layer; as well as Multiple pixels, each having multiple light-emitting elements, are disposed between the second organic insulating layer and the common electrode and are surrounded by the resin layer. The common electrode is in contact with the second organic insulating layer between two adjacent pixels. The plurality of light-emitting elements are chip-shaped micro-LEDs, each having a light-emitting layer and upper and lower electrodes. The light-emitting layer emits light, and the upper and lower electrodes are arranged above and below the light-emitting layer, separated by the light-emitting layer. The common electrode is electrically connected to the upper electrode of each of the light-emitting elements. The resin layer has a flat surface on one side of the upper electrode. The resin layer is divided and sealed by the common electrode between two adjacent pixels, according to each pixel.

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