Method and apparatus for decoding data in a communication or broadcasting system

Abstract

Disclosed are a communication scheme and system thereof that integrates Internet of Things technology and a 5G communication system, wherein the 5G communication system supports a high data transmission rate exceeding the data transmission rate of a 4G system. The present disclosure can be applied to smart businesses based on 5G communication technology and Internet of Things-related technologies (for example, businesses related to smart homes, smart buildings, smart cities, smart cars, connected cars, healthcare, digital education, retail businesses, security, and safety). A decoding method includes: decoding by an inner code; detecting errors by an outer code; determining a re-encoding method; and re-encoding. A method for processing a signal includes: decoding a first layer signal to determine a first LDPC information bit, encoding the first LDPC information bit and a first parity bit to determine a second parity bit; identifying a portion of the first LDPC information bit, and decoding a second layer signal.

Description

Technical Field

[0001] The present disclosure relates to a method and apparatus for decoding data in a communication or broadcasting system. Background Art

[0002] To meet the growing demand for wireless data traffic since the deployment of 4G communication systems, efforts have been underway to develop improved 5G or pre-5G communication systems. Consequently, 5G or pre-5G communication systems are also referred to as "beyond 4G networks" or "post-LTE systems." 5G communication systems are expected to be implemented in higher frequency (mmWave) bands, such as the 60 GHz band, to achieve higher data rates. To reduce radio wave propagation losses and increase transmission distance, technologies discussed in 5G communication systems include beamforming, massive multiple-input multiple-output (MIMO), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, and massive antenna technology. Furthermore, in 5G communication systems, development is underway to improve system networks based on advanced small cells, cloud radio access networks (RANs), ultra-dense networks, device-to-device (D2D) communications, wireless backhaul, mobile networks, cooperative communications, coordinated multipoint (CoMP), and receiver interference cancellation. In 5G systems, hybrid FSK and QAM modulation (FQAM) and sliding window superposition coding (SWSC) as advanced coding modulation (ACM) have also been developed, as well as filter bank multi-carrier (FBMC), non-orthogonal multiple access (NOMA) and sparse code multiple access (SCMA) as advanced access technologies.

[0003] The Internet is a human-centric network of connections where humans generate and consume information. It is now evolving into the Internet of Things (IoT), in which distributed entities such as things exchange and process information without human intervention. The Internet of Everything (IoE) has emerged. Connected through cloud servers, the IoE combines IoT technologies with big data processing techniques. Because IoT implementation requires technical elements such as sensing technology, wired / wireless communication and network infrastructure, service interface technology, and security technology, recent research has focused on sensor networks, machine-to-machine (M2M) communication, and machine-type communication (MTC). Such an IoT environment can provide intelligent Internet technology services that create new value for human life by collecting and analyzing data generated between connected things. Through the integration and combination of existing information technology (IT) with various industrial applications, the IoT can be applied to various fields, including smart homes, smart buildings, smart cities, smart cars (connected vehicles), smart grids, healthcare, smart appliances, and advanced medical services.

[0004] Accordingly, various attempts have been made to apply 5G communication systems to IoT networks. For example, beamforming, MIMO, and array antennas can be used to implement technologies such as sensor networks, machine-type communications (MTC), and machine-to-machine (M2M) communications. The application of cloud radio access networks (RAN), which utilize the aforementioned big data processing technology, can also be seen as an example of the convergence of 5G and IoT technologies.

[0005] Due to various channel noise, fading phenomena and inter-symbol interference (ISI), link performance may be significantly deteriorated in communication / broadcasting systems. Therefore, in order to realize high-speed digital communication or broadcasting systems that require high data throughput and high reliability, such as next-generation mobile communications, digital broadcasting and portable Internet, it is necessary to develop a technology for removing noise, fading and inter-symbol interference. As part of the research on noise removal, error correction codes have recently been actively studied to achieve a method of improving communication reliability by effectively reconstructing distorted information.

[0006] The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above information is applicable as prior art with respect to the present disclosure. Summary of the Invention

[0007] Technical issues

[0008] According to certain embodiments of the present disclosure, a method and apparatus are provided for performing decoding based on an LDPC code in a system requiring encoding or re-encoding for parity check, and then performing re-encoding based on the decoding result, CRC, and LDPC syndrome.

[0009] According to certain embodiments of the present disclosure, a method and apparatus are provided for: in a system requiring encoding or re-encoding for parity check, performing decoding based on an LDPC code, and then performing re-encoding based on characteristics of a parity check matrix of the LDPC code, a decoding result, a CRC, and an LDPC syndrome.

[0010] Solution to the problem

[0011] According to one aspect of the present disclosure, embodiments of a method for performing interference cancellation (IC) or successive interference cancellation (SIC) by a receiver in a wireless communication system are provided. According to some embodiments, the method includes: receiving a signal corresponding to a transport block and a code block; performing low-density parity check (LDPC) decoding using the signal and a parity check matrix to decode the code block; identifying a value of a first LDPC syndrome value based on a first square (first parity check bit) of the parity check matrix and at least a portion of the decoded code block; performing CRC detection on the decoded code block; and performing interference cancellation or successive interference cancellation based on the first LDPC syndrome value and the CRC detection result.

[0012] According to another aspect of the present disclosure, an embodiment of a receiver for performing interference cancellation or serial interference cancellation in a wireless communication system is provided. According to some embodiments, the receiver includes: a transceiver; and a controller configured to: receive a signal corresponding to a transport block and a code block, perform low-density parity check (LDPC) decoding using the signal and a parity check matrix to decode the code block, identify a value of a first LDPC syndrome value based on a first square (first parity check bit) of the check matrix and at least a portion of the decoded code block, perform CRC detection on the decoded code block, and perform IC or SIC based on the first LDPC syndrome value and the CRC detection result.

[0013] According to another aspect of the present disclosure, an embodiment of a method for a receiver for processing a multiple-input multiple-output (MIMO) signal associated with at least two layers in a wireless communication system is provided. According to certain embodiments, the method includes: decoding the MIMO signal based on at least a portion of a parity check matrix to determine first low-density parity-check (LDPC) information bits corresponding to a first layer signal of the MIMO signal; determining second parity bits based on the first LDPC information bits and the first parity bits; determining a portion of the first LDPC information bits; and determining a second layer signal of the MIMO signal to determine second LDPC information bits corresponding to the second layer signal, wherein the second layer signal is determined by removing signals corresponding to the portion of the first LDPC information bits, the first parity bits, and the second parity bits from the MIMO signal.

[0014] According to another aspect of the present disclosure, an embodiment of a receiver for processing a multiple-input multiple-output (MIMO) signal associated with at least two layers in a wireless communication system is provided. According to some embodiments, the receiver includes: a transceiver; a controller coupled to the transceiver and configured to: decode the MIMO signal based on at least a portion of a parity check matrix to determine first low-density parity-check (LDPC) information bits corresponding to a first layer signal of the MIMO signal, determine second parity bits based on the first LDPC information bits and the first parity bits, determine a portion of the first LDPC information bits, and determine a second layer signal of the MIMO signal to determine second LDPC information bits corresponding to the second layer signal, wherein the second layer signal is determined by removing signals corresponding to the portion of the first LDPC information bits, the first parity bits, and the second parity bits from the MIMO signal.

[0015] According to another aspect of the present disclosure, an embodiment of a method for receiving and processing a layer division multiplexing (LDM) signal generated from two or more layers of signals is provided. According to various embodiments, the method includes: decoding the LDM signal based on at least a portion of a parity check matrix to determine a first low-density parity check (LDPC) information bit, a first parity check bit, and a second parity check bit corresponding to the first layer signal; determining an LDPC syndrome, the LDPC syndrome corresponding to the decoded first LDPC information bit, the first parity check bit, and the second parity check bit; determining a modified (or transformed) second parity check bit based on the decoded second parity check bit and the determined LDPC syndrome; determining a second layer signal by removing a signal corresponding to the decoded first LDPC information bit, the first parity check bit, and the modified (or transformed) second parity check bit from the LDM signal; and decoding the second layer signal to determine a second LDPC information bit corresponding to the second layer signal, wherein the second parity check bit corresponds to at least a portion of a column of degree 1 in the parity check matrix.

[0016] Beneficial effects of the present invention

[0017] According to some embodiments of the present disclosure, variable-length and variable-rate LDPC codes may be efficiently supported.

[0018] Before proceeding with the following detailed description, it may be helpful to set forth the definitions of certain words and phrases used throughout this patent document: the terms "include" and "comprising," and their derivatives, mean including but not limited to; the term "or" is inclusive, meaning and / or; the phrases "associated with" and "associated therewith," and their derivatives, may mean: include, be included therein, interconnected with, contain, be contained within, connect to or be connected with, be coupled to or be coupled with, be communicative with, cooperate with, intertwine, be juxtaposed, be proximate to, be bound to or be bound with, have, have the property of, and the like; and the term "controller" means any device, system, or portion thereof that controls at least one operation, such device being implemented in hardware, firmware, or software, or some combination of at least two thereof. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.

[0019] In addition, the various functions described below may be implemented or supported by one or more computer programs, each of which is formed of computer-readable program code and embodied in a computer-readable medium. The terms "application" and "program" refer to one or more computer programs, software components, instruction sets, procedures, functions, objects, classes, instances, related data, or portions thereof, suitable for implementation in suitable computer-readable program code. The phrase "computer-readable program code" includes any type of computer code, including source code, object code, and executable code. The phrase "computer-readable medium" includes any type of medium that can be accessed by a computer, such as read-only memory (ROM), random access memory (RAM), hard drive, compact disc (CD), digital video disc (DVD), or any other type of memory. "Non-transitory" computer-readable media excludes: wired, wireless, optical, or other communication links that transmit temporary electrical or other signals. Non-transitory computer-readable media include: media that can permanently store data and media that can store data and then rewrite it, such as rewritable optical discs or erasable storage devices.

[0020] Definitions for certain words and phrases are provided throughout this patent document, those skilled in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts:

[0022] Figure 1 shows an example of the structure of a system LDPC codeword according to various embodiments of the present disclosure;

[0023] Figure 2 An example of a method of representing an LDPC code as a graph according to some embodiments of the present disclosure is shown;

[0024] FIG3A shows an example of cyclic characteristics of a QC-LDPC code according to various embodiments of the present disclosure;

[0025] FIG3B illustrates an example of a cyclic characteristic of a QC-LDPC code according to certain embodiments of the present disclosure;

[0026] Figure 4 An example of a transmitting device according to certain embodiments of the present disclosure is shown in block diagram form;

[0027] Figure 5 An example of a receiving device according to at least one embodiment of the present disclosure is shown in block diagram form;

[0028] 6A illustrates an example of the structure of a message indicating message passing operations of predetermined check nodes and variable nodes for LDPC decoding, according to certain embodiments of the present disclosure;

[0029] 6B illustrates an example of the structure of a message indicating message passing operations of predetermined check nodes and variable nodes for LDPC decoding according to some embodiments of the present disclosure;

[0030] Figure 7 An example of a configuration of an LDPC encoder according to various embodiments is shown in block diagram form;

[0031] Figure 8 shows, in block diagram form, an example of the configuration of a decoding apparatus according to some embodiments;

[0032] Figure 9 shows an example of the structure of an LDPC decoder according to some embodiments;

[0033] Figure 10 shows an example of the structure of a transport block according to certain embodiments;

[0034] Figure 11 shows an example of an LDPC encoding process according to certain embodiments of the present disclosure;

[0035] Figure 12 shows an example of an LDPC decoding process according to certain embodiments of the present disclosure;

[0036] FIG13A illustrates an example of a MIMO system according to certain embodiments of the present disclosure;

[0037] FIG13B illustrates an example of a MIMO system according to certain embodiments of the present disclosure;

[0038] Figure 14 An example of an SCM system according to certain embodiments of the present disclosure is shown;

[0039] Figure 15 An example of the operation of a transmitter in a communication system having a layered structure according to certain embodiments of the present disclosure is shown;

[0040] Figure 16 An example of the operation of a receiver in a communication system having a layered structure according to various embodiments of the present disclosure is shown;

[0041] FIG. 17A illustrates an example of a case where outer coding and inner coding are applied to FEC encoding and decoding, according to certain embodiments of the present disclosure;

[0042] FIG17B shows an example of a case where outer coding and inner coding are applied to FEC encoding and decoding according to some embodiments of the present disclosure;

[0043] Figure 18 shows an example of the structure of a parity check matrix of an LDPC code according to certain embodiments of the present disclosure;

[0044] FIG19A illustrates an example of a parity check matrix for an LDPC code, according to certain embodiments of the present disclosure;

[0045] FIG19B illustrates an example of a parity check matrix for an LDPC code, according to certain embodiments of the present disclosure;

[0046] Figure 20 An example of a decoding process based on LDPC and CRC codes according to various embodiments of the present disclosure is shown;

[0047] Figure 21 An example of a process for encoding a portion of a parity check in a decoding process based on LDPC and CRC codes according to some embodiments of the present disclosure is shown;

[0048] Figure 22 An example of a process for encoding a portion of a parity check in a decoding process based on LDPC and CRC codes according to certain embodiments of the present disclosure is shown;

[0049] Figure 23 An example of a process of encoding a portion of a parity check in a decoding process based on LDPC and CRC codes according to various embodiments of the present disclosure is shown;

[0050] Figure 24 An example of a process of encoding a portion of a parity check in a decoding process based on LDPC and CRC codes according to various embodiments of the present disclosure is shown; and

[0051] Figure 25 An example of a process of encoding a portion of a parity check in a decoding process based on LDPC and CRC codes according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0052] The following discussion Figures 1 to 25 The various embodiments used to describe the principles of the present disclosure in this patent document are merely exemplary and should not be interpreted in any way as limiting the scope of the present disclosure. Those skilled in the art will understand that the principles of the present disclosure can be implemented in any suitably arranged system or device.

[0053] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description of the present disclosure, when a detailed description of a known function or configuration incorporated herein may make the subject matter of the present disclosure quite unclear, its detailed description will be omitted. The terms described below are defined in consideration of the functions in the present disclosure and may vary depending on the user, the user's intention, or the user's habits. Therefore, the definition of the term should be determined based on the content of the entire specification.

[0054] Based on the decision of those skilled in the art, the main ideas of this disclosure can be applied to other communication systems with similar technical backgrounds through some modifications without significantly departing from the scope of this disclosure. For reference, the term "communication system" is a term that generally includes a broadcast system. However, in this disclosure, when the broadcast service of a communication system is the main service, for the sake of more accuracy, the communication system can be referred to as a broadcast system.

[0055] The advantages and features of the present disclosure and the manner in which they are achieved will become apparent by reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments set forth below, but may be implemented in a variety of different forms. The following embodiments are provided solely to fully disclose the present disclosure and to inform those skilled in the art of the scope of the present disclosure, and the present disclosure is limited only by the scope of the appended claims. Throughout the specification, the same or similar reference numerals represent the same or similar elements.

[0056] Low-density parity-check (LDPC) codes, first introduced by Robert G. Gallager in the 1960s, were long forgotten because, at the time, they were too complex to implement due to technological limitations. However, because turbo codes, proposed by Berrou, Glavieux, and Thitimajshima in 1993, achieved performance close to Shannon's channel capacity, extensive analysis of turbo codes' performance and characteristics has been conducted, and much research has been conducted on channel coding based on iterative decoding and graphs. Consequently, when LDPC codes were revisited in the late 1990s and decoding was performed using iterative decoding based on the sum-product algorithm on the Tanner graph corresponding to the LDPC codes, it was discovered that LDPC codes also achieved performance close to Shannon's channel capacity.

[0057] LDPC codes can generally be defined as parity-check matrices and can be represented using a bipartite graph called a Tanner graph. Generally speaking, LDPC codes are parity-check codes that have a low ratio of 1s (i.e., density) in the parity-check matrix when the length is very long, hence the term "low-density" parity-check code. Therefore, for the purposes of this disclosure, the techniques proposed based on LDPC codes can easily extend general parity-check matrix codes.

[0058] Figure 1 An example of the structure of a system LDPC codeword according to certain embodiments of the present disclosure is shown.

[0059] Reference Figure 1 , LDPC codeword reception includes K ldpc bits or symbols of information 102, performs encoding, and generates a ldpc In the following, for ease of description, it is assumed that a codeword including K ldpc bits of information 102 and generates a ldpc The code word of bits is 100. That is, when corresponding to K 1dpc Input bits of information When encoded, the codeword is generated That is, information and codewords are bit streams including a plurality of bits, and information bits and codeword bits refer to bits included in information and codewords, respectively. In general, when LDPC coded bits include bits such as

[0060] When information such as the same is transmitted, it is called a system code. The parity bit may be 104, and the number of parity bits N parity Can be N parity =N ldpc -K ldpc .

[0061] The LDPC code is a linear block code including a process of determining a codeword that satisfies conditions such as the following [Equation 1].

[0062] [Formula 1]

[0063]

[0064] in,

[0065] In [Equation 1], H represents the parity check matrix, C represents the codeword, ci represents the i-th bit of the codeword, and N ldpc Indicates the codeword length. Here, h i Denotes the i-th column of the parity check matrix (H).

[0066] The parity check matrix H consists of N ldpc Column, N ldpc The same as the number of bits of the LDPC codeword. [Equation 1] represents the i-th column (h i ) and the i-th codeword bit c i The sum of the products is "0", so the i-th column (h i ) and the i-th codeword bit c i Related.

[0067] Figure 2 An example of a method of representing an LDPC code as a graph according to certain embodiments of the present disclosure is shown.

[0068] refer to Figure 2 Certain embodiments of a method for representing an LDPC code as a graph are described with reference to an illustrative example of FIG.

[0069] Figure 2 An illustrative example of a parity check matrix H1 of an LDPC code including 4 rows and 8 columns and a Tanner graph representing the LDPC code is shown. Figure 2 , the number of columns of the parity check matrix H1 is 8, so the codeword generated is of length 8. The codeword generated by H1 is an LDPC code, and each column corresponds to 8 bits of code.

[0070] refer to Figure 2 For example, the Tanner graph of an LDPC code that performs encoding and decoding based on the parity check matrix H1 may include eight variable nodes, namely, x1202, x2204, x3206, x4208, x5210, x6212, x7214, and x8216, and four check nodes 218, 220, 222, and 224. The i-th column and the j-th row of the parity check matrix H1 of the LDPC code correspond to the variable nodes x1 and x2, respectively. iThe value at the intersection of the i-th column and the j-th row of the parity check matrix H1 of the LDPC code is 1, that is, Figure 2 As shown, a value other than 0 indicates that there is a connection variable node x in the Tanner graph. i and the edge of the i-th check node.

[0071] In the Tanner graph of an LDPC code, the degree of a variable node and a check node is the number of connecting lines connected to each node, which is equal to the number of non-zero entities in the column or row corresponding to the corresponding node in the parity check matrix of the LDPC code. For example, in Figure 2 In [1], the degrees of variable nodes x1202, x2204, x3206, x4208, x5210, x6212, x7214, and x8216 are 4, 3, 3, 3, 2, 2, 2, and 2, respectively, and the degrees of check nodes 218, 220, 222, and 224 are 6, 5, 5, and 5, respectively. In addition, Figure 2 The number of entities that are not 0 in each column of the parity check matrix H1 corresponds to the matching degrees 4, 3, 3, 3, 2, 2, 2 and 2 respectively. Figure 2 Variable nodes, and, in Figure 2 The number of entities that are not 0 in each row of the parity check matrix H1 corresponds to the matching degrees 6, 5, 5, and 5, respectively. Figure 2 For this reason, the degree of each variable node can be called the column degree or column weight, and the degree of the check node can be called the row degree or row weight.

[0072] According to some embodiments, Figure 2 In the bipartite graph shown, an iterative decoding algorithm based on the sum-product algorithm can be used to decode LDPC codes. The sum-product algorithm is a message passing algorithm, which is an algorithm that exchanges messages through the edges in the bipartite graph and calculates output messages from input messages to variable nodes or check nodes to perform updates.

[0073] Here, the value of the i-th coded bit can be determined based on the message of the i-th variable node. The value of the i-th coded bit can be determined by both hard decision and soft decision. Therefore, the performance of the i-th bit ci of the LDPC codeword can correspond to the performance of the i-th variable node of the Tanner graph, and the performance of the i-th variable node of the Tanner graph can be determined based on the position and number of 1s in the i-th column of the parity check matrix. In other words, N ldpc The performance of codeword bits may depend on the position and number of 1s in the parity check matrix, which means that the performance of LDPC codes is significantly affected by the parity check matrix. Therefore, it is necessary to design an efficient parity check matrix for LDPC codes with excellent performance.

[0074] For parity check matrices used in communication and broadcasting systems, quasi-cyclic LDPC codes (or QC-LDPC codes, hereinafter referred to as QC-LDPC codes) are often used for ease of implementation. QC-LDPC codes generally use quasi-cyclic parity check matrices.

[0075] QC-LDPC codes have a parity check matrix that includes a square matrix of zeros (zero matrix) or a cyclic permutation matrix. A permutation matrix is ​​a matrix in which each row or column has only one 1 and the rest are all 0s. Furthermore, a cyclic permutation matrix is ​​a matrix in which each element of the identity matrix is ​​cyclically rotated to the right.

[0076] Hereinafter, the QC-LDPC code is described in detail.

[0077] First, as shown in [Formula 2], define a circulant permutation matrix P of size L×L = (P i，j ). In [Formula 2], P ij (0≤i, i<Z) is the element (entity) in the i-th row and j-th column of the matrix P.

[0078] [Formula 2]

[0079]

[0080] In the permutation matrix P defined above i (0≤i<L), it can be noted that P is a cyclic permutation matrix obtained by cyclically shifting each element of the identity matrix having a size of L×L to the right i times.

[0081] The simplest parity check matrix H of the QC-LDPC code can be expressed as the following [Equation 3].

[0082] [Formula 3]

[0083]

[0084] If P -1 Defined as a zero matrix of size L×L, then, in [Formula 3], each index of the circulant permutation matrix or zero matrix has a value of {-1, 0, 1, 2, ..., L-1}. In addition, it can be noted that the parity check matrix H of [Formula 3] has a size of mL×nL because it has n column blocks and m row blocks.

[0085] When the parity check matrix of [Equation 3] is full rank, the size of the information bits of the QC-LDPC code corresponding to this parity check matrix is ​​obviously (nm)L. For convenience, the (nm) column blocks corresponding to these information bits are called information column blocks, and the m column blocks corresponding to the remaining parity check bits are called parity check column blocks. When the parity check matrix of [Equation 3] is not full rank, the size of the information bits is larger than (nm)L.

[0086] Typically, a binary matrix of size m×n is obtained by replacing a circulant permutation matrix and a 0 matrix in a parity check matrix of [Formula 3] with 1 and 0, and the binary matrix is ​​determined as a mother matrix or a base matrix M(H) of the parity check matrix H, and an integer matrix of size m×n is obtained by selecting an exponent of the circulant permutation matrix or the 0 matrix as shown in [Formula 3], and the integer matrix is ​​determined as an exponential matrix E(H) of the parity check matrix H.

[0087] [Formula 4]

[0088]

[0089] As a result, an integer included in the exponential matrix corresponds to a cyclic permutation matrix in the parity check matrix, and therefore, for convenience, the exponential matrix can be expressed as a sequence including integers. Generally, a parity check matrix can be expressed not only as an exponential matrix, but also as various sequences that can algebraically represent the same characteristics. Although, in the present disclosure, for convenience, the parity check matrix is ​​expressed as an exponential matrix or a sequence indicating the position of 1 in the parity check matrix, the sequence representation for identifying the position of 1 or 0 included in the parity check matrix is ​​varied. Therefore, the parity check matrix can be represented by various forms of sequences having the same algebraic effect, and is not limited to the method in this specification. The sequence can be referred to as various names, such as LDPC sequence, LDPC code sequence, LDPC matrix sequence, or parity check matrix sequence, in order to distinguish it from other sequences.

[0090] Furthermore, the transmitting / receiving device of the device can directly generate a parity check matrix and perform LDPC encoding and decoding. However, depending on the implementation characteristics, an exponential matrix or a sequence having the same algebraic effect as the parity check matrix can be used to perform LDPC encoding and decoding. Therefore, although the present disclosure describes encoding and decoding using a parity check matrix for convenience, various methods that can achieve the same effect as the parity check matrix are considered for implementing the actual device.

[0091] For reference, algebraically identical effects include the property that two or more different representations can be described as being logically or mathematically identical to one another, or that conversions can be performed between them.

[0092] Although the above example describes the case where the number of cyclic permutation matrices corresponding to one block is one for convenience, the present disclosure is not limited thereto and can also be applied to the case where multiple cyclic permutation matrices are included in one block. For example, when two cyclic permutation matrices are included in the position of the i-th row block and the j-th column block as shown in the following [Equation 5] When the sum of , its exponential matrix can be expressed as [Formula 6]. [Formula 6] shows a matrix in which two integers correspond to the i-th row and the j-th column, and the i-th row and the j-th column correspond to the row block and the column block including the sum of multiple circulant permutation matrices.

[0093] [Formula 5]

[0094]

[0095] [Formula 6]

[0096]

[0097] As described above, although in some embodiments, multiple cyclic permutation matrices can generally correspond to one row block and column block in the parity check matrix of the OC-LDPC code, for convenience, the example provided above only describes the case where one cyclic permutation matrix corresponds to one block. However, the subject matter of the present disclosure is not limited to this. For reference, a matrix of size L×L is called a cyclic permutation matrix.

[0098] A matrix or circulant in which multiple circulant permutation matrices are replicated in 1 row block and column block in this L×L size matrix.

[0099] At the same time, similar to the definition used in the above [Formula 3], another matrix or base matrix of the parity check matrix of the exponential matrix of [Formula 5] and [Formula 6] refers to: a binary matrix obtained by replacing the cyclic permutation matrix and the 0 matrix with 1 and 0, and the sum of multiple cyclic permutation matrices (i.e., permutation matrices) contained in 1 block is simply replaced by 1.

[0100] In some embodiments, the performance of the LDPC code is determined by the parity check matrix. Therefore, it is necessary to effectively design a parity check matrix of the LDPC code with good performance. In addition, a LDPC encoding or decoding method that supports various input lengths and code rates is needed.

[0101] Lifting is not only a method for efficiently designing QC-LDPC codes, but also a method for generating parity check matrices of various lengths from a given exponential matrix, or a method for generating LDPC codewords. That is, lifting is applied to efficiently design very large parity check matrices by configuring the L value to determine the size of a cyclic permutation matrix or a zero matrix from a given small mother matrix according to a specific rule; alternatively, lifting is a method for generating parity check matrices of various lengths or generating LDPC codewords by applying an appropriate L value to a given exponential matrix or a sequence corresponding thereto.

[0102] Examples of lifting methods and characteristics of QC-LDPC codes designed by such lifting are described in the available document: S. Myung, K. Yang, and Y. Kim, "Lifting Methods for Quasi-Cyclic LDPC Codes," IEEE Communications Letters, Vol. 10, pp. 489-491, June 2006.

[0103] First, when the LDPC code C0 is given, the S QC-LDPC codes designed by the lifting method are C1, ..., Cs, and the values ​​corresponding to the row block and column block sizes of the parity check matrix of each QC-LDPC code are L k C0 corresponds to the smallest LDPC code with the mother matrix of C1, ..., Cs as the parity check matrix, and the value of L0 corresponding to the size of the row block and column block is 1. For convenience, each code C k The parity check matrix H k An exponential matrix with size m×n Each index is chosen as the value {-1, 0, 1, 2, ..., L k -1}.

[0104] The traditional lifting method includes steps C0→C1→...→Cs, and has the following conditions: k+1 =q k+1 L k (q k+1 is a positive integer, k = 0, 1, ..., S-1). If the C S The parity check matrix H S , then, all QC-LDPC codes C0, C1, ..., C can be expressed using the following [Equation 7] according to the lifting method. S .

[0105] [Formula 7]

[0106]

[0107] [Formula 8]

[0108] E(H k )≡E(H S )mod L k

[0109] As mentioned above, not only larger QC-LDPC codes C1, ..., C S The method is called lifting, and an appropriate method such as [Equation 7] or [Equation 8] is used to obtain the value of C from a large code. k Generate a small code C i (i=k-1, k-2, ..., 1, 0) is also called boosting.

[0110] In the lifting method of [Equation 7] or [Equation 8], with each QC-LDPC code C k The size of the row block or column block in the parity check matrix corresponds to L k There is a multiple relationship between and, the exponential matrix is ​​selected by a specific method. By improving the algebraic or graphical characteristics of each parity check matrix designed by lifting, the conventional lifting method helps to easily design a QC-LDPC code with an improved error floor characteristic.

[0111] In general, it can be considered that the lifting can be used for LDPC encoding and decoding by changing the values ​​of the elements of the exponential matrix of [Equation 4] for various values ​​of L. For example, when the exponential matrix of [Equation 4] is E(a i，j ), and when the exponential matrix converted (or transformed) according to the L value is When , a conversion (or transformation) equation such as the following [Equation 9] can usually be applied.

[0112] [Formula 9]

[0113]

[0114] or

[0115]

[0116] In the above [Formula 9], f(x, L) can be defined in various forms, and for example, the definition of the following [Formula 10] can be used.

[0117] [Equation 10]

[0118]

[0119] or

[0120]

[0121] or

[0122]

[0123] In the above [Formula 10], mod(a, b) represents a modulo b operation on a, and D represents a constant, which is a predefined positive integer.

[0124] For reference, although the reference value for applying the conversion (or transformation) equation f in the conversion equation of [Equation 9] is 0, the reference value may be configured differently depending on the block size L. In addition, in the representation of the exponential matrix or the LDPC sequence, when the exponent corresponding to the 0 matrix is ​​excluded and defined from the beginning, the rule that the exponent value is less than 0 may be omitted in [Equation 9].

[0125] According to certain embodiments, LDPC encoding and decoding are described based on multiple exponential matrices or LDPC sequences within a predetermined base matrix. Specifically, the base matrix is ​​fixed to 1, and LDPC encoding and decoding are performed by determining the exponential matrix or the sequence of the LDPC code defined within the base matrix and applying a boosting technique to the exponential matrix or sequence, with the boosting technique being appropriate for the block size within each block size group. In this method, the elements or numbers included in the exponential matrix of the LDPC code or LDPC sequence can have different values, but these elements or numbers are located in exactly the same position within the base matrix. As described above, the exponential matrix of the LDPC sequence refers to the cyclic shift values ​​of the exponents of each cyclic permutation matrix, i.e., the bits or elements included in the cyclic permutation matrix. By arranging all elements or numbers to be identical, it is easier to identify the positions of the bits corresponding to the corresponding cyclic permutation matrix. For example, the exponential matrix or LDPC sequence corresponds to the cyclic shift values ​​of the bits corresponding to the block size (Z), and thus the exponential matrix can be variously referred to as a shift matrix, a shift value matrix, a shift sequence, or a shift value sequence.

[0126] As shown in the following [Equation 11], the block size (Z) to be supported is divided into multiple block size groups (or sets). It should be noted that the block size (Z) corresponds to the size Z×Z of the cyclic permutation matrix or cyclic matrix in the parity check matrix of the LDPC code.

[0127] [Equation 11]

[0128] Z1={2,4,8,16,32,64,128,256}

[0129] Z2={3,6,12,24,48,96,192,384}

[0130] Z3={5,10,20,40,80,160,320}

[0131] Z4={7,14,28,56,112,224}

[0132] Z5={9,18,36,72,144,288}

[0133] Z6={11,22,44,88,176,352}

[0134] Z7={13,26,52,104,208}

[0135] Z8={15,30,60,120,240}

[0136] The above [Equation 11] is only a non-limiting example, and other block sizes (Z) may be included in the block size group of the above [Equation 11]. As shown in the following [Equation 12], a block size included in an appropriate subset may be used, or an appropriate value may be added to or excluded from the block size group (or set) of [Equation 11] or [Equation 12] and used.

[0137] [Equation 12]

[0138] Z1'={8,16,32,64,128,256}

[0139] Z2′={12,24,48,96,192,384}

[0140] Z3′={10,20,40,80,160,320}

[0141] Z4′={14,28,56,112,224}

[0142] Z5'={9,18,36,72,144,288}

[0143] Z6'={11,22,44,88,176,352}

[0144] Z7'={13,26,52,104,208}

[0145] Z8'={15,30,60,120,240}

[0146] In the above [Equation 11] or [Equation 12], the characteristics of the block size groups include, but are not limited to, different granularities and ratios in the block size groups, and adjacent block sizes are all the same integer. In other words, the block sizes included in a group have a divisor or multiple relationship. The exponential matrix corresponding to the p-th group (p = 1, 2, ..., 8) is And, when the exponential matrix corresponding to Z included in the pth group is E p (Z)=(e i，j (Z)) when using f p (x, Z) = x(mod Z), the sequence conversion (or transformation) method shown in [Equation 9] is applied. That is, for example, as shown in the following [Equation 13], when the block size Z is determined to be Z = 28, for the exponential matrix (or LDPC sequence) corresponding to the fourth block size group including Z = 28 The exponential matrix (or LDPC sequence) E4(28)=(e i，j (28)) each element e i，j (28).

[0147] [Equation 13]

[0148]

[0149] or

[0150]

[0151] The conversion (or transformation) shown in the above [Formula 13] can also be expressed as the following [Formula 14].

[0152] [Equation 14]

[0153] E p (Z)=E p (modZ), Z∈Z p

[0154] For example, although it is assumed that the lifting or exponential matrix conversion (or transformation) method from [Equation 9], [Equation 10], or [Equation 11] to [Equation 14] is applied to the entire exponential matrix corresponding to the parity check matrix, the conversion (or transformation) method can be partially applied to the exponential matrix.

[0155] For example, in many cases, the submatrix corresponding to a parity check bit of the parity check matrix generally has a special structure for efficient coding. In this case, the coding method or complexity of the boosting may change. Therefore, in order to maintain the same coding method or complexity, boosting is applied to the submatrix corresponding to the parity check in the parity check matrix, and boosting may not be applied to part of the exponential matrix, or the boosting applied to the submatrix corresponding to the information bit may be different from the boosting applied to the exponential matrix. In other words, a boosting method applied to a sequence corresponding to the information bit and a boosting method applied to a sequence corresponding to the parity check bit can be differently configured in the exponential matrix, and a fixed value can be used without the need for sequence conversion (or transformation) because boosting is not applied to the partial sequence corresponding to the parity check bit or the entire sequence according to the situation.

[0156] Figure 4 An example of a transmitting apparatus according to certain embodiments of the present disclosure is shown in block diagram format.

[0157] Specifically, refer to Figure 4 In the illustrative example of FIG, in order to process variable-length input bits, the transmitting apparatus 400 may include a segmentation unit 410, a zero padding unit 420, an LDPC encoder 430, a rate matching unit 440, a modulator 450, etc. The rate matching unit 440 may include an interleaver 441 and a puncture / repetition / zero removal unit 442.

[0158] Here, in Figure 4 The elements shown in the illustrative example of are elements configured to perform encoding and modulation on variable length input bits. This is just one example. In some cases, Figure 4 Some of the elements shown in FIG. 5 may be omitted or changed, and other elements may be added.

[0159] At the same time, the transmitting device 400 determines the required parameters (for example, parameters for input bit length, modulation and code rate (ModCod), zero padding or zero shortening, parameters for LDPC code, code rate or codeword length of information, parameters for interleaving, parameters for repetition and redundancy removal, modulation scheme, etc.), and encodes the input bits based on the determined parameters so as to send the encoded input bits to the receiving device 500.

[0160] Since the number of input bits is variable, if the number of input bits is greater than a preset threshold, the input bits can be segmented into blocks of length less than or equal to the preset value. Each segmented block corresponds to an LDPC code block. If the number of input bits is less than or equal to the threshold, the input bits are not segmented and correspond to a single LDPC code block.

[0161] In certain embodiments, the transmitting device 400 may pre-store various parameters for encoding, interleaving, and modulation. Here, the parameters used for encoding may include at least one of the code rate, codeword length, and parity check matrix of the LDPC code. In addition, the parameters used for interleaving may include information about the interleaving rule, and the parameters used for modulation may include information about the modulation scheme. In addition, the information about puncturing may include the puncturing length. In addition, the information about repetition may include the repetition length. In the case of using the parity check matrix proposed in the present disclosure, the information about the parity check matrix may include the exponential value of the cyclic matrix or the value corresponding thereto.

[0162] In this case, each element configuring the transmitting device 400 may perform an operation using these parameters.

[0163] Meanwhile, although not shown, according to some embodiments, the transmitting device 400 may further include a controller (not shown) for controlling the operation of the transmitting device 400 .

[0164] Figure 5 An example of a receiving apparatus according to certain embodiments of the present disclosure is shown in block diagram format.

[0165] Specifically, if Figure 5 As shown in the non-limiting example of , in order to process variable length information, the receiving apparatus 500 may include a demodulator 510, a rate dematching unit 520, an LDPC decoder 530, a zero removal unit 540, and a desegmentation unit 550. The rate dematching unit 520 may include a log-likelihood ratio (LLR) insertion unit 522, an LLR combiner 523, a deinterleaver 524, and the like.

[0166] here, Figure 5 The components shown in FIG. 1 are used to implement Figure 4 The elements shown correspond to the functions of the elements. This is only a non-limiting example. Depending on the circumstances, some elements may be omitted or changed, or other elements may be added.

[0167] In the present disclosure, the parity check matrix can be read using a memory, can be pre-provided by the transmitting device or the receiving device, or can be directly generated in the transmitting device or the receiving device. In addition, the transmitting device can store or generate a sequence or index matrix corresponding to the parity check matrix and apply the sequence or index matrix to encoding. Similarly, the receiving device can store or generate a sequence or index matrix corresponding to the parity check matrix and apply the sequence or index matrix to decoding.

[0168] In the following, reference will be made to Figure 5 The operation of the receiver is described in detail with reference to an illustrative example of FIG.

[0169] References Non-Restrictive Figure 5 , the demodulator 510 demodulates the signal received from the transmitting device 400.

[0170] Specifically, the demodulator 510 corresponds to the modulator 450 of the transmitting device 400 and receives and demodulates a signal transmitted from the transmitting device 400 , thereby generating a value corresponding to a bit transmitted from the transmitting device 400 .

[0171] To this end, the receiving apparatus 500 may pre-store information about a modulation scheme for performing modulation according to a mode in the transmitting apparatus 400. Therefore, the demodulator 510 may demodulate a signal received from the transmitting apparatus 400 according to the mode and generate a value corresponding to an LDPC codeword bit.

[0172] Meanwhile, a value corresponding to a bit transmitted from the transmitting apparatus 400 may be a value of a likelihood ratio (LR) or a value of a log likelihood ratio (LLR).

[0173] Specifically, the LR value represents the ratio of the probability that a bit sent by transmitting device 400 is 0 to the probability that a bit sent by transmitting device 400 is 1. The LLR value can be expressed as the logarithm of the ratio of the probability that a bit sent by transmitting device 400 is 0 to the probability that a bit sent by transmitting device 400 is 1. Alternatively, the LR or LLR value can be obtained through hard decision based on the probability, the ratio between probabilities, or the logarithm of the ratio between probabilities. Therefore, the LR or LLR value can be represented by the bit value itself. The LR or LLR value can also be expressed as a predefined representative value based on the interval to which the probability, the ratio between probabilities, or the logarithm of the ratio between probabilities falls. Examples of methods for determining a predefined representative value based on the probability, the ratio between probabilities, or the interval to which the logarithm of the ratio between probabilities falls include methods that take quantization into account. In addition, various other values ​​corresponding to the probability, the ratio between probabilities, or the logarithm of the ratio between probabilities can be used.

[0174] In the present disclosure, in order to explain the reception method and operation of the device, an operation based on an LLR value has been described for convenience, but the present disclosure is not limited thereto.

[0175] The demodulator 510 includes a function of performing multiplexing (not shown) of LLR values. Specifically, the multiplexer (not shown) is an element corresponding to the bit demultiplexer (not shown) of the transmitting apparatus 400 and can perform operations corresponding to the bit demultiplexer (not shown).

[0176] To this end, the receiving apparatus 500 may pre-store information about parameters used by the transmitting apparatus 400 in order to perform demultiplexing and block interleaving operations. Therefore, the multiplexer (not shown) may reversely perform demultiplexing and block interleaving operations on the LLR values ​​corresponding to the cell words (information using the received LDPC codeword symbols as vector values), which are performed in the bit demultiplexer (not shown). Therefore, the LLR values ​​corresponding to the cell words may be multiplexed on a single bit basis.

[0177] The rate dematching unit 520 may additionally insert an LLR value into the LLR value output from the demodulator 510. In this case, the rate dematching unit 520 may insert a predetermined LLR value between the LLR values ​​output from the demodulator 510.

[0178] exist Figure 5 In a non-limiting example, the rate dematching unit 520 is an element corresponding to the rate matching unit 440 of the transmitting apparatus 400 and may perform operations corresponding to the interleaver 441 and the puncture / repetition / zero removal unit 442 .

[0179] First, the rate dematching unit 520 performs deinterleaving corresponding to the interleaver 441 of the transmitter. The LLR insertion unit 522 can insert LLR values ​​corresponding to the zero bits at the positions of the padded zero bits in the LDPC codeword into the output value of the deinterleaver 524. In some embodiments, the LLR values ​​corresponding to the padded zero bits (i.e., shortened zero bits) can be ∞ or -∞. However, ∞ or -∞ are theoretical values ​​and, therefore, can actually be the maximum or minimum LLR values ​​used in the receiving apparatus 500.

[0180] To this end, the receiving apparatus 500 may pre-store information about parameters used by the transmitting apparatus 400 to pad zero bits. Therefore, the rate dematching unit 520 may determine the positions of the zero bits padded in the LDPC codeword and insert LLR values ​​corresponding to the shortened zero bits at the corresponding positions.

[0181] In various embodiments, the LLR insertion unit 522 of the rate dematching unit 520 may insert LLR values ​​corresponding to punctured bits at positions in the LDPC codeword where bits are punctured. Here, the LLR values ​​corresponding to the punctured bits may be zero or another predetermined value. Generally speaking, puncturing parity bits of degree 1 does not improve performance during LDPC decoding. Therefore, if LLRs are not inserted at positions corresponding to some or all punctured positions, puncturing parity bits of degree 1 may not be used during LDPC decoding. However, to improve the efficiency of the parallel-based LDPC decoding process, the LLR insertion unit 522 may insert predetermined LLRs at positions corresponding to some or all order 1 punctured bits, regardless of the improvement in decoding performance.

[0182] To this end, the receiving apparatus 500 may pre-store information about the parameters used by the transmitting apparatus 400 in order to perform puncturing. Therefore, the LLR insertion unit 522 may insert LLR values ​​corresponding to punctured bits (e.g., LLR=0) at locations where LDPC information bits or parity bits are punctured. However, this process may be omitted at locations where some parity bits are punctured.

[0183] LLR combiner 523 can combine, that is, add the LLR values ​​output from LLR insertion unit 522 and demodulator 510. Specifically, LLR combiner 523 is a component corresponding to puncture / repeat / zero removal unit 442 of transmitter 400 and can perform operations corresponding to repetition unit 442. First, LLR combiner 523 can combine the LLR value corresponding to the repeated bit with another LLR value. Here, the other LLR value can be the LLR value of the bit (i.e., the LDPC information bit or parity bit selected to be repeated) that serves as the basis for generating the repeated bit in transmitter 400.

[0184] That is, in this non-limiting example, the transmitting apparatus 400 selects LDPC coded bits, repeats the selected LDPC coded bits between the LDPC information bits and the LDPC parity bits, and transmits the repeated LDPC coded bits to the receiving apparatus 500. Therefore, the LLR values ​​of the LDPC coded bits may include the LLR values ​​of the repeated LDPC coded bits and the LLR values ​​of the non-repeated LDPC coded bits. The LLR combiner 523 may combine the LLR values ​​corresponding to the same LDPC coded bits.

[0185] To this end, the receiving apparatus 500 may pre-store information about parameters for repetition in the transmitting apparatus 400. Therefore, the LLR combiner 523 may determine the LLR value of the repeated LDPC coded bits and combine the LLR value of the repeated LDPC coded bits with the LLR value of the LDPC coded bits as a basis for repetition.

[0186] In addition, the LLR combiner 523 can combine the LLR value corresponding to the retransmission or incremental redundancy (IR) bit with another LLR value. Here, the other LLR value can be an LLR value for part or all of the LDPC codeword bits, which serves as the basis for generating the retransmission or IR bit in the transmitting apparatus 400.

[0187] As described above, when a NACK occurs in HARQ, the transmitting apparatus 400 may transmit all or part of the codeword bits to the receiving apparatus 500 .

[0188] Therefore, the LLR combiner 523 may combine LLR values ​​for bits received through retransmission or IR with LLR values ​​for LDPC codeword bits received through a previous frame.

[0189] According to various embodiments, the receiving apparatus 500 may pre-store information about parameters for retransmitting or generating IR bits in the transmitting apparatus 400. Therefore, the LLR combiner 523 may determine the LLR value or the number of IR bits for retransmission, and may combine the determined LLR value with the LLR value for the LDPC coded bit as a basis for generating the retransmission bit.

[0190] The deinterleaver 524 may deinterleave the LLR values ​​output from the LLR combiner 523 .

[0191] Specifically, the deinterleaver unit 524 is an element corresponding to the interleaver 441 of the transmitting apparatus 400 , and may perform operations corresponding to those of the interleaver 441 .

[0192] In some embodiments, the receiving device 500 may pre-store information about the parameters used by the transmitting device 400 to perform interleaving. Therefore, with respect to the LLR values ​​corresponding to the transmitted LDPC coded bits, the deinterleaver 524 may reverse the interleaving operation performed by the interleaver 441 to deinterleave the LLR values ​​corresponding to the transmitted LDPC coded bits.

[0193] Based on the LLR value output from the rate dematching unit 520 , the LDPC decoder 530 may perform LDPC decoding.

[0194] Specifically, the LDPC decoder 530 is an element corresponding to the LDPC encoder 430 of the transmitting apparatus 400 , and may perform an operation corresponding to the LDPC encoder 430 .

[0195] According to some embodiments, the receiving apparatus 500 may pre-store information about parameters used in the transmitting apparatus 400 in order to perform LDPC encoding according to the mode. Therefore, according to the mode, the LDPC decoder 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520.

[0196] For example, based on an iterative decoding method based on a sum-product algorithm, the LDPC decoder 530 may perform LDPC decoding according to the LLR value output from the rate dematching unit 520; and, based on the LDPC decoding, the LDPC decoder 530 may output error-corrected bits.

[0197] The zero removal unit 540 may remove zero bits from the bits output from the LDPC decoder 530 .

[0198] Specifically, the zero removal unit 540 is an element corresponding to the zero padding unit 420 of the transmitting apparatus 400 , and may perform operations corresponding to the zero padding unit 420 .

[0199] According to some embodiments, the receiving apparatus 500 may pre-store information about parameters used to pad zero bits in the transmitting apparatus 400. Therefore, the zero removal unit 540 may remove the zero bits padded by the zero padding unit 420 from the bits output from the LDPC decoder 530.

[0200] The desegmentation unit 550 is an element corresponding to the segmentation unit 410 of the transmitting apparatus 400 , and may perform an operation corresponding to the segmentation unit 410 .

[0201] To this end, the receiving device 500 may pre-store information about the parameters used by the transmitting device 400 to perform segmentation. Therefore, the desegmentation unit 550 can combine the bits (i.e., the segments for the variable-length input bits output from the zero removal unit 540) and thus reconstruct the bits before segmentation.

[0202] In some embodiments, a method based on Figure 2 The iterative decoding algorithm of the sum-product algorithm on the bipartite graph shown is used to decode the LDPC code, and the sum-product algorithm is a message passing algorithm.

[0203] Hereinafter, a message passing operation generally used for LDPC decoding will be described with reference to the illustrative examples shown in FIG. 6A and FIG. 6B .

[0204] 6A and 6B illustrate examples of performing a message passing operation at any checksum variable node to perform LDPC decoding, according to certain embodiments of the present disclosure.

[0205] FIG6A shows a plurality of variable nodes 610, 620, 630, and 640 connected to a check node m 600 and the check node m 600. Referring to the non-limiting example of FIG6A, the T shown n′，m represents the message passed from variable node n′ 610 to check node m 600, and E n，m Indicates a message transmitted from check node m 600 to variable node n 630. Here, the set of all variable nodes connected to check node m 600 is defined as "N(m)", and the set excluding variable node n 630 from set N(m) is defined as "N(m)\n".

[0206] In this case, the message update rule based on the sum-product algorithm can be expressed as follows [Equation 15].

[0207] [Equation 15]

[0208]

[0209]

[0210] Here, the symbol (E n，m ) indicates message E n，m + and - signs, and |E n，m | indicates message E n，m In some embodiments, the function φ(x) can be expressed as follows [Equation 16].

[0211] [Equation 16]

[0212]

[0213] 6B, a plurality of check nodes 660, 670, 680, and 690 are shown connected to a variable node x 650 and a variable node x 650. In addition, the E y′，x represents the message passed from the check node y′ 660 to the variable node x 650, and T y，x represents a message transmitted from variable node x 650 to check node y 680. Here, the set of all check nodes connected to variable node x 650 is defined as "M(x)," and the set excluding check node y 680 from M(x) is defined as "M(x)\y." In this case, the message update rule based on the sum-product algorithm can be expressed as follows [Equation 17].

[0214] [Equation 17]

[0215]

[0216] Where Ex represents the initial message value of the variable node x.

[0217] In addition, the bit value of node x can be determined as follows [Equation 18].

[0218] [Equation 18]

[0219]

[0220] In this case, according to P x The value of determines the coded bits corresponding to node x.

[0221] For reference, the degree or weight of an LDPC code can represent a line connected to a variable node processor or a check node processor in terms of hardware, and can therefore be represented as a line, a (inter)connected line, an edge, etc. Furthermore, the degree or weight of an LDPC code can represent the number of messages (e.g., LLRs or values ​​corresponding to LLRs) input from, processed in, or output to a node processor (or node unit) in the hardware, or the degree or weight of an LDPC code can represent a value corresponding to the number of messages. In the hardware, the structure of input / output messages, processors, and connecting lines can also be represented as an interconnection network or a shift network.

[0222] Since the scheme shown with reference to FIG6A and FIG6B is a general decoding scheme, its detailed description will be omitted. In addition to the scheme described in FIG6A and FIG6B, other schemes can be applied to determine the message values ​​passed at the variable nodes and the check nodes. Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, "Factor Graphs and the Sum-Product Algorithm," IEEE Transactions on Information Theory, Vol. 47, No. 2, February 2001, pp. 498-519, incorporated herein by reference, shows another example of a decoding scheme.

[0223] Figure 7 An example of a detailed configuration of an LDPC encoder according to certain embodiments of the present disclosure is shown in a block diagram format.

[0224] K ldpc The bits can be used to configure K for the LDPC encoding apparatus 700. ldpc LDPC information bits i=(i0, i1, ..., ). The LDPC encoding apparatus 700 systematically encodes these K ldpc LDPC information bits are coded, so N ldpc LDPC codeword C = (c0, c1, ..., c Nldpc-1 )=(i0,i1,...,i Kldpc-1 ,p0,p1,...,p Nldpc-Kldpc-1 ).

[0225] As described in [Equation 1], the codeword is determined so that the product of the LDPC codeword and the parity check matrix becomes a zero vector. Figure 7 As a non-limiting example, the LDPC encoding apparatus 700 includes an LDPC encoder 710. Based on a parity check matrix or an exponential matrix or sequence corresponding thereto, the LDPC encoder 710 may perform LDPC encoding on input bits to generate an LDPC codeword. Here, the LDPC encoder 710 may perform LDPC encoding using a parity check matrix defined differently according to a code rate (i.e., a code rate of an LDPC code).

[0226] In some embodiments, the LDPC encoding device 700 may further include a memory (not shown) for pre-storing information about the code rate, codeword length, and parity check matrix of the LDPC code, and the LDPC encoder 710 may perform LDPC encoding using the above information. In the case of using the parity check matrix proposed in the present disclosure, the information about the parity check matrix may include information about the exponential value of the circulant matrix.

[0227] Figure 8 An example of a configuration of a decoding apparatus according to certain embodiments of the present disclosure is shown in a block diagram format.

[0228] according to Figure 8 For non-limiting example, the decoding device 800 may include an LDPC decoder 810.

[0229] The LDPC decoder 810 performs LDPC decoding on the LDPC codeword based on the parity check matrix or an exponential matrix or sequence corresponding thereto.

[0230] For example, by an iterative decoding algorithm, LDPC decoder 810 can perform LDPC decoding by delivering LLR values ​​corresponding to LDPC codeword bits to generate information bits. Here, LLR values ​​are channel values ​​corresponding to LDPC codeword bits and can be represented in various ways.

[0231] In this case, use Figure 7 In the illustrative example of LDPC encoder 710 shown in FIG, a transmitter may generate an LDPC codeword.

[0232] In this case, the LDPC decoder 810 may perform LDPC decoding by using a parity check matrix differently defined according to a code rate (ie, a code rate of an LDPC code).

[0233] Figure 9 An example of a diagram illustrating the structure of an LDPC decoder according to certain embodiments of the present disclosure.

[0234] Meanwhile, as described above, the LDPC decoder 810 may perform LDPC decoding using an iterative decoding algorithm, and here, the LDPC decoder 810 may be configured to Figure 9 The same structure as shown. However, Figure 9 The detailed configuration shown is only an example of one possible configuration.

[0235] according to Figure 9 illustrative example, the decoding device 900 includes an input processor 901, a memory 902, a variable node operator 904, a controller 906, a check node operator 908, an output processor 910, and the like.

[0236] The input processor 901 stores input values. Specifically, the input processor 901 may store LLR values ​​of a reception signal received through a radio channel.

[0237] Based on the parity check matrix corresponding to the block size (i.e., the length of the codeword) and the code rate of the received signal received through the radio channel, the controller 904 determines: the number of values ​​input to the variable node operator 904, the address value in the memory 902, the number of values ​​input to the check node operator 908, and the address value in the memory 902.

[0238] The memory 902 stores input data and output data of the variable node operator 904 and the check node operator 908 .

[0239] Based on the address information of the input data and the number of pieces of input data received from the controller 906, the variable node operator 904 receives a plurality of pieces of data from the memory 902 to perform a variable node operation. Thereafter, based on the address information of the output data and the information about the number of pieces of output data received from the controller 906, the variable node operator 904 stores the result obtained from the variable node operation in the memory 902. Furthermore, based on the data received from the input processor 901 and the memory 902, the variable node operator 904 inputs the result obtained from the variable node operation to the output processor 910. Here, the variable node operation has been described above based on FIG. 6.

[0240] According to some embodiments, based on the address information of the input data and the information about the number of pieces of input data received from the controller 906, the check node operator 908 receives data from the memory 902 to perform a check node operation. Thereafter, based on the address information of the output data and the information about the number of pieces of output data received from the controller 906, the check node operator 908 stores the result obtained by the check node operation in the memory 902. Here, the check node operation has been described above based on FIG. 6 .

[0241] Based on the data received from the variable node operator 904, the output processor 910 makes a hard decision on whether each information bit of the codeword of the sender is 0 or 1, and then outputs the result of the hard decision. The output value of the output processor 910 becomes the final decoded value. In this case, in Figure 6, the hard decision can be made based on the value obtained by adding all the message values ​​input to a variable node (the initial message value and all the message values ​​input from the check nodes).

[0242] Meanwhile, the memory 902 of the decoding apparatus 900 may pre-store information about the code rate, codeword length, and parity check matrix of the LDPC code, and the LDPC decoder 810 may perform LDPC decoding using this information. However, this is merely an example, and the corresponding piece of information may be provided from the transmitting side.

[0243] Figure 10 An example of the structure of a transport block according to certain embodiments of the present disclosure is shown.

[0244] refer to Figure 10 As a non-limiting example, to make the segments equal in length, you can add <null>(null value) bits. In addition, to match the information length of the LDPC code, you can add <null>(null) bit.

[0245] In communications and broadcasting systems, a method for applying various block sizes based on QC-LDPC codes has been described to support LDPC codes of various lengths. Typically, a lifting method, such as that described in [Equations 9] and

[10] , is used to appropriately transform (or transform) a sequence from an LDPC exponential matrix or sequence and apply it to various block sizes L. This approach offers many advantages because the system only needs to be implemented for one or a few sequences. However, as the number of block sizes to be supported increases, designing LDPC codes that perform well for all block sizes becomes extremely difficult.

[0246] In 5G NR, the transport block size (TBS) to be sent can be determined, and then, based on the TBS size determined by the following [base matrix determination method] and the code rate represented by the modulation and coding scheme (for reference, in the 5G NR standard, the base matrix can be represented as a base graph), one of two different base matrices of the LDPC code used for LDPC encoding or decoding can be determined.

[0247] [Method for determining basis matrix]

[0248] Based on the TBS size and the code rate indicated by the MCS (Modulation and Coding Scheme), the LDPC basis matrix for LDPC encoding and decoding of a transport block with a transport block size of A (TBS=A) can be determined as follows:

[0249] If A≤292 or A≤3824, and R≤0.67 or R≤0.25, LDPC encoding may be performed using LDPC base matrix 2.

[0250] Otherwise, LDPC encoding may be performed using LDPC base matrix 1.

[0251] In addition, according to the determined TBS, the number of CRC bits (L) to be added to the transport block can be determined as follows TB ).

[0252] [Method for determining the number of transport block CRC bits]

[0253] According to the TBS value, the CRC bit size L of the transport block with transport block size A (TBS=A) TB The value can be configured differently as follows.

[0254] If A>3824, then L TB =24, otherwise L TB =16.

[0255] Based on the total number of bits of the transport block (B = A + L) (in the total number of bits, CRC is added to the determined TBS size), by determining appropriate code blocks from the transport block, LDPC encoding is performed on each code block. At this time, in the 5G NR standard, the process of determining the code block size (CBS) is as follows:

[0256] [CBS Determination Method]

[0257] The input bit sequence for code block segmentation can be expressed as b0, b1,..., b B-1 (Here, B > 0). If B is greater than the maximum code block size K cb , then, segment the input bit sequence and append a CRC of L = 24 bits to each code block. The maximum code block size of LDPC base matrix 1 corresponds to K cb = 8448, while the maximum code block size of LDPC base matrix 2 corresponds to K cb = 3840.

[0258] Operation 1: The number of code blocks C can be determined.

[0259] - If B ≤ K cb , then L = 0, and C = 1, B' = B.

[0260] - Otherwise, then L = 24, and C = [B / (K cb - L)], B' = B + C × L.

[0261] Operation 2: The bits output through code block segmentation are cr0, cr1,..., cr(Kr - 1), where r can represent the code block number (here, 0 ≤ r < C), and Kr (= K) can represent the number of bits of the code block for code block number r. Here, K, that is, the number of bits included in each code block, can be calculated as follows:

[0262] - K' = B' / C;

[0263] - In the case of LDPC base matrix 1, K b = 22.

[0264] - In case 2 of LDPC base matrix 1,

[0265] If B > 640, then, K b = 10;

[0266] If 560 < B ≤ 640, then, K b = 9;

[0267] If 192 < B ≤ 560, then, K b = 8;

[0268] If B≤192, then K b =6.

[0269] Operation 3: Among the Z values ​​in [Table 1], determine the value that satisfies K b The minimum value Zc of ×Z≥K′. K=22Z c Configuration for LDPC basis matrix 1, K = 10Z c Configuration for LDPC basis matrix 2.

[0270] [Table 1]

[0271] Collection Index (iLs) Raise the size (Z) of the collection 0 {2，4，8，16，32，64，128，256} 1 {3，6，12，24，48，96，192，384} 2 {5，10，20，40，80，160，320} 3 {7，14，28，56，112，224} 4 {9，18，36，72，144，288} 5 {11，22，44，88，176，352} 6 {13，26，52，104，208} 7 {15，30，60，120，240}

[0272] In operation 2 of [CBS determination method], in the base matrix (or base graph) or parity check matrix of the LDPC code, K b The values ​​are respectively the values ​​corresponding to the columns or column blocks corresponding to the LDPC information bits, and K b The value can be compared with the maximum value of LDPC information bits (=K b Z c ) without performing zero shortening or zero padding. For example, even if the number of columns (or column blocks) corresponding to information bits in the LDPC base matrix 2 or the parity check matrix corresponding thereto is 10, in K b When the number of bits is set to 6, LDPC encoding / decoding is basically performed on the maximum 6Zc bits of information bits, and the parity check matrix is ​​used for at least (10-K b )Z c =4Z c The information bits corresponding to the columns are zero-shortened or zero-padded. Here, zero-shortening or zero-padded may mean that the transmitter and the receiver may assign a committed bit value such as 0 and may not use the corresponding part in the parity check matrix.

[0273] [Table 1] shows the candidate values ​​of the lifting size Z for LDPC encoding and decoding. LS , each Z value is included in a predetermined specific set. If the Z value is determined in operation 3 of [CBS determination method], then the set of Z values ​​or the index i corresponding thereto may be determined. LS A set of values, and the parity check matrix of the LDPC code corresponding to each index or the sequence corresponding thereto can also be determined. By applying a modular operation based on the lifting size Z to the parity check matrix of the LDPC code determined as described above or the sequence corresponding thereto, the parity check matrix or sequence is converted (or transformed), thereby supporting encoding and decoding of LDPC codes of various lengths. Even in 5G NR, each number contained in the parity check matrix or sequence of the LDPC code represents a value corresponding to a circulant permutation matrix (circulant permutation matrix or circular permutation matrix).

[0274] When a method for determining the value of the boosting size Z is predetermined, in some embodiments, the value of Z may be determined based on a range of a base matrix and a TBS value (or a value obtained by adding the number of CRC bits and the number of TBS). For example, when applying the TBS determination method defined in the 5G NR standard specification as well as the [base matrix determination method], [transport block CRC bit number determination method], and [CBS determination method], a set of boosting sizes such as [Table 2] may be defined and used, as shown below.

[0275] [Table 2]

[0276] Collection Index (iLs) Raise the size (Z) of the collection 0 {8,16,32,64,128,256} 1 {12,24,48,96,192,384} 2 {10,20,40,80,160,320} 3 {7,14,28,56,112,224} 4 {18,36,72,144,288} 5 {11,22,44,88,176,352} 6 {26,52,104,208} 7 {15,30,60,120,240}

[0277] [Table 2] shows a set of lifting sizes configured by excluding 2, 3, 4, 5, 6, 9, and 13 from [Equation 11] and [Table 1]. Therefore, since the minimum lifting size is 7 in the LDPC code-based communication system adopting [Table 2] as the lifting size, it can be seen that each column block of the parity check matrix of the LDPC code configured for LDPC encoding and decoding includes at least 7 columns.

[0278] Figure 11 and Figure 12 Examples of LDPC encoding and decoding processes based on a designed base matrix or exponential matrix according to various embodiments of the present disclosure are shown.

[0279] Figure 11 An example of an LDPC encoding process according to certain embodiments of the present disclosure is shown.

[0280] First, if Figure 11 As shown in operation 1110 of , the transmitter determines a transport block size (TBS) to be transmitted. Then, in operation 1120, the transmitter determines whether the TBS is greater than a maximum CBS or is equal to or less than the maximum CBS.

[0281] According to some embodiments, in operation 1130, if the TBS is greater than the maximum CBS, the transmitter performs segmentation on the transport block to re-determine the CBS, and if the TBS is less than or equal to the maximum CBS, the segmentation operation is omitted and the TBS is determined as the CBS.

[0282] In operation 1140, based on the CBS, the transmitter determines a value of a block size (Z) to be applied to LDPC encoding.

[0283] In operation 1150, the transmitter appropriately determines an LDPC index matrix or sequence according to the value of TBS, CBS, or block size (Z).

[0284] In addition, in operation 1160, based on the determined block size, index matrix or sequence, the transmitter performs LDPC encoding. For reference, according to some circumstances, operation 1150 may include a process of converting (or transforming) the determined LDPC index matrix or sequence based on the determined block size. Obviously, the LDPC index matrix, sequence or parity check matrix for LDPC encoding can be determined in various ways based on TBS or CBS according to the system. For example, first, based on TBS, the base matrix can be determined, and then, based on the determined base matrix and CBS, the LDPC index matrix, LDPC sequence or parity check matrix can be determined, or various other methods can also be applied.

[0285] The LDPC decoding process can be compared with Figure 12 The same is shown.

[0286] Figure 12 An example of an LDPC decoding process according to certain embodiments of the present disclosure is shown.

[0287] refer to Figure 12 As a non-limiting example, if the TBS is determined in operation 1210, the receiver determines whether the TBS is greater than the maximum CBS, or less than or equal to the maximum CBS in operation 1220.

[0288] In operation 1230, if the TBS is greater than the maximum CBS, the receiver determines the size of the CBS to which the segmentation is to be applied. If it is determined that the TBS is less than or equal to the maximum CBS, the TBS is determined to be the same as the CBS.

[0289] In certain embodiments, in operation 1240, the receiver determines a value of a block size (Z) to be applied to LDPC decoding.

[0290] In addition, in operation 1250, based on TBS, CBS or block size (Z) value, the receiver appropriately determines the LDPC index matrix or sequence. In addition, in operation 1260, based on the determined block size, index matrix or sequence, the receiver performs LDPC decoding. For reference, according to some situations, operation 1250 may include a process of converting (or transforming) a determined LDPC index matrix or sequence based on the determined block size. According to certain embodiments, according to the system, based on TBS or CBS, the LDPC index matrix, sequence or parity check matrix for LDPC decoding can be determined in various ways. For example, first, based on TBS, a base matrix can be determined, and then, based on the determined base matrix and CBS, an LDPC index matrix, sequence or parity check matrix can be determined, or various other methods can also be applied.

[0291] According to the above example, Figure 11 and Figure 12 In operations 1150 and 1250 of , a process of determining an exponential matrix or sequence of an LDPC code based on one of TBS, CBS, and block size (Z) has been described, respectively. However, various other methods are possible.

[0292] Based on Figure 11 and Figure 12 In some embodiments of the LDPC encoding and decoding process of the base matrix and exponential matrix (or LDPC sequence) of the LDPC code, some information bits used for the LDPC code are appropriately shortened, and some codeword bits are punctured and repeated, so as to support LDPC encoding and decoding of various code rates and lengths. For example, in Figure 11 and Figure 12 In the method, some information bits are shortened in the base matrix or exponential matrix determined for LDPC encoding and decoding, and then the information bits corresponding to the first two column blocks in the parity check matrix are punctured. In this case, some parity checks are punctured, or some LDPC code words are repeated. In this way, various information lengths (or code block lengths) and various code rates can be supported.

[0293] Furthermore, when zero shortening or zero padding of LDPC codes is used to support variable information lengths or variable coding rates, code performance can be improved based on the shortening sequence or shortening method. If the shortening sequence is preconfigured, coding performance can be improved by rearranging all or part of the sequence of a given base matrix. Furthermore, performance can be improved by appropriately determining the block size or the number of column blocks to which shortening is applied for a specific information length (or code block length CB).

[0294] According to some embodiments, the coding rate of the LDPC code can be adjusted by puncturing the codeword bits according to the coding rate. In the case of puncturing the parity bits corresponding to the columns with a degree of 1, the LDPC decoder can perform decoding without using all or part of the corresponding parts in the parity check matrix, thereby reducing the decoding complexity. However, in consideration of coding performance, a method for improving the performance of the LDPC code by adjusting the puncturing order of the parity bits or the sending order of the generated LDPC codewords is provided. For example, compared with the case of supporting a variable code rate by simply puncturing the parity bits, better performance can be supported when the parity bits and part of the information bits are appropriately punctured. In addition, in the case of performing repetition on some LDPC codewords in order to support a lower code rate, the LDPC coding performance can be improved by appropriately determining the repetition order in advance. For reference, the case where part of the information bits are punctured may indicate that the transmitter does not send Figure 1 The portion of information 102 that is not sent can therefore be processed (eg, erased) by the receiver.

[0295] According to various embodiments, during the LDPC encoding process, the transmitter may first determine the size of the input bits (or code blocks) to which the LDPC encoding is to be applied, determine the block size (Z) to which the LDPC encoding is to be applied based on the size of the code blocks, determine a suitable LDPC index matrix or sequence based on the determined block size, and then perform LDPC encoding based on the block size (Z) and the determined index matrix or LDPC sequence. In this case, the LDPC index matrix or sequence may be applied to the LDPC encoding without converting (or transforming) it, or, depending on certain circumstances, LDPC encoding may be performed by appropriately converting (or transforming) the LDPC index matrix or sequence based on the block size (Z).

[0296] Similarly, during LDPC decoding, the receiver can determine the size of the input bits (or code blocks) of the transmitted LDPC codeword, determine the block size (Z) to which LDPC decoding is applied based on the size of the input bits (or code blocks), determine a suitable LDPC index matrix or sequence based on the determined block size, and then perform LDPC decoding based on the block size (Z) and the determined index matrix or LDPC sequence. In this case, the LDPC index matrix or sequence can be applied to LDPC decoding without converting (or transforming) it, or, depending on certain circumstances, LDPC decoding can be performed by appropriately converting (or transforming) the LDPC index matrix or sequence based on the block size (Z).

[0297] Certain embodiments of the present disclosure include a method for improving decoding performance in a communication system or broadcasting system including a layer structure, such as a multiple-input multiple-output (MIMO) system or a superposition coded modulation (SCM) system to which LDPC coding is applied. For reference, the SCM system includes a layer division multiplexing (LDM) system as a representative example.

[0298] FIG. 13A illustrates an example of a MIMO system in accordance with certain embodiments of the present disclosure, and FIG. 13B illustrates an example of a MIMO system in accordance with certain embodiments of the present disclosure.

[0299] First, referring to the illustrative example of FIG. 13A , a transmitter 1310 transmits signals x1, x2, . . . and x2 to M transmit antennas, respectively. M Each signal (as N receiving antennas receive signals y1, y2, ... and y N ) is sent through the channel. ji When the channel between the i-th transmitting antenna and the i-th receiving antenna is modeled, the MIMO system of FIG13A is simplified as shown in FIG13B. In addition, the MIMO system can be simply summarized as the following [Equation 19].

[0300] [Equation 19]

[0301]

[0302] In [Equation 19], h ji represents the channel coefficient of the channel 1340 between the i-th transmitting antenna 1330 and the j-th receiving antenna 1350 as shown in FIG13B, and n j is the additive noise of the jth receiving antenna. As an example, the additive noise includes additive white Gaussian noise (AWGN).

[0303] Figure 14 is an example diagram of an SCM system according to certain embodiments of the present disclosure.

[0304] refer to Figure 14 In the illustrative example of FIG, appropriate channel coding, interleaving, and modulation are applied to one data stream by the BICM-1 block 1410. Appropriate channel coding, interleaving, and modulation are applied to the other data stream by the BICM-2 block 1420. Here, BICM stands for Bit Interleaved Coded Modulation. The two modulated signals that have passed through the BICM blocks are assumed to be S and C and S E .

[0305] As one of the two modulation signals, S E The signal strength of can be adjusted by the injection level controller 1430. E The signal strength of the signal adjustment is assumed to be "a*S E "Signal S C and a*S E are superimposed, such as "S C +a*S E ” etc. and is transmitted (here, “a” is a real number greater than 0). Depending on the situation, the intensity of the superimposed signal may be normalized to a specific size, such as b*(S C +a*S E ) etc. (here, b is a real number greater than 0).

[0306] Although, in Figure 14 A non-limiting example of a control S E However, the position of the injection level controller 1430 can be changed as long as the same effect can be achieved. In addition, the injection level controller 1430 can be omitted as long as the intensity of the modulated signal passing through each BICM block is adjusted to an appropriate level in advance. In addition, the power normalization block 1440 can be omitted in the case where the injection level is appropriately applied to each modulated signal that has passed through each BICM block. In addition, although Figure 14 Only two data streams are shown in FIG, however, it can be extended to two or more data streams.

[0307] 13A and 13B and the MIMO system shown in FIG. Figure 14 The SCM system shown in is a representative example of a system with a hierarchical structure. A system with such a hierarchical structure can be used as follows Figure 15 The coding method shown has a generalized hierarchical structure.

[0308] Figure 15 An example of operation of a transmitter in a communication system having a hierarchical structure according to certain embodiments of the present disclosure is shown.

[0309] refer to Figure 15 As a non-limiting example, assume that a transmitter of a predetermined communication system or broadcast system according to certain embodiments of the present disclosure has M independent information layers. The information bits contained in the kth layer are encoded kth times by the FEC encoder and then generated into the kth layer modulation symbol x by the modulator. k,j (j=1,2,...). Each modulation symbol x k,j It can be sent directly to the receiver through the channel, or it can be sent to the receiver through the channel after adjusting the size of the modulation symbols for any reason (for example, a portion of the size of each modulation symbol can be adjusted for power normalization). Figure 15 In each h i It can be a channel coefficient, a parameter for adjusting the signal size, or a value obtained by considering the above two (i.e., h i can be expressed as a product or sum of more detailed parameters). Similarly, S j Can be an input to a channel or an output from a channel.

[0310] exist Figure 15 In the non-limiting example, although, for convenience, the first FEC encoding 1510, the second FEC encoding 1520, ... and the Mth FEC encoding 1530 are represented by M FEC encoding blocks, in actual implementation, encoding can be performed using one FEC encoder or using two or more FEC encoders. Note Figure 15 The conceptual structure of the layered system is shown. Furthermore, each FEC code can be subdivided into concatenated codes, such as an outer code (not shown) and an inner code (not shown). The outer code used for the outer code (not shown) typically uses an algebraic code, which can perform relatively simple error detection or correction, such as a cyclic redundancy check (CRC) code, a Bose-Chaudhuri-Hochwengeim (BCH) code, or a Reed-Solomon (RS) code, but the outer code is not necessarily limited to these, and the above codes can be used in a repeated manner. The inner code used for the inner code (not shown) generally uses a relatively complex but error-correcting coding scheme, such as an LDPC code, a Turbo code, or a Polar code, but is not necessarily limited to these (for example, tail-biting convolutional codes or other algebraic codes can also be used, and multiple codes can be used in a repeated manner).

[0311] exist Figure 15 In the non-limiting example, although, for convenience, the first modulation 1540, the second modulation 1550, ..., the Mth modulation 1560 are represented by M modulation blocks, in actual implementation, one modulator is used for modulation, or two or more modulators may be used for modulation. Note Figure 15 The conceptual structure of the layered system is shown. Therefore, in actual implementation, FEC coding and modulation can be realized in many ways.

[0312] Figure 16 An example of a decoding scheme of a layered structure corresponding to a communication system or a broadcasting system is shown, which can be performed by Figure 15 The coding method shown has a layered structure.

[0313] further Figure 16 An example of an operation of a receiver in a communication system having a layered structure according to various embodiments of the present disclosure is illustrated.

[0314] refer to Figure 16 As a non-limiting example, first, for a signal y=(y1, y2, ..., y j , ...), in order to perform the first FEC decoding (indicated by reference numeral 1620) through the first demapping (indicated by reference numeral 1610) corresponding to the first layer, the receiver generates or determines a required value (e.g., LLR or LR value), and then, based on the generated or determined value, the receiver performs the first FEC decoding 1620. If the first FEC decoding 1620 is completed, then, based on the result or output of the first FEC decoding, the receiver appropriately eliminates interference from the received signal y. Figure 16 In the embodiment of the present invention, first interference cancellation is performed on the received signal based on at least a part or all of the result or output obtained from the first FEC decoding (indicated by reference numeral 1630). At this time, the FEC decoding result or output used for the first interference cancellation 1630 includes: a hard decision value, a soft decision value, or a combination of the hard decision value and the soft decision value.

[0315] exist Figure 16 In the figure, for convenience, the process of determining the values ​​required for FEC decoding (e.g., LLR, LR, etc.) is simply expressed as demapping, and here, demapping represents a receiver operation corresponding to the transmitter performing a process of mapping to a signal constellation by modulation according to a modulation scheme (e.g., all QPSK, QAM schemes such as 16-, 64-, 256-, or 1024-QAM, or phase shift keying (PSK) or amplitude sum PSK (APSK) schemes are possible). The above-mentioned demapping operation can be subdivided into several processes according to the situation. For example, after performing channel estimation, the demapping operation can be subdivided into a process of determining the values ​​required for FEC decoding (e.g., LLR, LR, etc.), corresponding to the codeword bits sent from the signal or symbol, and demodulating based on the result of the channel estimation. In this case, each of the demapping blocks 1610, 1640, and 1670 can be subdivided into a channel measurement block, a symbol to LLR conversion block, etc. Various subdivisions can be made according to the structure of the system. In addition, in Figure 16 In the example, for convenience, the demapped output value is used as the input of the FEC decoding block, and appropriate interleaving / deinterleaving can be applied according to the communication system. The above interleaving / deinterleaving can be included in the FEC decoding block.

[0316] According to the conventional method for interference cancellation, based on the FEC decoding result of the i-th layer, the appropriate modulation symbols are regenerated, and then the subtraction scheme is applied to the signal received from the channel or to the signal obtained by performing the (i-1)-th interference cancellation, so expressions such as "subtract", "remove" and "cancel" may be used. According to certain embodiments of the present disclosure, eliminating the influence of a specific signal from the received signal is generally expressed as removing or eliminating its influence, but it may also be expressed as subtracting its influence, or it may be replaced by other similar terms. In addition, in various embodiments according to the present disclosure, in the case of decoding the signal of a specific layer, since the signals of other layers other than the signal of the specific layer appear to be interference relative to the specific layer, the expression of interference cancellation or removal is used. However, in addition to interference cancellation, other terms with similar meanings thereto may also be used, which are about the subtraction, removal, exclusion or elimination operations of the signal components of other layers other than the specific layer, such as the elimination or removal of the injected signal. In addition, for convenience, although Figure 16 , an interference cancellation operation for canceling interference based on the order of specific layers is shown. However, it should be noted that interference cancellation can be performed for each of multiple layers, or based on the order of different layers. For example, when interference cancellation is performed on a signal of a second layer using a signal of a first layer, interference cancellation can be performed on a signal of a first layer using a signal of a second layer. In this case, the delay time caused by interference cancellation can be reduced.

[0317] For the corrected received signal obtained by the first interference cancellation 1630 (ie, the output obtained after performing the first interference cancellation) y 1st IC =(y1 1st IC ,...,y j 1st IC , ...), the receiver generates or determines values ​​(e.g., LLR or LR values, etc.) required for performing a second FEC decoding (indicated by reference numeral 1650) after performing a second demapping (indicated by reference numeral 1640), and then, based on the generated or determined values, performs the second FEC decoding 1650. Upon completion of the second FEC decoding 1650, its result or output is appropriately removed from the received signal y or the corrected received signal y. 1st IC .

[0318] exist Figure 16 In the embodiment of the present invention, based on at least a portion or all of the results of the second FEC decoding, the receiver performs a second interference cancellation (not shown) on the received signal or the corrected received signal. In this case, the result or output of the FEC decoding used for the second interference cancellation may use a hard decision value, a soft decision value, or a combination of hard and soft decision values. If the interference cancellation process and the FEC decoding process are completed to the last layer, then all pieces of data decoded for each layer can be reconstructed. As described above, because the interference cancellation process is performed sequentially for each layer, the above method is generally referred to as a serial interference cancellation or SIC scheme. However, as described above, interference cancellation does not need to be performed sequentially according to the layers. Interference cancellation can be performed simultaneously on different layers, or, at least until interference cancellation for a specific layer is completed, interference cancellation can also be performed on other layers. In this case, interference cancellation can also be referred to as serial interference cancellation in a broad sense, but can often be simply expressed as interference cancellation, partially parallel interference cancellation, or parallel (or simultaneous) interference cancellation.

[0319] exist Figure 16 In the non-limiting example, although, for convenience, the demapping, FEC decoding, and interference cancellation blocks are shown for each layer, in an actual system, multiple layers can share and use the demapping, FEC decoding, and interference cancellation blocks by using a single demapper, a single FEC decoder, or a single interference canceller. Needless to say, by using two or more demappers, two or more FEC decoders, or two or more interference cancellers, the demapping, FEC decoding, and interference cancellation blocks can be shared and used for each layer, or can be shared and used by multiple layers.

[0320] In some embodiments, each FEC decoder can be subdivided into a concatenated code format, such as an inner decoder (not shown) and an outer decoder (not shown). When the inner code is used for inner decoding (not shown), relatively complex coding methods with good error correction capabilities, such as LDPC codes, Turbo codes, and Polar codes, are used, but are not necessarily limited to these (for example, tail-biting convolutional codes or other algebraic codes can be used). When the outer code is used for outer decoding (not shown), cyclic redundancy check (CRC) codes, Bose-Chaudhuri-Hochwenghem (BCH) codes, and algebraic codes capable of relatively simple error detection or correction, such as Reed-Solomon (RS) codes, are widely used, but are not necessarily limited to these.

[0321] According to various embodiments of the present disclosure, a method for using a result obtained by performing a hard decision on a portion of the output or a result obtained from an FEC decoder to eliminate interference includes a method for re-encoding a portion of the parity bits based on the decoded information bits (not shown) and using the generated parity bits for interference elimination. The re-encoding process can be performed together in the FEC decoder, or it can be performed in a separate processor or module after the FEC decoder operation is terminated. Based on the decoded information bits, there are various methods for generating at least part or all of the parity by re-decoding. In addition, when an outer code is applied, there are various methods for generating parity based on the error detection result of the outer code, or there are various methods for using the generated parity. This will be described in detail later.

[0322] According to certain embodiments of the present disclosure, a method for handling detected errors due to incomplete correction of Figure 16 Errors generated from the channel during the FEC decoding process.

[0323] First, if an error is detected during the FEC decoding process of a specific layer, there is a high possibility that the information bits or code blocks in which the corresponding FEC decoding is performed contain errors, and therefore, the receiver may discard the corresponding information bits or code blocks and not use the corresponding information bits or code blocks. Figure 16 In the case where the IC or SIC scheme shown performs MIMO detection and decoding, decoding of a layer where an error is detected and subsequent layers is omitted, and a code block or information corresponding to the corresponding layer may be discarded by the receiver.

[0324] According to certain embodiments of the present disclosure, interference cancellation and FEC decoding may be performed sequentially based on the results obtained from decoding the layer where an error was detected. Here, if errors are sequentially detected in subsequent layers, further interference cancellation and decoding may not be performed. However, a method may be provided for sequentially performing interference cancellation and FEC decoding even if an error is detected, and then reusing the results obtained therefrom during MIMO detection (this method is referred to as iterative detection).

[0325] According to certain embodiments of the present disclosure, if no error is detected up to the i-th layer, but an error is detected in the (i+1)th layer, a method is provided for: maintaining demapping and FEC decoding of the (i+1)th layer, selecting a layer from the (i+2)th layer to the M-th layer, and, based on the result of FEC decoding, performing interference cancellation, demapping, and FEC decoding on the selected layer by the i-th layer. The operation of maintaining interference cancellation, demapping, and FEC decoding for the (i+1)th layer may be performed again at an appropriate time thereafter. As described above, in the event that an error is detected in a specific layer during the IC or SIC process, the order of the layers to which IC or SIC is applied may be changed, and the IC or SIC process may be applied to the specific layer again.

[0326] So far, non-limiting examples of the operation of the MIMO detection and FEC encoding and decoding processes have been described. Figure 16 The illustrative example shown proposes a method for efficiently performing interference cancellation when decoding a system having a layered structure to which a specific channel coding technique is applied.

[0327] According to some embodiments, first, for example, in the outer encoder 1710 and the inner encoder 1720 as shown in the illustrative example of FIG. 17A , it is assumed that: Figure 15 In the FEC coding method in a communication system or broadcasting system with a hierarchical structure, a coding scheme of a cascade code is applied. The various channel codes mentioned above can be used as the channel code of each of the outer encoder and the inner encoder, but in the present disclosure, for convenience, the inner code uses an LDPC code and the outer code uses a CRC code. However, the embodiment is not limited to this. When the coding scheme shown in Figure 17A is applied, the corresponding decoding scheme shown in Figure 17B can be applied. According to the definition of the outer code and the inner code, the transmitter performs inner coding after performing outer coding, and the receiver performs inner decoding through the inner decoder 1730 and then performs outer decoding through the outer decoder 1740.

[0328] Figure 18 An example of the structure of a parity check matrix of an LDPC code according to certain embodiments, which is an inner code applied to an FEC encoder and an FEC decoder to be described in this disclosure, is shown.

[0329] exist Figure 18 In the parity check matrix shown in the example, the number of columns is N and the number of rows is (M1+M2). In general, when the parity check matrix contains full rank, the number of columns corresponding to information bits in the parity check matrix is ​​equal to the total number of columns minus the total number of rows. That is, if Figure 18 The parity check matrix includes the full rank (M1+M2), then the number of information bits k is obtained from the formula N-(M1+M2). In this disclosure, for convenience, only the Figure 18 The parity check matrix includes a full rank case, but is not limited thereto.

[0330] first, Figure 18 The parity check matrix is ​​divided into: a first part of the parity check matrix (including submatrices A 1810 and B 1820), and a second part of the parity check matrix (including submatrices C 1840, D 1850, and E 1860). Submatrix O 1830 represents a zero matrix of size (M1×M2). Since submatrix O 1830 is a zero matrix of size (M1×M2), even if submatrix O is included in the first part of the parity check matrix, the matrix operation will not be affected. For this reason, in the present disclosure, for convenience, submatrix O 1830 defines a matrix as the first part of the parity check matrix, which is composed of submatrices A 1810 and B 1820, excluding the zero matrix of size (M1×M2). However, if necessary, submatrix O 1830 can include a zero matrix of size (M1×M2).

[0331] For convenience, Figure 18 An example of a parity check matrix is ​​referred to as H, and the information bits (or information bit vectors) corresponding to the submatrix A 1810 or the submatrix C 1840 are referred to as i=(i0, i1, ..., i K-1 ), the first parity check bit (or first parity check bit vector) corresponding to sub-matrix B 1820 or sub-matrix D 1850 is called The second parity bit (or second parity bit vector) corresponding to the submatrix E 1860 is called , [Formula 20] can be obtained from [Formula 1] as follows.

[0332] [Equation 20]

[0333]

[0334] Referring to [Equation 20] above, it can be seen that based on the information bit vector i and the first part of the parity check matrix, the first parity check vector p1 can be obtained (or calculated or determined). In addition, it can be seen that after obtaining the parity check vector, the parity check vector p2 can be obtained (or calculated or determined) based on the information bit vector i, the parity check vector p1 and the second part of the parity check matrix.

[0335] In this disclosure, the following structural features are limited to Figure 18 The corresponding parity check matrix.

[0336] Feature 1-1: In Figure 18 The parity check matrix is ​​defined as a quasi-cyclic parity check matrix, Figure 18 All column weights (i.e., column degrees) of submatrix B 1820 are 2 or greater, and not all column weights or all row weights are even numbers (i.e., one or more column degrees or row degrees in the base matrix or parity-check matrix may be odd numbers).

[0337] Feature 1-2: In Figure 18 When the parity check matrix is ​​not defined as a quasi-cyclic parity check matrix, Figure 18 Submatrix B 1820 of has a lower triangular matrix structure, and all diagonal entities or elements of submatrix B 1820 may have a value of 1. Therefore, there may be at least one column having a column weight or column degree of 1 in submatrix B 1820. In addition, not all column weights or all row weights may be even numbers (i.e., the weights or degrees of one or more columns or rows in the parity-check matrix may be odd numbers).

[0338] Feature 2: Figure 18 In the case where the parity check matrix is ​​defined as a quasi-cyclic parity check matrix, at least one column block in the submatrix B 1820 in feature 1-1 has a column weight or degree of 3 or greater.

[0339] Feature 3: Figure 18 The submatrix E of has column weight 1 and row weight 1. Therefore, the submatrix E 1860 can be the identity matrix, or, by applying appropriate column permutation or row permutation thereto, the submatrix E 1860 can be converted (or transformed) to the identity matrix (i.e., the submatrix E 1860 is the identity matrix or has characteristics equivalent thereto). Figure 18 The parity check matrix of is defined as a quasi-cyclic parity check matrix, and the submatrix E can be divided into multiple unit matrices.

[0340] FIG19A and FIG19B show examples of parity check matrices satisfying the above-mentioned features 1-1, 2, and 3 according to various embodiments of the present disclosure. FIG19A shows an example of a parity check matrix satisfying the above-mentioned features 1-1, 2, and 3 according to various embodiments of the present disclosure. Figure 18 A non-limiting example of the case where k=22*Z, M1=4*Z and M2=2*Z. FIG. 19B shows the case where Figure 18 A non-limiting example of the case where k=10*Z, M1=4*Z, and M2=7*Z. Here, Z represents the block size defined in [Equation 9] to [Equation 14], and Z corresponds to the size of the cyclic permutation matrix, because the parity check matrix of Figures 19A and 19B represents the exponential matrix of the quasi-cyclic parity check matrix, in the case where the cyclic permutation matrix based on [Equation 2] is expressed as, for example, the exponential matrix of [Equation 4]. Reference Figure 18 As a non-limiting example, the submatrix corresponding to the submatrix E 1860, which consists of M2 columns with a column degree of 1, can be regarded as a single parity check code and is easy to expand. Figure 18 The submatrix C 1840, the submatrix D 1850 and the portion of the submatrix E 1860 may be configured in the form of a parity check matrix extending a single parity check code, and since N=k+M1+M2, it is noted that as M2 increases, the codeword length N also increases.

[0341] Due to Figure 18 The code rate of the LDPC code corresponding to the parity check matrix of Figures 19A and 19B is K / N. Note that as M2 becomes lower, a lower codeword code rate can be generated. In other words, LDPC encoding and decoding can be performed based on a parity check matrix that can support a lower code rate by further expanding the column with a degree of 1 while including Figures 19A and 19B.

[0342] If the value of [Equation 11] is used as the lifting size for LDPC encoding or decoding of the parity check matrix of the quasi-cyclic LDPC code, then at least two columns can constitute a column block of the parity check matrix; if the value of [Equation 12] is used as the lifting size for LDPC encoding or decoding, then at least eight columns can configure a column block of the parity check matrix; if the value of [Table 2] is used as the lifting size for LDPC encoding or decoding, then at least seven columns can configure a column block of the parity check matrix. Therefore, in a communication system in which the lifting size of [Table 2] is basically applied to the parity check matrix of an LDPC code, there can be at least seven columns of degree 3, and the LDPC code has a reference such as satisfying characteristics 1-1, 2, and 3. Figure 18 , the structures shown in the examples of Figures 19A and 19B.

[0343] In the case where a CRC code is applied as an outer code and an LDPC code is applied as an inner code, Figure 20 An example of FEC decoding operation according to certain embodiments of the present disclosure is shown.

[0344] Specifically, Figure 20 An example of a decoding process based on LDPC and CRC codes according to some embodiments of the present disclosure is shown in a flowchart format.

[0345] Typically, in operation 210, the receiver performs LDPC decoding, and then, in operation 220, the receiver checks the LDPC syndrome and determines whether any error is detected. The codeword that can be obtained by hard decision after performing LDPC decoding is given as And when the parity check matrix used in decoding is given as H, the LDPC syndrome has a value determined by [Equation 21].

[0346] [Equation 21]

[0347]

[0348] If the codeword sent by the actual transmitter is given as c, then H·c is established by [Equation 1] T = 0. In the case where decoding is successfully performed, the syndrome s of [Equation 21] should also have a zero value (0) (in the case where the value of the LDPC syndrome is zero, it can be said that the LDPC syndrome value has been identified and passed). However, in the case where the value of the LDPC syndrome is not zero (or if the value of the LDPC syndrome has not passed), then this situation means that

[0349] Among them, Figure 20 In a case where the value of the LDPC syndrome s in operation 2020 is not zero, the receiver may directly perform exception processing (processing or handling) in operation 2050 to determine whether to use the LDPC-decoded information bits or code blocks at an upper layer of the system, or whether to discard the information bits or code blocks.

[0350] However, even if the value of the LDPC syndrome s is not zero in operation 2020, the receiver may not directly perform the exception processing in operation 2050 and may perform CRC detection (or checking) on ​​the information bits in operation 2030. This is because according to the result of LDPC decoding in operation 2010, although the codeword decoding failed, it is very likely that after LDPC decoding, errors only remain in the parity bits, and no errors exist in the information bits. Therefore, in some embodiments, in operation 2030, CRC detection is performed to determine whether any errors in the information bits are detected.

[0351] If it is determined that the information bit vector is successfully decoded, the decoding process ends through CRC detection in operation 2030. If it is determined that an error is included in the information bit vector as a result of CRC detection in operation 2030, the receiver may perform exception processing on the decoded information bit vector or code block in operation 2050 to determine whether to use the relevant information vector or code block at a system upper layer or whether to discard the information vector or code block.

[0352] Note that, in the present disclosure, “exception handling” includes operations to be performed if it is determined that decoding has failed or is likely to fail, in addition to operations to be performed if decoding progresses successfully in all processes.

[0353] In addition, the receiving end may generate an instruction or flag indicating the success or failure of decoding and pass it to the upper layer. The upper layer may determine how to process the decoded information bits or code blocks based on the instruction or flag (e.g., determining a retransmission request).

[0354] For reference, in the case where the decoded codeword is another codeword different from the codeword c, even in [Equation 21] The LDPC syndrome may be zero. Since it is impossible to detect this error (undetected error) by the LDPC code, this undetected error can be detected by performing CRC detection after LDPC decoding.

[0355] In addition, the syndrome value s can be obtained (or calculated or determined) by a calculation process based on the parity check matrix and the decoded codeword as shown in [Equation 21], or, when implementing the LDPC decoder, can be easily obtained based on the LDPC decoder. For example, in [Equation 15], decoding can be performed based on the amplitude and sign of the message used in the decoding process for LDPC decoding. At this time, the syndrome value s can be obtained (or calculated or determined) by the operation of the plus sign (+) or the minus sign (-). For example, in the implementation of the actual decoder, the syndrome value as a binary digit can be easily obtained based on the appropriate exclusive OR (XOR) operation by matching the plus sign (+) with 0 and the minus sign (-) with 1. In particular, from the characteristics implemented in the LDPC iterative decoding process, it is easy to identify whether the syndrome value is zero. For reference, based on the sign of each bit of the message for which LDPC decoding is performed, the hard decision of the codeword of the LDPC decoding can also be easily determined.

[0356] The following describes, according to certain embodiments of the present disclosure, Figure 18 In a communication system in which a parity check matrix having a structure (e.g., FIG. 19A and FIG. 19B ) is used, the following is performed: Figure 16 The decoding operation is performed on the hierarchical structure shown in the figure.

[0357] Generally, because LDPC codes are defined based on a parity-check matrix, they can be considered an algebraic code. However, because probabilistic decoding methods are typically used, the error probability of each bit of the codeword is affected to some extent by the degree of each bit. When probabilistic decoding methods are used, parity bits, which generally have a low degree, may be prone to errors. Therefore, parity bits with relatively low degrees are generally susceptible to decoding errors. In particular, parity bits with a degree of 1 are most prone to errors and may become even more prone to errors when channel measurement fails.

[0358] In some embodiments of the communication system, parity bits are typically discarded without regard to any errors, and since the information bits are only transmitted to and used by upper layers, any errors in the parity bits have little impact on the operation of the system. Figure 16 In the case of performing decoding using the same hierarchical structure as shown, the parity check of the decoding may also affect the decoding performance of any other layer due to interference cancellation. In this regard, re-encoding based on the decoded information bits for parity check is already a common technique. In the present disclosure, it is proposed to: Figure 18 A method for efficient re-encoding and a method for performance improvement when applying LDPC encoding and decoding are provided for a parity check matrix of a structure.

[0359] As described above, LDPC codes have an error probability for each bit that varies according to the degree of each bit. In particular, LDPC codes are characterized in that, when the degree of a bit is 2 or higher, the bit error rate BER (bit error rate or bit error ratio) decreases rapidly compared to the BER when the degree of a bit is 1. When the information bits are successfully decoded, codeword bits (especially parity bits) with a degree of 2 or higher rarely make errors, but even when the information bits are successfully decoded, codeword bits with a degree of 1 may include multiple bit errors. For this reason, in the case where a method based on Figure 18 In a communication system for LDPC encoding and decoding of a parity check matrix, regardless of whether any error is generated in the information bits, a portion of the syndrome value corresponding to the second part of the parity check matrix composed of submatrices C (1840), D (1850) and E (1860) may not be a zero value with a very high probability. That is, as in [Equation 22], the syndrome value determined in the first part of the parity check matrix composed of submatrices A (1810) and B (1820) of Figure 19 (which may include submatrix O (1830)), and the syndrome value determined in the second part of the parity check matrix composed of submatrices C (1840), D (1850) and E (1860) are called the first part s1 of the LDPC syndrome and the second part s2 of the LDPC syndrome, and s2 is a non-zero vector with a very high probability regardless of the decoding result. (In [Equation 22], and represent result bit vectors obtained by performing hard decision on the LDPC decoding results of the information bit vector, the first parity check vector, and the second parity check vector, respectively).

[0360] [Equation 22]

[0361]

[0362] To determine the success or failure of LDPC decoding, the LDPC syndrome can be used in its entirety. However, as with the first part s1 of the LDPC syndrome, in the parity check matrix, the success or failure of decoding can also be determined based on the syndrome or at least a portion of the syndrome based on a submatrix [A(1810)B(1820)] comprising columns of degree 2 or higher and rows of degree 1 that are independent of the parity check bits (similarly, in the case where the first part of the parity check matrix comprises a matrix of zeros such as submatrix O(1830), the actual syndrome value is determined based on the submatrices A(1810) and B(1820) consisting of columns of degree 2 or higher).

[0363] exist Figure 21 , an embodiment is shown for the case where decoding success or failure is determined based on the first part s1 of the syndrome, and for the case where IC or SIC is applied in a hierarchical system.

[0364] Figure 21 An example of partially re-encoding parity in a decoding process based on LDPC and CRC codes according to certain embodiments of the present disclosure is shown.

[0365] refer to Figure 21 As a non-limiting example, first, in operation (2110), the receiver performs LDPC decoding, and then, in operation (2120), the receiver determines whether the LDPC syndrome becomes zero. It should be noted that instead of using the entire portion of the LDPC syndrome, only the first portion s1 of the LDPC syndrome is used. That is, the receiver can determine whether the first portion of the syndrome is zero.

[0366] If it is determined that the value of the first part s1 of the syndrome is zero (i.e., LDPC decoding is successful), then based on this result, the receiver performs CRC detection (or checking) in operation 2130. If it is determined that no error occurred even in the CRC detection, then it can be determined that the information bits or code blocks were ultimately decoded successfully. Therefore, the receiver re-encodes the parity bits with a degree of 1, or, at least in operation 2140, partially re-encodes the parity bits with a degree of 1 (i.e., the second parity bit vector or at least a portion thereof). Therefore, based on the information bits and first parity bits obtained through LDPC decoding and the re-encoded second parity bits or at least a portion thereof, after IC or SIC is applied to the received signal, it is used to perform FEC decoding on the next layer.

[0367] According to some embodiments, Figure 21 In operation 2120 , when it is determined that the value of the first part s1 of the syndrome is not zero, re-encoding may be achieved through various operations.

[0368] For example, if the first part s1 of the syndrome does not have a zero value, then first, in operation 2150, the receiver determines whether a comparison with the threshold value I is performed. max The same number of LDPC decoding, threshold I max is the number of iterative decoding times set in the system. Then, if the value of the first part s1 of the syndrome is still not zero even if LDPC decoding is performed as many times as the maximum number of iterative decoding times, the receiver may assume that the decoding has failed and perform appropriate exception processing in operation 2160. In the communication system, the LDPC syndrome value may be identified or calculated each time LDPC iterative decoding is performed, but it is also possible to identify or calculate the LDPC syndrome value after the maximum number of LDPC iterative decoding times is performed. In this case, Figure 21 Operation 2150 may be omitted in

[0066] Operation 2150 may be used as part of the LDPC decoding process in operation (2110).

[0369] exist Figure 21 In the non-limiting example of FIG, it is shown that only when the first part s1 of the syndrome has a zero value, CRC detection (or check) is performed in operation 2130. However, depending on the communication system, when decoding of the information bits is successful but any error may occur in a part of the first parity bits, CRC detection may be performed even when the first part s1 of the syndrome does not have a zero value.

[0370] Figure 22 An example of partially re-encoding parity in a decoding process based on LDPC and CRC codes according to certain embodiments of the present disclosure is shown.

[0371] refer to Figure 22 As a non-limiting example, if the value of the first part s1 of the syndrome is determined to be zero in operation 2220, then, after this process, the same procedure as Figure 21 The same operation is performed in .

[0372] In some embodiments, in operation 2220, if it is determined that the first part s1 of the syndrome does not have a zero value, the receiver may perform a CRC check in operation 2250. If it is determined through the CRC check that no error actually occurred in the information bits (i.e., no error occurred in the CRC check), then in operation 2260, the receiver may re-encode the second parity bits or at least a portion thereof, and may also re-encode the first parity bits or at least a portion thereof. If it is determined in operation 2250 that the CRC check failed, exception handling may be performed in operation 2270.

[0373] exist Figure 18 and [Equation 20], by using Figure 4 and 5 The allocated resources for data transmission shown in FIG. 1 may be used to puncture the first parity check vector and the second parity check vector by applying rate matching thereto. In conjunction with the case where the second parity check bit or at least a portion thereof is transmitted from the transmitter, as described above Figure 21 and 22 However, if the transmitter supports re-encoding at a very high code rate, the second parity check bits can be completely punctured by rate matching, or the first parity check bits can be partially punctured. In the case where the first parity check bits are also partially punctured, Figure 21 The second parity check vector may not be re-encoded in operation 2140. Furthermore, puncturing may be applied to a portion of the first parity check vector reconstructed by LDPC decoding (not shown) so as to allow the first parity check vector to be substantially consistent in length with the first parity check vector transmitted from the transmitter. Similarly, in the case where the first parity check bits are also partially punctured, Figure 22 In operation 2240, the second parity-check vector may not be re-encoded, and puncturing may be applied to a portion of the first parity-check vector reconstructed by LDPC decoding (not shown) to ensure that the length of the first parity-check vector is substantially the same as the length of the first parity-check vector sent from the transmitter. The fact that the first part s1 of the syndrome does not have an all-zero value determined in operation 2220 and has passed the CRC check in operation 2250 may mean that there are no errors in the information bits, but there may be errors in the LDPC parity check bits. Therefore, in operation 2260, the second parity-check vector may not be re-encoded, and at least a portion of the first parity-check vector (not shown) may be re-encoded to ensure that the length of the first parity-check vector is substantially the same as the length of the first parity-check vector sent from the transmitter. In operation 2260, after the entire first parity-check vector is re-encoded, puncturing (not shown) may be applied to ensure that the length of the first parity-check vector is substantially the same as the length of the first parity vector sent from the transmitter.

[0374] As described above, the recoding method may vary depending on whether the second parity bits having a degree of 1 are punctured or a portion of the first parity bits having a degree of 2 or higher are punctured. The method of determining whether the first parity bits are partially punctured may be applied in various ways. For example, if Figure 12 In the LDPC decoding process shown, the block size Z is determined. Based on the block size, the maximum length of the first parity-check bit vector can be determined. If the total length of the LDPC parity-check bits is less than the maximum length of the first parity-check bit vector, it can be determined that the first parity-check bit vector is partially punctured. For reference, when the LDPC code uses the parity check matrix of Figures 19A and 19B, it can be easily determined that the maximum length of the first parity-check bit vector is 4*Z.

[0375] In the case where the codeword bits generated by LDPC coding are partially punctured and the punctured codeword bits are not sent by the transmitter, from the perspective of the receiver, it can be considered that the punctured codeword bits are erased from the channel. That is, although the punctured codeword bits do not actually pass through the channel, it can be considered that as they pass through the channel, the punctured codeword bits are in a state where it is impossible to identify whether the relevant codeword bits are 0 or 1. According to the LDPC decoder, after converting the punctured bits into a value indicating that the punctured bits cannot be identified as 0 or 1, the punctured bits are decoded. For example, zero (0) can be used when using LLR values, and one (1) can be used when using LR values. These values ​​can be set to different values ​​according to the decoder.

[0376] Generally, although codeword bits of degree 2 or higher are punctured, they greatly affect the LDPC iterative decoding performance because: during the LDPC iterative decoding process, the message value (e.g., LLR) that can determine whether the relevant bit is 0 or 1 is continuously updated. Therefore, the value of LLR=0 is inserted into the punctured parity check bits of degree 2 by the LDPC decoder and used for decoding. It is very likely that the punctured parity check bits of degree 2 are also reconstructed without error. At the same time, in the case where codeword bits of degree 1 are punctured, they do not affect the performance improvement during the LDPC iterative decoding process. Therefore, punctured parity check bits of degree 1 are generally not used in LDPC decoders. For example, using a codeword bit with Figure 18 In the case of an LDPC code with a parity check matrix of a structure, decoding can be performed using only part of the sub-matrices C(1840), D(1850) and E(1860) in the LDPC decoding. In the case of partial puncturing of parity check bits with a degree of 1. It should be noted that through efficient parallel processing, the punctured parity check bits with a degree of 1 can be partially used for decoding. All punctured parity check bits with a degree of 1 can be used for a simple implementation of the decoder, but the disadvantage of this method is that it increases the computational complexity of the decoder without having an effect on performance improvement. As described above, when decoding is performed using only part of the sub-matrices C(1840), D(1850) and E(1860) in the LDPC decoding process, the second part of the syndrome can be only partially obtained according to the rate matching in [Equation 22].

[0377] Furthermore, in some embodiments, the transmitter may puncture a portion of the information bits and transmit the remaining information bits to improve performance in some communication systems or broadcast systems. Generally, when bits corresponding to all or a portion of the columns with the highest column weight or column degree are punctured, good block error rate (BLER) performance may be provided. In this case, performing the following steps in a particular layer: Figure 21 and Figure 22 After the decoding shown, before IC or SIC is applied, the bits corresponding to the punctured information bits are removed or discarded at the transmitter, and then converted into appropriate modulation symbols to which IC or SIC is applied, and decoding is performed at another layer based on the signal obtained by IC or SIC. As a specific and non-limiting example, in Figure 21 Operation 2140 or Figure 22 After operation 2240 or 2260, an operation of removing or discarding information bits punctured by a transmitter (not shown) may be added.

[0378] In some embodiments, when the receiver determines that the first part s1 of the syndrome has a value of zero and Figure 22 When no error occurs in the CRC check (CRC passes or succeeds), the first parity check vector is generally not re-encoded. In this case, even when the transmission code rate is very high and the first parity check bits (or vectors) are partially punctured, re-encoding is not performed. As described above, only the process of puncturing a portion of the first parity check bits determined by LDPC decoding before applying IC or SIC is added.

[0379] However, when it is determined that the first part s1 of the syndrome does not have an all-zero value and no error occurs in the CRC detection (CRC passes or succeeds), that is, it is determined that there is no error in the information bits but an error may occur in a part of the first parity bits, then another operation may be performed. Figure 23 illustrative example to specify the operation.

[0380] Figure 23 An example of partially re-encoding parity in a decoding process based on LDPC and CRC codes according to various embodiments of the present disclosure is shown.

[0381] According to some embodiments, Figure 22 Operation 2260 includes a re-encoding process of the first parity check vector. However, generally, since the higher the degree of the first parity check vector, the lower the probability of error, the receiver does not re-encode the parity check bits with a degree of 3 in the first parity check bit vector as in operation 2310, but uses the decoding results as they are. Based on these values, the receiver can re-encode the first parity check bits with a degree of 2 or at least a portion thereof (the degree 3 and the degree 2 of the first parity check bit vector represent the degrees determined in the sub-matrix [A(1810)B(1820)], and the sub-matrix [A(1810)B(1820)] is the same as that in Figure 18 and corresponds to the first part s1 of the syndrome defined in [Equation 22]. For reference, the submatrix [A(1810)B(1820)] includes rows that are irrelevant to the parity bits of degree 1 in the entire parity check matrix. As described above, in operation 2310, according to rate matching, the receiver can partially puncture the recoded or regenerated first parity bits, or partially recode or regenerate the second parity bits (hereinafter, for convenience, expressed as "recoding"). In addition, depending on the communication system, there are information bits punctured by the transmitter, and in operation 2320, the receiver should puncture the information bits at the same position before IC or SIC. In the case where no information bits are punctured in the transmitter, operation 2320 can be omitted.

[0382] like Figure 23 As shown in operation 2310 of , the method of re-encoding the first parity check vector of degree 2 may be further subdivided and then performed. For example, in the case where the first part s1 of the syndrome does not have a zero value in operation 2220, the re-encoding method may be applied in different manners in operation 2310 depending on the position of the non-zero value in the first part of the syndrome.

[0383] For example, in some embodiments, in the case where the non-zero value in the first part of the syndrome is correlated with a portion of the parity bits of degree 3, the receiver modifies operation 2310 and performs recoding on the entire first parity check vector. In the case where the non-zero value in the first part of the syndrome is not correlated with a portion of the parity bits of degree 3, the receiver may perform recoding on the first parity check vector of degree 2 or at least a portion thereof as in operation 2310. For example, in the case where LDPC decoding is performed based on a parity check matrix of the same form as FIG. 19A , the parity check bits corresponding to the first column block in the first parity check bits (based on the 23rd column block of the entire parity check matrix) are bits of degree 3. In the case where at least one or more non-zero positions in the first part s1 of the LDPC syndrome correspond to the first or second or fourth row blocks, recoding is performed on the entire first parity check. In the case where all non-zero positions in the first part s1 of the LDPC syndrome correspond to the third row blocks, recoding is performed only on the first parity check vector of degree 2. Figure 23 The re-encoding is shown in operation 2310.

[0384] Similarly, in the case where LDPC encoding is performed based on the parity check matrix of the same form as that of FIG. 19B , the parity check bits corresponding to the first column block in the first parity check bits (based on the 11th column block of the entire parity check matrix) are bits of degree 3. When at least one or more non-zero positions in the first part s1 of the LDPC syndrome correspond to the first, third, or fourth row blocks, all first parity checks are re-encoded. In the case where all non-zero positions in the first part s1 of the LDPC syndrome correspond to the second row blocks, the following encoding can be performed only on the first parity check vector of degree 2. Figure 23 The re-encoding is shown in operation 2310.

[0385] For reference, the meaning that the syndrome value is associated with a specific bit or the syndrome value corresponds to a specific bit means that a specific parity bit affects the determination of the syndrome value in [Equation 21] and [Equation 22].

[0386] It should be noted that in the present disclosure, “exception handling” includes, in addition to operations performed when decoding progresses successfully in all processes, operations performed when it is determined that decoding has failed or is likely to fail.

[0387] For example, in the error handling substantially in Figures 20 to 23 , when the receiver determines that LDPC decoding fails, the receiver can determine whether to use or discard the information vector or code block for which decoding is performed. Another example of error handling, in which layered decoding as shown in Figure 16 is performed, the receiver can apply a method that utilizes the information vector or code block determined to fail or likely to fail in decoding for interference cancellation, rather than discarding these information vectors or code blocks.

[0388] For example, when performing interference cancellation on the FEC decoding of another layer, the receiver can use the hard decision result for the LDPC decoding result in operation 2010, and can use the soft decision result value output from the LDPC decoder as it is. At least a part of the parity check bits and the information vector or code block determined to fail or likely to fail in LDPC decoding can be used to perform interference cancellation (however, the bits punctured by the transmitter should be excluded). Another error handling that ignores the decoding of the relevant code block may be related to the method of determining the decoding schedule, similar to performing FEC decoding for another layer.

[0389] The process of partially or fully re-encoding in combination with the parity check bits of the LDPC code has been described for the embodiments of the present disclosure as above, so as to apply effective and performance-improving interference cancellation in the receiving operation in a communication system or a broadcast system (similar to a MIMO or SCM system) that performs decoding based on a hierarchical structure. Additionally, these embodiments can be any combination of re-encoding methods based on CRC and LDPC syndrome as described below.

[0390] Case 1) <The first part of the LDPC syndrome = 0 and CRC is true (or CRC passes)>

[0391] Method 1-1: Re-encode all parity checks (however, perform re-encoding considering the parity check bits punctured by the transmitter)

[0392] Method 1-2: Use the decoding result (or output) for parity check bits of degree 3 or higher, and re-encode at least a part of the parity checks of degree 2 or lower (however, perform re-encoding considering the parity check bits punctured by the transmitter)

[0393] Method 1-3: Use the decoding result (or output) for parity check bits of degree 2 or higher, and re-encode at least a part of the parity checks of degree 1 (however, perform re-encoding considering the parity check bits punctured by the transmitter, but for parity check bits of degree 1, if not transmitted by the transmitter, then these parity check bits can be excluded from the re-encoding)

[0394] Case 2) <The first part of the LDPC syndrome ≠ 0 and CRC is true (or CRC passes)>

[0395] Method 2-1: Determine that the FEC decoding of the relevant layer fails and perform exception handling

[0396] Method 2-2: Recode all parity checks (however, perform recoding considering the parity check bits punctured by the transmitter)

[0397] Method 2-3: Use the decoding result (or output) for parity check bits with degree 3 or higher, and recode at least a part of the parity checks with degree 2 or lower (however, perform recoding considering the parity check bits punctured by the transmitter)

[0398] Method 2-4: Use the decoding result (or output) for parity check bits with degree 2, and recode at least a part of the parity checks with degree 1 (however, perform recoding considering the parity check bits punctured by the transmitter, but for parity check bits with degree 1, if not transmitted by the transmitter, these parity check bits can be excluded from the recoding)

[0399] Case 3) <The first part of the LDPC syndrome = 0 and CRC fails (or CRC is in error)>

[0400] Method 3-1: Determine that the FEC decoding of the relevant layer fails and perform exception handling

[0401] Method 3-2: Use the decoding result (or output) for parity check bits with degree 2 or higher, and recode at least a part of the parity checks with degree 1 (however, perform recoding considering the parity check bits punctured by the transmitter, but for parity check bits with degree 1, if not transmitted by the transmitter, these parity check bits can be excluded from the recoding) Case 4) <The first part of the LDPC syndrome ≠ 0 and CRC fails (or CRC is in error)>

[0402] Method 4-1: Determine that the FEC decoding of the relevant layer fails and perform exception handling

[0403] In Case 1), Case 2), Case 3) and Case 4), for other parity check bits or information bits except the recoded parity check bits, basically use the LDPC decoding result (or output) as it is. For example, based on the LDPC decoding result with hard decision and recoded parity check bits, generate appropriate modulation symbols and then perform interference cancellation. In addition, a part of the soft decision result value output from the LDPC decoding result can be used to perform interference cancellation.

[0404] According to certain embodiments, if parity check bits that are punctured but not transmitted by the transmitter are used even after interference cancellation, the result may be distorted. Therefore, since it is necessary to exclude the relevant punctured parity check bits, perform re - encoding, or apply appropriate puncturing after re - encoding, this operation is omitted in cases 1), 2), 3), and 4). Similarly, even if information bits are partially punctured by the transmitter, the punctured information bits are also punctured or excluded before interference cancellation is performed. In addition, since the transmitter applies interleaving and the like to the LDPC - encoded bits, it should be understood that the receiver requires a de - interleaving process corresponding to the interleaving. The detailed description thereof will be omitted at this point.

[0405] The following non - restrictive examples show that the re - encoding method of parity check bits can be combined in various ways with cases 1), 2), 3), and 4).

[0406] [Re - encoding method 1]

[0407] Case 1) <The first part of the LDPC syndrome = 0 and CRC is true (or CRC passes)>

[0408] Method 1 - 3: Use the decoding result (or output) for parity check bits with degree 2 or higher, and re - encode at least a part of the parity check bits with degree 1 (however, re - encoding is performed considering the parity check bits punctured by the transmitter, but for parity check bits with degree 1, if they are not transmitted by the transmitter, these parity check bits can be excluded from the re - encoding)

[0409] Case 2) <The first part of the LDPC syndrome ≠ 0 and CRC is true (or CRC passes)>

[0410] Method 2 - 1: Determine that the FEC decoding of the relevant layer fails and perform exception handling

[0411] Case 3) <The first part of the LDPC syndrome = 0 and CRC fails (or CRC is in error)>

[0412] Method 3 - 1: Determine that the FEC decoding of the relevant layer fails and perform exception handling

[0413] Case 4) <The first part of the LDPC syndrome ≠ 0 and CRC fails (or CRC is in error)>

[0414] Method 4 - 1: Determine that the FEC decoding of the relevant layer fails and perform exception handling

[0415] For reference, cases 2), 3), and 4) in re - encoding method 1 can be combined and used as follows

[0416] Case 5) <The first part of the LDPC syndrome ≠ 0 or CRC fails (or CRC error)>

[0417] Method 2-1: Determine that the FEC decoding of the relevant layer fails and perform exception handling

[0418] [Redundancy encoding method 2]

[0419] Case 1) <The first part of the LDPC syndrome = 0 and CRC is true (or CRC passes)>

[0420] Method 1-3: For parity check bits with a degree of 2 or higher, use the decoding result (or output) as it is, and re-encode at least a part of the parity check bits with a degree of 1 (however, re-encoding is performed considering the parity check bits punctured by the transmitter, and for parity check bits with a degree of 1, if not transmitted by the transmitter, these parity check bits can be excluded from the re-encoding)

[0421] Case 2) <The first part of the LDPC syndrome ≠ 0 and CRC is true (or CRC passes)>

[0422] Method 2-2: Re-encode all parity checks (however, re-encoding is performed considering the parity check bits punctured by the transmitter)

[0423] Case 3) <The first part of the LDPC syndrome = 0 and CRC fails (or CRC error)>

[0424] Method 3-1: Determine that the FEC decoding of the relevant layer fails and perform exception handling.[[ID=二十六]]

[0425] Case 4) <The first part of the LDPC syndrome ≠ 0 and CRC fails (or CRC error)>

[0426] Method 4-1: Determine that the FEC decoding in the relevant layer fails and perform exception handling.

[0427] [Redundancy encoding method 3]

[0428] Case 1) <The first part of the LDPC syndrome = 0 and CRC is true (or CRC passes)>

[0429] Method 1-3: For parity check bits with a degree of 2 or higher, use the decoding result (or output) as it is, and re-encode at least a part of the parity check bits with a degree of 1 (however, re-encoding is performed considering the parity check bits punctured by the transmitter, and for parity check bits with a degree of 1, if transmitted by the transmitter, these parity check bits can be excluded from the re-encoding)

[0430] Case 2) <The first part of the LDPC syndrome ≠ 0 and CRC is true (or CRC passes)>

[0431] Method 2-3: For parity check bits with a degree of 3 or higher, use the decoding result (or output) as it is, and re-encode at least a part of the parity check bits with a degree of 2 or lower (however, the re-encoding is performed considering the parity check bits punctured by the transmitter).

[0432] Case 3) <The first part of the LDPC syndrome = 0 and CRC fails (or CRC error)>

[0433] Method 3-1: Determine that the FEC decoding in the relevant layer fails and perform exception handling.

[0434] Case 4) <The first part of the LDPC syndrome ≠ 0 and CRC fails (or CRC error)>

[0435] Method 4-1: Determine that the FEC decoding in the relevant layer fails and perform exception handling.

[0436] For reference, in re-encoding methods 2 and 3, cases 3) and 4) can be combined as follows:

[0437] Case 6) <CRC fails (or CRC error)>

[0438] Method 3-1: Determine that the FEC decoding in the relevant layer fails and perform exception handling.

[0439] For cases 1), 2), 3), and 4), in the re-encoding methods for parity check bits and their various combination methods, a method of performing re-encoding considering the number of iterative decodings of LDPC decoding is not described. However, LDPC decoding generally performs iterative decoding within a predetermined maximum number of iterative decodings. During the LDPC decoding process, the LDPC syndrome can be easily and continuously checked. Therefore, before the number of iterative decodings reaches the maximum number of iterative decodings as Figure 21 shown, when it is checked that the LDPC syndrome (or the first part of the LDPC syndrome) is zero, the LDPC decoding can stop. After checking the CRC, the re-encoding process as in cases 1), 2), 3), and 4) can be performed based on the CRC result.

[0440] According to certain embodiments, re-encoding of the parity bits is performed by combining the methods suggested in Case 1), Case 2), Case 3), and Case 4), including the re-encoding methods 1 to 3 described above, as appropriate, and based on the results, interference can then be eliminated from the received signal for hierarchical structure decoding. However, in cases where it is difficult to determine success in FEC decoding, it is better to use the result of LDPC decoding as it is rather than performing re-encoding. This is because determining that FEC decoding failed means that an error occurred in a portion of the information bits, and re-encoding the parity on this basis may show that the parity actually sent is significantly different from the re-encoded parity. Therefore, in the case where any error is detected by the outer code including CRC, the relevant information bits (or code blocks) are discarded. However, in the case where interference is eliminated although any error is detected, interference elimination is performed by using the result (or output) of LDPC decoding as it is to support better performance.

[0441] Various re-encoding methods that can be obtained by combining the methods suggested in Case 1), Case 2), Case 3), and Case 4) include the re-encoding methods 1 to 3 described above. Depending on the situation, the various re-encoding methods can be variably applied according to the system configuration. For example, the re-encoding method can be variably applied according to the error detection capability of the outer code.

[0442] A method for variably applying a re-encoding method of a parity check depending on the size of a TBS and the error detection capability of a CRC according to various embodiments of the present disclosure will be described below.

[0443] First, it can be assumed that, in some embodiments, in a communication system, when the TBS is greater than 3824, the CRC uses 24 bits, and when the TBS is equal to or less than 3824, the CRC uses 16 bits. The reason for setting different numbers of CRC bits according to the TBS is to reduce any unnecessary overhead.

[0444] However, when CRC bits are applied differently depending on the TBS, the probability of undetected errors varies depending on the number of CRC bits (depending on the system, it can be described as the false alarm rate). The more CRC bits, the lower the probability of undetected errors, and the fewer CRC bits, the higher the probability of undetected errors.

[0445] When a communication system uses 24 CRC bits (i.e., TBS greater than 3824), the required undetected error probability can be easily achieved due to the sufficiently large CRC bit number. However, when a communication system uses 16 CRC bits (i.e., TBS less than or equal to 3824), the required undetected error probability may not be achieved due to the insufficient CRC bit number. In this case, LDPC syndrome-based error detection and CRC-based error detection can achieve the required undetected error probability.

[0446] As a result, when 24 bits are used as the number of CRC bits in a communication system, that is, when the TBS is greater than 3824, error detection using only the CRC is sufficient. Therefore, it can be determined that if no errors are detected in the CRC, then no errors will occur in the decoded information bits (or code blocks) regardless of the LDPC syndrome result. In this case, by applying recoding method 2, even if the first part of the LDPC syndrome does not have a zero value, it can be expected that all parity checks can be reconstructed without errors by recoding the parity checks.

[0447] However, in the case where 16 bits are used as the number of CRC bits in a communication system, that is, when TBS is equal to or less than 3824, the number of CRC bits is insufficient to achieve the undetected error probability required in the system. Therefore, even if no error is detected based on the CRC bits, if the first part of the LDPC syndrome is not zero, it may be difficult to determine that the decoded information bits (or code blocks) are successfully decoded. In this case, by applying recoding method 1, if the first part of the LDPC syndrome does not have an all-zero value, then it can be determined that EFC decoding has failed, and then exception processing can be applied. In the case where the error detection capability of the CRC is not high (compared to what is required in the system), at least a portion of the first part of the LDPC system is checked, and in the case where it is determined that an error has occurred, if at least a portion of the first part of the LDPC system does not have an all-zero value, the CRC error detection process can be omitted.

[0448] As described below, certain embodiments according to the present disclosure include a variable application of a recoding method for parity (blocks may be transport blocks or code blocks, as the case may be) that depends on the BLER required in the communication system.

[0449] According to some embodiments, a communication system or a broadcast system operates with a target BLER value set. The target BLER value is a BLER value that can be substantially achieved. That is, when the system operates normally, errors close to the target BLER occur. Assume that the communication system supports services with different target BLERs. For example, in 5G services, in the case of enhanced mobile broadband (eMBB) services, the target BLER is generally around 0.1, which is a relatively high value. In the case of ultra-reliable and low-latency communication (URLLC) services, the target BLER is approximately 0.0001 or 0.00001, which is a low value.

[0450] Generally speaking, it can be considered that in the case of a service with a target BLER of 0.0001 or 0.00001, the service operates in an environment where the signal-to-noise ratio (SNR) of the signal received from the communication system is somewhat high (compared to another service with a target BLER of 0.1 with a high value). In the case of a relatively high SNR, through LDPC decoding, the error probability of parity check bits with a degree of 2 or higher may be significantly reduced in LDPC encoding. As described above, in the case of a very low target BLER, although the CRC is passed, the probability that any error is still included in the first parity check vector corresponding to the first part of the LDPC syndrome is also very low. Therefore, regardless of the result of the LDPC syndrome, the simplified re-encoding method described below can be applied.

[0451] [Re-encoding method 4]

[0452] Case 6) <CRC fails (or CRC error)>

[0453] Method 3-1: Determine that the FEC decoding fails in the relevant layer and perform exception handling.

[0454] Case 7) <CRC is true (or CRC passes)>

[0455] Method 1-3: For parity check bits with a degree of 2 or higher, use the decoding result (or output) as it is, and re-encode at least a part of the parity check bits with a degree of 1 (perform re-encoding considering the parity check bits punctured by the transmitter, and for parity check bits with a degree of 1 that are not transmitted, these parity check bits can be excluded from the re-encoding

[0456] As a result, in the case where the target BLER of these services has a relatively high value of approximately 0.1, one of re-encoding methods 1 to 3 is supported. In the case where the target BLER of these services has a relatively low value of approximately 0.0001 or 0.00001, a simplified method such as re-encoding method 4 can be adopted.

[0457] In some embodiments, the target BLER may be indicated directly, but may also be indicated indirectly through any of a variety of methods. A target BLER indication method may be used depending on the channel quality indicator (CQI) table or modulation and coding scheme (MCS) table actually used for transmission and reception in the communication system. For example, it can be considered that: when the first CQI table or the second CQI table is used, the target BLER indicates 0.1; when the third CQI table is used, the target BLER indicates 0.00001. In the present disclosure, the above-described method of indicating the BLER using the CQI or MCS table is merely an exemplary embodiment, and thus the scope of the present disclosure is not limited thereto. The following table is a specific example of using this method.

[0458] [Table 3] Example of using a method of indicating a target BLER as a CQI table

[0459]

[0460] According to the above example, if Table 1 or Table 2 is set as the CQI table from higher layer signaling in the communication system, it can be expected that the error probability set as a target in the communication system is a value approximately 0.1 or a value equal to or less than 0.1. In other words, the communication system can basically operate with a target BLER of 0.1.

[0461] Meanwhile, if "Table 3" is set as the CQI table from higher-layer signaling in the communication system, it can be expected that the error probability set as a target in the communication system is a value approximately 0.00001 or a value equal to or less than 0.00001. In other words, the communication system can basically operate at a target BLER of 0.00001.

[0462] Changing the parity recoding method according to the target BLER (or the BLER required in the system) can be replaced by a recoding method based on parameters corresponding to a CQI table or other target BLER set in higher layer signaling.

[0463] The following describes the variable application of the parity recoding method according to the channel coding rate R in the communication system according to various embodiments of the present disclosure. Figure 18 In the case of performing channel coding on an LDPC code having a structure of , redundancy can be performed in parity check bits of degree 1 and parity check bits of degree 2 or higher in the first parity check vector (in the first parity check vector, degree 2 indicates that the degree determined in the submatrix [A(1810)B(1820)] is determined by the number of bits corresponding to Figure 18 The first part s1 of the syndrome defined in [Equation 22] and the entire parity check matrix of the first part s1 of the syndrome defined in [Equation 22] consists of columns with degree 2 or higher and rows with degree 1 that are not related to parity check). The degree of punctured parity bits can be determined based on the TBS or CBS value, the LDPC code rate, and the base matrix or parity check matrix used for LDPC coding. Therefore, the recoding method can be variably applied based on the channel coding rate.

[0464] Certain embodiments of the present disclosure have been described with reference to the case where a CRC code is used as an outer code. However, any outer code with error detection capabilities is also applicable to the embodiments of the present disclosure described in a similar manner. Because BCH codes have both error correction and error detection capabilities, error detection is performed after decoding an inner code such as an LDPC code, and then error correction processing is performed. Therefore, BCH codes are applicable to the embodiments of the present disclosure. For example, the process of identifying or checking the CRC in Case 1), Case 2), Case 3), Case 4), Case 5), Case 6), and Case 7) can be replaced by a process of "error detection through BCH" or a process of "error detection after error correction through BCH" for application.

[0465] As described above, the LDPC syndrome value s can be obtained through the calculation process based on the parity check matrix and the decoded codeword as shown in [Equation 21] and [Equation 22]. However, the LDPC syndrome value s can also be easily obtained based on the characteristics implemented by the LDPC decoder. For example, in [Equation 15], the LDPC syndrome value s can be easily obtained by operating on the + or - sign of the message used in the decoding process for LDPC decoding. In the actual implementation of the decoder, the + sign corresponds to zero (0) and the - sign corresponds to one (1), which is a binary number. The syndrome value can be easily obtained by an exclusive OR (XOR) operation.

[0466] However, regardless of whether any error occurs in the information bits or code blocks, the syndrome value associated with the parity bit of degree 1 has a non-zero value with a very high probability. Figure 18 The syndrome value (second syndrome part) s2 determined by the second part of the parity check matrix of the submatrices C (1840), D (1850), and E (1960) in [Equation 22] is not suitable for determining the characteristics of LDPC decoding. In other words, the process of calculating or determining the second syndrome part s2 may cause unnecessary overhead in the LDPC decoding process.

[0467] Therefore, a method for a receiver to modify the operation to calculate or determine the second part s2 of the syndrome similar to [Equation 22] and use the second part s2 of the syndrome in the re-encoding process. [Equation 23] shows that the second part s2 of the syndrome can be used based on Figure 18 The modified LDPC syndrome value obtained by combining the sub-matrices A(1810), B(1820), C(1840) and D(1850) in [Equation 22].

[0468] [Equation 23]

[0469]

[0470] In [Equation 23], the first part s1 of the syndrome is the same as in [Equation 22], but the second part s2' of the modified syndrome is determined by the sub-matrices C(1840) and D(1850), which is different from the second part s2 of the syndrome determined by the sub-matrices C(1840), D(1850), and E(1860). The second part of the modified syndrome can be obtained (or calculated or determined) by a process that is almost the same as the process of obtaining the second part of the existing syndrome, without increasing the complexity of the actual implementation in the terminal. Figure 18 When the neutron matrix E (1860) is the identity matrix (or a matrix having the same algebraic characteristics as the identity matrix), the second part of the modified syndrome is actually determined to be the same as the bits re-encoded for the parity check bits of degree 1. In addition, as in [Equation 24], the second part s2' of the modified syndrome is the same as the result obtained (or calculated or determined) by adding (XORing) the result value of the parity check bit of degree 1 obtained by LDPC decoding to the second part of the existing syndrome defined in [Equation 22].

[0471] [Equation 24]

[0472]

[0473] As a result, the recoding of the parity check bits of degree 1 in the LDPC coded bits does not consider the submatrix corresponding to the parity check bits of degree one (1) in the entire parity check matrix. For the submatrix associated with the information bits or the parity check bits of degree 2 or higher as shown in [Equation 23], the recoding can be determined based on the LDPC syndrome or the modified syndrome value, or based on the existing LDPC syndrome and the LDPC decoding result as shown in [Equation 24].

[0474] Since it can be easily determined during the iterative decoding process of performing LDPC decoding that the number of LDPC syndrome values ​​is the same as the maximum number of iterative decoding times, re-encoding may not be performed after the LDPC syndrome and CRC detection result are identified.

[0475] In certain embodiments according to the present disclosure, whether it is LDPC syndrome or CRC detection, the implementation characteristics of the LDPC decoder can be used to re-encode the parity check bits of degree 1 during the LDPC iterative decoding process. In this case, according to Figures 21 to 23 As well as the LDPC syndrome or CRC detection results described in the above embodiments, the re-encoding process is sequentially performed, thereby enabling IC or SIC to be performed.

[0476] In some embodiments, during the LDPC iterative decoding process, the re-encoding result of the parity bits with a degree of 1 is determined by [Equation 23] or [Equation 24]. IC or SIC can be performed after determining one of the following two issues: either: determining whether to use the re-encoded result as the parity bit for IC or SIC application based on the LDPC syndrome or the CRC test result after LDPC decoding is completed; or: determining whether to use the parity bit obtained by LDPC decoding as the parity bit for IC or SIC application.

[0477] exist Figure 24 and Figure 25 An example of an operation flow chart of the above embodiment is shown in FIG.

[0478] Figure 24 An example of partially re-encoding parity in a decoding process based on LDPC and CRC codes according to certain embodiments of the present disclosure is shown.

[0479] exist Figure 24 In a non-limiting example, the re-encoding operation of the second parity check vector (i.e., the parity check bits of degree 1) is performed by operation 2420 in combination with the LDPC decoding in operation 2410, which can be easily implemented by the LDPC syndrome or modified LDPC syndrome as described in [Equation 23] or [Equation 24].

[0480] According to certain embodiments, when the first part of the LDPC syndrome has an all-zero value in operation 2430 and it is determined in operation 2450 that the result of the CRC detection does not contain an error, the re-encoded parity bits determined in operation 2420 are determined as a second parity vector of the IC or SIC in operation 2470.

[0481] In case the first part of the syndrome does not have an all-zero value, even if iterative decoding is performed in operations 2430 and 2440 up to the maximum number of iterative decoding times, or it is determined that any error occurs due to CRC detection, exception handling is performed in operation 2460 .

[0482] However, the embodiments of the present disclosure are not limited thereto, nor are they limited to the examples described below.

[0483] In some embodiments, when the first portion of the LDPC syndrome is not an all-zero value, but it is determined that no error has occurred as a result of CRC error detection, the first parity-check bit vector is re-encoded, and then the second parity-check bit vector may be re-encoded based on the reconstructed information bits (or code blocks) and the re-encoded first parity-check bit vector. This is because if the first portion of the LDPC syndrome of the first parity-check bit vector obtained by LDPC decoding does not have an all-zero value, the re-encoded first parity-check vector determined in operation 2420 may be unreliable.

[0484] However, in Figure 18 In the parity check matrix of , if the submatrix D (1850) is a 0 matrix in which all elements are zero, then the parity check bits having a degree of 2 or higher (i.e., the first parity check vector) and the parity check bits having a degree of 1 (i.e., the second parity check vector) can be generated independently of each other. Therefore, the process of re-encoding the second parity check bit vector based on the first parity check vector can be omitted, and the second parity check vector determined in operation 2420 can be used in operation 2470.

[0485] Determining the parity check vector after LDPC decoding has been described above. Figure 24 It is understood that operation 2420 of the present disclosure may be performed in any operation after LDPC decoding and may be performed together with LDPC decoding.

[0486] Figure 25 is a flowchart illustrating partial re-encoding of parity in a decoding process based on LDPC and CRC codes

[0487] Figure 25 An embodiment similar to Figure 22 However, the re-encoding operation of the second parity check vector (i.e., the parity check bits of degree 1) is performed together with the LDPC decoding in operation 2510 through operation 2520. The re-encoding operation can be easily implemented by the LDPC syndrome described in [Equation 23] or [Equation 24] or the modified LDPC syndrome.

[0488] In a case where the first part of the LDPC syndrome is an all-zero value in operation 2530 and it is determined that the result of the CRC detection in operation 2540 is error-free, the receiver determines the re-encoded parity bits determined in operation 2520 as a second parity vector for IC or SIC in operation 2550.

[0489] In operation 2550, the receiver may determine the first parity check vector obtained as a result of LDPC decoding as it is as the first parity check vector for IC or SIC. For ease of implementation, the first parity check vector is re-encoded based on the information bits (or code blocks) obtained by LDPC decoding, and then the re-encoded first parity check vector may be determined as the first parity check vector for IC or SIC (a description of puncturing information bits and performing puncturing on parity check bits by the receiver will be omitted).

[0490] If it is determined in operation 2530 that the first portion of the syndrome does not have an all-zero value, and no errors occur as a result of CRC detection in operation 2560, it is expected that a portion of the parity check bits of degree 2 or greater may include any errors. Therefore, the receiver recodes the parity check bits of degree 2 or greater (i.e., the first parity check vector). In addition, based on the information bits (or code blocks) obtained through LDPC decoding or the recoded first parity check vector, the receiver may recode the second parity check vector as needed (the description of the information bits punctured by the receiver will be omitted, and the description of the puncturing operation for the parity check bits will be omitted). This is because if the first portion of the LDPC syndrome of the second parity check bit vector obtained through LDPC decoding does not have a zero value, the recoded second parity check vector determined in operation 2520 may be unreliable.

[0491] However, if the submatrix D(1850) is a 0 matrix in which all elements are zero, then Figure 18 In the parity check matrix of , parity check bits with a degree of 2 or greater (i.e., the first parity check vector) and parity check bits with a degree of 1 (i.e., the second parity check vector) can be generated independently of each other. Therefore, in operation 2570, the process of re-encoding the second parity check bit vector based on the first parity check bit vector can also be omitted for the first parity check vector. The first parity check bit vector determined in operation 2520 can be used in operation 2550 or 2580.

[0492] The above has described the determination of the parity check vector after LDPC decoding. However, referring to Figure 25 It should be understood that operation 2520 of the present disclosure may be performed in any step or operation after LDPC decoding, or may be performed together with LDPC decoding.

[0493] For ease of explanation, operations 2550 and 2580 are Figure 25 However, it should be noted that in some embodiments, operations 2550 and 2580 can be implemented in one process.

[0494] exist Figure 24 and Figure 25 In the illustrative example of FIG, if any error is determined to have occurred as a result of CRC error detection, exception processing is performed. Exception processing refers to an operation other than the standard hierarchical structure decoding operation, and the exception processing method is to interrupt the above-mentioned hierarchical structure decoding, or apply the result of LDPC decoding to IC or SIC without re-encoding (or only partially apply re-encoding), or perform LDPC decoding on another layer and apply it to IC or SIC, etc.

[0495] Similar to the second part of the modified LDPC syndrome defined in [Equation 23] and [Equation 24], based on the matrix A(1810) and Figure 18 The first part S1′ of the modified syndrome determined by the information vector in [Equation 22] can be easily implemented to re-encode parity bits of degree 2 or higher as in [Equation 25].

[0496] [Equation 25]

[0497]

[0498] based on We can obtain the formula from [Equation 20] Re-encoded first parity vector In other words, if the LDPC decoded information bit vector has no errors (or the CRC detection detects no errors), then re-encoding can be performed based on the LDPC decoded information bits (or code blocks) and the first part of the LDPC syndrome.

[0499] For reference, in [Eq. 24] and Figure 24 and Figure 25 The LDPC syndrome or re-encoded parity bits described in the above may not take into account the parity bits punctured by the transmitter; for convenience, a detailed description thereof is omitted here. For example, Figure 18 The sub-matrix E (1860) of is fully used to determine the second part of the LDPC syndrome. However, to take into account the punctured parity bits, usually only a portion of the sub-matrix E (1860) can be used.

[0500] It should also be noted that in determining Figure 24 and Figure 25 When the parity bits for IC or SIC are used, the parity bits punctured by the transmitter may be excluded. Furthermore, it should be noted that when the transmitter punctures and transmits a portion of the information bits (or code blocks), the relevant information bits (or code blocks) for IC or SIC may also be punctured.

[0501] In certain embodiments according to the present disclosure, based on Figure 18

[0045] For a parity check matrix having a structure of

[0046] , recoding methods for parity check bits for IC or SIC applications have been proposed for various embodiments. By further limiting Figure 18 structure, a re-encoding method having a simpler form can be applied to these embodiments.

[0502] For example, in Figure 18 In the parity check matrix, if the submatrix D(1850) is a 0 matrix in which all elements are zero, then the parity check bits with a degree of 2 or higher (i.e., the first parity check vector) and the parity check bits with a degree of 1 (i.e., the second parity check vector) can be generated independently of each other.

[0503] That is, whether to re-encode the parity check bits of degree 1 can be determined based solely on the error detection result of the outer code, such as CRC detection, without considering the first part s1 of the LDPC syndrome. In other words, when it is determined that the CRC detection result is error-free, regardless of the first part of the LDPC syndrome, the re-encoded second parity check vector can be determined in [Equation 23] or [Equation 24] based on the second part of the LDPC syndrome and the second parity check vector after LDPC decoding (or a portion thereof), or the re-encoded second parity check vector can be determined based on the modified second part of the LDPC syndrome.

[0504] Meanwhile, in the case where the submatrix D (1850) is a matrix other than the 0 matrix, after the parity bits of degree 2 or higher are determined, at least a portion of the parity bits of degree 1 may need to be encoded or re-encoded. In other words, if the submatrix D (1850) is another matrix other than the 0 matrix relative to the embodiment of the present disclosure, then re-encoding (or syndrome correction) is generally performed on the parity bits of degree 2 or higher, and if the parity bits change as a result of LDPC decoding, then, based on the result of the LDPC decoding, at least a portion of the parity bits of degree 1 should be re-encoded (or syndrome correction).

[0505] It should be understood that the embodiments described in the present disclosure can be combined to generate new specific embodiments. As a specific combination method, another embodiment of performing IC or SIC decoding by re-encoding is given in re-encoding method 5 below.

[0506] [Recoding Method 5]

[0507] 1) A receiver receives a signal corresponding to a transport block and a code block generated from a transmitter having a hierarchical structure.

[0508] 2) Based on the received signal, the sizes of the transport block and code block are determined.

[0509] 3) Based on the determined size of the transmission block or code block, determine a parity check matrix.

[0510] 4) Perform LDPC decoding based on the received signal and the determined parity check matrix to decode the code block.

[0511] 5) Determine a first LDPC syndrome based on the decoded code block and at least a portion of the first parity bits.

[0512] 6) Determine the CRC for the decoded code block.

[0513] 7) Based on the determined first LDPC syndrome value and CRC, perform IC or SIC.

[0514] Examples of methods for performing IC or SIC may include at least one of the methods described below. However, embodiments of the present disclosure are not limited thereto.

[0515] i) When CRC is false (or fails), IC or SIC is not performed (or IC or SIC is skipped). As another example, in the case of CRC failure, a method for applying IC or SIC can be applied that is based on the result of LDPC decoding without re-encoding.

[0516] ii) when the first LDPC syndrome is an all-zero value and the determined CRC is true (or passes), re-encoding the second parity bits based on the decoded code block and the first parity bits (or at least a portion thereof), and performing IC or SIC based on the decoded first parity bits and at least a portion of the re-encoded second parity bits.

[0517] iii) when the size of the transport block is greater than a predetermined value, the first LDPC syndrome is not an all-zero value, and the determined CRC is true (or passes), re-encoding the first parity bits based on the decoded code block, re-encoding the second parity bits based on the decoded code block and the re-encoded first parity bits, and performing IC or SIC based on at least a portion of the re-encoded first parity bits and the second parity bits.

[0518] iv) When the size of the transport block is equal to or smaller than a predetermined value and the first LDPC syndrome is not all zeros, IC or SIC is not performed (or the performance of IC or SIC is skipped).

[0519] 8) The first parity check bits correspond to columns of degree 2 or higher in the parity check matrix, and the second parity check bits correspond to columns of degree 1 in the parity check matrix.

[0520] For reference, in the re-encoding method 5, it should be noted that the second parity check bit or the first parity check bit can be re-encoded together according to the LDPC syndrome or the modified LDPC syndrome in the process 4) or 5). In this case, at least the second parity check bit may not be re-encoded in the process 7). In addition, the first LDPC syndrome generally indicates the same Figure 18 The LDPC syndrome, LDPC information bits, and first parity bits associated with the sub-matrices A (1810) and B (1820) of FIG. However, in the case where the first parity bits are punctured and transmitted by the transmitter through rate matching, it may indicate an LDPC syndrome associated only with the LDPC information bits and at least a portion of the received first parity bits.

[0521] Another example of a specific combination method for performing IC or SIC decoding by recoding is described below in [Recoding Method for SCM or LDM System] or [Recoding Method for Multi-layer System]. Recoding Method 6 indicates a recoding method based on [Equation 24]. In Recoding Method 6, Figure 18 The structure of the parity check matrix satisfies property 1-1 (or property 1-2), property 2, and property 3. The above method is equally applicable to both MIMO systems and SCM systems.

[0522] An example of implementation code according to the above method is shown below.

[0523] [Table 4] Implementation code example

[0524]

[0525] In the table above, "o_EACH_PRTY_GEN" refers to the re-encoded (or regenerated) parity with a degree of 1, corresponding to Figure 18 There are various ways to recode the parity bits of degree 1. This corresponds to after LDPC decoding as shown in [Equation 24] Figure 18 The method performs re-encoding by performing an exclusive-OR (XOR, ^) operation on a value of "rPRTY_GEN" indicating the second portion of the LDPC syndrome (corresponding to the parity bits of degree 1) to remove the LDPC decoding result corresponding to the parity bits of degree 1. In other words, "rPRTY_GEN" includes an exclusive-OR value of the LDPC information bits (or code blocks) generated or determined by LDPC decoding, parity bits of degree 2 or higher, and parity bits of degree 1. Since the XOR operation of "rMUXED_EDGE_DLY[EDGEIW-1]" on the parity bits of the LDPC decoded degree 1 eliminates the influence, the re-encoded (or regenerated) parity of degree 1 is composed of the LDPC decoded information bits and the parity bits of degree 2 (for reference, "rDLY_CP_PHI_EN" and "rMUXED_EDGE_DLY[EDGEIW-1]" represent control values ​​to indicate the area where the above operation is valid).

[0526] Examples of certain embodiments according to the above process are provided below.

[0527] [Recoding method of SCM or LDM system]

[0528] 1) A receiver receives a superposition coded modulation (SCM) or layer division multiplexing (LDM) signal generated by two or more layers of signals.

[0529] 2) Based on at least a portion of the parity check matrix, the receiver decodes the LDM signal to determine or generate first LDPC information bits, first parity check bits, and second parity check bits corresponding to the first layer signal.

[0530] 3) The receiver determines the LDPC syndrome corresponding to the decoded first LDPC information bit, the first parity check bit, and the second parity check bit.

[0531] 4) Based on the decoded second parity bits and the determined LDPC syndrome, the receiver determines (or generates) modified second parity bits.

[0532] 5) The receiver determines a second layer signal by removing signals corresponding to the decoded first LDPC information bits and first parity bits and the modified second parity bits from the LDM signal.

[0533] 6) The receiver decodes the second layer signal to determine the second LDPC information bits corresponding to the second layer signal.

[0534] The second parity bit may correspond to a column having a degree of 1 in the parity check matrix.

[0535] Another example of a recoding method and apparatus in an SCM system according to certain embodiments is described below.

[0536] [Recoding method for multi-layer system]

[0537] 1) First, a receiver receives a superposition coded modulation (SCM) signal or a layer division multiplexing (LDM) signal generated by two or more layers. (This method can be applied to a receiver capable of receiving and processing MIMO signals of a MIMO system associated with two or more layers.)

[0538] 2) Based on at least a portion of the parity check matrix, a first LDPC decoder is configured to decode the LDM signal to determine or generate at least a first LDPC information bit (or code block) and a first parity check bit corresponding to the first layer signal in the SCM signal (or LDM signal).

[0539] 3) Based on the parity check matrix, the encoder (or processor) encodes the first LDPC information bit and the first parity check bit to generate the second parity check bit, or, based on the parity check matrix, the encoder encodes the first LDPC information bit to generate the first parity check bit or the second parity check bit. In the latter case, the first parity check bit generated by encoding may be different from the first parity check bit decoded in the above 2) process.

[0540] 4-1) In the case where the transmitter punctures information bits of a specific length (e.g., a multiple of block length Z, such as 2*Z) and transmits the remaining information bits, at least one processor may determine a portion of the first LDPC information bits by excluding the punctured information bits corresponding to the specific length from the decoded first LDPC information bits. In addition, in the case where a portion of the parity bits is punctured by rate matching, the operation may include determining a portion of the parity bits by excluding the punctured parity bits. Further, in the case where a portion of the first LDPC information bits or a portion of the parity bits is repeated by rate matching, the operation may include additionally determining a portion of the first LDPC information bits or a portion of the parity bits (for example, for convenience, this operation may be referred to as dematching).

[0541] 4-2) When interleaving is applied in the transmitter, all or at least a portion of the codeword involved in the interleaving operation includes: the first LDPC information bit (or a portion thereof), the first parity bit (or a portion thereof), or may include: the second parity bit (or a portion thereof) in the same manner as the transmitter. Depending on rate matching, the codeword may include a portion of repeated LDPC information bits or parity bits. It should be noted that when decoding is performed on the received signal, deinterleaving corresponding to the interleaving performed in the transmitter is performed, and the same interleaving as in the transmitter is performed to perform interference cancellation.

[0542] 4-3) According to some embodiments, in order to determine or generate an appropriately modulated symbol or signal, it may include: an operation of mapping the interleaved first LDPC information bit (or a portion thereof), the first parity bit (or a portion thereof), or the second parity bit (or a portion thereof) to an appropriate constellation point (it should be noted that when decoding the received signal, the receiver performs a constellation point mapping corresponding to the constellation point mapping performed by the transmitter, and performs the same constellation point mapping as the transmitter, thereby achieving interference cancellation).

[0543] For the rate dematching or determination (or generation) of modulation symbols (symbols or signs) in the above 4-1) to 4-3), operations such as determining the target code rate and modulation order based on the MCS information or MCS index information sent from the transmitter can be additionally performed.

[0544] 5) In order to determine or generate a second LDPC information bit corresponding to a second-layer signal, wherein the second-layer signal is determined or generated by subtracting, removing, excluding or eliminating the first-layer signal corresponding to the first LDPC information bit (or at least a portion of the first LDCP information bit), the first parity bit (or at least a portion of the first parity bit) or the second parity bit (or at least a portion of the second parity bit) from the LDM signal, and the second LDPC decoder is configured to decode the determined or generated second-layer signal.

[0545] 6) The parity check matrix can be configured as follows:

[0546] The first part of the parity check matrix includes a first submatrix A (1810) corresponding to the first LDPC information bit and a second submatrix B (1820) corresponding to the first parity check bit and including columns with a degree of 2 and columns with a degree of 1.

[0547] According to some embodiments, the second portion of the parity check matrix includes a third submatrix C (1840) corresponding to the first LDPC information bits, a fourth submatrix D (1850) corresponding to the first parity check bits, and a fifth submatrix E (1860) as an identity matrix that at least partially corresponds to the second parity check bits. For convenience, only parity check matrices that satisfy at least one of properties 1-2, property 2, and property 3 are described. However, it should be understood that the same application can also be applied to parity check matrices that satisfy at least one of properties 1-1, property 2, and property 3.

[0548] Features of a decoding device or a receiving device according to the above method may be described below.

[0549] A receiver for receiving and processing a layer division multiplexing (LDM) signal generated from a first layer signal and a second layer signal, comprising: a first low-density parity check (LDPC) decoder configured to decode the LDM signal so as to determine (or generate) first LDPC information bits and first parity check bits corresponding to the first layer signal in the LDM signal based on a parity check matrix; a processor configured to: encode the first LDPC information bits and the first parity check bits to generate second parity check bits based on the parity check matrix or the first LDPC information bits, thereby generating the first parity check bits and the second parity check bits based on the parity check matrix; the processor is configured to exclude the punctured information bits corresponding to the specific length from the decoded first LDPC information bits in the case of information bits being punctured and the remaining information bits being sent by a transmitter in the system. The invention relates to a method for determining a portion of the first LDPC information bits in a case where interleaving is required; a processor configured to interleave the first LDPC information bits (or at least a portion of the first LDPC information bits), the first parity bits (or at least a portion of the first parity bits), and the second parity bits (or at least a portion of the second parity bits) when interleaving is required, and the processor is configured to map the interleaved first LDPC information bits (or at least a portion of the first LDPC information bits), the first parity bits (or at least a portion of the first parity bits), and the second parity bits (or at least a portion of the second parity bits) to appropriate constellation points, so as to determine or generate an appropriate modulation symbol or signal based on the first LDPC information bits (or at least a portion of the first LDPC information bits), the first parity bits (or at least a portion of the first parity bits), and the second parity bits (or at least a portion of the second parity bits).

[0550] The receiver may also include a second LDPC decoder, which is configured to decode the generated second-layer signal so as to determine (or generate) second LDPC information bits corresponding to the generated second-layer signal by removing the first signal layer, the first signal layer corresponding to: (interleaved) first LDPC information bits (or at least a portion of the first LDPC information bits), first parity bits (or at least a portion of the first parity bits) and second parity bits (or at least a portion of the second parity bits), wherein the parity check matrix includes: a first part, and a second part, the first part including: a first submatrix corresponding to the first LDPC information bits and a second submatrix corresponding to the first parity bits and including columns with a degree of 2 and a column with a degree of 1; and the second part including: a third submatrix corresponding to the first LDPC information bits, a fourth submatrix corresponding to the first parity bits and a fifth submatrix corresponding at least partially to the second parity bits and serving as a unit matrix.

[0551] In the above specific embodiments, for convenience, only the parity check matrix that satisfies at least one of the properties 1-2, 2, and 3 is described. The same application can be applied to a parity check matrix that generally satisfies at least one of the properties 1-1, 2, and 3 or has the same Figure 18 , FIG19A and FIG19B have the same parity check matrix structure. In addition, in the above embodiment, each operation and processor can be entirely included in the receiver, or only a portion thereof can be included in the receiver. In addition, each operation can be implemented by multiple processors or an integrated processor.

[0552] In the case where the receiving apparatus described in conjunction with the embodiment of [Re-encoding method and apparatus] is applied to an LDM or MIMO system, rearrangement will be performed as described below.

[0553] A receiver for receiving and processing a layer division multiplexing (LDM) signal having at least two layers, comprising: a first decoder configured to decode first low-density parity check (LDPC) information bits and first parity check bits corresponding to a first layer signal from the LDM signal based on at least a portion of a parity check matrix; a processor configured to encode the first LDPC information bits and the first parity check bits to generate second parity check bits; and a second decoder configured to decode second LDPC information bits corresponding to the second layer signal, determining (or obtaining or generating) the second layer signal by removing the first layer signal corresponding to the first LDPC information bits, the first parity check bits, and the second parity check bits from the LDM signal; wherein the parity check matrix includes the parity check bits. The invention relates to a first part of a matrix and a second part of a parity check matrix; the first part of the parity check matrix includes a first submatrix A (1810) and a second submatrix B (1820), wherein the first submatrix A (1810) corresponds to the first LDPC information bit, and the second submatrix B (1820) is composed of columns with a degree of 2 and only one column with a degree of 1, and is a lower triangular matrix corresponding to the first parity check bit; the second part of the parity check matrix includes a third submatrix C (1840), a fourth submatrix D (1850) and a fifth submatrix E (1860), wherein the third submatrix C (1840) corresponds to the first LDPC information bit, the fourth submatrix D (1850) corresponds to the first parity check bit, and the fifth submatrix E (1860) serves as a unit matrix and corresponds to the second parity check bit.

[0554] The following situation may be arranged alternatively.

[0555] A receiver for receiving and processing a MIMO signal having at least two layers comprises: a first decoder configured to decode the MIMO signal so as to determine (or generate) first low-density parity-check (LDPC) information bits corresponding to a first layer signal of the MIMO signal based on at least a portion of a parity-check matrix; a processor configured to encode the first LDPC information bits and the first parity-check bits to determine (or generate) second parity-check bits; and a processor configured to determine (or identify) a portion of the LDPC information bits; and a second decoder configured to decode a second layer signal of the MIMO signal so as to determine (or generate) second LDPC information bits corresponding to the second layer signal, by removing from the MIMO signal the information bits corresponding to the first layer signal. A second layer signal is determined (or obtained or generated) based on signals corresponding to a portion of an LDPC information bit, a first parity check bit, and a second parity check bit, wherein the parity check matrix includes a first portion of the parity check matrix and a second portion of the parity check matrix; the first portion of the parity check matrix includes: a first submatrix A (1810) corresponding to the LDPC first information bit and a second submatrix B (1820) consisting of columns with a degree of 2 and at least 7 columns with a degree of 3 corresponding to the first parity check bit; and the second portion of the parity check matrix includes: a third submatrix C (1840) corresponding to the first LDPC information bit, a fourth submatrix D (1850) corresponding to the first parity check bit, and a fifth submatrix E (1860) as a unit matrix corresponding to the second parity check bit.

[0556] A receiving method described in an embodiment in combination with [re-encoding method of SCM or LDM system] or [re-encoding method of multi-layer system] will be rearranged as described below.

[0557] A method for receiving and processing a layer division multiplexing (LDM) signal having at least two layers at a receiver, comprising decoding the LDM signal to determine (or generate) a first low-density parity check (LDPC) information bit and a first parity check bit corresponding to a first layer signal of the LDM signal based on at least a portion of a parity check matrix, encoding the first LDPC information bit and the first parity check bit to determine (or generate) a second parity check bit, and decoding the second layer signal of the LDM signal to determine (or generate) a second LDPC information bit corresponding to the second layer signal; and determining (or obtaining) a first low-density parity check (LDPC) information bit and a first parity check bit corresponding to a first layer signal of the LDM signal by removing signals corresponding to the first LDPC information bit, the first parity check bit, and the second parity check bit from the LDM signal. or generating) the second layer signal; wherein the parity check matrix includes a first part and a second part of the parity check matrix, the first part of the parity check matrix includes: a first submatrix A (1810) and a second submatrix B (1820), the first submatrix A (1810) corresponding to the first LDPC information bit, and the second submatrix B (1820) consisting of columns with a degree of 2 and only one column with a degree of 1, and being a lower triangular matrix, corresponding to the first parity check bit; the second part of the parity check matrix includes: a third submatrix C (1840) corresponding to the first LDPC information bit, a fourth submatrix D (1850) corresponding to the first parity check bit, and a fifth submatrix E (1860) corresponding to the second parity check bit and being a unit matrix.

[0558] The method may alternatively be described below.

[0559] A method for receiving and processing a MIMO signal having at least two layers at a receiver, comprising decoding the MIMO signal to determine (or generate) first low-density parity-check (LDPC) information bits corresponding to a first layer signal of the MIMO signal based on at least a portion of a parity-check matrix, encoding the first LDPC information bits and the first parity-check bits to determine (or generate) second parity-check bits and determining (or identifying) a portion of the LDPC information bits, and decoding the second layer signal of the MIMO signal to determine (or generate) second LDPC information bits corresponding to the second layer signal, by removing the portion corresponding to the first LDPC information bits, the first parity-check bits, and the second parity-check bits from the MIMO signal. The second layer signal is determined (or obtained or generated) based on a special signal, wherein the parity check matrix includes a first part and a second part of the parity check matrix, the first part of the parity check matrix includes: a first submatrix A (1810) and a second submatrix B (1820), the first submatrix A (1810) corresponding to the first LDPC information bit, the second submatrix B (1820) corresponding to the first parity check bit and consisting of columns with a degree of 2 and at least 7 columns with a degree of 3, and the second part of the parity check matrix includes: a third submatrix C (1840) corresponding to the first LDPC information bit, a fourth submatrix D (1850) corresponding to the first parity check bit, and a fifth submatrix E (1860) corresponding to the second parity check bit and serving as a unit matrix.

[0560] In certain embodiments, such as those described above, for convenience, the process of regenerating parity bits based on error detection and according to an outer code such as a BCH or CRC code is omitted. However, it can be determined that the process of regenerating parity based on the error detection results of the outer code as described in [Recoding Method 1] to [Recoding Method 5] is performed. When a CRC code is used as an outer code, only error detection can be performed. However, when a BCH code is used, in addition to error detection, error correction can also be performed. For example, if it is determined that there are no errors, the parity can be recoded or regenerated in whole or in part by performing BCH decoding and error detection on the information bits after LDPC decoding. However, if it is determined that any error has occurred, the operation of regenerating parity can be omitted. The process of regenerating parity can be performed regardless of whether error detection is performed. Specifically, after performing BCH decoding, parity generation can be performed instead of omitting error detection.

[0561] In the [Recoding Method for an SCM or LDM System] or the [Recoding Method for a Multi-Layer System], the first parity check applied to determine or generate the second parity check may be a parity check determined or generated by the first decoder or during the first decoding process, or may be a parity check determined or generated by encoding based on the first LDPC information bits, or may be a parity check determined or generated by the first decoder or during the first decoding process. The first LDPC decoder and the second LDPC decoder may be implemented as a single LDPC decoder (i.e., the first and second LDPC decoders are substantially identical) or as two separate decoders. When the parity check matrix of the LDPC code used in the first LDPC decoder is given as the first parity check matrix and the parity check matrix of the LDPC code used in the second decoder is given as the second parity check matrix, the first parity check matrix and the second parity check matrix may generally use different parity check matrices. However, depending on the situation, they may use the same parity check matrix. Furthermore, the encoder in item 3) of the [Recoding Method for an SCM or LDM System] and the [Recoding Method for a Multi-Layer System] may be implemented as a separate encoder. However, the encoder can be implemented based on a processor to process the syndrome as described above. The recoding process of [the recoding method for an SCM or LDM system] and [the recoding method for a multi-layer system] can be performed based on the above-mentioned implementation code. In addition, in the case of a two-layer LDM or SCM system, the layer on which decoding is first performed is given as the first layer, and the layer on which decoding is subsequently performed after performing the interference cancellation operation is given as the second layer, and the first layer can use a modulation and coding combination that is equal to or stronger than the second layer in terms of performance robustness. More robust performance may mean that under the same signal-to-noise ratio (SNR) conditions, greater spectral efficiency or a larger product of the modulation order and the code rate can be supported, or a lower BLER can be supported.

[0562] In addition, the above embodiment can be applied to all systems that can divide signals into two or more layers, including SCM systems, LDM systems, MIMO systems or NOMA systems. That is, after receiving modulated signals generated by two or more layers (for example: SCM signals, LDM signals, MIMO signals, NOMA signals, etc.), the receiver can perform data decoding on the second layer by performing data decoding on the first layer according to the received signal, and then, based on the decoded data, appropriately perform interference elimination from the received signal, as in the above embodiment. This operation can be performed in a manner of eliminating interference in sequence. Alternatively, the first and second layers of the received signal have been decoded separately, and the process of determining the second layer signal by generating a modulated signal for the first layer based on the decoded first layer data and removing them from the received signal, and the process of determining the first layer signal by generating a modulated signal for the second layer based on the decoded second layer data and removing them from the received signal can be performed independently (or simultaneously or in parallel) (here, the data can indicate LDPC information bits and / or parity bits, etc.). Each layer can be decoded again based on the signal whose interference is eliminated independently (or simultaneously or in parallel).

[0563] In the drawings describing the methods of the present disclosure, the order of description does not always correspond to the order in which the steps of each method are performed, and the sequential relationship between the steps may change, or the steps may be performed in parallel.

[0564] Alternatively, some elements may be omitted, and only some elements may be included in the drawings describing the method of the present disclosure without departing from the essential spirit and scope of the present disclosure.

[0565] Furthermore, without departing from the essential spirit and scope of the present disclosure, part or all of the contents of the various embodiments may be combined in the method according to the present disclosure.

[0566] Although the present disclosure has been described above by way of exemplary embodiments, various changes and modifications may be provided by those skilled in the art. Such changes and modifications are intended to fall within the scope of the appended claims. Furthermore, in the operational flow charts of the present disclosure, for convenience, the operations represented by different blocks are described as being performed by multiple processors, but in actual systems, they may also be performed entirely by a single processor.

[0567] Although the present disclosure has been described with various embodiments, various changes and modifications may occur to those skilled in the art. The present disclosure is intended to encompass such changes and modifications as fall within the scope of the appended claims.< / null> < / null>

Claims

1. A method, performed by a receiver, for processing multiple-input multiple-output (MIMO) signals associated with at least two layers in a communication system, the method comprising: Decoding the MIMO signal based on at least a portion of a parity check matrix to determine first low-density parity check (LDPC) information bits corresponding to a first layer of the MIMO signal; Determining a second parity bit based on the first LDPC information bit and the first parity bit; determining a portion of the first LDPC information bits; and determining a second layer signal of the MIMO signal to determine a second LDPC information bit corresponding to the second layer signal, wherein the second layer signal is determined by removing signals corresponding to the portion of the first LDPC information bits, the first parity check bits, and the second parity check bits from the MIMO signal, and Wherein, all column weights of a submatrix of the parity check matrix corresponding to the first parity check bit are greater than or equal to 2, and at least one of the column weights is greater than or equal to 3.

2. The method according to claim 1, wherein Decoding the MIMO signal includes: identifying a number of input bits based on the MIMO signal; identifying a block size based on the number of input bits; and The parity-check matrix corresponding to the block size is identified.

3. The method according to claim 1, wherein The portion of the first LDPC information bits is determined by puncturing at least one information bit of the first LDPC information bits.

4. The method according to claim 1, wherein Determining the second layer signal includes interleaving at least a portion of the first LDPC information bits, the first parity bits, and the second parity bits.

5. The method according to claim 4, wherein Determining the second layer signal includes performing modulation based on the interleaved portion of the first LDPC information bits, the interleaved first parity bits, and the interleaved second parity bits.

6. The method according to claim 1, wherein Decoding the MIMO signal includes: identifying a first LDPC syndrome value based on the first LDPC information bits and at least a portion of the first parity bits; and When the first LDPC syndrome value is 0 and the cyclic redundancy check detection performed on the first layer signal is successful, the second parity bit is determined based on the first LDPC information bit and the first parity bit, the cyclic redundancy check is CRC.

7. A receiver for processing multiple-input multiple-output (MIMO) signals associated with at least two layers in a communication system, the receiver comprising: transceiver; as well as a controller coupled to the transceiver and configured to: Decoding the MIMO signal based on at least a portion of a parity check matrix to determine first low-density parity check (LDPC) information bits corresponding to a first layer of the MIMO signal, wherein the low-density parity check (LDPC) matrix is ​​used. determining a second parity bit based on the first LDPC information bit and the first parity bit, determining a portion of the first LDPC information bits, and, determining a second layer signal of the MIMO signal to determine a second LDPC information bit corresponding to the second layer signal, wherein the second layer signal is determined by removing signals corresponding to the portion of the first LDPC information bits, the first parity check bits, and the second parity check bits from the MIMO signal, and Wherein, all column weights of a submatrix of the parity check matrix corresponding to the first parity check bit are greater than or equal to 2, and at least one of the column weights is greater than or equal to 3.

8. The receiver according to claim 7, wherein The controller is configured to: identifying a number of input bits based on the MIMO signal, Based on the number of input bits, identifying the block size, and The parity-check matrix corresponding to the block size is identified.

9. The receiver according to claim 7, wherein The controller is configured to puncture at least one of the first LDPC information bits.

10. The receiver according to claim 7, wherein The controller is configured to interleave at least a portion of the first LDPC information bits, the first parity bits, and the second parity bits.

11. The receiver according to claim 10, wherein The controller is configured to perform modulation based on an interleaved portion of the first LDPC information bits, the interleaved first parity bits, and the interleaved second parity bits.

12. The receiver according to claim 7, wherein The controller is configured to: identifying a first LDPC syndrome value based on at least a portion of the first LDPC information bits and the first parity bits, and When the first LDPC syndrome value is 0 and the cyclic redundancy check detection performed on the first layer signal is successful, the second parity bit is determined based on the first LDPC information bit and the first parity bit, the cyclic redundancy check is CRC.

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