Wafer is centered in the slot to improve azimuthal thickness uniformity around the wafer edge

Abstract

The present invention relates to centering a wafer in a slot to improve azimuthal thickness uniformity at the edge of the wafer. A method for reducing wafer slip during film deposition includes evacuating a process chamber while the wafer is supported on lift pins or a carrier ring, and lowering the wafer onto a support member configured to minimize wafer slip during film deposition. A multi-station process chamber, such as a process chamber for atomic layer deposition, may include a chuckless pedestal at each station, each station having a wafer support configured to prevent the wafer from moving more than 400 microns off center. To minimize the air cushion under the wafer, the wafer support may provide a gap of at least 2 mils between the back side of the wafer and the surface of the pedestal facing the wafer.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 201710604907.2, application date July 24, 2017, invention name “Centering the chip in the groove to improve the azimuthal thickness uniformity of the chip edge”, and applicant is “Rum Research Company”. Technical Field

[0002] The present disclosure is generally directed to a method of improving uniformity of films deposited on a wafer supported on a chuckless pedestal in a semiconductor processing tool. Certain aspects of the present disclosure are directed to preventing wafer slippage during deposition of a film on the wafer. Background Art

[0003] During deposition in the processing chamber, the film can be deposited on the front side of the wafer. For example, in atomic layer deposition (ALD), the film can be deposited layer by layer by successive dosing and activation steps. In the ALD processing chamber, a precursor gas can be directed to the wafer, and the precursor gas can be chemically adsorbed onto the surface of the wafer to form a monolayer. Additional precursor gases that react with the monolayer can be introduced, and then a purge gas can be introduced to remove excess precursor and gaseous reaction byproducts. The precursor gases can be pulsed alternately without overlapping, and the cycle can be repeated as many times as needed to form a film of appropriate thickness.

[0004] However, when the wafer is held by a chuckless method, wafer slippage may occur and result in uneven thickness of the film deposited at the edge of the wafer. For example, during the deposition process, the wafer may be supported on a wafer support that provides a gap between the wafer and the upper surface of the susceptor, and the air cushion in the gap may cause the wafer to move (slip) so that the wafer moves closer to one edge of the pocket where the wafer is located. If the wafer is not centered in the pocket, the film thickness may be uneven at the edge of the wafer.

[0005] It would therefore be desirable to provide a solution to the wafer slip problem during film deposition to improve azimuthal thickness uniformity at the wafer edge. Summary of the invention

[0006] A method for processing a semiconductor substrate (wafer) is disclosed herein, wherein the method comprises: supporting the wafer above a wafer-facing surface of a chuckless pedestal in a processing chamber; evacuating the processing chamber to a reduced pressure that is effective in reducing slippage of the wafer when placed on a wafer support extending from the wafer-facing surface of the pedestal; lowering the wafer onto the wafer support while the processing chamber is at the reduced pressure, and supporting the wafer a sufficient distance above the wafer-facing surface of the chuckless pedestal to reduce slippage during deposition of a film on the wafer; and depositing a film on the wafer while the wafer is supported on the wafer support, wherein after deposition of the film, the off-center wafer slips less than 400 microns from its initial position.

[0007] In one embodiment, the processing chamber includes at least a first station, a second station, a third station, and a fourth station, the first station having a first chuckless pedestal and a first carrier ring at a periphery thereof supporting a first wafer, the second station having a second chuckless pedestal and a second carrier ring at a periphery thereof supporting a second wafer, the third station having a third chuckless pedestal and a third carrier ring at a periphery thereof, and the fourth station having a fourth chuckless pedestal and a fourth carrier ring at a periphery thereof, the method further comprising: simultaneously raising the first carrier ring, the second carrier ring, the third carrier ring, and the fourth carrier ring at the first station, the second station, the third station, and the fourth station; The first, second, third and fourth carrier rings are indexed so that the first and second wafers on the first and second carrier rings move to the third and fourth stations; the processing chamber is evacuated to a pressure that effectively reduces the slippage of the first and second wafers when placed on wafer supports extending from wafer-facing surfaces of the third and fourth chuckless pedestals; and the first and second wafers are lowered onto the wafer supports of the third and fourth chuckless pedestals while the processing chamber is under the reduced pressure. The method may also include: transferring a third wafer and a fourth wafer into the processing chamber at the first station and the second station; supporting the third wafer and the fourth wafer on raised lift pins at the first station and the second station; evacuating the processing chamber to a pressure effective to reduce slippage of the third wafer and the fourth wafer when placed on the wafer supports at the first station and the second station; and while the processing chamber is under the reduced pressure, lowering the lift pins at the first station and the second station so as to support the third wafer and the fourth wafer on the wafer supports of the first and second chuckless pedestals.

[0008] In some implementations, the method includes flowing a gas onto the front side of the wafer while the pressure in the process chamber is reduced to the reduced pressure. Preferably, the wafer support includes at least three minimum contact area (MCA) support members extending at least 2 mils above the wafer facing surface, at least 4 mils above the wafer facing surface, or at least 6 mils above the wafer facing surface.

[0009] In some implementations, the wafer is supported on lift pins while the pressure in the process chamber is reduced to the reduced pressure, and the wafer is lowered onto the wafer support by lowering the lift pins while maintaining the process chamber at the reduced pressure.

[0010] In some implementations, the wafer is supported on a carry ring while the pressure in the processing chamber is reduced to the reduced pressure.

[0011] In some implementations, the reduced pressure is 0.5 Torr or less, 0.2 Torr or less, or 0.1 Torr or less.

[0012] In some implementations, the film deposition includes atomic layer deposition (ALD) on the front side of the wafer. By reducing the slip of the wafer, the non-uniformity of the film thickness at a distance of 1.8 mm from the outer edge of the wafer can be about 0.5% or less, and / or the film thickness variation at a distance of 1.5 mm from the outer edge of the wafer can be less than 5 angstroms.

[0013] In some implementations, film deposition may be performed in a single station of a process chamber, or film deposition may be performed sequentially in four stations of a process chamber.

[0014] Specifically, some aspects of the present invention can be described as follows:

[0015] 1. A method for reducing wafer slip during deposition of a film on a wafer, the method comprising:

[0016] supporting the wafer on lift pins or a carry ring so that the wafer is above a wafer support on a non-chuck base facing surface in a processing chamber with a gap between an outer edge of the wafer and a wall of a slot;

[0017] evacuating the process chamber to a reduced pressure while supporting the wafer on the lift pins or carry ring above the wafer support to effectively reduce slippage of the wafer when placed on a wafer support extending from the wafer-facing surface of the pedestal;

[0018] lowering the lift pins or carry ring so that the wafer is lowered onto the wafer support while the processing chamber is at the reduced pressure and supports the wafer a sufficient distance above the wafer-facing surface of the chuckless pedestal to reduce lateral slippage in the grooves during deposition of a film on the wafer;

[0019] A film is deposited on the wafer while the wafer is supported on the wafer support, wherein after depositing the film, the off-center wafer slips less than 400 microns from its initial position.

[0020] 2. The method of clause 1, wherein after depositing the film, the off-center wafer slips less than 200 microns from its initial position.

[0021] 3. The method of clause 1, wherein the reduced pressure is less than 0.5 Torr.

[0022] 4. A method of reducing slippage of a wafer during deposition of a film on the wafer, the method comprising:

[0023] supporting the wafer above a wafer-facing surface of a non-chuck pedestal in a processing chamber;

[0024] evacuating the processing chamber to a reduced pressure effective to reduce slippage of the wafer when placed on a wafer support extending from the wafer-facing surface of the susceptor;

[0025] lowering the wafer onto the wafer support while the processing chamber is at the reduced pressure and supporting the wafer a sufficient distance above the wafer-facing surface of the chuckless pedestal to reduce slippage during deposition of a film on the wafer;

[0026] depositing a film on the wafer while the wafer is supported on the wafer support, wherein after depositing the film, the off-center wafer slips less than 400 microns from its initial position;

[0027] wherein the processing chamber comprises at least a first station, a second station, a third station and a fourth station, the first station having a first chuckless base and a first carrier ring at its periphery supporting a first wafer, the second station having a second chuckless base and a second carrier ring at its periphery supporting a second wafer, the third station having a third chuckless base and a third carrier ring at its periphery, and the fourth station having a fourth chuckless base and a fourth carrier ring at its periphery, the method further comprising: simultaneously raising the first carrier ring, the second carrier ring, the third carrier ring and the fourth carrier ring at the first station, the second station, the third station and the fourth station ; indexing the first carrier ring, the second carrier ring, the third carrier ring and the fourth carrier ring so that the first wafer and the second wafer on the first carrier ring and the second carrier ring are moved to the third station and the fourth station; evacuating the processing chamber to a pressure that effectively reduces the slippage of the first wafer and the second wafer when placed on a wafer support extending from a wafer-facing surface of the third and fourth chuckless pedestals; while the processing chamber is under the reduced pressure, lowering the first wafer and the second wafer onto the wafer supports of the third and fourth chuckless pedestals.

[0028] 5. The method according to claim 4 further includes: transferring a third wafer and a fourth wafer into the processing chamber at the first station and the second station; supporting the third wafer and the fourth wafer on raised lift pins at the first station and the second station; evacuating the processing chamber to a pressure that effectively reduces the slippage of the third wafer and the fourth wafer when placed on the wafer supports at the first station and the second station; while the processing chamber is under the reduced pressure, lowering the lift pins at the first station and the second station so as to support the third wafer and the fourth wafer on the wafer supports of the first chuckless base and the second chuckless base.

[0029] 6. The method of clause 1, wherein the wafer support comprises at least three minimum contact area (MCA) support members.

[0030] 7. The method of clause 1, wherein the wafer support extends at least 2 mils above the wafer-facing surface.

[0031] 8. The method of clause 1, wherein the wafer support extends at least 4 mils above the wafer-facing surface.

[0032] 9. The method of clause 1, wherein the wafer support extends at least 6 mils above the wafer-facing surface.

[0033] 10. The method of clause 1, further comprising flowing a gas onto the front side of the wafer while the pressure in the process chamber is reduced to the reduced pressure.

[0034] 11. The method of clause 1, wherein the wafer is supported on lift pins while the pressure in the process chamber is reduced to the reduced pressure.

[0035] 12. The method of clause 11, wherein the wafer is lowered onto the wafer support by lowering the lift pins while maintaining the process chamber at the reduced pressure.

[0036] 13. The method of clause 1, wherein the wafer is supported on a carry ring while the pressure in the processing chamber is reduced to the reduced pressure.

[0037] 14. The method of clause 1, wherein the reduced pressure is 0.2 Torr or less.

[0038] 15. The method of clause 1, wherein the reduced pressure is 0.05 Torr or less.

[0039] 16. The method of clause 1, wherein the film deposition comprises atomic layer deposition (ALD) on a front side of the wafer.

[0040] 17. The method of clause 16, wherein the film thickness variation at a distance of 1.5 mm from the outer edge of the wafer is less than 5 angstroms.

[0041] 18. The method of clause 16, wherein the film deposition is performed in a single processing station of the processing chamber.

[0042] 19. The method according to clause 16, wherein the film deposition is performed sequentially in four stations of the process chamber. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1A A schematic cross-sectional view of an exemplary apparatus for processing a wafer is shown.

[0044] Figure 1B An enlarged view of a cross-sectional schematic diagram of an exemplary apparatus for processing a wafer is shown.

[0045] Figure 2 A top view of a schematic diagram of an exemplary multi-station processing tool is shown.

[0046] Figure 3 A perspective view of an example pedestal having a plurality of wafer supports configured to extend from the pedestal, including an outer wafer support and an inner wafer support, is shown.

[0047] Figure 4 A perspective view of an example pedestal having a plurality of wafer supports configured to extend from the pedestal, including an inner wafer support, is shown.

[0048] Figure 5 A side view schematic illustrating wafer sag caused by an inner wafer support of an example susceptor having a carry ring is shown.

[0049] Fig. 6A A perspective cutaway view of a portion of an example susceptor having a carrier ring is shown.

[0050] Figure 6B Shows that there is Fig. 6A A cross-sectional view of a portion of an example base of a carrier ring.

[0051] Figure 6C Shows that there is Fig. 6A A cross-sectional view of the outer edge of an exemplary susceptor of a carry ring and wafer.

[0052] Figure 7 A depiction of automatic wafer centering (AWC) data for a standard wafer transfer process for stations 1 and 2 of a four-station deposition chamber is shown, wherein the wafer is placed on a chuckless pedestal having a minimum contact area (MCA) support extending 2 mils above the substrate-facing surface of the pedestal, and the chamber pressure is 0.5 Torr during placement of the wafer on the wafer support.

[0053] Figures 8A-8B A depiction of AWC data comparing two wafer placement processes for stations 1-4 of a four-station deposition chamber is shown, where Fig. 8A Data is shown for a standard wafer placement process where the wafer is lowered onto an MCA having a height of 2 mils and a chamber pressure of 0.5 Torr, and Figure 8B Data is shown for a low pressure wafer placement process where the wafer is lowered onto an MCA having a height of 4 mils and the pump-to-base chamber pressure is <0.01 Torr when the wafer is placed on a wafer support.

[0054] Fig. 9 Graphs of chamber pressure (P), gas flow (MFC), and throttle valve position (TV) for standard wafer placement are shown.

[0055] Fig.10 Graphs of chamber pressure (P), gas flow (MFC), and throttle valve position (TV) for low pressure wafer placement are shown. DETAILED DESCRIPTION

[0056] In the following description, many specific details are set forth in order to provide a thorough understanding of the concepts presented. The concepts presented can be practiced without some or all of these specific details. In other cases, well-known processing operations are not described in detail to avoid unnecessarily obscuring the concepts. Although some concepts will be described in conjunction with specific embodiments, it should be understood that these embodiments are not intended to be restrictive.

[0057] introduce

[0058] In this application, the terms "semiconductor substrate", "wafer", "substrate", "wafer substrate" and "partially fabricated integrated circuit" are used interchangeably. One of ordinary skill in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer during any of the many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present invention is implemented on a wafer. However, the present invention is not limited to this. The workpiece can have a variety of shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present invention include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0059] Figure 1A A cross-sectional schematic diagram of an exemplary apparatus for processing a wafer is shown. The apparatus 100 can be used to process a wafer 101. The apparatus 100 can include a processing chamber 102 having an upper chamber portion 102a and a lower chamber portion 102b. The apparatus 100 can also include a susceptor 140 configured to support the wafer 101. In some implementations, the susceptor 140 can be used as a power supply electrode. In some implementations, the susceptor 140 can be electrically coupled to a power supply 104 via a matching network 106. The power supply 104 can be controlled by a system controller 110, wherein the system controller 110 can be configured with various instructions for performing operations of the apparatus 100. The system controller 110 can be configured with instructions for performing process input and control 108, which can include process recipes, such as power levels, timing parameters, deposition parameters, process gases, movement of the wafer 101, etc.

[0060] In some embodiments, the apparatus 100 may include lift pins 120 controllable by a lift pin control 122. The lift pins 120 may be used to elevate the wafer 101 from the pedestal 140 to enable a wafer handling system (eg, an end effector) to transfer the wafer 101 to and from the pedestal 140.

[0061] In some implementations, the apparatus 100 can include a gas supply manifold 112 configured to receive a process gas 114. In some embodiments, the system controller 110 can control the delivery of the process gas 114 via the gas supply manifold 112. The selected process gas 114 can be delivered to a showerhead 150, and the showerhead 150 can distribute the selected process gas 114 toward the wafer 101 supported on the susceptor 140. It should be understood that the showerhead 150 can have any suitable shape and can have any suitable number and arrangement of ports for distributing the process gas 114 to the wafer 101.

[0062] Also shown is a carrier ring 200 surrounding an outer region of the susceptor 140. The carrier ring 200 can be configured to support the wafer 101 during transfer of the wafer 101 to and from the susceptor 140. The carrier ring 200 can include an annular body positioned around an outer region of the susceptor 140. One or more contact structures 180 (e.g., spider forks) can be configured to elevate the wafer 101 and the carrier ring 200. The carrier ring 200 can be elevated with the wafer 101 so that the wafer 101 can be transferred to another station, such as another station in a multi-station processing tool.

[0063] In some implementations, the processing chamber 102 of the apparatus 100 can be configured to deposit a film on the wafer 101. In some implementations, the processing chamber 102 can be a capacitively coupled plasma processing chamber. For example, the processing chamber 102 can be configured to deposit a film by PECVD or ALD.

[0064] Figure 1B An enlarged view of a cross-sectional schematic diagram of an exemplary apparatus for processing a wafer is shown. Apparatus 100 may be configured to deposit a film on wafer 101 by ALD. The film may include an ALD oxide. Figure 1A 100. However, in some implementations, such as Figure 1B As shown, power 104 may be provided to a spray head 150 .

[0065] In some implementations, the apparatus 100 may further include one or more wafer supports (not shown) configured to extend from the pedestal 140 to support the wafer 101 above a wafer-facing surface of the pedestal 140. Figure 3-5 The one or more wafer supports are discussed.

[0066] Figure 2A top view of a schematic diagram of an exemplary multi-station processing tool is shown. The multi-station processing tool may include four processing stations. The top view is a top view of the lower chamber portion 102b, with the upper chamber portion 102a removed for ease of illustration. The four processing stations may be accessed by a spider fork 280. Each spider fork 280 includes a first arm and a second arm, each arm being located around a portion of each side of the base 140. The spider fork 280 uses an engagement and rotation mechanism 220 that may, for example, raise and lift a carrier ring 200 from its lower surface, wherein each carrier ring 200 may support a wafer. This action of lifting the carrier ring 200 may be performed simultaneously from the processing stations, and then the engagement and rotation mechanism 220 rotates before lowering the carrier ring 200 to the next processing station in at least one or more processing stations, thereby performing further processing on the corresponding wafer.

[0067] Figure 3 A perspective view of an example pedestal having a plurality of wafer supports configured to extend from the pedestal, including an outer wafer support and an inner wafer support, is shown. Figure 3 The illustrated base 300 may be incorporated into Figure 1A and 1B In the apparatus 100 of , the pedestal 300 can be configured to receive a wafer (not shown) for a deposition process such as ALD. The pedestal 300 includes a wafer-facing surface 302 extending from a central axis 320 to an outer edge 324. The wafer-facing surface 302 can be a circular area defined by a diameter 322. The wafer-facing surface 302 can be referred to as a table or a central top surface of the pedestal 300.

[0068] A plurality of wafer supports 304a, 304b, 304c, 304d, 304e, and 304f may extend from the pedestal 300 and be configured to support a wafer at a horizontal plane above the wafer-facing surface 302. The wafer supports 304a, 304c, and 304e may constitute outer wafer supports, and the wafer supports 304b, 304d, and 304f may constitute inner wafer supports. When the wafer is supported from the wafer-facing surface 302 by the wafer supports 304a, 304b, 304c, 304d, 304e, and 304f, the horizontal plane above the wafer-facing surface 302 may be defined by the vertical position of the back side of the wafer. Figure 3 In the embodiment of the present invention, the plurality of wafer supports 304a, 304b, 304c, 304d, 304e and 304f include six wafer supports, but any number of wafer supports (eg, any number between approximately 3 and 30 wafer supports) may be assigned to support a wafer.

[0069] In some implementations, the pedestal 300 may include a plurality of wafer supports 304a, 304b, 304c, 304d, 304e, and 304f. The wafer supports 304a, 304b, 304c, 304d, 304e, and 304f may be referred to as minimum contact area (MCA) supports, which are used to maintain a small gap between the pedestal 300 and the back of the wafer. When high precision or tolerance is required and / or minimal physical contact is desired to reduce the risk of defects, MCA supports may be used to improve the precision fit between surfaces. The wafer supports 304a, 304b, 304c, 304d, 304e, and 304f may be separate components, such as sapphire balls or pins located within a recess of the pedestal 300 or integrated into the pedestal 300. The wafer supports 304a, 304b, 304c, 304d, 304e, and 304f may be made of any suitable insulating material (e.g., a dielectric material). The height of the wafer supports 304a, 304b, 304c, 304d, 304e, and 304f may be adjustable so that the gap size may be controlled to control the slippage of the wafer during film deposition. In some implementations, the height may be between about 0.002 inches (2 mils) and about 0.010 inches (10 mils), between about 2 mils and about 7 mils, or about 4 mils above the wafer-facing surface 302 of the pedestal 300.

[0070] Although a small gap may be required between the wafer and the pedestal 300 to normalize the impedance, the air cushion under the wafer can cause the wafer to move (slip) away from the center of the pedestal during placement of the wafer on the wafer support. However, if the wafer supports 304a, 304b, 304c, 304d, 304e, and 304f provide sufficient gap between the wafer and the pedestal 300, the effect of the air cushion under the wafer can be reduced. To further reduce the possibility of wafer slip during placement of the wafer, the chamber pressure can be reduced prior to placement of the wafer, thereby minimizing or eliminating the air cushion under the wafer when the wafer is placed on the wafer support. By providing a wafer support having sufficient height, wafer slip can be reduced during film deposition on the wafer, thereby providing better film thickness uniformity at the outer edge of the wafer.

[0071] The base 300 may include a plurality of recesses 306a, 306b, and 306c configured to accommodate lift pins. As described above, the lift pins may be used to lift the wafer from the wafer supports 304a, 304b, 304c, 304d, 304e, and 304f to allow engagement by a wafer handling system (e.g., an end effector). During wafer placement, the wafer may be supported on the lift pins as the chamber pressure is reduced, and the lift pins are lowered to place the wafer on the wafer support as the chamber pressure is reduced.

[0072] Adjacent to the outer edge 324 of the wafer-facing surface 302, the susceptor 300 may also include an annular surface 310 extending around a peripheral region of the susceptor 300. The annular surface 310 may define a peripheral region of the susceptor 300 and surround the wafer-facing surface 302, but at a step down from the wafer-facing surface 302. That is, the vertical position of the annular surface 310 may be lower than the vertical position of the wafer-facing surface 302.

[0073] In some implementations, a plurality of carrier ring support structures 312a, 312b, and 312c may be positioned at the outer edge of the annular surface 310. The carrier ring support structures 312a, 312b, and 312c may be symmetrically arranged around the annular surface 310. The carrier ring support structures 312a, 312b, and 312c may be used as MCA supports for supporting the carrier rings. In some implementations, the carrier ring support structures 312a, 312b, and 312c may extend beyond the outer edge of the annular surface 310. In some implementations, the height of the top surface of the carrier ring support structures 312a, 312b, and 312c may be higher than the height of the annular surface 310, so that the carrier ring may be supported at a predetermined distance above the annular surface 310. Each of the carrier ring support structures 312a, 312b, and 312c may include a recess 313 through which an extension protruding from the underside of the carrier side passes when the carrier ring is supported on the carrier ring support structure 312a, 312b, and 312c. The cooperation of the extension with the recess 313 in the carrier ring support structure 312a, 312b, and 312c may provide secure positioning of the carrier ring. Although Figure 3 Three carrier ring support structures 312a, 312b, and 312c are shown, but any number of carrier ring support structures along and anywhere along the outer edge of the annular surface 310 may be used.

[0074] Typically, a susceptor having a wafer support holds the wafer such that the wafer is substantially parallel to the susceptor or such that the wafer support minimizes deflection or sagging of the wafer. Figure 3 The wafer supports 304a, 304b, 304c, 304d, 304e and 304f in FIG. 3 are arranged to support the wafer above a substantially uniform gap maintained between the wafer and the wafer-facing surface 302. Figure 3 The wafer supports 304a, 304b, 304c, 304d, 304e and 304f in the embodiment are arranged to support the wafer so as to minimize wafer deflection and sagging. Figure 3The base 300 in can have six adjustable MCA supports 304a, 304b, 304c, 304d, 304e, and 304f, wherein three MCA supports 304b, 304d, and 304f are evenly arranged on a 5 inch bolt circle, and three MCA supports 304a, 304c, and 304e are evenly arranged on a 10 inch bolt circle. The MCA supports 304b, 304d, and 304f can be arranged in a triangular pattern at 60 degrees, and the MCA supports 304a, 304c, and 304e can be arranged in a triangular pattern at 60 degrees.

[0075] Figure 4 A perspective view of an example pedestal having a plurality of wafer supports configured to extend from the pedestal, including an inner wafer support, is shown. Figure 4 The illustrated base 400 may be incorporated into Figure 1A and 1B In the apparatus 100 of , the pedestal 400 can be configured to receive a wafer for a deposition process (e.g., ALD). The pedestal 400 includes a wafer-facing surface 402 extending from a central axis 420 to an outer edge 424. The wafer-facing surface 402 can be a circular area defined by a diameter 422.

[0076] A plurality of wafer supports 404 a , 404 b , and 404 c may extend from the pedestal 400 and be configured to support a wafer at a level above the wafer-facing surface 402 . Figure 4 The plurality of wafer supports 404a, 404b and 404c may be incorporated into Figure 1A and 1B The wafer supports 404a, 404b and 404c may be arranged symmetrically around the central axis 420 of the wafer-facing support. The horizontal plane above the wafer-facing surface 402 may be defined by the vertical position of the back side of the wafer when the wafer is supported by the wafer supports 404a, 404b and 404c from the wafer-facing surface 402. Figure 4 In the embodiment, the plurality of wafer supports 404a, 404b and 404c include three wafer supports, but any number of wafer supports (e.g., any number of wafer supports between about 3 and 30 wafer supports) may be allocated to support a wafer. Three or more wafer supports 404a, 404b and 404c may constitute an inner wafer support.

[0077] In some implementations, the pedestal 400 may include a plurality of wafer supports 404a, 404b, and 404c. The wafer supports 404a, 404b, and 404c may be referred to as MCA supports, which are used to maintain a small gap between the pedestal 400 and the back of the wafer. When high precision or tolerance is required and / or minimal physical contact is desired to reduce the risk of defects, the MCA supports may be used to improve the precision fit between the surfaces. The wafer supports 404a, 404b, and 404c may be independent components, such as sapphire balls or pins located in a recess of the pedestal 400 or integrated into the pedestal 400. The wafer supports 404a, 404b, and 404c may be made of any suitable insulating material (e.g., a dielectric material). The height of the wafer supports 404a, 404b, and 404c may be adjustable, so that the gap size may be controlled. In some implementations, the height can be between about 2 mils and about 10 mils, between about 2 mils and about 7 mils, or about 4 mils above the wafer-facing surface 402 of the pedestal 400. A gap is provided between the back side of the wafer and the pedestal 400, wherein the size of the gap is designed to minimize slippage of the wafer during placement of the wafer and during deposition of a film on the wafer.

[0078] In addition, the base 400 may include a plurality of recesses 406a, 406b, and 406c configured to accommodate lift pins. As described above, the lift pins may be used to elevate the wafer from the wafer supports 404a, 404b, and 404c to allow engagement by a wafer handling system (e.g., an end effector). Details of an end effector with an integrated aligner may be found in commonly assigned U.S. Pat. No. 9,299,598, the disclosure of which is incorporated herein by reference.

[0079] Figure 5 A side view of a schematic diagram of wafer sag caused by an inner wafer support for an example susceptor having a carry ring is shown. Figure 5 In the embodiment of the present invention, the pedestal 500a may include a table or wafer-facing surface 502a facing the back of the wafer 501a. The pedestal 500a may also include an annular surface 510a located around the wafer-facing surface 502a and one step down from the wafer-facing surface 502a. The wafer 501a may include a central area and an outer edge, wherein the wafer 501a can sag / deflect at its outer edge. The outer edge of the wafer 501a may extend beyond the wafer-facing surface 502a and extend on the annular surface 510a. The carrying ring 520a surrounds the outer edge of the wafer-facing surface 502a. The carrying ring 520a may include an annular body positioned around the outer area of ​​the pedestal 500a.

[0080] Fig. 6AA perspective cutaway view of a portion of an example pedestal with a carrier ring is shown. A carrier ring 630 is shown held atop a carrier ring support 612 above an annular surface 610. In some implementations, a carrier ring extension 631 is located within a recess 613 of the carrier ring support 612. Additionally, a wafer 601 is shown resting on a wafer-facing surface 602 of the pedestal 600, wherein the wafer 601 is supported by a wafer support (not shown). The height of the carrier ring support 612 is adjustable to allow adjustment of the distance above the annular surface 610 of the pedestal 600. In some implementations, the carrier ring support 612 includes a spacer 616 (e.g., a shim) for adjusting the height of at least one of the carrier ring supports 612. That is, when the carrier ring 630 rests on the carrier ring support 612, the spacer 616 can be selected to provide a controlled distance between the carrier ring 630 and the annular surface 610. It should be understood that there may be zero, one, or more than one spacer 616 selected and positioned beneath the carry ring support 612 to provide a desired distance between the annular surface 610 and the carry ring 630 .

[0081] Additionally, the load ring supports 612 and the spacers 616 can be secured to the base 600 by fastening hardware 614. In some implementations, the hardware 614 can include screws, bolts, nails, pins, or other types of hardware suitable for securing the load ring supports 612 and the spacers 616 to the base 600. In other implementations, other techniques / materials for securing the load ring supports 612 and the spacers 616 to the base 600 can be used, such as a suitable adhesive.

[0082] Figure 6B Shows that there is Fig. 6A 612. The overall height of the carry ring support 612 can be defined by the combined height of the spacer 616 and the carry ring support 612. This can also determine the extent to which the top surface of the carry ring support 612 is higher than the annular surface 610 of the pedestal 600.

[0083] Figure 6C Shows that there is Fig. 6A 601 from the carrier ring 630, and the carrier ring 630 from the annular surface 610. The one or more gaps may provide a path for delivering process gases (e.g., precursors, free radical species, etc.) to the back side of the wafer 601. Figure 6CAs shown, the carrier ring 630 includes an annular body having a top surface 632 and a surface 634 that is stepped down. The top surface 632 and the surface 634 that is stepped down may be joined together by a transition step. It should be understood that the surface 634 that is stepped down is defined near the inner diameter 636 of the carrier ring 630 and extends outward from the inner diameter 636. The top surface 632 extends from the surface 634 that is stepped down to the outer diameter 637 (eg, Figure 6B ).

[0084] A lower gap G1 may exist between the bottom surface of the carrier ring 630 and the annular surface 610 of the susceptor 600. Additionally, an upper gap G2 may exist between the top surface of the carrier ring 630 and the backside of the wafer 601. It should be understood that each of the lower gap G1 and the upper gap G2 provides a path for process gases to be delivered to the backside of the wafer 601 during the deposition process. Therefore, controlling these gaps may also minimize backside deposition.

[0085] When the carry ring 630 is supported by the carry ring support 612 , the size of the lower gap G1 may be defined by the vertical spacing between the annular surface 610 and the bottom surface of the carry ring 630 .

[0086] When the wafer 601 is supported above the wafer-facing surface 602 by one or more wafer supports, the size of the upper gap G2 between the wafer 601 and the carrier ring 630 may be defined by the vertical spacing between the surface 634 of the next step down and the back side of the wafer 601. It should be understood that the size of the upper gap G2 may be caused by various factors, including the size of the lower gap G1, the thickness of the carrier ring 630 in the area of ​​the surface 634 of the next step down, the difference in vertical position between the annular surface 610 and the wafer-facing surface 602, and the distance above the wafer-facing surface 602 when the wafer 601 is held by one or more wafer supports.

[0087] In some implementations, the lower gap G1 can be less than about 16 mils, such as between about 0 mils and 6 mils. In some implementations, the upper gap G2 can be less than about 10 mils, such as between about 0 mils and 5 mils. In some implementations, the upper gap G2 can be less than about 3 mils or less than about 1 mil. In the case where the upper gap G2 is less than about 1 mil or even 0 mils, an edge seal can be formed to limit backside deposition.

[0088] Back to Figure 1A and 1B, the system controller 110 may be configured with instructions for performing one or more operations of the apparatus, including for controlling the operation of one or more wafer supports. Control of the one or more wafer supports may include, for example, controlling the spatial arrangement and / or height of the one or more wafer supports. The system controller 110 may also control other parameters for limiting backside deposition, such as the size of the gap between the bottom surface of the carrier ring and the pedestal and the size of the gap between the upper surface of the carrier ring and the wafer.

[0089] The system controller 110 provides the electronics and interface controls required to operate the device 100. The system controller 110 (which may include one or more physical or logical controllers) controls some or all of the properties of the device 100. The system controller 110 typically includes one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for implementing appropriate control operations as described herein may be executed on the processor. These instructions may be stored on a storage device associated with the system controller 110, or they may be provided over a network. In some implementations, the system controller 110 executes system control software.

[0090] The system control software in the apparatus 100 may include instructions for controlling conditions in the processing chamber 102. This may include instructions for controlling susceptor temperature, lift pins, wafer supports, gas flow, chamber pressure, wafer position, wafer rotation, timing, carrier ring position, and other parameters performed by the apparatus 100. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components necessary to perform various process tool processes. The system control software may be encoded in any suitable computer readable programming language.

[0091] In some implementations, the system control software includes input / output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each stage of positioning a wafer by positioning one or more wafer supports may include one or more instructions for execution by the system controller 110, each stage of controlling the gap between the wafer and the susceptor and between the wafer and the carrier ring may include one or more instructions for execution by the system controller 110, and each stage of depositing a film on a wafer may include one or more instructions for execution by the system controller 110. In some implementations, the stages of positioning a substrate and deposition may be arranged sequentially so that all instructions for a processing stage are executed simultaneously with that processing stage.

[0092] Other computer software and / or programs may be used in some implementations. Examples of programs or program segments for this purpose include a wafer positioning program, a wafer support positioning program, a carrier ring positioning program, a pressure control program, a heater control program, and a potential / current power supply control program. Other examples of programs or program segments for this purpose include a timing control program, a lift pin positioning program, a susceptor positioning program, a susceptor temperature control program, a nozzle temperature control program, a process gas control program, and a purge gas control program.

[0093] In another embodiment, the wafer is supported on a chuckless pedestal such that a uniform gap is maintained between the wafer edge and the slot edge (eg, ceramic focus ring). Reducing the variation in the gap can provide better control over the uniformity of deposited film thickness at the wafer edge.

[0094] When depositing films on a wafer held in a chuckless pedestal, wafer slip can occur in an outward direction toward the chamber corners. For example, during film deposition with a standard wafer placed on a wafer support having a 2 mil height and at a chamber pressure of 0.5 Torr, the center of the wafer can slip more than 500 microns away from the center of the chuckless pedestal. Figure 7 Automatic wafer centering (AWC) data for standard wafer placement is depicted, where stations 1 and 2 of a four-station deposition chamber are shown, and the AWC data for stations 1 and 2 indicate that wafer slip can be in the range of 500 to 1000 microns. In an oxide deposition chamber, an air cushion can exist below the wafer, and wafer slip can cause the wafer to contact the wall of the pedestal pocket at the edge of the wafer. Wafer slip can be attributed to the "hockey stick compression" effect caused by the gas below the wafer, resulting in reduced friction and enabling the wafer to move. Slips of about 500 microns or more can cause a small gap or no gap on one edge of the wafer, and a gap larger than the desired gap on the opposite edge of the wafer. Changes in gap size can cause changes in the way the plasma sheath is generated at the edge of the wafer, resulting in changes in the thickness of the deposited film. For example, a thickness change of about 5 angstroms can occur in an outer region 1.5 mm from the edge of the wafer. Currently, it is desired to manufacture memory and logic device dies to the outer bevel of the wafer, and changes in film thickness at the outer edge can affect the yield and performance of memory and logic devices. While a susceptor with a wafer chuck can be used to address this problem, the addition of the chuck increases the cost of the processing chamber and requires significant changes to the susceptor.

[0095] To minimize wafer slip, various methods can be used. In one implementation, the gas can be pumped out when the wafer is in a pin-up configuration before the wafer is lowered to the pedestal. Alternatively, the gas can flow over the front of the wafer to avoid particle contamination of the front of the wafer due to rapid pressure transitions during pump down. In another implementation, the wafer can be supported on a wafer support that provides sufficient resistance / friction to hold the wafer by increasing the number and / or material of the wafer supports that contact the back of the wafer. In another implementation, the gas conduction between the wafer and the upper surface of the pedestal can be increased by increasing the height of the wafer support to at least 4 mils.

[0096] In one embodiment, a method for reducing slippage of a wafer during deposition of a film on a wafer includes supporting the wafer above a wafer-facing surface of a chuckless pedestal in a processing chamber; evacuating the processing chamber to a pressure effective to reduce slippage of the wafer when placed on a wafer support extending from the wafer-facing surface of the pedestal; lowering the wafer to an initial position on the wafer support with the back side of the wafer located a sufficient distance above the wafer-facing surface of the chuckless pedestal to reduce slippage during deposition of the film on the wafer; depositing a film on the wafer; and removing the wafer from the wafer support, wherein slippage of the wafer from its initial position is less than 400 microns when the wafer is removed from the wafer support.

[0097] Compared to a standard wafer placement operation in which the wafer is lowered onto a wafer support extending 2 mils from the wafer-facing surface of the pedestal and the chamber pressure is 0.5 Torr when the wafer is lowered onto the wafer support, in a low pressure wafer placement operation, the wafer support may extend 4 mils from the wafer-facing surface and the chamber pressure may be less than 0.5 Torr, preferably 0.1 Torr or less. The following table provides a comparison of film thickness uniformity and wafer slip, where "MCA" means minimum contact area pin, NU% means the % non-uniformity determined by measuring the maximum film thickness (Tmax) and minimum film thickness (Tmin) measured at 73 points collected in a polar pattern up to 1.8 mm from the edge of the wafer, NU% = (Tmax-Tmin) / 2.

[0098]

[0099] During the film deposition process, four wafers can be processed with or without moving the wafers from station to station. For example, in a film deposition process in which the wafers are moved from station to station and the film is sequentially deposited at each station, wafer placement can be performed as follows in a four-station chamber with four pedestals having four carrier rings and two loading ports: (1) two processed wafers are removed from stations 1 and 2, and the two wafers (wafers 1 and 2) can be simultaneously transferred into the chamber and loaded onto the lift pins of the pedestals at stations 1 and 2, (2) the two wafers can be lowered onto the wafer supports of the pedestals at stations 1 and 2, (3) the spider fork can simultaneously lift the four carrier rings at stations 1-4 and rotate them 180° to move wafers 1 and 2 to stations 3 and 4, (4) two additional wafers (wafers 3 and 4) can be simultaneously transferred into the chamber and loaded onto the lift pins of the pedestals at stations 1 and 2, (5) while wafers 1 and 2 are being lowered onto the wafer supports of the pedestals at stations 3 and 4, wafers 3 and 4 can be lowered onto the wafer supports at stations 1 and 2. Film deposition can be performed sequentially by depositing a portion of the film at each station. At the end of the deposition process, the processed wafers are indexed to return wafers 1 and 2 to stations 1 and 2 so that they can be kept in the same order as when they were inserted into the chamber. New wafers 1 and 2 are exchanged with processed wafers 1 and 2, new wafers 1 and 2 are indexed 180°, new wafers 3 and 4 are exchanged with processed wafers 3 and 4, and the film deposition process is repeated sequentially with new wafers in four steps by performing a portion of film deposition at each station. In sequential deposition, a low-pressure transfer is performed each time the wafer is indexed to the next station. Therefore, compared with standard wafer placement without evacuation during wafer placement, the low-pressure wafer placement process reduces wafer throughput due to the additional time required to perform the depressurization step.

[0100] Figures 8A-8B Shown is a depiction of AWC data comparing two wafer placement processes for stations 1-4 of a four-station deposition chamber. Fig. 8A Data is shown for a standard wafer placement process where the wafer is lowered onto a chuckless pedestal with a 2 mil height MCA and a chamber pressure of 0.5 Torr. Fig. 8A The data in show that the various distances the wafer slipped radially outward during film deposition averaged over 500 microns. Figure 8B Data is shown for a low pressure wafer placement process where the wafer was lowered onto an MCA having a 4 mil height and the chamber pressure was pumped down to a base pressure of <0.01 Torr. Figure 8B The AWC data in show that the average wafer slip is reduced to less than 200 microns. However, robot errors and thermal expansion between calibration and processes can cause possible deviations from 0 (center) of up to 200 microns. Therefore, AWC data below 200 microns indicates that the wafer may be centered without slip.

[0101] Fig. 9 A standard wafer placement process for a four-station chamber with two load ports is shown, where the initial chamber pressure is 0.5 Torr during the transfer of wafers 1 and 2, wafers 1 and 2 are lowered onto the wafer supports of the susceptors at stations 1 and 2, the carry rings at stations 1-4 are raised and rotated (spindle index) to move wafers 1 and 2 to stations 3 and 4, the carry rings are lowered onto the susceptors at stations 1-4, wafers 3 and 4 are transferred into the chamber and lowered onto lift pins at stations 1 and 2, the lift pins are lowered to place wafers 1 and 2 on the wafer supports at stations 1 and 2, and film deposition is performed.

[0102] Fig.10 A low-pressure wafer placement process of a four-station chamber with two loading ports is shown, wherein wafers 1 and 2 are transferred into the chamber at an initial chamber pressure of 0.5 Torr, wafers 1 and 2 are lowered onto lift pins of susceptors at stations 1 and 2, the pressure in the chamber is reduced to 0.1 Torr or less, wafers 1 and 2 are lowered onto wafer supports of susceptors at stations 1 and 2, the pressure in the chamber is increased to 0.5 Torr, the carry rings at stations 1-4 are raised and rotated (spindle indexing) to move wafers 1 and 2 to stations 3 and 4, the carry rings are lowered onto susceptors at stations 1-4, wafers 3 and 4 are transferred into the chamber and lowered onto lift pins at stations 1 and 2, the chamber pressure is reduced to 0.1 Torr or less, the lift pins are lowered to place wafers 3 and 4 on wafer supports at stations 1 and 2, and simultaneously the carry rings at stations 3 and 4 lower wafers 1 and 2 onto wafer supports at stations 3 and 4, and film deposition is performed.

[0103] The transfer process can be performed with an empty chamber or when a wafer exchange is performed after the film deposition process. During film deposition, the wafer can remain at the same station throughout the deposition process. Alternatively, partial film deposition can be performed at each station, which requires wafer transfer from station to station. To minimize wafer slip during the film deposition process, the wafer is placed on a wafer support using the low pressure process described above.

[0104] During a film deposition process in which wafers are processed sequentially at four stations, wafers may enter and exit the chamber two at a time. Fig.10is a diagram showing four pump-to-base pressure steps that occur during wafer placement. Assuming film deposition occurs on wafer 1 at station 3, and the wafer is indexed four times so that wafer 1 ends up at station 2, the transfer process is as follows. In step 1, the four processed wafers (PW1, PW2, PW3, PW4) are arranged with PW1 at station 2 (S2), PW2 at station 3 (S3), PW3 at station 4 (S4), and PW4 at station 1 (S1). In order to hold the wafers in the desired order, the spindle is indexed to return PW1 and PW2 to S1 and S2 so that they can be removed from the chamber first. In step 2, a first pump-to-base pressure (PB1) is performed to reduce the chamber pressure to below 0.5 Torr, preferably below 0.1 Torr, for example below 0.01 Torr. In step 3, when the chamber is at PB1, the spindle is lowered to drop the processed wafer (PW1, PW2, PW3, PW4) onto the carrier ring (CR1, CR2, CR3, CR4), PW1 is lowered onto the wafer support at S1, PW2 is lowered onto the wafer support at S2, PW3 is lowered onto the wafer support at S3, and PW4 is lowered onto the wafer support at S4. In step 4, the lift pins at S1 and S2 are raised to raise the processed wafers (PW1 and PW2) at S1 and S2. In step 5, the end effector removes PW1 and PW2 from the chamber at S1 and S2. In step 6, the lift pins at S1 and S2 are lowered. In step 7, the end effector transfers new wafers (W1 and W2) into the chamber. In step 8, the lift pins at S1 and S2 are raised to remove W1 and W2 from the end effector. In step 9, the end effector is removed from the chamber. In step 10, a second pump down to base pressure (PB2) is performed to reduce the pressure of the chamber to less than 0.5 Torr, preferably less than 0.1 Torr, such as 0.01 Torr or less. In step 11, while the chamber is under PB2, the lift pins at S1 and S2 are lowered to place W1 and W2 on the wafer supports at S1 and S2. In step 12, the spindle is raised to raise the carrier rings (CR1, CR2, CR3, CR4) together with the wafers (W1, W2, PW3, PW4). In step 13, the spindle is indexed (rotated) to move the processed wafers (PW3 and PW4) on the carrier rings (CR3 and CR4) from S3 and S4 to S1 and S2, and to move CR1 / W1 and CR2 / W2 to S3 and S4. In step 14, a third pump down to base pressure (PB3) is performed to reduce the chamber pressure to less than 0.5 Torr, preferably less than 0.1 Torr, such as less than 0.01 Torr, as the spindle moves upward. In step 15, the spindle is lowered to place the wafers (W1, W2, PW3, PW4) on the wafer supports at S3, S4, S1, and S2. In step 16, lift pins at S1 and S2 raise PW3 and PW4.In step 17, the end effector removes PW3 and PW4 from the lift pins at S1 and S2 and moves PW3 and PW4 out of the chamber. In step 18, the end effector transfers new wafers (W3 and W4) into the chamber. In step 19, the lift pins at S1 and S2 are raised to remove W3 and W4 from the end effector. In step 20, the end effector is taken out of the chamber. In step 21, while the lift pins are raised at S1 and S2, a fourth pump down to base pressure (PB4) is performed to reduce the chamber pressure to less than 0.5 Torr, preferably less than 0.1 Torr, such as less than 0.01 Torr. In step 22, in the chamber under PB4, the lift pins at S1 and S2 are lowered to place W3 and W4 on the wafer supports at S1 and S2. Subsequently, film deposition is performed by depositing film material on the wafer by depositing all the film while the wafer remains in one station or by depositing a portion of the film at each station to sequentially deposit the film. Sequential deposition has the advantage of increasing overall film uniformity because each wafer is processed at all four stations, in which case wafer placement is more precise due to the low pressure placement as the wafer is transferred to each successive station.

[0105] In sequential film deposition, four wafers (W1, W2, W3, W4) are moved from station to station in four stations (S1, S2, S3, S4) as follows. After a first deposition step (in which a portion of the desired film thickness is deposited on the wafer), the wafer is indexed by raising the spindle to raise the four carrier rings (CR1, CR2, CR3, CR4) together with the wafer (W1, W2, W3, W4), the spindle is rotated 90°, the chamber pressure is reduced to below 0.5 Torr, preferably below 0.1 Torr, such as below 0.01 Torr, under the reduced chamber pressure, the spindle is lowered to place the wafer on the wafer support at the four stations (W1 at S2, W2 at S3, W3 at S4, S4 at S1), and a second deposition step is performed to deposit a portion of the desired total thickness. After the second deposition step, the four wafers are raised as the spindle raises the four carrier rings, the spindle rotates 90°, the chamber pressure is reduced to less than 0.5 Torr, preferably less than 0.1 Torr, such as less than 0.01 Torr, the spindle is lowered at the reduced pressure to place the wafers on the wafer supports at the four stations, wherein W1 is at S3, W2 is at S4, W3 is at S1 and W4 is at S2, and a third film deposition step is performed to deposit a portion of the desired total thickness. After the third deposition step, the four wafers are raised as the spindle raises the four carrier rings, the spindle rotates 90°, the chamber pressure is reduced to less than 0.5 Torr, preferably less than 0.1 Torr, such as less than 0.01 Torr, the spindle is lowered at the reduced pressure to place the wafers on the wafer supports at the four stations, wherein W1 is at S3, W2 is at S4, W3 is at S1 and W4 is at S2, and a fourth film deposition is performed to deposit the film to the desired thickness. After the fourth deposition step, the processed wafer is removed from the chamber and a new wafer is loaded into the chamber as described above.

[0106] Although the above has been described in detail for the purpose of clarity and understanding, it is apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways to implement the described processes, systems and devices. Therefore, the described embodiments are considered to be illustrative rather than restrictive.

Claims

1. A method for reducing wafer slip during deposition of a film on a wafer, the method comprising: supporting the wafer on lift pins or a carry ring so that the wafer is positioned above a wafer support on a wafer-facing surface of a non-chuck pedestal in a processing chamber with a gap between an outer edge of the wafer and a wall of a pedestal slot; evacuating the process chamber to a reduced pressure less than 0.5 Torr while supporting the wafer on the lift pins or carry ring and above the wafer support; lowering the lift pins or carry ring so that the wafer is lowered onto the wafer support while the processing chamber is at the reduced pressure and supports the wafer a sufficient distance above the wafer-facing surface of the chuckless pedestal to reduce lateral slippage in the pedestal slots during deposition of a film on the wafer; A film is deposited on the wafer while the wafer is supported on the wafer support, wherein after depositing the film, the off-center wafer slips less than 400 microns from its initial position.

2. A method for reducing wafer slip during deposition of a film on a wafer, the method comprising: supporting the wafer on lift pins or a carry ring so that the wafer is above a wafer support on a wafer-facing surface of a non-chuck pedestal in a processing chamber; evacuating the process chamber to a reduced pressure while supporting the wafer on the lift pins or carry ring above the wafer support to effectively reduce slippage of the wafer when placed on a wafer support extending from the wafer-facing surface of the pedestal; lowering the lift pins or carry ring so that the wafer is lowered onto the wafer support while the processing chamber is at the reduced pressure and supports the wafer at a distance in the range of 2 to 10 mils above the wafer-facing surface of the chuckless pedestal during deposition of a film on the wafer; A film is deposited on the wafer while the wafer is supported on the wafer support, wherein after depositing the film, the off-center wafer slips less than 400 microns from its initial position.

3. A method of reducing wafer slip during deposition of a film on a wafer, the method comprising: supporting the wafer on lift pins or a carry ring so that the wafer is above a wafer support on a wafer-facing surface of a non-chuck pedestal in a processing chamber; evacuating the process chamber to a reduced pressure less than 0.5 Torr while supporting the wafer on the lift pins or carry ring and above the wafer support; lowering the lift pins or carry ring so that the wafer is lowered onto the wafer support while the processing chamber is at the reduced pressure and supports the wafer at a distance in the range of 2 to 10 mils above the wafer-facing surface of the chuckless pedestal during deposition of a film on the wafer; A film is deposited on the wafer while the wafer is supported on the wafer support, wherein after depositing the film, the off-center wafer slips less than 400 microns from its initial position.

4. A method of reducing wafer slip during deposition of a film on a wafer, the method comprising: supporting the wafer on lift pins or a carry ring so that the wafer is positioned above a wafer support on a wafer-facing surface of a non-chuck pedestal in a processing chamber with a gap between an outer edge of the wafer and a wall of a pedestal slot; evacuating the process chamber to a reduced pressure less than 0.5 Torr while supporting the wafer on the lift pins or carry ring and above the wafer support; lowering the lift pins or carry ring so that the wafer is lowered onto the wafer support while the processing chamber is under the reduced pressure and supports the wafer above the wafer-facing surface of the chuckless pedestal and at least 2 mils above the wafer-facing surface of the chuckless pedestal during deposition of a film on the wafer; A film is deposited on the wafer while the wafer is supported on the wafer support, wherein after depositing the film, the off-center wafer slips less than 400 microns from its initial position.

5. A method of reducing wafer slip during deposition of a film on a wafer, the method comprising: supporting the wafer on lift pins or a carry ring so that the wafer is positioned above an adjustable wafer support on a wafer-facing surface of a non-chuck pedestal in a processing chamber with a gap between an outer edge of the wafer and a wall of a pedestal slot; evacuating the process chamber to a reduced pressure less than 0.5 Torr while supporting the wafer on the lift pins or carry ring and above the wafer support; lowering the lift pins or carry ring so that the wafer is lowered onto the wafer support and supports the wafer above the wafer-facing surface of the chuckless pedestal while the processing chamber is under the reduced pressure, and adjusting the height of the wafer support so that the gap between the wafer and the chuckless pedestal is sized to minimize slippage of the wafer during wafer placement and during film deposition on the wafer; A film is deposited on the wafer while the wafer is supported on the wafer support, wherein after depositing the film, the off-center wafer slips less than 400 microns from its initial position.

6. A method of reducing wafer slip during deposition of a film on a wafer, the method comprising: supporting the wafer on lift pins or a carry ring so that the wafer is positioned above a wafer support on a wafer-facing surface of a non-chuck pedestal in a processing chamber with a gap between an outer edge of the wafer and a wall of a pedestal slot; evacuating the process chamber to a reduced pressure less than 0.5 Torr while supporting the wafer on the lift pins or carry ring and above the wafer support; lowering the lift pins or carry ring so that the wafer is lowered onto the wafer support while the processing chamber is at the reduced pressure and supports the wafer at a distance in the range of 2 to 10 mils above the wafer-facing surface of the chuckless pedestal during deposition of a film on the wafer; A film is deposited on the wafer while the wafer is supported on the wafer support, and a uniform gap is maintained between the outer edge of the wafer and the wall of the pedestal groove during the deposition of the film on the wafer.

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