Display device

Abstract

A display device includes scan lines extending in a first direction, data lines extending in a second direction crossing the first direction and receiving a data voltage, a first driving voltage line extending in the second direction and receiving a first driving voltage, a second driving voltage line extending in the second direction and receiving a second driving voltage different from the first driving voltage, and pixels connected with the scan lines and the data lines. Each of the pixels includes first, second, and third sub-pixels disposed in the first direction. The first driving voltage line and the second driving voltage line are alternately disposed in the first direction. A position of the first driving voltage line in a first pixel is different from a position of the second driving voltage line in a second pixel. The second pixel is adjacent to the first pixel in the first direction.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a display device. BACKGROUND

[0002] As the information society develops, the demand for display devices for displaying images has diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation systems, and smart TVs ("TVs"). Examples of display devices include flat panel display devices such as liquid crystal display ("LCD") devices, field emission display ("FED") devices, or light emitting diode ("LED") display devices.

[0003] A light emitting display device includes a light emitting element capable of self-emitting in each sub-pixel of a display panel, and can thus display an image without a backlight unit for providing light to the display panel. Each sub-pixel of a light emitting display device can include a light emitting element, a driving transistor that controls the amount of driving current applied to the light emitting element from a driving voltage line according to a data voltage from a data line, and a plurality of switching transistors that are turned on in response to a scan signal from a scan line. If the driving transistor is arranged adjacent to the data line connected to the adjacent sub-pixel, the driving transistor can be affected by the data line of the adjacent sub-pixel. SUMMARY

[0004] Embodiments of the present application provide a display device capable of preventing or inhibiting driving transistors of sub-pixels from being affected by data lines connected to their respective adjacent sub-pixels.

[0005] Embodiments of the present application provide a display device including scan lines extending in a first direction, data lines extending in a second direction crossing the first direction and receiving data voltages, first driving voltage lines extending in the second direction and receiving first driving voltages, second driving voltage lines extending in the second direction and receiving second driving voltages different from the first driving voltages, and pixels connected to the scan lines and the data lines. Each of the pixels includes first, second, and third sub-pixels disposed in the first direction. The first driving voltage lines and the second driving voltage lines are alternately disposed in the first direction. A position of one of the first driving voltage lines in a first pixel among the pixels is different from a position of one of the second driving voltage lines in a second pixel among the pixels. The second pixel is adjacent to the first pixel in the first direction.

[0006] At least one of the first driving voltage lines and the second driving voltage lines can be arranged in each of the pixels.

[0007] The first driving voltage lines and the second driving voltage lines can be alternately arranged in the first direction between the first and second sub-pixels of the 3N-2-th pixel among the pixels, between the second and third sub-pixels of the 3N-1-th pixel among the pixels, and between the third sub-pixel of the 3N-th pixel and the first sub-pixel of the 3N+1-th pixel among the pixels, where N is a positive integer.

[0008] One of the first driving voltage lines can be disposed between the first and second sub-pixels of the first pixel, and one of the second driving voltage lines can be disposed between the second and third sub-pixels of the second pixel.

[0009] Another one of the first driving voltage lines can be disposed between the third sub-pixel of a third pixel among the pixels and the first sub-pixel of a fourth pixel among the pixels. Another one of the second driving voltage lines can be disposed between the first and second sub-pixels of the fourth pixel. The third pixel can be adjacent to the second pixel in the first direction. The fourth pixel can be adjacent to the third pixel in the first direction.

[0010] Still another one of the first driving voltage lines can be disposed between the second and third sub-pixels of a fifth pixel among the pixels, and still another one of the second driving voltage lines can be disposed between the third sub-pixel of a sixth pixel among the pixels and the first sub-pixel of a seventh pixel among the pixels. The fifth pixel can be adjacent to the fourth pixel in the first direction. The sixth pixel can be adjacent to the fifth pixel in the first direction. The seventh pixel can be adjacent to the sixth pixel in the first direction.

[0011] The first driving voltage lines and the second driving voltage lines can be alternately arranged in the first direction between the first and second sub-pixels of the 2N-1-th pixel, where N is a positive integer, and between the second and third sub-pixels of the 2N-th pixel.

[0012] A position of one of the first driving voltage lines in a first pixel among the pixels can be between a first transistor of one of the sub-pixels and a data line among the data lines connected to a next sub-pixel adjacent to the one sub-pixel in the first pixel.

[0013] Another one of the first driving voltage lines can be disposed between the first and second sub-pixels of a third pixel among the pixels. Another one of the second driving voltage lines can be disposed between the second and third sub-pixels of a fourth pixel among the pixels. The third pixel can be adjacent to the second pixel in the first direction. The fourth pixel can be adjacent to the third pixel in the first direction.

[0014] The first driving voltage lines and the second driving voltage lines can be alternately arranged in the first direction between the second and third sub-pixels of the 2N-1th pixel, between the first and second sub-pixels of the 2Nth pixel, and between the third sub-pixel of the 2Nth pixel and the first sub-pixel of the 2N+1th pixel, where N is a positive integer.

[0015] One of the first driving voltage lines can be arranged between the second and third sub-pixels of the first pixel. One of the second driving voltage lines can be arranged between the first and second sub-pixels of the second pixel.

[0016] Another one of the first driving voltage lines can be arranged between the third sub-pixel of the second pixel and the first sub-pixel of a third pixel among the pixels. Another one of the second driving voltage lines can be arranged between the second and third sub-pixels of the third pixel. The third pixel can be adjacent to the second pixel in the first direction.

[0017] Still another one of the first driving voltage lines can be arranged between the first and second sub-pixels of a fourth pixel among the pixels. Still another one of the second driving voltage lines can be arranged between the third sub-pixel of the fourth pixel and the first sub-pixel of a fifth pixel among the pixels. The fourth pixel can be adjacent to the third pixel in the first direction, and the fifth pixel can be adjacent to the fourth pixel in the first direction.

[0018] An embodiment of the present application provides a display apparatus including scan lines extending in a first direction, data lines extending in a second direction crossing the first direction and receiving data voltages, first driving voltage lines extending in the second direction and receiving first driving voltages, second driving voltage lines extending in the second direction and receiving second driving voltages different from the first driving voltages, third driving voltage lines extending in the second direction to which third driving voltages different from the first and second driving voltages are applied, and pixels connected with the scan lines and the data lines. Each of the pixels includes first, second, and third sub-pixels arranged in the first direction. The first, second, and third driving voltage lines are alternately arranged in the first direction. A position of one of the first driving voltage lines in a first pixel among the pixels is different from a position of one of the second driving voltage lines in a second pixel among the pixels. The second pixel is adjacent to the first pixel in the first direction. At least one of the first, second, and third driving voltage lines is arranged in each of the pixels.

[0019] The position of a third driving voltage line in the third pixel of a pixel may be different from the position of the first driving voltage line in the first pixel and the position of the second driving voltage line in the second pixel.

[0020] The first driving voltage line, the second driving voltage line, and the third driving voltage line can be alternately set in a first direction between the first and second sub-pixels of the 3N-2th pixel (where N is a positive integer), between the second and third sub-pixels of the 3N-1th pixel, and between the third sub-pixel of the 3Nth pixel and the first sub-pixel of the 3N+1th pixel.

[0021] The position of one of the third driving voltage lines in the third pixel can be the same as the position of the first driving voltage line in the first pixel, but different from the position of the second driving voltage line in the second pixel.

[0022] The first driving voltage line, the second driving voltage line, and the third driving voltage line can be alternately arranged in a first direction between the first and second sub-pixels of the 2N-1th pixel (where N is a positive integer) and between the second and third sub-pixels of the 2Nth pixel.

[0023] The position of the second driving voltage line in the second pixel may be different from the position of the first driving voltage line in the first pixel and the position of one of the third driving voltage lines in the second pixel.

[0024] The first driving voltage line, the second driving voltage line, and the third driving voltage line can be alternately set in a first direction between the second and third sub-pixels of the 2N-1 pixel (where N is a positive integer), between the first and second sub-pixels of the 2N pixel, and between the third sub-pixel of the 2N pixel and the first sub-pixel of the 2N+1 pixel.

[0025] Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include: a first transistor, wherein a driving current flowing between a first electrode and a second electrode of the first transistor is controlled according to a voltage applied to the gate electrode of the first transistor; a light-emitting element, connected between the first transistor and a first driving voltage line; a second transistor, connected between the first electrode of the light-emitting element and a second driving voltage line; and a first capacitor, connected between the second electrode of the first transistor and the third transistor, wherein the third transistor is connected between the first capacitor and a third driving voltage line.

[0026] Embodiments of the present invention provide a display device including scan lines extending in a first direction, data lines extending in a second direction crossing the first direction and receiving a data voltage, first driving voltage lines extending in the second direction and receiving a first driving voltage, second driving voltage lines extending in the second direction and receiving a second driving voltage different from the first driving voltage, and pixels connected with the scan lines and the data lines. Each of the pixels includes first, second, third, and fourth sub-pixels disposed in the first direction. One of the first driving voltage lines and one of the second driving voltage lines are disposed in each of the pixels.

[0027] The first driving voltage lines and the second driving voltage lines can be alternately disposed in the first direction.

[0028] The first driving voltage lines and the second driving voltage lines can be alternately disposed in the first direction between the first and second sub-pixels of the 2N-1th pixel, between the fourth sub-pixel of the 2N-1th pixel and the first sub-pixel of the 2Nth pixel, between the third and fourth sub-pixels of the 2Nth pixel, and between the fourth sub-pixel of the 2Nth pixel and the first sub-pixel of the 2N+1th pixel, where N is a positive integer.

[0029] The first driving voltage lines and the second driving voltage lines can be alternately disposed in the first direction between the second and third sub-pixels of the 2N-1th pixel, between the fourth sub-pixel of the 2N-1th pixel and the first sub-pixel of the 2Nth pixel, between the second and third sub-pixels of the 2Nth pixel, and between the fourth sub-pixel of the 2Nth pixel and the first sub-pixel of the 2N+1th pixel, where N is a positive integer.

[0030] The display device can further include third driving voltage lines extending in the second direction and receiving a third driving voltage, where the third driving voltage can be different from each of the first and second driving voltages. The first, second, and third driving voltage lines can be alternately disposed in the first direction.

[0031] The first, second, and third driving voltage lines can be alternately disposed in the first direction between the first and second sub-pixels of the 2N-1th pixel, between the fourth sub-pixel of the 2N-1th pixel and the first sub-pixel of the 2Nth pixel, between the third and fourth sub-pixels of the 2Nth pixel, and between the fourth sub-pixel of the 2Nth pixel and the first sub-pixel of the 2N+1th pixel, where N is a positive integer.

[0032] The first, second, and third driving voltage lines can be alternately disposed in the first direction between the second and third sub-pixels of the 2N-1th pixel, between the fourth sub-pixel of the 2N-1th pixel and the first sub-pixel of the 2Nth pixel, between the second and third sub-pixels of the 2Nth pixel, and between the fourth sub-pixel of the 2Nth pixel and the first sub-pixel of the 2N+1th pixel, where N is a positive integer.

[0033] Embodiments of the present disclosure provide a display apparatus including scan lines extending in a first direction, data lines extending in a second direction crossing the first direction and receiving a data voltage, driving voltage lines extending in the second direction and receiving a driving voltage, and sub-pixels connected with the scan lines, the data lines, and the driving voltage lines. Each of the sub-pixels can include a first transistor controlling a driving current flowing between a first electrode and a second electrode of the first transistor according to a voltage applied to a gate electrode of the first transistor. One of the driving voltage lines can be disposed between the first transistor of one of the sub-pixels and a data line adjacent to a data line connected with the one of the sub-pixels among the data lines.

[0034] Each of the sub-pixels can further include a first capacitor connected between the second electrode of the first transistor and a third transistor connected between the first capacitor and one of the driving voltage lines.

[0035] Each of the sub-pixels can further include a light emitting element connected between the first transistor and one of the driving voltage lines.

[0036] Each of the sub-pixels can further include a light emitting element emitting light according to the driving current of the first transistor and a second transistor connected between a first electrode of the light emitting element and one of the driving voltage lines. BRIEF DESCRIPTION OF DRAWINGS

[0037] These and / or other features of the present disclosure will become apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 is a perspective view of a display apparatus according to an embodiment of the present disclosure;

[0039] Figure 2 is a block diagram of the display apparatus of Figure 1

[0040] Figure 3 is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure;

[0041] ​Figure 4 is a waveform diagram illustrating signals applied to Figure 3 subpixels of the display panel of

[0042] Figure 5 is a layout diagram of a pixel of a display panel according to an embodiment of the present disclosure;

[0043] Figure 6 is a layout diagram of a first pixel of the display panel of Figure 5

[0044] Figure 7 is a layout diagram of a second pixel of the display panel of Figure 5

[0045] Figure 8 is a detailed layout diagram of a second subpixel of the second pixel of the display panel of Figure 7

[0046] Figure 9 is a cross-sectional view of the display panel of Figure 8 taken along line I-I’ of Figure 5

[0047] Figure 10 is a cross-sectional view of the display panel of Figure 8 taken along line II-II’ of Figure 5

[0048] Figure 11 is a cross-sectional view of the display panel of Figure 8 taken along line III-III’ of Figure 5

[0049] Figure 12 illustrates a change in gray scale between a first region and a second region of the display panel of Figure 5 depending on the presence of a first driving voltage line and a second driving voltage line of Figure 5

[0050] is a layout diagram of a pixel of a display panel according to another embodiment of the present disclosure; Figure 13

[0051] is a layout diagram of a second subpixel of a third pixel of the display panel of Figure 14 Figure 13 is a layout diagram of a pixel of a display panel according to another embodiment of the present disclosure;

[0052] Figure 15 is a layout diagram of a pixel of a display panel according to another embodiment of the present disclosure;

[0053] Figure 16 is a layout diagram of a pixel of a display panel according to another embodiment of the present disclosure;

[0054] Figure 17 ​​​​​​​is a layout diagram of pixels of a display panel according to another embodiment of the disclosure;

[0055] Figure 18 is a layout diagram of pixels of a display panel according to another embodiment of the disclosure;

[0056] Figure 19 is a layout diagram of pixels of a display panel according to another embodiment of the disclosure;

[0057] Figure 20 is a layout diagram of pixels of a display panel according to another embodiment of the disclosure;

[0058] Figure 21 is a layout diagram of pixels of a display panel according to another embodiment of the disclosure;

[0059] Figure 22 is a layout diagram of pixels of a display panel according to another embodiment of the disclosure;

[0060] Figure 23 is a layout diagram of pixels of a display panel according to another embodiment of the disclosure; and

[0061] Figure 24 is a layout diagram of pixels of a display panel according to another embodiment of the disclosure. DETAILED DESCRIPTION

[0062] The present application now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0063] It will be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0064] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, including "at least one," unless the context clearly indicates otherwise. "Or" means "and / or." "At least one of A and B" means "A and / or B." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0066] "About" or "approximately," as used herein, includes the recited value and the average value determined as would be understood by one of ordinary skill in the art to be within an acceptable range of deviation for a particular value when taking into account the measurement at issue and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0068] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an illustrated region can typically have a rough and / or nonlinear shape. Additionally, an illustrated sharp corner can typically have a rounded shape. Thus, the regions illustrated in the figures are schematic and are not intended to illustrate the precise shape of a region but are intended to show the general shape of the region. It is further noted that the regions illustrated in the figures are not necessarily drawn to scale and that the dimensions of regions can be arbitrarily enlarged or reduced for the sake of clarity.

[0069] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0070] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0071] Referring to Figure 1The display device 10, as a device for displaying a moving or still image, can be used not only as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer ("PC"), a smart watch, a watch phone, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player ("PMP"), a navigation system, and an ultra mobile PC ("UMPC"), but also as a display screen of various other products such as a television ("TV"), a notebook computer, a monitor, a billboard, and an Internet of Things ("IoT") device.

[0072] The display device 10 can be an organic light emitting diode ("OLED") display device using an OLED, an inorganic light emitting diode ("ILED") display device using an inorganic semiconductor, or a micro light emitting diode ("micro-LED") display device using a micro-LED. As an example, the display device 10 will be described hereinafter as an OLED display device, but the present disclosure according to the present application is not limited thereto.

[0073] The display device 10 includes a display panel 100, a display driving circuit 200, and a circuit board 300.

[0074] The display panel 100 can have a substantially rectangular shape in a plan view, which shape has a short side in a first direction (i.e., an X-axis direction) and a long side in a second direction (i.e., a Y-axis direction). The corners at which the short side in the first direction (i.e., the X-axis direction) and the long side in the second direction (i.e., the Y-axis direction) meet can be rounded to have a predetermined curvature or can be right-angled. The planar shape of the display panel 100 according to the present application is not particularly limited, and the display panel 100 can have various other shapes such as a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape. The display panel 100 can be flat, but the present disclosure according to the present application is not limited thereto. Alternatively, the display panel 100 can include curved portions formed at both ends of the display panel 100 and having uniform or varying curvatures. The display panel 100 can be flexible, e.g., bendable, foldable, or rollable.

[0075] The display panel 100 can include a main area MA and a sub area SA.

[0076] The main area MA can include a display area DA in which an image is displayed and a non-display area NDA which is peripheral to the display area DA and in which an image is not displayed. The non-display area NDA can be defined as an area from an edge of the display area DA to an edge of the display panel 100.

[0077] The sub-area SA can protrude from one side of the main area MA in the second direction (or Y-axis direction). The length of the sub-area SA in the first direction (or X-axis direction) can be less than the length of the main area MA in the first direction (or X-axis direction), and the length of the sub-area SA in the second direction (or Y-axis direction) can be less than the length of the main area MA in the second direction (or Y-axis direction). However, the present disclosure according to the present application is not limited thereto.

[0078] Figure 1 The sub-area SA is illustrated as not being folded, but the sub-area SA can be folded downward to be placed on the bottom surface of the display panel 100. When the sub-area SA is folded downward, the sub-area SA can overlap the main area MA in the thickness direction (i.e., Z-axis direction) of the substrate SUB1 (see FIG. 1). The display driving circuit 200 can be disposed in the sub-area SA. Figure 9

[0079] The display driving circuit 200 can include or be formed as an integrated circuit ("IC") and can be attached on the display panel 100 in a chip on glass ("COG") or chip on plastic ("COP") manner or by ultrasonic bonding, but the present disclosure according to the present application is not limited thereto. Alternatively, the display driving circuit 200 can be attached on the circuit board 300 in a chip on film ("COF") manner.

[0080] The circuit board 300 can be attached to one end of the sub-area SA of the display panel 100 by an anisotropic conductive film. As a result, the circuit board 300 can be electrically connected with the display panel 100 and the display driving circuit 200. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a COF.

[0081] Figure 2 is a block diagram of a display apparatus. Figure 1

[0082] Referring to Figure 2 , the display apparatus 10 further includes a scan driving unit 410, an emission driving unit 420, and a power supply unit 430. The display apparatus 10 can further include the timing controller 210 and the data driver 220.

[0083] In the display area DA of the display panel 100, not only the sub-pixel SP but also a scan line, a first emission line EL1, a second emission line EL2, and a data line DL connected with the sub-pixel SP can be disposed. The scan line can include a scan write line GWL, a scan control line GCL, a first scan bias line EBL1, and a second scan bias line EBL2.

[0084] ​​The scan write lines GWL, the scan control lines GCL, the first scan bias lines EBL1, and the second scan bias lines EBL2 can extend in a first direction (or an X-axis direction). The first emission lines EL1 and the second emission lines EL2 can extend in the first direction (or the X-axis direction). The data lines DL can extend in a second direction (or a Y-axis direction) crossing the first direction (or the X-axis direction).

[0085] Each of the subpixels SP can be connected with one of the scan write lines GWL, one of the scan control lines GCL, one of the first scan bias lines EBL1, one of the second scan bias lines EBL2, one of the first emission lines EL1, one of the second emission lines EL2, and one of the data lines DL.

[0086] Each of the subpixels SP can include a driving transistor, one or more switching transistors, a light emitting element, and a capacitor. The switching transistors can be turned on by a scan write signal from one of the scan write lines GWL, and can thus apply a data voltage from one of the data lines DL to a gate electrode of the driving transistor. The driving transistor supplies a driving current to the light emitting element according to the data voltage applied to the gate electrode of the driving transistor. The driving transistor and the switching transistors can be thin film transistors ("TFTs"). The light emitting element can emit light according to the driving current of the driving transistor. The light emitting element can be an OLED including a first electrode, an organic light emitting layer, and a second electrode. The capacitor can maintain the data voltage applied to the gate electrode of the driving transistor for a predetermined amount of time. The driving transistor, the switching transistors, the light emitting element, and the capacitor will be described later with reference to FIGS. 2A and 2B. Figure 3 Each of the subpixels SP is described in further detail.

[0087] In the non-display area NDA of the display panel 100, a scan driving unit 410 for applying a signal to the scan write lines GWL, the scan control lines GCL, the first scan bias lines EBL1, and the second scan bias lines EBL2, and an emission driving unit 420 for applying a signal to the first emission lines EL1 and the second emission lines EL2 can be arranged. The scan driving unit 410 can be arranged at one side of the display panel 100, and the emission driving unit 420 can be arranged at the opposite side of the display panel 100. However, the present disclosure according to this application is not limited thereto.

[0088] The scan driving unit 410 can be connected with the timing controller 210 of the display driving circuit 200. The scan driving unit 410 can receive a scan driving unit control signal SCS from the timing controller 210.

[0089] The scan driving unit 410 can include a scan write signal output part 411, a scan control signal output part 412, a first scan bias signal output part 413, and a second scan bias signal output part 414. The scan write signal output part 411 can generate a scan write signal according to a scan driving unit control signal SCS, and can output the scan write signal to a scan write line GWL. The scan control signal output part 412 can generate a scan control signal according to the scan driving unit control signal SCS, and can output the scan control signal to a scan control line GCL. The first scan bias signal output part 413 can generate a first scan bias signal according to the scan driving unit control signal SCS, and can output the first scan bias signal to a first scan bias line EBL1. The second scan bias signal output part 414 can generate a second scan bias signal according to the scan driving unit control signal SCS, and can output the second scan bias signal to a second scan bias line EBL2.

[0090] The emission driving unit 420 can be connected with the timing controller 210 of the display driving circuit 200. The emission driving unit 420 can receive an emission control signal ECS from the timing controller 210.

[0091] The emission driving unit 420 can include a first emission driver 421 and a second emission driver 422. The first emission driver 421 can generate a first emission signal according to the emission control signal ECS, and can output the first emission signal to a first emission line EL1. The second emission driver 422 can generate a second emission signal according to the emission control signal ECS, and can output the second emission signal to a second emission line EL2.

[0092] The timing controller 210 of the display driving circuit 200 receives digital video data DATA and timing signals from the circuit board 300. The timing controller 210 can generate a scan driving unit control signal SCS for controlling an operation timing of the scan driving unit 410, an emission control signal ECS for controlling an operation timing of the emission driving unit 420, and a data control signal DCS for controlling an operation timing of the data driver 220. The timing controller 210 can output the scan driving unit control signal SCS and the emission control signal ECS to the scan driving unit 410 and the emission driving unit 420, respectively. The timing controller 210 can output the digital video data DATA and the data control signal DCS to the data driver 220.

[0093] The data driver 220 converts the digital video data DATA into an analog (positive / negative) data voltage and outputs the analog data voltage to the data line DL. As a result, the sub-pixel SP is selected by the scan write signal from the scan driving unit 410, and the data voltage supplied from the data driver 220 can be supplied to the selected sub-pixel SP.

[0094] The power supply unit 430 can generate a plurality of driving voltages and can supply the driving voltages to the display panel 100. For example, the power supply unit 430 can generate a first driving voltage VSS, a second driving voltage VINT, a third driving voltage VREF, and a fourth driving voltage VDD, and can supply the first driving voltage VSS, the second driving voltage VINT, the third driving voltage VREF, and the fourth driving voltage VDD to the display panel 100. The first driving voltage VSS, the second driving voltage VINT, the third driving voltage VREF, and the fourth driving voltage VDD will be described later with reference to FIGS. 4A and 4B. Figure 3 The first driving voltage VSS, the second driving voltage VINT, the third driving voltage VREF, and the fourth driving voltage VDD will be described later with reference to FIGS. 4A and 4B.

[0095] Figure 3 is a circuit diagram of a sub-pixel according to an embodiment of the disclosure.

[0096] Referring to Figure 3 , the sub-pixel SP can be connected with the scan write line GWL, the scan control line GCL, the first scan bias line EBL1, the second scan bias line EBL2, the first emission line EL1, the second emission line EL2, and the data line DL. Further, the sub-pixel SP can be connected with the first driving voltage line VSL to which a low potential voltage, i.e., the first driving voltage VSS is supplied, the second driving voltage line VIL to which an initialization voltage, i.e., the second driving voltage VINT is applied, the third driving voltage line VRL to which a reference voltage, i.e., the third driving voltage VREF is applied, and the fourth driving voltage line VDL to which a high potential voltage, i.e., the fourth driving voltage VDD is applied. That is, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VIL can be an initialization voltage line, the third driving voltage line VRL can be a reference voltage line, and the fourth driving voltage line VDL can be a high potential voltage line. The first driving voltage VSS can be lower than the second driving voltage VINT. The third driving voltage VREF can be higher than the fourth driving voltage VDD. The fourth driving voltage VDD can be higher than the second driving voltage VINT.

[0097] The sub-pixel SP can include a plurality of transistors (first to eighth transistors) T1 to T8, a light emitting element LE, a first capacitor Cpr, and a second capacitor Cst.

[0098] The first transistor T1 can include a gate electrode, a first electrode, and a second electrode. The first transistor T1 can be a driving transistor that controls a drain-source current (hereinafter, referred to as a driving current Ids) flowing between the first electrode and the second electrode of the first transistor T1 according to a data voltage applied to the gate electrode of the first transistor T1. The driving current Ids flowing through a channel of the first transistor T1 is proportional to a square of a difference between a gate-source voltage Vgs of the first transistor T1 and a threshold voltage Vth, as shown by Equation (1):

[0099] Ids = k' x (Vgs - Vth) 2 …(1)

[0100] where k' denotes a proportional coefficient determined by a structure and physical characteristics of the first transistor T1, Vgs denotes a gate-source voltage of the first transistor T1, and Vth denotes a threshold voltage of the first transistor T1.

[0101] The light emitting element LE emits light according to the driving current Ids. An amount of light emitted by the light emitting element LE can be proportional to the driving current Ids. The light emitting element LE can be disposed between the seventh transistor T7 and the first driving voltage line VSL. A first electrode of the light emitting element LE can be connected with a second electrode of the seventh transistor T7, and a second electrode of the light emitting element LE can be connected with the first driving voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode.

[0102] The light emitting element LE can be an OLED including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. Alternatively, the light emitting element LE can be an ILED including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. Alternatively, the light emitting element LE can be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer disposed between the first electrode and the second electrode. Alternatively, the light emitting element LE can be a micro LED.

[0103] The second transistor T2 can be disposed between the first electrode of the light emitting element LE and the second driving voltage line VIL. The second transistor T2 can be turned on by a first scan bias signal from the first scan bias line EBL1 to connect the first electrode of the light emitting element LE with the second driving voltage line VIL. As a result, a second driving voltage VINT from the second driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The first scan bias line EBL1 can be connected with a gate electrode of the second transistor T2, a first electrode of the second transistor T2 can be connected with the first electrode of the light emitting element LE, and a second electrode of the second transistor T2 can be connected with the second driving voltage line VIL.

[0104] The third transistor T3 can be arranged between the first electrode of the first capacitor Cpr and the third driving voltage line VRL. The third transistor T3 can be turned on by a first scan bias signal from the first scan bias line EBL1 to connect the first electrode of the first capacitor Cpr with the third driving voltage line VRL. As a result, a third driving voltage VREF from the third driving voltage line VRL can be applied to the first electrode of the first capacitor Cpr. A gate electrode of the third transistor T3 can be connected with the first scan bias line EBL1, a second electrode of the third transistor T3 can be connected with the first electrode of the first capacitor Cpr, and a first electrode of the third transistor T3 can be connected with the third driving voltage line VRL.

[0105] The fourth transistor T4 can be arranged between the first electrode of the first capacitor Cpr and the data line DL. The fourth transistor T4 can be turned on by a scan write signal from the scan write line GWL to connect the first electrode of the first capacitor Cpr with the data line DL. As a result, a data voltage from the data line DL can be applied to the first electrode of the first capacitor Cpr. A gate electrode of the fourth transistor T4 can be connected with the scan write line GWL, a second electrode of the fourth transistor T4 can be connected with the first electrode of the first capacitor Cpr, and a first electrode of the fourth transistor T4 can be connected with the data line DL.

[0106] The fifth transistor T5 can be arranged between the gate electrode and the second electrode of the first transistor T1. The fifth transistor T5 can be turned on by a scan control signal from the scan control line GCL to connect the gate electrode of the first transistor T1 with the second electrode of the first transistor T1. That is, when the fifth transistor T5 is turned on, the gate electrode and the second electrode of the first transistor T1 are connected, and as a result, the first transistor T1 operates as a diode. A gate electrode of the fifth transistor T5 can be connected with the scan control line GCL, a first electrode of the fifth transistor T5 can be connected with the second electrode of the first transistor T1, and a second electrode of the fifth transistor T5 can be connected with the gate electrode of the first transistor T1.

[0107] The sixth transistor T6 can be arranged between the first electrode of the first transistor T1 and the fourth driving voltage line VDL. The sixth transistor T6 can be turned on by a first emission signal from the first emission line EL1 to connect the first electrode of the first transistor T1 with the fourth driving voltage line VDL. As a result, a fourth driving voltage VDD from the fourth driving voltage line VDL can be applied to the first electrode of the first transistor T1. A gate electrode of the sixth transistor T6 can be connected with the first emission line EL1, a first electrode of the sixth transistor T6 can be connected with the fourth driving voltage line VDL, and a second electrode of the sixth transistor T6 can be connected with the first electrode of the first transistor T1.

[0108] The seventh transistor T7 can be connected between the second electrode of the first transistor T1 and the first electrode of the light emitting element LE. The seventh transistor T7 can be turned on by the second emission signal from the second emission line EL2 to connect the second electrode of the first transistor T1 and the first electrode of the light emitting element LE. The gate electrode of the seventh transistor T7 can be connected with the second emission line EL2, the first electrode of the seventh transistor T7 can be connected with the second electrode of the first transistor T1, and the second electrode of the seventh transistor T7 can be connected with the first electrode of the light emitting element LE. When both the sixth transistor T6 and the seventh transistor T7 are turned on, the driving current Ids can be supplied to the light emitting element LE.

[0109] The eighth transistor T8 can be connected between the second electrode of the first transistor T1 and the second emission line EL2. The eighth transistor T8 can be turned on by the second scan bias signal from the second scan bias line EBL2 to connect the second electrode of the first transistor T1 and the second emission line EL2. The gate electrode of the eighth transistor T8 can be connected with the second scan bias line EBL2, the first electrode of the eighth transistor T8 can be connected with the second emission line EL2, and the second electrode of the eighth transistor T8 can be connected with the second electrode of the first transistor T1.

[0110] The first capacitor Cpr can be formed between the second electrode of the first transistor T1 and the first electrode of the third transistor T3. The first electrode of the first capacitor Cpr can be connected with the first electrode of the third transistor T3, and the second electrode of the first capacitor Cpr can be connected with the second electrode of the first transistor T1.

[0111] The second capacitor Cst is formed between the gate electrode of the first transistor T1 and the fourth driving voltage line VDL. The first electrode of the second capacitor Cst can be connected with the gate electrode of the first transistor T1, and the second electrode of the second capacitor Cst can be connected with the fourth driving voltage line VDL.

[0112] One of the first electrode and the second electrode of each of the first to eighth transistors T1 to T8 can be a source electrode, and the other of the first electrode and the second electrode of each of the first to eighth transistors T1 to T8 can be a drain electrode. The active layer of the first to eighth transistors T1 to T8 can include or be formed of any one of polysilicon, amorphous silicon, and oxide semiconductor. In the case where the active layer of the first to eighth transistors T1 to T8 includes or is formed of polysilicon, the active layer of the first to eighth transistors T1 to T8 can be formed by a low temperature polysilicon (“LTPS”) process.

[0113] Figure 3The illustration shows that the first transistor T1 through the eighth transistor T8 are P-type metal-oxide-semiconductor field-effect transistors (“MOSFETs”), but the present disclosure according to the invention is not limited thereto. Alternatively, the first transistor T1 through the eighth transistor T8 may be N-type MOSFETs.

[0114] Figure 3 The illustration shows a sub-pixel SP comprising eight transistors and two capacitors, but the configuration of the sub-pixel SP according to the present invention is not limited to... Figure 3 As shown in the image.

[0115] Figure 4 The diagram illustrates the application to Figure 3 The waveform diagram of the signal of the sub-pixel.

[0116] Figure 4 The diagram shows the sources and respectively. Figure 3 The scan write line GWL, scan control line GCL, first scan bias line EBL1, second scan bias line EBL2, first transmit line EM1 and second transmit line EM2 of the sub-pixel SP are connected to the scan write line GWL, scan control line GCL, first scan bias line EBL1, second scan bias line EBL2, first transmit line EM1 and second transmit line EM2, and the scan write signal GW, scan control signal GC, first scan bias signal EB1, second scan bias signal EB2, first transmit signal EM1 and second transmit signal EM2.

[0117] Reference Figure 4 The scan write signal GW is used to control the on / off state of the fourth transistor T4. The scan control signal GC is used to control the on / off state of the fifth transistor T5. The first scan bias signal EB1 is used to control the on / off state of the second transistor T2 and the third transistor T3. The second scan bias signal EB2 is used to control the on / off state of the eighth transistor T8. The first transmit signal EM1 is used to control the on / off state of the sixth transistor T6. The second transmit signal EM2 is used to control the on / off state of the seventh transistor T7.

[0118] The scan write signal GW, the scan control signal GC, the first scan bias signal EB1, the second scan bias signal EB2, the first emission signal EM1, and the second emission signal EM2 can be generated at intervals of a first frame period. The first frame period can include a first period t1 to a seventh period t7. The first period t1 can be a period during which the gate electrode of the first transistor T1 is initialized, the second period t2 can be a period during which a threshold voltage is sampled to the gate electrode of the first transistor T1, the third period t3 can be a period during which a data voltage is supplied to the gate electrode of the first transistor T1, the fourth period t4 to the sixth period t6 can be a period during which an on-bias voltage is applied to the first transistor T1 and the first electrode of the light-emitting element LE is initialized, and the seventh period t7 is a period during which the light-emitting element LE emits light according to a drive current Ids from the first transistor T1.

[0119] The scan write signal GW can have a gate-on voltage during the third period t3, and can have a gate-off voltage during other periods. The scan control signal GC can have a gate-on voltage during the first period t1 to the third period t3, and can have a gate-off voltage during other periods. The first scan bias signal EB1 can have a gate-on voltage during the first period t1, the second period t2, the fifth period t5, and the sixth period t6, and can have a gate-off voltage during other periods. The second scan bias signal EB2 can have a gate-on voltage during the fourth period t4 and the fifth period t5, and can have a gate-off voltage during other periods. The first emission signal EM1 can have a gate-on voltage during the second period t2 and the seventh period t7, and can have a gate-off voltage during other periods. The second emission signal EM2 can have a gate-on voltage during the first period t1, the sixth period t6, and the seventh period t7, and can have a gate-off voltage during other periods.

[0120] The gate-on voltage can correspond to an on-voltage at which the second transistor T2 to the eighth transistor T8 can be turned on. The gate-off voltage can be an off-voltage at which the second transistor T2 to the eighth transistor T8 can be turned off. The gate-on voltage can be lower than the gate-off voltage.

[0121] Hereinafter, the operation of the sub-pixel SP during the first period t1 to the seventh period t7 will be described with reference to Figure 3 and Figure 4

[0122] ​First, since the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned on during the first period t1, the gate electrode of the first transistor T1 and the first electrode of the light emitting element LE can be connected to the second drive voltage line VIL. As a result, the gate electrode of the first transistor T1 and the first electrode of the light emitting element LE can be initialized to the second drive voltage VINT of the second drive voltage line VIL.

[0123] Further, since the third transistor T3 is turned on during the first period t1, the first electrode of the first capacitor Cpr can be connected to the third drive voltage line VRL. As a result, the first electrode of the first capacitor Cpr can be initialized to the third drive voltage VREF from the third drive voltage line VRL.

[0124] Second, since the fifth transistor T5 and the sixth transistor T6 are turned on during the second period t2, the first transistor T1 can operate as a diode, and the fourth drive voltage VDD from the fourth drive voltage line VDL can be applied to the first electrode of the first transistor T1. Since the gate-source voltage Vgs of the first transistor T1 is lower than the threshold voltage of the first transistor T1, the first transistor T1 can form a current path until the gate-source voltage Vgs reaches the threshold voltage. As a result, during the second period t2, the threshold voltage of the first transistor T1 can be sampled to the gate electrode of the first transistor T1.

[0125] Further, since the second transistor T2 is turned on during the second period t2, the second drive voltage VINT from the second drive voltage line VIL can be applied to the first electrode of the light emitting element LE. Further, since the third transistor T3 is turned on during the second period t2, the third drive voltage VREF from the third drive voltage line VRL can be applied to the first electrode of the first capacitor Cpr.

[0126] Third, since the fourth transistor T4 is turned on during the third period t3, the first electrode of the first capacitor Cpr can be connected to the data line DL. As a result, the data voltage from the data line DL can be applied to the first electrode of the first capacitor Cpr.

[0127] Further, since the fifth transistor T5 is turned on during the third period t3, the gate electrode and the second electrode of the first transistor T1 can be connected together. Thus, a voltage change in the first electrode of the first capacitor Cpr can be reflected to the gate electrode of the first transistor T1. As a result, the data voltage can be applied (or sampled) to the gate electrode of the first transistor T1.

[0128] Fourth, since the eighth transistor T8 is turned on during the fourth period t4, a gate cutoff voltage of the second emission signal EM2 from the second emission line EL2 can be applied to the second electrode of the first transistor T1. As a result, a current corresponding to a voltage at the gate electrode of the first transistor T1 can flow between the first and second electrodes of the first transistor T1 during the fourth period t4. That is, an on bias voltage can be applied to the first transistor T1.

[0129] Fifth, since the second and third transistors T2 and T3 are turned on during the fifth period t5, the first electrode of the light emitting element LE can be initialized to the second drive voltage VINT from the second drive voltage line VIL, and the first electrode of the first capacitor Cpr can be initialized to the third drive voltage VREF from the third drive voltage line VRL. Also, since the eighth transistor T8 is turned on during the fifth period t5, an on bias voltage can be applied to the first transistor T1.

[0130] Sixth, since the second and seventh transistors T2 and T7 are turned on during the sixth period t6, the second electrode of the first transistor T1 and the first electrode of the light emitting element LE can be initialized to the second drive voltage VINT from the second drive voltage line VIL. Also, since the third transistor T3 is turned on during the sixth period t6, the first electrode of the first capacitor Cpr can be initialized to the third drive voltage VREF from the third drive voltage line VRL.

[0131] Seventh, since the sixth and seventh transistors T6 and T7 are turned on during the seventh period t7, the first electrode of the first transistor T1 can be connected with the fourth drive voltage line VDL, and the second electrode of the first transistor T1 can be connected with the light emitting element LE. As a result, a drive current Ids flowing in the first transistor T1 according to a voltage at the gate electrode of the first transistor T1 can be supplied to the light emitting element EL.

[0132] Figure 5 is a layout diagram of a pixel of a display panel according to an embodiment of the disclosure.

[0133] For convenience, Figure 5 Only the first to sixth pixels PX1 to PX6 provided in the first direction (or X-axis direction) in the display panel 100 are illustrated.

[0134] Referring to Figure 5Each of the first to sixth pixels PX1 to PX6 can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 disposed in a first direction (or an X-axis direction). The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can respectively emit light of a first color, a second color, and a third color, and the first color, the second color, and the third color can be red, green, and blue, respectively. However, the present disclosure according to the present application is not limited to the combination and order of the colors. Figure 5 It is illustrated that each of the first to sixth pixels PX1 to PX6 includes three sub-pixels, but the number of sub-pixels of each of the first to sixth pixels PX1 to PX6 is not particularly limited.

[0135] The first driving voltage lines VSL and the second driving voltage lines VIL can extend in a second direction (or a Y-axis direction). The first driving voltage lines VSL and the second driving voltage lines VIL can be alternately disposed in the first direction (or the X-axis direction). That is, the first driving voltage lines VSL and the second driving voltage lines VIL can be disposed in the first direction (or the X-axis direction) in the order of the first driving voltage line VSL, the second driving voltage line VIL, the first driving voltage line VSL, and the second driving voltage line VIL.

[0136] One of the first driving voltage lines VSL or one of the second driving voltage lines VIL can be disposed in each pixel. For example, the first driving voltage lines VSL can be disposed in the first pixel PX1, the third pixel PX3, and the fifth pixel PX5, and the second driving voltage lines VIL can be disposed in the second pixel PX2, the fourth pixel PX4, and the sixth pixel PX6.

[0137] The positions of the first driving voltage lines VSL in the first pixel PX1, the third pixel PX3, and the fifth pixel PX5 can be the same as the positions of the second driving voltage lines VIL in the second pixel PX2, the fourth pixel PX4, and the sixth pixel PX6. That is, the first driving voltage lines VSL can be disposed between the second sub-pixel SP2 and the third sub-pixel SP3 of the first pixel PX1, between the second sub-pixel SP2 and the third sub-pixel SP3 of the third pixel PX3, and between the second sub-pixel SP2 and the third sub-pixel SP3 of the fifth pixel PX5. The second driving voltage lines VIL can be disposed between the second sub-pixel SP2 and the third sub-pixel SP3 of the second pixel PX2, between the second sub-pixel SP2 and the third sub-pixel SP3 of the fourth pixel PX4, and between the second sub-pixel SP2 and the third sub-pixel SP3 of the sixth pixel PX6.

[0138] By disposing one of the first driving voltage lines VSL or one of the second driving voltage lines VIL between the second sub-pixel SP2 and the third sub-pixel SP3 of each pixel, as Figure 5As shown in FIG. 1, the first transistor T1 of the second sub-pixel SP2 can be effectively prevented or suppressed from being affected by the data line DL connected to the third sub-pixel SP3. Hereinafter, this will be described with reference to Figure 6 and Figure 7 This will be described in detail.

[0139] Figure 6 is a layout diagram of the first pixel of Figure 5 is a layout diagram of the second pixel of Figure 7 Figure 5

[0140] Figure 6 FIG. 1 illustrates the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the first pixel PX1, and Figure 7 FIG. 2 illustrates the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the second pixel PX2.

[0141] Referring to Figure 6 and Figure 7 In each of the first pixel PX1 and the second pixel PX2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be disposed in a first direction (or an X-axis direction). The second drive voltage line VIL can include a second horizontal drive voltage line HVIL extending in the first direction (or the X-axis direction) and a second vertical drive voltage line VVIL extending in a second direction (or a Y-axis direction). The third drive voltage line VRL can include a third horizontal drive voltage line HVRL extending in the first direction (or the X-axis direction) and a third vertical drive voltage line VVRL extending in the second direction (or the Y-axis direction). The fourth drive voltage line VDL can include a fourth horizontal drive voltage line HVDL extending in the first direction (or the X-axis direction), a fourth vertical drive voltage line VVDL extending in the second direction (or the Y-axis direction), and a storage voltage line VSTL extending in the first direction (or the X-axis direction).

[0142] ​​In each of the first, second, and third sub-pixels SP1, SP2, and SP3, the third horizontal drive voltage line HVRL, the scan write line GWL, the first scan bias line EBL1, the second horizontal drive voltage line HVIL, the first emission line EL1, the fourth horizontal drive voltage line HVDL, the storage voltage line VSTL, the repair line RPL, the scan control line GCL, the second scan bias line EBL2, and the second emission line EL2 can extend in a first direction (or an X-axis direction) and can be disposed in a second direction (or a Y-axis direction). In each of the first, second, and third sub-pixels SP1, SP2, and SP3, the data line DL, the fourth vertical drive voltage line VVDL, and the third vertical drive voltage line VVRL can extend in the second direction (or the Y-axis direction) and can be disposed in the first direction (or the X-axis direction).

[0143] The first drive voltage line VSL can be disposed between the second and third sub-pixels SP2 and SP3 of the first pixel PX1. The second vertical drive voltage line VVIL of the second drive voltage line VIL can be disposed between the second and third sub-pixels SP2 and SP3 of the second pixel PX2.

[0144] Each of the first, second, and third sub-pixels SP1, SP2, and SP3 of each of the first and second pixels PX1 and PX2 can include the first through eighth transistors T1 to T8, the first capacitor Cpr, and the second capacitor Cst.

[0145] The first transistor T1 can be disposed between two adjacent data lines DL in the first direction (or the X-axis direction). The first transistor T1 can be disposed between the fourth horizontal drive voltage line HVDL and the repair line RPL in the second direction (or the Y-axis direction). The first transistor T1 can overlap the storage voltage line VSTL in the third direction (i.e., the Z-axis direction).

[0146] The second transistor T2 can be disposed between the first scan bias line EBL1 and the first emission line EL1 in the second direction (or the Y-axis direction). At least a portion of the second transistor T2 can overlap the data line DL and the second horizontal drive voltage line HVIL in the third direction (i.e., the Z-axis direction).

[0147] The third transistor T3 can be disposed between the fourth vertical drive voltage line VVDL and the third vertical drive voltage line VVRL in the first direction (or the X-axis direction). The third transistor T3 can be disposed between the scan write line GWL and the first scan bias line EBL1 in the second direction (or the Y-axis direction).

[0148] The fourth transistor T4 can be disposed between the data line DL and the fourth vertical driving voltage line VVDL in the first direction (or the X-axis direction). The fourth transistor T4 can be disposed between the scan write line GWL and the first scan bias line EBL1 in the second direction (or the Y-axis direction).

[0149] The fifth transistor T5 can be disposed between the repair line RPL and the scan control line GCL in the second direction (or the Y-axis direction). At least a portion of the fifth transistor T5 can overlap the fourth vertical driving voltage line VVDL in the third direction (i.e., the Z-axis direction).

[0150] The sixth transistor T6 can be disposed between the first emission line EL1 and the first transistor T1 in the second direction (or the Y-axis direction). At least a portion of the sixth transistor T6 can overlap the fourth horizontal driving voltage line HVDL and the fourth vertical driving voltage line VVDL in the third direction (i.e., the Z-axis direction).

[0151] The seventh transistor T7 can be disposed between the data line DL and the fourth vertical driving voltage line VVDL in the first direction (or the X-axis direction). The seventh transistor T7 can be disposed between the repair line RPL and the scan control line GCL in the second direction (or the Y-axis direction).

[0152] The eighth transistor T8 can be disposed between the scan control line GCL and the second emission line EL2 in the second direction (or the Y-axis direction). The eighth transistor T8 can overlap the second scan bias line EBL2 and the fourth vertical driving voltage line VVDL in the third direction (i.e., the Z-axis direction).

[0153] The first capacitor Cpr can include a first capacitor electrode CPRE1 and a second capacitor electrode CPRE2 overlapping in the third direction (i.e., the Z-axis direction). That is, the first capacitor electrode CPRE1 can be a first electrode of the first capacitor Cpr, and the second capacitor electrode CPRE2 can be a second electrode of the first capacitor Cpr. The first capacitor Cpr can be disposed between the first emission line EL1 and the first scan bias line EBL1 in the second direction (or the Y-axis direction). The first capacitor Cpr can overlap the second horizontal driving voltage line HVIL, the third vertical driving voltage line VVRL, and the fourth vertical driving voltage line VVDL in the third direction (i.e., the Z-axis direction).

[0154] The second capacitor Cst can include the gate electrode G1 of the first transistor T1 and a portion of the storage voltage line VSTL overlapping the gate electrode G1 of the first transistor T1 in the third direction (i.e., the Z-axis direction). That is, the gate electrode G1 of the first transistor T1 can be a first electrode of the second capacitor Cst, and the portion of the storage voltage line VSTL can be a second electrode of the second capacitor Cst. The second capacitor Cst can be arranged between two adjacent data lines DL in the first direction (or the X-axis direction). The second capacitor Cst can be arranged between the fourth horizontal driving voltage line HVDL and the repair line RPL in the second direction (or the Y-axis direction). The second capacitor Cst can overlap the third vertical driving voltage line VVRL and the fourth vertical driving voltage line VVDL in the third direction (i.e., the Z-axis direction).

[0155] Referring to Figure 6 and Figure 7 , the first transistors T1 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be affected by their respective adjacent data lines DL. For example, if a white gray data voltage is applied to the gate electrodes G1 of the first transistors T1 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 and a black gray data voltage is applied to the data lines DL, the voltage at the gate electrodes G1 of the first transistors T1 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can increase due to the presence of the data lines DL. As a result, the driving current Ids of the first transistors T1 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can become lower than a desired driving current Ids, and the emission luminance of the light emitting elements LE of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can also become lower than a desired emission luminance. That is, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can display a gray level lower than a desired gray level, in which case the quality of the display can decrease, as shown in Figure 12 .

[0156] To prevent or inhibit the first transistors T1 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 from being affected by the data lines DL, it is preferable that the first driving voltage line VSL and the second vertical driving voltage line VVIL of the second driving voltage line VIL be alternately disposed between every two adjacent sub-pixels SP. However, in this case, the integration density of the sub-pixels SP can increase, and the pixels per inch (“PPI”) can thus increase. As a result, there can not be enough space to alternately dispose the first driving voltage line VSL and the second vertical driving voltage line VVIL of the second driving voltage line VIL between every two adjacent sub-pixels SP.

[0157] In the case where the first, second, and third sub-pixels SP1, SP2, and SP3 emit red, green, and blue light, respectively, the luminance of the corresponding pixel can be most affected by the luminance variation in the second sub-pixel SP2 and least affected by the luminance variation in the third sub-pixel SP3. Therefore, it is necessary to minimize the luminance variation of the second sub-pixel SP2 to minimize the luminance variation of the corresponding pixel.

[0158] In each of the first to sixth pixels PX1 to PX6, the second vertical driving voltage line VVIL of the first driving voltage line VSL or the second driving voltage line VIL can be arranged between the first transistor T1 of the second sub-pixel SP2 and the data line DL of the third sub-pixel SP3, which is the data line DL most adjacent to the first transistor T1 of the second sub-pixel SP2, to minimize the luminance variation of the second sub-pixel SP2. As a result, the first transistor T1 of the second sub-pixel SP2 can be effectively prevented or suppressed from being affected by the data line DL of the third sub-pixel SP3.

[0159] Figure 6 and Figure 7 The second vertical driving voltage line VVIL of the first driving voltage line VSL or the second driving voltage line VIL is illustrated as being arranged between the first transistor T1 of the second sub-pixel SP2 and the data line DL of the third sub-pixel SP3, but the present disclosure according to the present application is not limited thereto. That is, by providing the second vertical driving voltage line VVIL of the first driving voltage line VSL or the second driving voltage line VIL between the first transistor T1 of the first sub-pixel SP1 and the data line DL of the second sub-pixel SP2, the first transistor T1 of the first sub-pixel SP1 can be prevented or suppressed from being affected by the data line DL of the second sub-pixel SP2. In addition, by providing the second vertical driving voltage line VVIL of the first driving voltage line VSL or the second driving voltage line VIL between the first transistor T1 of the third sub-pixel SP3 and the data line DL of the first sub-pixel SP1 of the next pixel, the first transistor T1 of the third sub-pixel SP3 can be effectively prevented or suppressed from being affected by the data line DL of the first sub-pixel SP1 of the next pixel.

[0160] Figure 8 is Figure 7 a detailed layout of the second sub-pixel of the second pixel of

[0161] Referring to Figure 8The active layer ACT can include a third horizontal driving voltage line HVRL provided in the first direction (or X-axis direction), and channels CH1 to CH8, first electrodes S1 to S8, and second electrodes D1 to D8 of the first to eighth transistors T1 to T8. The third horizontal driving voltage line HVRL, the channel CH3, the first electrode S3, and the second electrode D3 of the third transistor T3, and the channel CH4, the first electrode S4, and the second electrode D4 of the fourth transistor T4 can be connected to each other. The channels CH1, CH2, and CH5 to CH8, the first electrodes S1, S2, and S5 to S8, and the second electrodes D1, D2, and D5 to D8 of the first to fifth transistors T1 to T5 can be connected to each other.

[0162] The channels CH1 to CH8 of the first to eighth transistors T1 to T8 can be semiconductor regions, and the third horizontal driving voltage line HVRL and the first electrodes S1 to S8 and the second electrodes D1 to D8 of the first to eighth transistors T1 to T8 can be conductive regions having conductivity.

[0163] The first gate metal layer GML1 can include gate electrodes G1 to G8 of the first to eighth transistors T1 to T8 and a second electrode CPRE2 of the first capacitor Cpr. The gate electrodes G1 to G8 of the first to eighth transistors T1 to T8 and the second electrode CPRE2 of the first capacitor Cpr can be formed as an island.

[0164] The second gate metal layer GML2 can include a storage voltage line VSTL, a repair line RPL, and a first electrode CPRE1 of the first capacitor Cpr. The first electrode CPRE1 of the first capacitor Cpr can be formed as an island.

[0165] The first source metal layer SDL1 can include a scan write line GWL extending in the first direction (or X-axis direction), a first scan bias line EBL1, a second horizontal driving voltage line HVIL, a first emission line EL1, a fourth horizontal driving voltage line HVDL, a scan control line GCL, a second scan bias line EBL2, and a second emission line EL2. The first source metal layer SDL1 can further include a data connection electrode DCE, a third driving connection electrode VRE, a first capacitor connection electrode CPB1, a second capacitor connection electrode CPB2, a first anode connection electrode ANDE1, and a gate connection electrode GCE formed as an island.

[0166] The gate connection electrode GCE can be connected to the gate electrode G1 of the first transistor T1 through a first gate contact hole GCT1. The gate connection electrode GCE can be connected to the second electrode D5 of the fifth transistor T5 through a ninth gate contact hole GCT9.

[0167] The first scan bias line EBL1 can be connected with the gate electrode G2 of the second transistor T2 through a second gate contact hole GCT2. The first scan bias line EBL1 can be connected with the gate electrode G3 of the third transistor T3 through a third gate contact hole GCT3.

[0168] The scan write line GWL can be connected with the gate electrode G4 of the fourth transistor T4 through a fourth gate contact hole GCT4. The scan control line GCL can be connected with the gate electrode G5 of the fifth transistor T5 through a fifth gate contact hole GCT5.

[0169] The first emission line EL1 can be connected with the gate electrode G6 of the sixth transistor T6 through a sixth gate contact hole GCT6. The second emission line EL2 can be connected with the gate electrode G7 of the seventh transistor T7 through a seventh gate contact hole GCT7. The second scan bias line EBL2 can be connected with the gate electrode G8 of the eighth transistor T8 through an eighth gate contact hole GCT8.

[0170] The second horizontal drive voltage line HVIL can be connected with the second electrode D2 of the second transistor T2 through a first initialization contact hole VICT1. The third drive connection electrode VRE can be connected with the first electrode S3 of the third transistor T3 through a first reference contact hole VRCT1. The data connection electrode DCE can be connected with the first electrode S4 of the fourth transistor T4 through a first data contact hole DCT1.

[0171] The fourth horizontal drive voltage line HVDL can be connected with the first electrode S6 of the sixth transistor T6 through a first high potential contact hole VDCT1. The fourth horizontal drive voltage line HVDL can be connected with the storage voltage line VSTL through a second high potential contact hole VDCT2.

[0172] The second emission line EL2 can be connected with the first electrode S8 of the eighth transistor T8 through an emission contact hole ECT. The first anode connection electrode ANDE1 can be connected with the second electrode D7 of the seventh transistor T7 through a first anode contact hole ANCT1.

[0173] The first capacitor connection electrode CPB1 can be connected with the second electrodes D3 and D4 of the third transistor T3 and the fourth transistor T4 through a second capacitor contact hole CPCT2. The first capacitor connection electrode CPB1 can be connected with the first electrode CPRE1 of the first capacitor Cpr through a first capacitor contact hole CPCT1.

[0174] The second capacitor connection electrode CPB2 can be connected with the second electrode CPRE2 of the first capacitor Cpr through a third capacitor contact hole CPCT3. The second capacitor connection electrode CPB2 can be connected with the second electrode D1 of the first transistor T1 through a fourth capacitor contact hole CPCT4.

[0175] The second source metal layer SDL2 can include a (data line) DL, a fourth vertical driving voltage line VVDL, a third vertical driving voltage line VVRL, a second vertical driving voltage line VVIL, and a first driving voltage line VSL extending in a second direction (or Y-axis direction) (or a Y direction). Figure 6 Figure 7 The second source metal layer SDL2 can further include a second anode connection electrode ANDE2 formed as an island.

[0176] The data line DL can be connected with the data connection electrode DCE through a second data contact hole DCT2. A size of the second data contact hole DCT2 can be greater than a size of the first data contact hole DCT1.

[0177] The third vertical driving voltage line VVRL can be connected with a third driving connection electrode VRE through a second reference contact hole VRCT2. A size of the second reference contact hole VRCT2 can be greater than a size of the first reference contact hole VRCT1.

[0178] The fourth vertical driving voltage line VVDL can be connected with a fourth horizontal driving voltage line HVDL through a third high potential contact hole VDCT3. A size of the third high potential contact hole VDCT3 can be greater than each of a size of the first high potential contact hole VDCT1 and a size of the second high potential contact hole VDCT2.

[0179] The second vertical driving voltage line VVIL can be connected with a second horizontal driving voltage line HVIL through a second initialization contact hole VICT2. The second horizontal driving voltage line HVIL can include a protruding portion PP protruding in the second direction (or Y-axis direction) in a region in which the second horizontal driving voltage line HVIL overlaps the second vertical driving voltage line VVIL, as shown in FIG. 2B, and the second vertical driving voltage line VVIL can be connected with the protruding portion PP. Figure 8

[0180] The first driving voltage line VSL can be connected with a first driving connection electrode VSE through a first driving contact hole VSCT, as shown in FIG. 2B. The first driving connection electrode VSE can be formed as an island. Figure 6

[0181] Since the second vertical driving voltage line VVIL is disposed between the gate electrode G1 of the first transistor T1 of the second sub-pixel SP2 and the data line DL of the third sub-pixel SP3, as shown in FIG. 2B, the gate electrode G1 of the first transistor T1 of the second sub-pixel SP2 can be effectively prevented or suppressed from being affected by the data line DL of the third sub-pixel SP3. Figure 8

[0182] ​​​​Furthermore, a second vertical driving voltage line VVIL is arranged between the gate connection electrode GCE and the data line DL of the third sub-pixel SP3, and the gate connection electrode GCE is connected to the gate electrode G1 of the first transistor T1 of the second sub-pixel SP2. As a result, the influence of the gate connection electrode GCE of the second sub-pixel SP2 on the data line DL of the third sub-pixel SP3 can be prevented or suppressed. Therefore, the influence of the gate electrode G1 of the first transistor T1 of the second sub-pixel SP2 on the data line DL of the third sub-pixel SP3 can be further prevented or suppressed.

[0183] Furthermore, the second vertical driving voltage line VVIL is arranged between the second electrode D5 of the fifth transistor T5 and the data line DL of the third sub-pixel SP3. The second electrode D5 is connected to the gate electrode G1 of the first transistor T1 via the gate connection electrode GCE. As a result, the influence of the second electrode D5 of the fifth transistor T5 on the data line DL of the third sub-pixel SP3 can be effectively prevented or suppressed. Therefore, the influence of the gate electrode G1 of the first transistor T1 on the data line DL of the third sub-pixel SP3 can be further prevented or suppressed.

[0184] Figure 9 It is along Figure 8 The line I-I' obtained Figure 5 A cross-sectional view of the display panel. Figure 10 It is along Figure 8 The line II-II' obtained Figure 5 A cross-sectional view of the display panel. Figure 11 It is along Figure 8 The line III-III' obtained Figure 5 A cross-sectional view of the display panel.

[0185] For convenience, Figure 9 to Figure 11 Only the illustration is shown. Figure 8 The fourth transistor T4, the first capacitor Cpr, the first anode connection electrode ANDE1 and the second anode connection electrode ANDE2, the seventh transistor T7, the first transistor T1, the second horizontal drive voltage line HVIL and the second vertical drive voltage line VVIL.

[0186] Reference Figure 9 to Figure 11 The TFT layer (TFTL), the light-emitting element layer (EML), and the encapsulation layer (TFE) can be sequentially arranged on the substrate (SUB1).

[0187] The TFT layer TFTL includes a black matrix layer BML, a buffer film BF, an active layer ACT, a first gate metal layer GML1, a second gate metal layer GML2, a first source metal layer SDL1, a second source metal layer SDL2, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a first organic film 160, and a second organic film 161.

[0188] The black matrix layer BML can be disposed on one surface of the substrate SUB1. The black matrix layer BML can overlap the channel CH1 of the first transistor T1 in the third direction (i.e., the Z-axis direction) to block light incident on the channel CH1 of the first transistor T1, but the present disclosure according to the present application is not limited thereto. Alternatively, the black matrix layer BML can overlap not only the channel CH1 of the first transistor T1 but also at least one of the channels CH2 to CH8 of the second to eighth transistors T2 to T8 to block light incident not only on the channel CH1 of the first transistor T1 but also on at least one of the channels CH2 to CH8 of the second to eighth transistors T2 to T8. The third direction (i.e., the Z-axis direction) can be a thickness direction of the substrate SUB1 or the display panel 100. The black matrix layer BML can be a single layer or a multi-layer film including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. The black matrix layer BML can not be provided.

[0189] The buffer film BF can be disposed on the black matrix layer BML. The buffer film BF can be disposed on a surface of the substrate SUB1 to protect the organic light-emitting layer 172 of the TFT and light-emitting element layer EML from moisture that can penetrate the substrate SUB1 susceptible to moisture. The buffer film BF can be composed of a plurality of inorganic films alternately stacked. For example, the buffer film BF can be formed as a multi-layer film in which one or more inorganic films such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0190] The active layer ACT can be disposed on the buffer film BF. The active layer ACT can include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. In a case where the active layer ACT includes or is formed of polycrystalline silicon or an oxide semiconductor, the active layer ACT doped with ions can have electrical conductivity.

[0191] The gate insulating film 130 can be disposed on the active layer ACT. The gate insulating film 130 can be disposed on the channels CH1 to CH8 of the first to eighth transistors T1 to T8. The gate insulating film 130 can be an inorganic layer such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0192] The first gate metal layer GML1 can be arranged on the gate insulating film 130. The first gate metal layer GML1 can be a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0193] The first interlayer insulating film 141 can be arranged on the first gate metal layer GML1 and on a portion of the active layer ACT. The first interlayer insulating film 141 can be an inorganic film such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 can include a plurality of inorganic films.

[0194] The second gate metal layer GML2 can be arranged on the first interlayer insulating film 141. The second gate metal layer GML2 can be a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0195] The second interlayer insulating film 142 can be arranged on the second gate metal layer GML2. The second interlayer insulating film 142 can be an inorganic film such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 can include a plurality of inorganic films.

[0196] The first source metal layer SDL1 can be arranged on the second interlayer insulating film 142. The first source metal layer SDL1 can be a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0197] The first organic film 160 can be arranged on the first source metal layer SDL1 to planarize the first source metal layer SDL1 against a height difference resulting from the active layer ACT, the first gate metal layer GML1, the second gate metal layer GML2, and the first source metal layer SDL1. The first organic film 160 can be an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0198] The second source metal layer SDL2 can be arranged on the first organic film 160. The second source metal layer SDL2 can be a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0199] The second organic film 161 can be arranged on the second source metal layer SDL2 to planarize the second source metal layer SDL2 against any height difference. The second organic film 161 can be an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0200] The first to eighth transistors T1 to T8 are arranged in the semiconductor device 100. Figure 9 and Figure 10The first to eighth transistors T1 to T8 are illustrated as top-gate TFTs in which the gate electrodes G1 to G8 are arranged above the active layer ACT, but the present disclosure according to the present application is not limited thereto. Alternatively, the first to eighth transistors T1 to T8 can be bottom-gate TFTs in which the gate electrodes G1 to G8 are arranged below the active layer ACT, or dual-gate TFTs in which the gate electrodes G1 to G8 are arranged above and below the active layer ACT.

[0201] The first data contact hole DCT1 can be a hole that exposes the first electrode S4 of the fourth transistor T4 outside the first interlayer insulating film 141 and the second interlayer insulating film 142. The data connection electrode DCE can be connected to the first electrode S4 of the fourth transistor T4 through the first data contact hole DCT1.

[0202] The second data contact hole DCT2 can be a hole that exposes the data connection electrode DCE outside the first organic film 160. The data line DL can be connected to the data connection electrode DCE through the second data contact hole DCT2.

[0203] The first capacitor contact hole CPCT1 can be a hole that exposes the first electrode CPRE1 of the first capacitor Cpr outside the second interlayer insulating film 142. The first capacitor connection electrode CPB1 can be connected to the first electrode CPRE1 of the first capacitor Cpr through the first capacitor contact hole CPCT1.

[0204] The second capacitor contact hole CPCT2 can be a hole that exposes the second electrode D4 of the fourth transistor T4 outside the first interlayer insulating film 141 and the second interlayer insulating film 142. The first capacitor connection electrode CPB1 can be connected to the second electrode D4 of the fourth transistor T4 through the second capacitor contact hole CPCT2.

[0205] The third capacitor contact hole CPCT3 can be a hole that exposes the second electrode CPRE2 of the first capacitor Cpr outside the first interlayer insulating film 141 and the second interlayer insulating film 142. The second capacitor connection electrode CPB2 can be connected to the second electrode CPRE2 of the first capacitor Cpr through the third capacitor contact hole CPCT3.

[0206] The fourth capacitor contact hole CPCT4 can be a hole that exposes the second electrode D1 of the first transistor T1 outside the first interlayer insulating film 141 and the second interlayer insulating film 142. The second capacitor connection electrode CPB2 can be connected to the second electrode D1 of the first transistor T1 through the fourth capacitor contact hole CPCT4.

[0207] The first anode contact hole ANCT1 can be a hole exposing the second electrode D7 of the seventh transistor T7 outside the first interlayer insulating film 141 and the second interlayer insulating film 142. The first anode connecting electrode ANDE1 can be connected with the second electrode D7 of the seventh transistor T7 through the first anode contact hole ANCT1.

[0208] The second anode contact hole ANCT2 can be a hole exposing the first anode connecting electrode ANDE1 outside the first organic film 160. The second anode connecting electrode ANDE2 can be connected with the first anode connecting electrode ANDE1 through the second anode contact hole ANCT2.

[0209] The second initialization contact hole VICT2 can be a hole exposing the second horizontal drive voltage line HVIL outside the first organic film 160. The second vertical drive voltage line VVIL can be connected with the second horizontal drive voltage line HVIL through the second initialization contact hole VICT2.

[0210] Figure 6 The first drive contact hole VSCT can be a hole exposing the first drive connecting electrode VSE outside the first organic film 160. The first drive voltage line VSL can be connected with the first drive connecting electrode VSE through the first drive contact hole VSCT.

[0211] The light emitting element layer EML is disposed on the TFT layer TFTL. The light emitting element layer EML includes the light emitting element 170 and the bank 180.

[0212] The light emitting element 170 and the bank 180 are disposed on the second organic film 161. The light emitting element 170 can include a first electrode 171, an organic light emitting layer 172, and a second electrode 173.

[0213] The first electrode 171 can be disposed on the second organic film 161. The first electrode 171 can be connected with the second anode connecting electrode ANDE2 through the third anode contact hole ANCT3. The third anode contact hole ANCT3 can be a hole exposing the second anode connecting electrode ANDE2 outside the second organic film 161.

[0214] In a top emission structure that emits light in a direction from the organic light emitting layer 172 to the second electrode 173, the first electrode 171 can include or be formed of a metal material having high reflectivity, such as a stack of Al and Ti (e.g., Ti / Al / Ti), a stack of Al and indium tin oxide (“ITO”) (e.g., ITO / Al / ITO), silver (Ag)-palladium (Pd)-copper (Cu) (“APC”) alloy, or a stack of APC alloy and ITO (e.g., ITO / APC / ITO).

[0215] A bank 180 can be disposed on the second organic film 161 to define the first electrode 171 and thus the emission area EA2 of the second sub-pixel SP2. The bank 180 can cover edges of the first electrode 171. The bank 180 can be an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0216] The emission area EA2 of the second sub-pixel SP2 can involve an area in which the first electrode 171, the organic light emitting layer 172, and the second electrode 173 are sequentially stacked to cause holes from the first electrode 171 and electrons from the second electrode 173 to combine together in the organic light emitting layer 172 to emit light.

[0217] The organic light emitting layer 172 is disposed on the first electrode 171. The organic light emitting layer 172 can include an organic material and can thus emit light of a specific color. For example, the organic light emitting layer 172 can include a hole transport layer, an organic material layer, and an electron transport layer.

[0218] The organic light emitting layer 172 of the first sub-pixel SP1 can emit light of a first color, the organic light emitting layer 172 of the second sub-pixel SP2 can emit light of a second color, and the organic light emitting layer 172 of the third sub-pixel SP3 can emit light of a third color. Alternatively, the organic light emitting layer 172 can be formed commonly (i.e., integrally) for all of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 and can emit white light, in which case the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can respectively overlap the first color filter layer, the second color filter layer, and the third color filter layer.

[0219] The second electrode 173 can be disposed on the organic light emitting layer 172. The second electrode 173 can cover the organic light emitting layer 172. The second electrode 173 can be a common layer formed commonly (i.e., integrally) for all of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. A capping layer can be disposed on the second electrode 173.

[0220] In a top emission structure, the second electrode 173 can include or be formed of a transparent metal material such as ITO or indium zinc oxide (“IZO”), or a semi-transparent metal material such as magnesium (Mg), Ag, or an alloy thereof. In the case in which the second electrode 173 includes or is formed of the semi-transparent metal material, emission efficiency of the second electrode 173 can be improved due to a microcavity.

[0221] A encapsulation layer TFE can be disposed on the light emitting element layer EML. The encapsulation layer TFE can include at least one inorganic film to effectively prevent oxygen or moisture from permeating into the light emitting element layer EML. The encapsulation layer TFE can further include at least one organic film to protect the light emitting element layer EML from foreign substances such as dust.

[0222] Alternatively, instead of the encapsulation layer TFE, a substrate can be disposed on the light emitting element layer EML, and a space between the light emitting element layer EML and the substrate can be a vacuum, or can have a filling film disposed therein. The filling film can be an epoxy filling film or a silicone filling film.

[0223] Figure 12 illustrates a change in gray scale between a first region and a second region of a display panel depending on the presence of Figure 5 a first driving voltage line and a second driving voltage line, Figure 5 a display panel.

[0224] Referring to Figure 12 In a case where the middle upper region and the middle lower region of the display panel 100 display a black (B) image and the other regions of the display panel 100 display a white (W) image, it is desirable that the first region A1 which is a left middle region of the display panel 100 and the second region A2 which is a center region of the display panel 100 display the same W image. However, since the middle upper region and the middle lower region of the display panel 100 both display the B image, the gate electrode G1 of the first transistor T1 of the second sub-pixel SP2 in the second region A2 can be affected by the black gray data voltage applied to the data line DL of the third sub-pixel SP3 adjacent to the second sub-pixel SP2. Accordingly, the voltage applied to the gate electrode G1 of the first transistor T1 of the second sub-pixel SP2 in the second region A2 can increase and can thus become higher than the voltage applied to the gate electrode G1 of the first transistor T1 of the second sub-pixel SP2 in the first region A1. In this case, the W image displayed in the second region A2 can become slightly darker than the W image displayed in the first region A1, as shown in (a) of FIG. 11. Figure 12

[0225] As described above with reference to Figure 5 to Figure 11 the second vertical driving voltage line VVIL of the first driving voltage line VSL or the second driving voltage line VIL is disposed between the second sub-pixel SP2 and the third sub-pixel SP3 of each pixel, specifically, between the first transistor T1 of the second sub-pixel SP2 and the data line DL of the third sub-pixel SP3. As a result, the first transistor T1 of the second sub-pixel SP2 can be effectively prevented or suppressed from being affected by the data line DL of the third sub-pixel SP3. In this case, the W image displayed in the second region A2 and the W image displayed in the first region A1 can become almost the same, as shown in (a) of FIG. 12. Figure 12 ​as shown in (b) of FIG. 10. That is, any difference between the W image displayed in the second area A2 and the W image displayed in the first area A1 can be prevented or reduced.

[0226] Figure 13 is a layout of pixels of a display panel according to another embodiment of the disclosure.

[0227] Figure 13 The embodiment of Figure 5 The embodiment of

[0228] Referring to Figure 13 , the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be alternately disposed in the first direction (or the X-axis direction). For example, the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be disposed in the first direction (or the X-axis direction) in the order of the first driving voltage line VSL, the second driving voltage line VIL, the third driving voltage line VRL, the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL, but the disclosure according to the present disclosure is not limited thereto. Alternatively, the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be disposed in the first direction (or the X-axis direction) in the order of the second driving voltage line VIL, the first driving voltage line VSL, and the third driving voltage line VRL.

[0229] One of the first driving voltage line VSL, one of the second driving voltage line VIL, or one of the third driving voltage line VRL can be disposed in each pixel. For example, the first driving voltage line VSL can be disposed in the first pixel PX1 and the fourth pixel PX4, the second driving voltage line VIL can be disposed in the second pixel PX2 and the fifth pixel PX5, and the third driving voltage line VRL can be disposed in the third pixel PX3 and the sixth pixel PX6.

[0230] The position of the first drive voltage line VSL in the first pixel PX1 and the fourth pixel PX4 can be the same as the position of the second drive voltage line VIL in the second pixel PX2 and the fifth pixel PX5. Also, the position of the first drive voltage line VSL in the first pixel PX1 and the fourth pixel PX4 can be the same as the position of the third drive voltage line VRL in the third pixel PX3 and the sixth pixel PX6. For example, the first drive voltage line VSL can be arranged between the second sub-pixel SP2 and the third sub-pixel SP3 of the first pixel PX1 and between the second sub-pixel SP2 and the third sub-pixel SP3 of the fourth pixel PX4, the second drive voltage line VIL can be arranged between the second sub-pixel SP2 and the third sub-pixel SP3 of the second pixel PX2 and between the second sub-pixel SP2 and the third sub-pixel SP3 of the fifth pixel PX5, and the third drive voltage line VRL can be arranged between the second sub-pixel SP2 and the third sub-pixel SP3 of the third pixel PX3 and between the second sub-pixel SP2 and the third sub-pixel SP3 of the sixth pixel PX6.

[0231] By providing one of the first drive voltage lines VSL, one of the second drive voltage lines VIL, or one of the third drive voltage lines VRL between the second sub-pixel SP2 and the third sub-pixel SP3 of each pixel, as shown in FIG. 1A, it is possible to effectively prevent or suppress the first transistor T1 of the second sub-pixel SP2 from being affected by the adjacent data line DL connected to the third sub-pixel SP3. Figure 13

[0232] Figure 14 is a layout diagram of the second sub-pixel of the third pixel of Figure 13

[0233] The embodiment of Figure 14 differs from the embodiment of Figure 8 only in that the third vertical drive voltage line VVRL is arranged between the second sub-pixel SP2 and the third sub-pixel SP3 of the third pixel PX3, and thus the following description will mainly focus on the difference from Figure 8

[0234] Referring to Figure 14 , the third vertical drive voltage line VVRL of the third drive voltage line VRL can be arranged between the first transistor T1 of the second sub-pixel SP2 and the data line DL of the third sub-pixel SP3. Thus, it is possible to effectively prevent or suppress the first transistor T1 of the second sub-pixel SP2 from being affected by the data line DL connected to the third sub-pixel SP3.

[0235] The third vertical drive voltage line VVRL can include a protruding portion PP2 protruding in the first direction (or the X-axis direction) to be connected to the third drive connection electrode VRE. ​​

[0236] Figure 15 is a layout diagram of pixels of a display panel according to another embodiment of the disclosure.

[0237] Figure 15 Embodiments of Figure 5 Embodiments of

[0238] Referring to Figure 15 , the first driving voltage lines VSL and the second driving voltage lines VIL can be alternately disposed in the first direction (or X-axis direction). One of the first driving voltage lines VSL or one of the second driving voltage lines VIL can be disposed in each pixel.

[0239] The first driving voltage lines VSL and the second driving voltage lines VIL can be alternately disposed in the first direction (or X-axis direction) between the first and second sub-pixels SP1 and SP2 of the 3N-2 pixel (where N is a positive integer), between the second and third sub-pixels SP2 and SP3 of the 3N-1 pixel, and between the third sub-pixel SP3 of the 3N pixel and the first sub-pixel SP1 of the 3N+1 pixel. For example, the first driving voltage lines VSL can be arranged between the first and second sub-pixels SP1 and SP2 of the first pixel PX1, between the third sub-pixel SP3 of the third pixel PX3 and the first sub-pixel SP1 of the fourth pixel PX4, and between the second and third sub-pixels SP2 and SP3 of the fifth pixel PX5, and the second driving voltage lines VIL can be arranged between the second and third sub-pixels SP2 and SP3 of the second pixel PX2, between the first and second sub-pixels SP1 and SP2 of the fourth pixel PX4, and between the third sub-pixel SP3 of the sixth pixel PX6 and the first sub-pixel SP1 of the seventh pixel (not shown).

[0240] It can be effectively prevented or suppressed that the first transistor T1 of the first sub-pixel SP1 of the 3N-2 pixel is affected by the data line DL connected to the second sub-pixel SP2 of the 3N-2 pixel. It can be prevented or suppressed that the first transistor T1 of the second sub-pixel SP2 of the 3N-1 pixel is affected by the data line DL connected to the third sub-pixel SP3 of the 3N-1 pixel. It can be effectively prevented or suppressed that the first transistor T1 of the third sub-pixel SP3 of the 3N pixel is affected by the data line DL connected to the first sub-pixel SP1 of the 3N+1 pixel.

[0241] In Figure 5In one embodiment, since the brightness of the first pixel PX1 to the sixth pixel PX6 is most affected by the brightness variation in the second sub-pixel SP2 of the first pixel PX1 to the sixth pixel PX6, the first driving voltage line VSL and the second driving voltage line VIL are used to block the second sub-pixels SP2 of the first pixel PX1 to the sixth pixel PX6 from their respective adjacent data lines DL to minimize the brightness variation in the second sub-pixels SP2 of the first pixel PX1 to the sixth pixel PX6. Conversely, in Figure 15 In one embodiment, the first driving voltage line VSL and the second driving voltage line VIL are used to alternately block the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 of the first pixel PX1 to the sixth pixel PX6, regardless of whether the brightness of the first pixel PX1 to the sixth pixel PX6 is most affected by the brightness change of the first sub-pixel SP1, the second sub-pixel SP2 or the third sub-pixel SP3 of the first pixel PX1 to the sixth pixel PX6.

[0242] By setting one of the first driving voltage lines VSL or one of the second driving voltage lines VIL between two adjacent sub-pixels SP of each pixel, such as Figure 15 As shown, the first transistor T1 of one of two adjacent sub-pixels SP can be effectively prevented or suppressed from being affected by the data line DL connected to the third sub-pixel SP3 of the corresponding pixel.

[0243] Figure 16 This is a pixel layout diagram of a display panel according to another embodiment of the present disclosure.

[0244] Figure 16 Implementation examples and Figure 15 The difference in the embodiment is that the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL are alternately arranged in the first direction (or the X-axis direction).

[0245] Reference Figure 16 The first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or the X-axis direction) in the order of first driving voltage line VSL, second driving voltage line VIL, and third driving voltage line VRL, but the present disclosure according to the invention is not limited thereto. Alternatively, the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or the X-axis direction) in the order of second driving voltage line VIL, first driving voltage line VSL, and third driving voltage line VRL.

[0246] One of the first driving voltage lines VSL, one of the second driving voltage lines VIL, or one of the third driving voltage lines VRL can be disposed in each pixel. For example, the first driving voltage lines VSL can be disposed in the first pixel PX1 and the fourth pixel PX4, the second driving voltage lines VIL can be disposed in the second pixel PX2 and the fifth pixel PX5, and the third driving voltage lines VRL can be disposed in the third pixel PX3 and the sixth pixel PX6.

[0247] The positions of the first driving voltage lines VSL in the first pixel PX1 and the fourth pixel PX4 can be different from the positions of the second driving voltage lines VIL in the second pixel PX2 and the fifth pixel PX5. Also, the positions of the first driving voltage lines VSL in the first pixel PX1 and the fourth pixel PX4 can be different from the positions of the third driving voltage lines VRL in the third pixel PX3 and the sixth pixel PX6. Also, the positions of the second driving voltage lines VIL in the second pixel PX2 and the fifth pixel PX5 can be different from the positions of the third driving voltage lines VRL in the third pixel PX3 and the sixth pixel PX6.

[0248] In an embodiment, the first driving voltage lines VSL can be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 of the first pixel PX1 and between the first sub-pixel SP1 and the second sub-pixel SP2 of the fourth pixel PX4, the second driving voltage lines VIL can be disposed between the second sub-pixel SP2 and the third sub-pixel SP3 of the second pixel PX2 and between the second sub-pixel SP2 and the third sub-pixel SP3 of the fifth pixel PX5, and the third driving voltage lines VRL can be disposed between the third sub-pixel SP3 of the third pixel PX3 and the first sub-pixel SP1 of the fourth pixel PX4 and between the third sub-pixel SP3 of the sixth pixel PX6 and the first sub-pixel SP1 of the seventh pixel (not shown).

[0249] In Figure 16 In an embodiment of the above, the first driving voltage lines VSL, the second driving voltage lines VIL, and the third driving voltage lines VRL are used to alternately block the first sub-pixels SP1, the second sub-pixels SP2, and the third sub-pixels SP3 of the first pixel PX1 to the sixth pixel PX6 regardless of whether the luminance of the first pixel PX1 to the sixth pixel PX6 is most affected by the luminance change in the first sub-pixel SP1, the second sub-pixel SP2, or the third sub-pixel SP3 of the first pixel PX1 to the sixth pixel PX6.

[0250] By providing one of the first driving voltage lines VSL, one of the second driving voltage lines VIL, or one of the third driving voltage lines VRL between two adjacent sub-pixels SP of each pixel, as Figure 16As shown in FIG. 1, the first transistor T1 of one of the two adjacent sub-pixels SP can be effectively prevented or inhibited from being affected by the data line DL connected to the third sub-pixel SP3 of the corresponding pixel.

[0251] Figure 17 is a layout diagram of a pixel of a display panel according to another embodiment of the disclosure.

[0252] Figure 17 The embodiment of Figure 5 The embodiment of differs from the embodiment of in that the positions of the first drive voltage lines VSL in the first pixel PX1, the third pixel PX3, and the fifth pixel PX5 are different from the positions of the second drive voltage lines VIL in the second pixel PX2, the fourth pixel PX4, and the sixth pixel PX6.

[0253] Referring to Figure 17 , the first drive voltage lines VSL and the second drive voltage lines VIL can be alternately disposed in the first direction (or the X-axis direction). One of the first drive voltage lines VSL or one of the second drive voltage lines VIL can be arranged in each pixel.

[0254] The first drive voltage lines VSL and the second drive voltage lines VIL can be alternately disposed in the first direction (or the X-axis direction) between the first sub-pixel SP1 and the second sub-pixel SP2 of the (2N-1)th pixel and between the second sub-pixel SP2 and the third sub-pixel SP3 of the 2Nth pixel.

[0255] In an embodiment, the first drive voltage lines VSL can be arranged between the first sub-pixel SP1 and the second sub-pixel SP2 of the first pixel PX1, between the first sub-pixel SP1 and the second sub-pixel SP2 of the third pixel PX3, and between the first sub-pixel SP1 and the second sub-pixel SP2 of the fifth pixel PX5, and the second drive voltage lines VIL can be arranged between the second sub-pixel SP2 and the third sub-pixel SP3 of the second pixel PX2, between the second sub-pixel SP2 and the third sub-pixel SP3 of the fourth pixel PX4, and between the second sub-pixel SP2 and the third sub-pixel SP3 of the sixth pixel PX6.

[0256] The first transistor T1 of the first sub-pixel SP1 of the (2N-1)th pixel can be effectively prevented or inhibited from being affected by the data line DL connected to the second sub-pixel SP2 of the (2N-1)th pixel. The first transistor T1 of the second sub-pixel SP2 of the 2Nth pixel can be effectively prevented or inhibited from being affected by the data line DL connected to the third sub-pixel SP3 of the 2Nth pixel.

[0257] In Figure 17In one embodiment, since the brightness of the first pixel PX1 to the sixth pixel PX6 is affected more by the brightness of the first sub-pixel SP1 and the second sub-pixel SP2 of the first pixel PX1 to the sixth pixel PX6 than by the brightness of the third sub-pixel SP3 of the first pixel PX1 to the sixth pixel PX6, the first driving voltage line VSL and the second driving voltage line VIL are used to alternately block the first sub-pixel SP1 and the second sub-pixel SP2 of the first pixel PX1 to the sixth pixel PX6 to minimize the brightness variation in the first sub-pixel SP1 and the second sub-pixel SP2 of the first pixel PX1 to the sixth pixel PX6.

[0258] By setting one of the first driving voltage lines VSL or one of the second driving voltage lines VIL between the first sub-pixel SP1 and the second sub-pixel SP2 of each pixel, or between the second sub-pixel SP2 and the third sub-pixel SP3 of each pixel, such as Figure 17 As shown, the first transistor T1 of the first sub-pixel SP1 can be effectively prevented or suppressed from being affected by the data line DL connected to the second sub-pixel SP2, or the first transistor T1 of the second sub-pixel SP2 can be prevented or suppressed from being affected by the data line DL connected to the third sub-pixel SP3.

[0259] Figure 18 This is a pixel layout diagram of a display panel according to another embodiment of the present disclosure.

[0260] Figure 18 Implementation examples and Figure 17 The difference in the embodiment is that the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL are alternately arranged in the first direction (or the X-axis direction).

[0261] Reference Figure 18 The first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or the X-axis direction) in the order of first driving voltage line VSL, second driving voltage line VIL, and third driving voltage line VRL, but the present disclosure according to the invention is not limited thereto. Alternatively, the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or the X-axis direction) in the order of second driving voltage line VIL, first driving voltage line VSL, and third driving voltage line VRL.

[0262] One of the first driving voltage lines VSL, one of the second driving voltage lines VIL, or one of the third driving voltage lines VRL can be disposed in each pixel. The first driving voltage lines VSL, the second driving voltage lines VIL, and the third driving voltage lines VRL can be alternately provided in the first direction (or the X-axis direction) between the first and second sub-pixels SP1 and SP2 of the 2N-1th pixel and between the second and third sub-pixels SP2 and SP3 of the 2Nth pixel.

[0263] The position of the first driving voltage line VSL in the first pixel PX1 can be the same as the position of the third driving voltage line VRL in the third pixel PX3 and the position of the second driving voltage line VIL in the fifth pixel PX5. The position of the first driving voltage line VSL in the first pixel PX1 can be different from the position of the second driving voltage line VIL in the second pixel PX2, the position of the first driving voltage line VSL in the fourth pixel PX4, and the position of the third driving voltage line VRL in the sixth pixel PX6.

[0264] In an embodiment, the first driving voltage lines VSL can be disposed between the first and second sub-pixels SP1 and SP2 of the first pixel PX1 and between the second and third sub-pixels SP2 and SP3 of the fourth pixel PX4, the second driving voltage lines VIL can be disposed between the second and third sub-pixels SP2 and SP3 of the second pixel PX2 and between the first and second sub-pixels SP1 and SP2 of the fifth pixel PX5, and the third driving voltage lines VRL can be disposed between the first and second sub-pixels SP1 and SP2 of the third pixel PX3 and between the second and third sub-pixels SP2 and SP3 of the sixth pixel PX6.

[0265] In Figure 18 In an embodiment of the above-described aspect, since the luminance of the first to sixth pixels PX1 to PX6 is more affected by the luminance of the first and second sub-pixels SP1 and SP2 of the first to sixth pixels PX1 to PX6 than by the luminance of the third sub-pixels SP3 of the first to sixth pixels PX1 to PX6, the first driving voltage lines VSL, the second driving voltage lines VIL, and the third driving voltage lines VRL are alternately used to block the first and second sub-pixels SP1 and SP2 of the first to sixth pixels PX1 to PX6 to minimize the luminance variation in the first and second sub-pixels SP1 and SP2 of the first to sixth pixels PX1 to PX6.

[0266] By providing one of the first driving voltage lines VSL, one of the second driving voltage lines VIL, or one of the third driving voltage lines VRL between the first and second sub-pixels SP1 and SP2 of each pixel or between the second and third sub-pixels SP2 and SP3 of each pixel, as Figure 18As shown in FIG. 1, the first transistor T1 of the first sub-pixel SP1 can be effectively prevented or inhibited from being affected by the data line DL connected to the second sub-pixel SP2, or the first transistor T1 of the second sub-pixel SP2 can be prevented or inhibited from being affected by the data line DL connected to the third sub-pixel SP3.

[0267] Figure 19 is a layout diagram of a pixel of a display panel according to another embodiment of the disclosure.

[0268] Figure 19 The embodiment of Figure 5 The embodiment of differs from the embodiment of in that the first drive voltage line VSL or the second drive voltage line VIL (i.e., one of the first drive voltage line VSL and the second drive voltage line VIL) is disposed in the 2N-1th pixel in the first direction (or the X-axis direction), and both the first drive voltage line VSL and the second drive voltage line VIL are disposed in the 2Nth pixel in the first direction (or the X-axis direction).

[0269] Referring to Figure 19 , the first drive voltage line VSL and the second drive voltage line VIL can be alternately disposed in the first direction (or the X-axis direction). The first drive voltage line VSL and the second drive voltage line VIL can be alternately disposed in the first direction (or the X-axis direction) between the second sub-pixel SP2 and the third sub-pixel SP3 of the 2N-1th pixel, between the first sub-pixel SP1 and the second sub-pixel SP2 of the 2Nth pixel, and between the third sub-pixel SP3 of the 2Nth pixel and the first sub-pixel SP1 of the 2N+1th pixel.

[0270] In an embodiment, the first drive voltage line VSL can be disposed between the second sub-pixel SP2 and the third sub-pixel SP3 of the first pixel PX1, between the third sub-pixel SP3 of the second pixel PX2 and the first sub-pixel SP1 of the third pixel PX3, between the first sub-pixel SP1 and the second sub-pixel SP2 of the fourth pixel PX4, between the second sub-pixel SP2 and the third sub-pixel SP3 of the fifth pixel PX5, and between the third sub-pixel SP3 of the sixth pixel PX6 and the first sub-pixel SP1 of the seventh pixel (not shown), and the second drive voltage line VIL can be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 of the second pixel PX2, between the second sub-pixel SP2 and the third sub-pixel SP3 of the third pixel PX3, between the third sub-pixel SP3 of the fourth pixel PX4 and the first sub-pixel SP1 of the fifth pixel PX5, and between the first sub-pixel SP1 and the second sub-pixel SP2 of the sixth pixel PX6.

[0271] The first transistor T1 of the second sub-pixel SP2 of the 2N-1 pixel can be effectively prevented or suppressed from being affected by the data line DL connected to the third sub-pixel SP3 of the 2N-1 pixel. The first transistor T1 of the first sub-pixel SP1 of the 2N pixel can be effectively prevented or suppressed from being affected by the data line DL connected to the second sub-pixel SP2 of the 2N pixel. The first transistor T1 of the third sub-pixel SP3 of the 2N pixel can be effectively prevented or suppressed from being affected by the data line DL connected to the first sub-pixel SP1 of the 2N+1 pixel.

[0272] exist Figure 5 In one embodiment, the first driving voltage line VSL and the second driving voltage line VIL are alternately arranged in a first direction (or X-axis direction) in units of every three sub-pixels SP, while... Figure 19 In one embodiment, the first driving voltage line VSL and the second driving voltage line VIL are alternately arranged in a first direction (or X-axis direction) at units of every two sub-pixels SP. Therefore, with Figure 5 Compared to the previous embodiment, Figure 19 In some embodiments, the number of sub-pixels SP that can be blocked by the first driving voltage line VSL, the second driving voltage line VIL, and the data line DL can be increased.

[0273] Figure 20 This is a pixel layout diagram of a display panel according to another embodiment of the present disclosure.

[0274] Figure 20 Implementation examples and Figure 19 The difference in the embodiment is that the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL are alternately arranged in the first direction (or the X-axis direction).

[0275] Reference Figure 20 The first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or the X-axis direction) in the order of first driving voltage line VSL, second driving voltage line VIL, and third driving voltage line VRL, but the present disclosure according to the invention is not limited thereto. Alternatively, the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or the X-axis direction) in the order of second driving voltage line VIL, first driving voltage line VSL, and third driving voltage line VRL.

[0276] The first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be alternately arranged in the first direction (or the X-axis direction) between the second and third sub-pixels SP2 and SP3 of the 2N-1th pixel, between the first and second sub-pixels SP1 and SP2 of the 2Nth pixel, and between the third sub-pixel SP3 of the 2Nth pixel and the first sub-pixel SP1 of the 2N+1th pixel, respectively.

[0277] The position of the first driving voltage line VSL in the first pixel PX1 can be the same as the position of the first driving voltage line VSL in the third pixel PX3 and the position of the first driving voltage line VSL in the fifth pixel PX5. The position of the second driving voltage line VIL in the second pixel PX2 can be the same as the position of the second driving voltage line VIL in the fourth pixel PX4 and the position of the second driving voltage line VIL in the sixth pixel PX6. The position of the third driving voltage line VRL in the second pixel PX2 can be the same as the position of the third driving voltage line VRL in the fourth pixel PX4 and the position of the third driving voltage line VRL in the sixth pixel PX6.

[0278] In an embodiment, the first driving voltage line VSL can be arranged between the second and third sub-pixels SP2 and SP3 of the first pixel PX1, between the second and third sub-pixels SP2 and SP3 of the third pixel PX3, and between the second and third sub-pixels SP2 and SP3 of the fifth pixel PX5, the second driving voltage line VIL can be arranged between the first and second sub-pixels SP1 and SP2 of the second pixel PX2, between the first and second sub-pixels SP1 and SP2 of the fourth pixel PX4, and between the first and second sub-pixels SP1 and SP2 of the sixth pixel PX6, and the third driving voltage line VRL can be arranged between the third sub-pixel SP3 of the second pixel PX2 and the first sub-pixel SP1 of the third pixel PX3, between the third sub-pixel SP3 of the fourth pixel PX4 and the first sub-pixel SP1 of the fifth pixel PX5, and between the third sub-pixel SP3 of the sixth pixel PX6 and the first sub-pixel SP1 of the seventh pixel (not shown).

[0279] In an embodiment of the display panel according to the disclosure, Figure 20 In an embodiment of the display panel according to the disclosure,

[0280] Figure 21 is a layout diagram of a pixel of a display panel according to another embodiment of the disclosure.

[0281] Referring to Figure 21 Each of the pixels PX1, PX2, PX1', and PX2' can include first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 disposed in a first direction (or an X-axis direction). The first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 can respectively emit light of a first color, a second color, a third color, and a fourth color. That is, the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 can emit light of different colors. Alternatively, two of the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 can emit light of the same color. For example, the second and fourth sub-pixels SP2 and SP4 can emit light of the same color. In this example, the first color can be red, the second and fourth colors can be green, and the third color can be blue, but the present disclosure of the present application is not limited thereto. Each of the pixels PX1, PX2, PX1', and PX2' is illustrated as including four sub-pixels SP, but the number of sub-pixels SP included in each of the pixels PX1, PX2, PX1', and PX2' is not particularly limited.

[0282] The first and second pixels PX1 and PX2 can be alternately disposed in the first direction (or the X-axis direction). The first and second pixels PX1' and PX2' can be alternately disposed in the first direction (or the X-axis direction). The first and first pixels PX1 and PX1' can be alternately disposed in the second direction (or the Y-axis direction). The second and second pixels PX2 and PX2' can be alternately disposed in the second direction (or the Y-axis direction).

[0283] In each of the first and second pixels PX1 and PX2, the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 can be sequentially disposed from left to right. In contrast, in each of the first and second pixels PX1' and PX2', the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 can be sequentially disposed from right to left.

[0284] The first sub-pixel SP1 of the first pixel PX1 and the fourth sub-pixel SP4 of the 1' pixel PX1' can be disposed in the second direction (or Y-axis direction). The second sub-pixel SP2 of the first pixel PX1 and the third sub-pixel SP3 of the 1' pixel PX1' can be disposed in the second direction (or Y-axis direction). The third sub-pixel SP3 of the first pixel PX1 and the second sub-pixel SP2 of the 1' pixel PX1' can be disposed in the second direction (or Y-axis direction). The fourth sub-pixel SP4 of the first pixel PX1 and the first sub-pixel SP1 of the 1' pixel PX1' can be disposed in the second direction (or Y-axis direction).

[0285] The first sub-pixel SP1 of the second pixel PX2 and the fourth sub-pixel SP4 of the 2' pixel PX2' can be disposed in the second direction (or Y-axis direction). The second sub-pixel SP2 of the second pixel PX2 and the third sub-pixel SP3 of the 2' pixel PX2' can be disposed in the second direction (or Y-axis direction). The third sub-pixel SP3 of the second pixel PX2 and the second sub-pixel SP2 of the 2' pixel PX2' can be disposed in the second direction (or Y-axis direction). The fourth sub-pixel SP4 of the second pixel PX2 and the first sub-pixel SP1 of the 2' pixel PX2' can be disposed in the second direction (or Y-axis direction).

[0286] The first driving voltage line VSL and the second driving voltage line VIL can extend in the second direction (or Y-axis direction). The first driving voltage line VSL and the second driving voltage line VIL can be alternately disposed in the first direction (or X-axis direction). That is, the first driving voltage line VSL and the second driving voltage line VIL can be disposed in the first direction (or X-axis direction) in the order of the first driving voltage line VSL, the second driving voltage line VIL, the first driving voltage line VSL, and the second driving voltage line VIL. One of the first driving voltage line VSL and one of the second driving voltage line VIL can be disposed in each pixel.

[0287] The position of the first driving voltage line VSL in the first pixel PX1 can be different from the position of the first driving voltage line VSL in the second pixel PX2. The position of the second driving voltage line VIL in the first pixel PX1 can be the same as the position of the second driving voltage line VIL in the second pixel PX2. The position of the first driving voltage line VSL in the first pixel PX1 can be different from the position of the second driving voltage line VIL in the first pixel PX1 and the position of the second driving voltage line VIL in the second pixel PX2.

[0288] The first driving voltage line VSL and the second driving voltage line VIL can be alternately disposed in the first direction (or X-axis direction) between the first and second sub-pixels SP1 and SP2 of the (2N-1)th pixel, between the fourth sub-pixel SP4 of the (2N-1)th pixel and the first sub-pixel SP1 of the 2Nth pixel, between the third and fourth sub-pixels SP3 and SP4 of the 2Nth pixel, and between the fourth sub-pixel SP4 of the 2Nth pixel and the first sub-pixel SP1 of the (2N+1)th pixel (not shown).

[0289] In an embodiment, the first driving voltage line VSL can be disposed between the first and second sub-pixels SP1 and SP2 of the first pixel PX1 and between the third and fourth sub-pixels SP3 and SP4 of the second pixel PX2, and the second driving voltage line VIL can be disposed between the fourth sub-pixel SP4 of the first pixel PX1 and the first sub-pixel SP1 of the second pixel PX2 and between the fourth sub-pixel SP4 of the second pixel PX2 and the first sub-pixel SP1 of the third pixel PX3.

[0290] The position of the first driving voltage line VSL in the 1’th pixel PX1’ can be different from the position of the first driving voltage line VSL in the 2’th pixel PX2’. The position of the second driving voltage line VIL in the 1’th pixel PX1’ can be the same as the position of the second driving voltage line VIL in the 2’th pixel PX2’. The position of the first driving voltage line VSL in the 1’th pixel PX1’ can be different from the position of the second driving voltage line VIL in the 1’th pixel PX1’ and the position of the second driving voltage line VIL in the 2’th pixel PX2’.

[0291] The first driving voltage line VSL and the second driving voltage line VIL can be alternately disposed in the first direction (or X-axis direction) between the third and fourth sub-pixels SP3 and SP4 of the (2N-1)’th pixel, between the first sub-pixel SP1 of the (2N-1)’th pixel and the fourth sub-pixel SP4 of the 2N’th pixel, between the first sub-pixel SP1 of the 2N’th pixel and the second sub-pixel SP2, and between the first sub-pixel SP1 of the 2N’th pixel and the fourth sub-pixel SP4 of the (2N+1)’th pixel (not shown).

[0292] In an embodiment, the first driving voltage line VSL can be disposed between the third and fourth sub-pixels SP3 and SP4 of the 1’th pixel PX1’ and between the first and second sub-pixels SP1 and SP2 of the 2’th pixel PX2’, and the second driving voltage line VIL can be disposed between the first sub-pixel SP1 of the 1’th pixel PX1’ and the fourth sub-pixel SP4 of the 2’th pixel PX2’ and between the first sub-pixel SP1 of the 2’th pixel PX2’ and the fourth sub-pixel SP4 of the 3’th pixel (not shown).

[0293] In Figure 21 In an embodiment of the display panel according to the present disclosure, the first driving voltage line VSL and the second driving voltage line VIL can be used to block the first sub-pixel SP1, the third sub-pixel SP3, and the fourth sub-pixel SP4 adjacent to each other between every two adjacent sub-pixels in the first direction (or the X-axis direction) or in the second direction (or the Y-axis direction), regardless of which of the first sub-pixel SP1 to the fourth sub-pixel SP4 of each pixel affects the maximum brightness of the corresponding pixel. Therefore, the first transistors T1 of the first sub-pixel SP1, the third sub-pixel SP3, and the fourth sub-pixel SP4 can be effectively prevented or inhibited from being affected by their respective adjacent data lines DL.

[0294] Figure 22 is a layout diagram of a pixel of a display panel according to another embodiment of the present disclosure.

[0295] Figure 22 The embodiment of the display panel according to the present disclosure is different from the embodiment of the display panel according to the present disclosure in that the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL are alternately arranged in the first direction (or the X-axis direction). Figure 21 The embodiment of the display panel according to the present disclosure is different from the embodiment of the display panel according to the present disclosure in that the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL are alternately arranged in the first direction (or the X-axis direction).

[0296] Referring to Figure 22 , the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or the X-axis direction) in the order of the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL, but the present disclosure according to the present disclosure is not limited thereto. Alternatively, the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or the X-axis direction) in the order of the second driving voltage line VIL, the first driving voltage line VSL, and the third driving voltage line VRL.

[0297] The first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be alternately arranged in the first direction (or the X-axis direction) between the first sub-pixel SP1 and the second sub-pixel SP2 of the 2N-1th pixel, between the fourth sub-pixel SP4 of the 2N-1th pixel and the first sub-pixel SP1 of the 2Nth pixel, between the third sub-pixel SP3 and the fourth sub-pixel SP4 of the 2Nth pixel, and between the fourth sub-pixel SP4 of the 2Nth pixel and the first sub-pixel SP1 of the 2N+1th pixel (not shown).

[0298] In an embodiment, the first driving voltage line VSL can be arranged between the first and second sub-pixels SP1 and SP2 of the first pixel PX1 and between the fourth sub-pixel SP4 of the second pixel PX2 and the first sub-pixel SP1 of a third pixel (not shown), one of the third driving voltage lines VRL can be arranged between the third and fourth sub-pixels SP3 and SP4 of the second pixel PX2, and one of the second driving voltage lines VIL can be arranged between the fourth sub-pixel SP4 of the first pixel PX1 and the first sub-pixel SP1 of the second pixel PX2.

[0299] Further, the first, second, and third driving voltage lines VSL, VIL, and VRL can be alternately provided in the first direction (or X-axis direction) between the third and fourth sub-pixels SP3 and SP4 of the (2N-1)'th pixel, between the first sub-pixel SP1 of the (2N-1)'th pixel and the fourth sub-pixel SP4 of the 2N'th pixel, between the first and second sub-pixels SP1 and SP2 of the 2N'th pixel, and between the first sub-pixel SP1 of the 2N'th pixel and the fourth sub-pixel SP4 of the (2N+1)'th pixel (not shown).

[0300] In an embodiment, the first driving voltage line VSL can be arranged between the third and fourth sub-pixels SP3 and SP4 of the 1'st pixel PX1' and between the first sub-pixel SP1 of the 2'nd pixel PX2' and the fourth sub-pixel SP4 of a 3'rd pixel (not shown), one of the second driving voltage lines VIL can be arranged between the first sub-pixel SP1 of the 1'st pixel PX1' and the fourth sub-pixel SP4 of the 2'nd pixel PX2', and one of the third driving voltage lines VRL can be arranged between the first and second sub-pixels SP1 and SP2 of the 2'nd pixel PX2'.

[0301] In Figure 22 In an embodiment, the first, second, and third driving voltage lines VSL, VIL, and VRL can be used to block the first, third, and fourth sub-pixels SP1, SP3, and SP4 adjacent to each other between every two adjacent sub-pixels in the first direction (or X-axis direction) or in the second direction (or Y-axis direction), regardless of which of the first to fourth sub-pixels SP1 to SP4 of each pixel affects the maximum brightness of the corresponding pixel. Thus, the first transistors T1 of the first, third, and fourth sub-pixels SP1, SP3, and SP4 can be effectively prevented or suppressed from being affected by their respective adjacent data lines DL.

[0302] Figure 23 is a layout diagram of a pixel of a display panel according to another embodiment of the disclosure.

[0303] Figure 23 Embodiments of the present application are different from embodiments of the present application Figure 21 in that the first driving voltage line VSL is arranged between the second and third sub-pixels SP2 and SP3 of the first pixel PX1, the second and third sub-pixels SP2 and SP3 of the 1' pixel PX1', the second and third sub-pixels SP2 and SP3 of the second pixel PX2, and the second and third sub-pixels SP2 and SP3 of the 2' pixel PX2'.

[0304] Referring to Figure 23 , the first and second driving voltage lines VSL and VIL can be alternately arranged in the first direction (or X-axis direction) between the second and third sub-pixels SP2 and SP3 of the 2N-1 pixel, between the fourth sub-pixel SP4 of the 2N-1 pixel and the first sub-pixel SP1 of the 2N pixel, between the second and third sub-pixels SP2 and SP3 of the 2N pixel, and between the fourth sub-pixel SP4 of the 2N pixel and the first sub-pixel SP1 of the 2N+1 pixel (not shown).

[0305] In embodiments, the first driving voltage line VSL can be arranged between the second and third sub-pixels SP2 and SP3 of the first pixel PX1 and between the second and third sub-pixels SP2 and SP3 of the second pixel PX2, and the second driving voltage line VIL can be arranged between the fourth sub-pixel SP4 of the first pixel PX1 and the first sub-pixel SP1 of the second pixel PX2 and between the fourth sub-pixel SP4 of the second pixel PX2 and the first sub-pixel SP1 of the third pixel (not shown).

[0306] Further, the first and second driving voltage lines VSL and VIL can be alternately arranged in the first direction (or X-axis direction) between the second and third sub-pixels SP2 and SP3 of the (2N-1)' pixel, between the first sub-pixel SP1 of the (2N-1)' pixel and the fourth sub-pixel SP4 of the 2N' pixel, between the second and third sub-pixels SP2 and SP3 of the 2N' pixel, and between the first sub-pixel SP1 of the 2N' pixel and the fourth sub-pixel SP4 of the (2N+1)' pixel (not shown).

[0307] In embodiments, the first driving voltage line VSL can be arranged between the second and third sub-pixels SP2 and SP3 of the 1' pixel PX1' and between the second and third sub-pixels SP2 and SP3 of the 2' pixel PX2', and the second driving voltage line VIL can be arranged between the first sub-pixel SP1 of the 1' pixel PX1' and the fourth sub-pixel SP4 of the 2' pixel PX2' and between the first sub-pixel SP1 of the 2' pixel PX2' and the fourth sub-pixel SP4 of the 3' pixel (not shown).

[0308] As Figure 23 indicated in FIG. 1, since the luminance of each pixel is most affected by the sub-pixels SP emitting green light, i.e., the second sub-pixel SP2 and the fourth sub-pixel SP4, the second sub-pixel SP2 and the fourth sub-pixel SP4 in every two adjacent sub-pixels in the first direction (or X-axis direction) or in the second direction (or Y-axis direction) can be blocked using the first driving voltage line VSL and the second driving voltage line VIL. Thus, the first transistor T1 of the second sub-pixel SP2 and the fourth sub-pixel SP4 can be effectively prevented or inhibited from being affected by their respective adjacent data lines DL.

[0309] Figure 24 is a layout diagram of a pixel of a display panel according to another embodiment of the disclosure.

[0310] Figure 24 The embodiment of Figure 23 differs from the embodiment of

[0311] Referring to Figure 24 , the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or X-axis direction) in the order of the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL, but the present disclosure according to the present application is not limited thereto. Alternatively, the first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be arranged in the first direction (or X-axis direction) in the order of the second driving voltage line VIL, the first driving voltage line VSL, and the third driving voltage line VRL.

[0312] The first driving voltage line VSL, the second driving voltage line VIL, and the third driving voltage line VRL can be alternately arranged in the first direction (or X-axis direction) between the second sub-pixel SP2 and the third sub-pixel SP3 of the 2N-1th pixel, between the fourth sub-pixel SP4 of the 2N-1th pixel and the first sub-pixel SP1 of the 2Nth pixel, between the second sub-pixel SP2 and the third sub-pixel SP3 of the 2Nth pixel, and between the fourth sub-pixel SP4 of the 2Nth pixel and the fourth sub-pixel SP4 of the 2N+1th pixel (not shown).

[0313] In an embodiment, the first driving voltage line VSL can be arranged between the second and third sub-pixels SP2 and SP3 of the first pixel PX1 and between the fourth sub-pixel SP4 of the second pixel PX2 and the first sub-pixel SP1 of the third pixel (not shown), one of the second driving voltage lines VIL can be arranged between the fourth sub-pixel SP4 of the first pixel PX1 and the first sub-pixel SP1 of the second pixel PX2, and one of the third driving voltage lines VRL can be arranged between the second and third sub-pixels SP2 and SP3 of the second pixel PX2.

[0314] Further, the first, second, and third driving voltage lines VSL, VIL, and VRL can be alternately provided in the first direction (or X-axis direction) between the second and third sub-pixels SP2 and SP3 of the (2N-1)'th pixel, between the first sub-pixel SP1 of the (2N-1)'th pixel and the fourth sub-pixel SP4 of the 2N'th pixel, between the second and third sub-pixels SP2 and SP3 of the 2N'th pixel, and between the first sub-pixel SP1 of the 2N'th pixel and the fourth sub-pixel SP4 of the (2N+1)'th pixel (not shown).

[0315] In an embodiment, the first driving voltage line VSL can be arranged between the second and third sub-pixels SP2 and SP3 of the 1'st pixel PX1' and between the first sub-pixel SP1 of the 2'nd pixel PX2' and the fourth sub-pixel PX4 of the 3'rd pixel (not shown), one of the second driving voltage lines VIL can be arranged between the first sub-pixel SP1 of the 1'st pixel PX1' and the fourth sub-pixel SP4 of the 2'nd pixel PX2', and one of the third driving voltage lines VRL can be arranged between the second and third sub-pixels SP2 and SP3 of the 2'nd pixel PX2'.

[0316] As shown in FIG. 1A, since the luminance of each pixel is most affected by their green-emitting sub-pixels SP, i.e., the second and fourth sub-pixels SP2 and SP4, the first, second, and third driving voltage lines VSL, VIL, and VRL can be used to block the second and fourth sub-pixels SP2 and SP4 in every two adjacent sub-pixels in the first direction (or X-axis direction) or in the second direction (or Y-axis direction). Thus, the first transistors T1 of the second and fourth sub-pixels SP2 and SP4 can be effectively prevented or suppressed from being affected by their respective adjacent data lines DL. Figure 24

[0317] In an embodiment of the display apparatus, since the driving voltage lines are arranged between adjacent sub-pixels in each pixel, the first transistor of one sub-pixel can be prevented or suppressed from being affected by the data line connected to the adjacent sub-pixel. ​

[0318] The present application should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the concept of the application to those skilled in the art.

[0319] While the present application has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit or scope of the application as defined by the appended claims.

Claims

1. A display device comprising: scan lines extending in a first direction; data lines extending in a second direction crossing the first direction and receiving data voltages; first drive voltage lines extending in the second direction and receiving first drive voltages; second drive voltage lines extending in the second direction and receiving second drive voltages different from the first drive voltages; and pixels connected to the scan lines and the data lines, wherein each of the pixels includes first, second, and third sub-pixels arranged in the first direction, the first drive voltage lines and the second drive voltage lines are alternately arranged in the first direction, a position of one of the first drive voltage lines in a first one of the pixels is different from a position of one of the second drive voltage lines in a second one of the pixels, the second one of the pixels is adjacent to the first one of the pixels in the first direction, and wherein each of the position of the one of the first drive voltage lines in the first one of the pixels and the position of the one of the second drive voltage lines in the second one of the pixels is between a first transistor of one of the first, second, and third sub-pixels and a data line of the data lines connected to a next one of the first, second, and third sub-pixels adjacent to the one of the first, second, and third sub-pixels in the corresponding pixel. At least one of the first drive voltage lines and the second drive voltage lines is arranged in each of the pixels.

2. The display device according to claim 1, wherein The first drive voltage lines and the second drive voltage lines are alternately arranged in the first direction between the first sub-pixel and the second sub-pixel of a 3N-2 one of the pixels, between the second sub-pixel and the third sub-pixel of a 3N-1 one of the pixels, and between the third sub-pixel of a 3N one of the pixels and the first sub-pixel of a 3N+1 one of the pixels, and N is a positive integer.

3. The display device according to claim 1, wherein 4. The display device according to claim 1, wherein the one of the first drive voltage lines is arranged between the first sub-pixel and the second sub-pixel of the first one of the pixels, and the one of the second drive voltage lines is arranged between the second sub-pixel and the third sub-pixel of the second one of the pixels.

5. The display device according to claim 1 or 4, wherein another one of the first drive voltage lines is arranged between the third sub-pixel of a third one of the pixels and the first sub-pixel of a fourth one of the pixels, another one of the second drive voltage lines is arranged between the first sub-pixel and the second sub-pixel of the fourth one of the pixels, the third one of the pixels is adjacent to the second one of the pixels in the first direction, and the first drive voltage lines and the second drive voltage lines are alternately arranged in the first direction between the first sub-pixel and the second sub-pixel of a 3N-2 one of the pixels, between the second sub-pixel and the third sub-pixel of a 3N-1 one of the pixels, and between the third sub-pixel of a 3N one of the pixels and the first sub-pixel of a 3N+1 one of the pixels, and N is a positive integer. the fourth pixel is adjacent to the third pixel in the first direction.

6. The display device according to claim 5, wherein another one of the first drive voltage lines is arranged between the second sub-pixel and the third sub-pixel of a fifth pixel among the pixels, another one of the second drive voltage lines is arranged between the third sub-pixel of a sixth pixel among the pixels and the first sub-pixel of a seventh pixel among the pixels, the fifth pixel is adjacent to the fourth pixel in the first direction, the sixth pixel is adjacent to the fifth pixel in the first direction, and the seventh pixel is adjacent to the sixth pixel in the first direction.

7. The display device according to claim 1, wherein the first drive voltage lines and the second drive voltage lines are alternately arranged in the first direction between the first sub-pixel and the second sub-pixel of a (2N - 1)th pixel among the pixels and between the second sub-pixel and the third sub-pixel of a 2Nth pixel among the pixels, and N is a positive integer.

8. The display device according to claim 1 or 4, wherein another one of the first drive voltage lines is arranged between the first sub-pixel and the second sub-pixel of a third pixel among the pixels, another one of the second drive voltage lines is arranged between the second sub-pixel and the third sub-pixel of a fourth pixel among the pixels, the third pixel is adjacent to the second pixel in the first direction, and the fourth pixel is adjacent to the third pixel in the first direction.

9. The display device according to claim 1, wherein the first drive voltage lines and the second drive voltage lines are alternately arranged in the first direction between the second sub-pixel and the third sub-pixel of a (2N - 1)th pixel among the pixels, between the first sub-pixel and the second sub-pixel of a 2Nth pixel among the pixels, and between the third sub-pixel of the 2Nth pixel and the first sub-pixel of a (2N + 1)th pixel among the pixels, and N is a positive integer.

10. The display device according to claim 1, wherein the one of the first drive voltage lines is arranged between the second sub-pixel and the third sub-pixel of the first pixel, and the one of the second drive voltage lines is arranged between the first sub-pixel and the second sub-pixel of the second pixel.

11. The display device according to claim 1 or 10, wherein another one of the first drive voltage lines is arranged between the third sub-pixel of the second pixel and the first sub-pixel of a third pixel among the pixels, another one of the second drive voltage lines is arranged between the second sub-pixel and the third sub-pixel of the third pixel, and the third pixel is adjacent to the second pixel in the first direction.

12. The display device according to claim 11, wherein a further one of the first drive voltage lines is arranged between the first sub-pixel and the second sub-pixel of a fourth one of the pixels, a further one of the second drive voltage lines is arranged between the third sub-pixel of the fourth one of the pixels and the first sub-pixel of a fifth one of the pixels, the fourth one of the pixels is adjacent to the third one of the pixels in the first direction, and the fifth one of the pixels is adjacent to the fourth one of the pixels in the first direction.

13. A display device comprising: scan lines extending in a first direction; data lines extending in a second direction crossing the first direction and receiving data voltages; first drive voltage lines extending in the second direction and receiving first drive voltages; second drive voltage lines extending in the second direction and receiving second drive voltages different from the first drive voltages; third drive voltage lines extending in the second direction and receiving third drive voltages different from each of the first drive voltages and the second drive voltages; and pixels connected to the scan lines and the data lines, wherein each of the pixels includes first, second, and third sub-pixels arranged in the first direction, the first, second, and third drive voltage lines are alternately arranged in the first direction, a position of one of the first drive voltage lines in a first one of the pixels is different from a position of one of the second drive voltage lines in a second one of the pixels, the second one of the pixels is adjacent to the first one of the pixels in the first direction, at least one of the first, second, and third drive voltage lines is arranged in each of the pixels, and wherein each of the position of the one of the first drive voltage lines in the first one of the pixels and the position of the one of the second drive voltage lines in the second one of the pixels is between a first transistor of one of the first, second, and third sub-pixels in the corresponding pixel and a data line among the data lines connected to a next one of the first, second, and third sub-pixels adjacent to the one of the first, second, and third sub-pixels. a position of one of the third drive voltage lines in a third one of the pixels is different from the position of the one of the first drive voltage lines in the first one of the pixels and the position of the one of the second drive voltage lines in the second one of the pixels.

14. The display device of claim 13, wherein, ​ 15. The display device of claim 13, wherein, The first driving voltage line, the second driving voltage line, and the third driving voltage line are alternately arranged in the first direction between the first sub-pixel and the second sub-pixel of a 3N-2 pixel among the pixels, between the second sub-pixel and the third sub-pixel of a 3N-1 pixel among the pixels, and between the third sub-pixel of a 3N pixel among the pixels and the first sub-pixel of a 3N+1 pixel among the pixels, and N is a positive integer.

16. The display device of claim 13, wherein, A position of one of the third driving voltage lines in a third pixel among the pixels is the same as the position of the one of the first driving voltage lines in the first pixel, and is different from the position of the one of the second driving voltage lines in the second pixel.

17. The display device of claim 13, wherein, The first driving voltage line, the second driving voltage line, and the third driving voltage line are alternately arranged in the first direction between the first sub-pixel and the second sub-pixel of a 2N-1 pixel among the pixels and between the second sub-pixel and the third sub-pixel of a 2N pixel among the pixels, and N is a positive integer.

18. The display device of claim 13, wherein, The position of the one of the second driving voltage lines in the second pixel is different from the position of the one of the first driving voltage lines in the first pixel and a position of one of the third driving voltage lines in the second pixel.

19. The display device of claim 13, wherein, The first driving voltage line, the second driving voltage line, and the third driving voltage line are alternately arranged in the first direction between the second sub-pixel and the third sub-pixel of a 2N-1 pixel among the pixels, between the first sub-pixel and the second sub-pixel of a 2N pixel among the pixels, and between the third sub-pixel of the 2N pixel and the first sub-pixel of a 2N+1 pixel among the pixels, and N is a positive integer.

20. The display device of claim 13, wherein, Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes: The first transistor controls a driving current flowing between a first electrode and a second electrode of the first transistor according to a voltage applied to a gate electrode of the first transistor; The light emitting element is connected between the first transistor and one of the first driving voltage lines; The second transistor is connected between a first electrode of the light emitting element and one of the second driving voltage lines; and The first capacitor is connected between the second electrode of the first transistor and a third transistor, The third transistor is connected between the first capacitor and one of the third driving voltage lines.

Images