Memory device including resistive memory cells and electronic device including the same

Abstract

Disclosed are a memory device including resistive memory cells and an electronic device including the same. The memory device includes a first nonvolatile memory including resistive memory cells and a controller. The controller can be configured to provide first data, a first program command, and a first address to the first nonvolatile memory. The controller can be configured to receive second data from the first nonvolatile memory in response to the first program command, which is a verify read from the resistive memory cells programmed with the first data. The controller can be configured to compare the first data with the second data to detect a number of faulty cells. When the number of the detected faulty cells is greater than a reference value, the controller can be configured to generate third data obtained by inverting the first data, and provide the third data to the first nonvolatile memory. The first data can include an inversion flag bit.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0076231, entitled "Memory Device Including Resistive Memory Cells and Electronic Device Including the Memory Device", filed with the Korean Intellectual Property Office on June 23, 2020, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a memory device including resistive memory cells and an electronic device including the memory device. Background Technology

[0004] Non-volatile memory devices using resistive materials include phase-change random access memory (PRAM), resistive RAM (RRAM), and magnetic RAM (MRAM). While dynamic memory (DRAM) and flash memory use electrical charge to store data, non-volatile memory devices using resistive materials store data using phase-change state RAM (PRAM) based on chalcogenide alloys, resistive change RAM (RRAM) based on variable resistivity materials, and resistive change RAM (MRAM) based on the magnetization state of ferromagnetic materials in MTJ (magnetic tunnel junction) thin films.

[0005] MRAM (Magnetic Random Access Memory) has attracted much attention due to its high read and write speeds, high durability, non-volatility, and low power consumption. Furthermore, MRAM can use magnetic materials as the information storage medium. Summary of the Invention

[0006] An embodiment relates to a memory device comprising: a first non-volatile memory including resistive memory cells; and a controller configured to control the first non-volatile memory. The controller may be configured to provide the first non-volatile memory with first data, a first programming command, and a first address. The controller may be configured to receive second data from the first non-volatile memory in response to the first programming command, which is a verification read from a resistive memory cell programmed with the first data. The controller may be configured to compare the first data with the second data to detect the number of faulty cells. When the detected number of faulty cells is greater than the reference value, the controller may be configured to generate third data obtained by inverting the first data and provide the third data to the first non-volatile memory. The first data may include an inverted flag bit.

[0007] The embodiments also relate to a memory device comprising: a memory cell array including resistive memory cells; read / write circuitry connected to the memory cell array via bit lines; an address decoder connected to the memory cell array via word lines; and control logic connected to the read / write circuitry and the address decoder. The read / write circuitry may be connected to a controller. The read / write circuitry may be configured to receive first data including an inverted flag bit. The control logic may be configured to receive a first programming command. The address decoder may be configured to receive a first address. The read / write circuitry, control logic, and address decoder may be configured to program the resistive memory cells based on the first data, the first programming command, and the first address. The read / write circuitry may be configured to provide the controller with second data generated by applying a verification voltage to a bit line connected to the resistive memory cells. The read / write circuitry may be configured to receive third data obtained by inverting the first data from the controller in response to the second data when the number of faulty cells detected by comparing the first and second data is greater than a reference value. The read / write circuitry, control logic, and address decoder may be configured to program the resistive memory cells based on the third data, the first programming command, and the first address.

[0008] The embodiments also relate to an electronic device comprising: a non-volatile memory including resistive memory cells; a controller configured to control the non-volatile memory; and a host configured to provide programming commands and read commands to the controller. The controller may be configured to provide first data, programming commands, and an address to the non-volatile memory. The controller may be configured to receive second data from the non-volatile memory in response to a programming command, the second data being a verification read from a resistive memory cell programmed with the first data. The controller may be configured to provide third data to the non-volatile memory obtained by inverting the first data when the number of faulty cells detected by comparing the first data and the second data is greater than the reference value. The non-volatile memory may be configured to program the resistive memory cells with the third data. The host may be configured to provide read commands and an address to the controller. The controller may be configured to provide read commands and an address to the non-volatile memory, receive fourth data obtained by reading the resistive memory cells from the non-volatile memory in response to a read command, and provide fifth data to the host obtained by inverting the fourth data. The first data may include an inverted flag bit. Attached Figure Description

[0009] The features will become apparent to those skilled in the art from the detailed description of the exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram used to illustrate an electronic device according to some example embodiments.

[0011] Figure 2It is used for explanation Figure 1 A block diagram of non-volatile memory.

[0012] Figure 3 It is shown Figure 2 A diagram of a memory cell array.

[0013] Figure 4 It is shown Figure 3 An example diagram of memory cells in a memory cell array.

[0014] Figure 5 This is an example diagram illustrating a variable resistor element according to some example embodiments.

[0015] Figure 6 This is an example diagram illustrating a variable resistor element according to some example embodiments.

[0016] Figure 7 This is a diagram illustrating data according to some example embodiments.

[0017] Figure 8 and Figure 9 This is a flowchart illustrating the operation of an electronic device according to some example embodiments.

[0018] Figure 10 This is a diagram illustrating data according to some example embodiments.

[0019] Figure 11 This is a flowchart illustrating the operation of an electronic device according to some example embodiments.

[0020] Figure 12 It is a diagram used to illustrate the operation of an electronic device according to some example embodiments.

[0021] Figure 13 This is a diagram illustrating the operation of a non-volatile memory according to some example embodiments.

[0022] Figure 14 This is a flowchart illustrating the operation of an electronic device according to some example embodiments.

[0023] Figure 15 This is a diagram illustrating data according to some example embodiments.

[0024] Figure 16 This is a flowchart illustrating the operation of an electronic device according to some example embodiments.

[0025] Figure 17 This is a flowchart illustrating the operation of an electronic device according to some example embodiments.

[0026] Figure 18This is a flowchart illustrating the operation of an electronic device according to some example embodiments.

[0027] Figure 19 It is a diagram used to illustrate the operation of an electronic device according to some example embodiments.

[0028] Figure 20 This is a block diagram illustrating a non-volatile memory according to some example embodiments.

[0029] Figure 21 This is a block diagram illustrating a memory device according to some example embodiments.

[0030] Figure 22 This is an example diagram illustrating a memory device according to some example embodiments.

[0031] Figure 23 This is an example diagram illustrating a memory chip according to some example embodiments. Detailed Implementation

[0032] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0033] In the following text, reference will be made to Figures 1 to 4 The description includes an electronic device 1 comprising a non-volatile memory 200.

[0034] Figure 1 This is a block diagram used to illustrate an electronic device according to some example embodiments. Figure 2 It is used for explanation Figure 1 A block diagram of non-volatile memory. Figure 3 It is shown Figure 2 A diagram of a memory cell array. Figure 4 It is shown Figure 3 An example diagram of memory cells in a memory cell array.

[0035] Reference Figure 1 The electronic device 1 may include a host 10 and a memory device 20.

[0036] In some example embodiments, host 10 can be connected to memory device 20 via an interface. In some example embodiments, host 10 can transmit signals to memory device 20 to control memory device 20. Furthermore, for example, host 10 can receive signals from memory device 20 to process data included in the signals.

[0037] In some example embodiments, host 10 may include a central processing unit (CPU), a controller, an application-specific integrated circuit (ASIC), etc. Alternatively, host 10 may include memory chips such as DRAM (Dynamic Random Access Memory), SRAM (Static RAM), PRAM (Phase Change RAM), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), and RRAM (Resistive RAM).

[0038] The memory device 20 may include a controller 100 and a non-volatile memory 200. In some example embodiments, the non-volatile memory 200 may include MRAM (Magnetic Random Access Memory), PRAM (Phase Change RAM), RRAM (Resistive RAM), etc. The non-volatile memory 200 may not be a resistive memory and may include various non-volatile memories such as EPROM (Electrically Erasable Programmable ROM), flash memory, and FRAM (Ferroelectric RAM).

[0039] The controller 100 and the non-volatile memory 200 can be connected to each other via an interface. The controller 100 can access the non-volatile memory 200. In some example embodiments, the controller 100 can control read operations, write operations, and erase operations on the non-volatile memory 200. The controller 100 can serve as an interface between the host 10 and the non-volatile memory 200. The controller 100 can operate in conjunction with firmware used to control the non-volatile memory 200.

[0040] The controller 100 may include an inversion module 110, an error correction code module 120 (ECC module), a buffer 130, etc. The inversion module 110, the error correction code module 120, and the buffer 130 can be electrically connected to each other through corresponding interfaces. In addition, the inversion module 110, the error correction code module 120, and the buffer 130 can send and receive signals including data to each other.

[0041] In some example embodiments, the inversion module 110 may include a detector 112 and an inverter 114. However, in some other example embodiments, the inversion module 110 does not include the detector 112 and the inverter 114, and can operate independently. Furthermore, the operation of the inversion module 110 may also be performed by the controller 100 itself. The operation of the inversion module 110 including the detector 112 and the inverter 114 will be described below.

[0042] Error correction code module 120 can add parity checks to the data to be programmed in non-volatile memory 200. Error correction code module 120 can correct errors in the data to be read from non-volatile memory 200 based on the parity check. Error correction code module 120 can use at least one of various codes (such as LDPC (Low Density Parity Check) codes, BCH (Bose-Chaudhuri-Hocquenghem) codes, RS (Reed-Solomon) codes, and polar codes) to generate parity checks and correct errors.

[0043] For example, buffer 130 may temporarily store data provided by the configuration of controller 100, host 10, and nonvolatile memory 200. Furthermore, buffer 130 may provide temporarily stored data to the configuration of controller 100, host 10, and nonvolatile memory 200. In some example embodiments, buffer 130 may include volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM), and may also include nonvolatile memory such as flash memory, PRAM (phase-change random access memory), MRAM (magnetic random access memory), ReRAM (resistive random access memory), and FRAM (ferroelectric random access memory).

[0044] Although buffer 130 is shown as being included in controller 100, buffer 130 may be included in non-volatile memory 200. In some example embodiments, buffer 130 may be a page buffer of read / write circuitry 240.

[0045] For example, the interface between host 10 and storage device 20 may include various communication standards such as USB (Universal Serial Bus), MMC (Multimedia Card), PCI (Peripheral Component Interconnect), PCI-E (High-Speed ​​PCI), ATA (Advanced Technology Accessories), Serial ATA, Parallel ATA, SCSI (Small Computer Small Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), and FireWire.

[0046] The memory device 20 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash memory cards (CF), smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, and MMCmicro), SD cards (SD, mini SD, micro SD, and SDHC), universal flash storage (UFS), etc. Furthermore, the memory device 20 may include a solid-state drive (SSD) integrated into a single semiconductor device.

[0047] Reference Figure 2The non-volatile memory 200 may include a memory cell array 210, an address (ADDR) decoder 220, a voltage generator 230, a read / write circuit 240, and control logic 250.

[0048] The memory cell array 210 can be connected to the address decoder 220 via word lines WL. The memory cell array 210 can be connected to the read / write circuitry 240 via bit lines BL. The memory cell array 210 may include multiple memory cells (e.g., memory cells MC). In some example embodiments, memory cells arranged in the row direction may be connected to word lines WL. In some example embodiments, memory cells arranged in the column direction may be connected to bit lines BL.

[0049] Address decoder 220 can be connected to memory cell array 210 via word line WL. Address decoder 220 can operate in response to control of control logic 250. Address decoder 220 can receive address ADDR from controller 100. Address decoder 220 can receive voltage from voltage generator 230 for operations such as programming and reading.

[0050] Address decoder 220 can decode the row address and column address in the received address ADDR. Address decoder 220 can use the decoded row address to select word line WL. The decoded column address DCA can be provided to read / write circuitry 240. In some example embodiments, address decoder 220 may include row decoder, column decoder, address buffer, etc.

[0051] Voltage generator 230 can generate voltages for access operations under the control of control logic 250. In some example embodiments, voltage generator 230 can generate programming voltages and programming verification voltages for performing programming operations. In some example embodiments, voltage generator 230 can generate read voltages for performing read operations, and erase voltages and erase verification voltages for performing erase operations. Furthermore, voltage generator 230 can provide the voltages for performing each operation to address decoder 220.

[0052] The read / write circuit 240 can be connected to the memory cell array 210 via bit line BL. The read / write circuit 240 can send data to and receive data from the controller 100. The read / write circuit 240 can operate in response to control logic 250. The read / write circuit 240 can receive the decoded column address DCA from the address decoder 220. The read / write circuit 240 can use the decoded column address DCA to select bit line BL.

[0053] In some example embodiments, the read / write circuitry 240 may program received data into the memory cell array 210. The read / write circuitry 240 may read data from the memory cell array 210 and provide the read data to an external source (e.g., controller 100). In some example embodiments, the read / write circuitry 240 may include configurations such as a detection amplifier, a write driver, column select circuitry, and a page buffer.

[0054] Control logic 250 can be connected to address decoder 220, voltage generator 230, and read / write circuitry 240. Control logic 250 controls the operation of non-volatile memory 200. Control logic 250 operates in response to control signals CTRL and commands CMD (e.g., write command, read command, etc.) provided from controller 100.

[0055] Reference Figure 3 and Figure 4 The memory cell array 210 may include multiple memory cells MC. The memory cells MC may be arranged along the row and column directions. For example, the memory cells MC may include variable resistor elements VR and cell transistors CT.

[0056] The gate of a cell transistor CT can be connected to word lines WL1 to WLn. The gates of cell transistors CTs located in the row direction can be connected together to a single word line (e.g., the first word line WL1). The gates of cell transistors CTs in another row can be connected to other word lines.

[0057] One end of a single-cell transistor CT can be connected to one end of a variable resistor element VR. The other end of a single-cell transistor CT can be connected to a source line (e.g., source line SL1 and source line SL2). The other ends of a pair of adjacent single-cell transistors CT can be connected together to a single source line (e.g., source line SL1).

[0058] One end of the variable resistor element VR can be connected to bit lines BL1 to BLm. The other end of the variable resistor elements VR arranged in the column direction can be connected together to a single bit line (e.g., the first bit line BL1).

[0059] The variable resistor element VR can have a low resistance state and a high resistance state depending on the bias condition. By adjusting the state of the variable resistor element VR to one of the low resistance state and the high resistance state, data can be stored in the variable resistor element VR.

[0060] Reference Figure 4The variable resistance element VR may include a free layer FL, a pinning layer PL, and a tunneling layer TL. In some example embodiments, the free layer FL, the pinning layer PL, and the tunneling layer TL may be disposed between the first line BL1 and the unit transistor CT. The tunneling layer TL may be disposed between the free layer FL and the pinning layer PL.

[0061] Figure 5 This is an example diagram illustrating a variable resistor element according to some example embodiments.

[0062] Reference Figure 5 The magnetization direction of the pinned layer PL can be fixed. Depending on the bias, the magnetization direction of the free layer FL can be the same as or opposite to the magnetization direction of the pinned layer PL.

[0063] The resistance of the variable resistor VR decreases when the magnetization directions of the free layer FL and the pinned layer PL are parallel (in the same direction). Conversely, the resistance of the variable resistor VR increases when the magnetization directions of the free layer FL and the pinned layer PL are antiparallel (in opposite directions). This resistance difference can be used to indicate the stored information, such as bits of data.

[0064] In some example embodiments, when current flows from the free layer FL to the pinned layer PL, electrons can move from the pinned layer PL to the free layer FL. Electrons flowing in the pinned layer PL can be deflected along the magnetization direction of the pinned layer PL. The free layer FL can be magnetized by electrons deflected along the magnetization direction of the pinned layer PL. In some example embodiments, the free layer FL can be magnetized in the same direction as the magnetization direction of the pinned layer PL.

[0065] In some example embodiments, when current flows from the pinned layer PL to the free layer FL, electrons can move from the free layer FL back to the pinned layer PL. Some of the electrons injected into the pinned layer PL can be reflected from the pinned layer PL back to the free layer FL. The reflected electrons can be deflected in the direction of magnetization of the pinned layer PL. The direction of deflection of the reflected electrons can be opposite to the direction of magnetization of the pinned layer PL. The free layer FL can be magnetized by the deflected electrons. Therefore, the free layer FL can be magnetized in a direction opposite to the direction of magnetization of the pinned layer PL.

[0066] Figure 6 This is an example diagram illustrating a variable resistor element according to some example embodiments.

[0067] Reference Figure 6 The variable resistance element VR' may include a pinned layer PL', a free layer FL', and a tunneling layer TL'. Figure 5 The variable resistor element VR is different. Figure 6 The pinned layer PL' and free layer FL' of the variable resistive element VR' can have a perpendicular magnetization direction.

[0068] Reference Figure 5 and Figure 6 The free layers FL and FL' included in the memory cell MC may have magnetization directions that are parallel or opposite to those of the pinned layers PL and PL'.

[0069] Depending on the direction of the write current flowing through the variable resistor element VR, the data to be written to the memory cell MC can be different.

[0070] In some example embodiments, when current flows from the free layer FL to the pinned layer PL, the free layer FL is magnetized in the same direction as the magnetization direction of the pinned layer PL, the resistance value of the variable resistor element VR decreases, and the data "0" can be written to the memory cell MC. In some example embodiments, when current flows from the pinned layer PL to the free layer FL, the free layer FL is magnetized in the opposite direction to the magnetization direction of the pinned layer PL, the resistance value of the variable resistor element VR increases, and the data "1" can be written to the memory cell MC.

[0071] Figure 7 This is a diagram illustrating data according to some example embodiments. Figure 8 and Figure 9 This is a flowchart illustrating the operation of an electronic device according to some example embodiments. Figure 10 This is a diagram illustrating data according to some example embodiments.

[0072] The number of faulty cells that occur when data "0" is written to memory cell MC can be greater than the number of faulty cells that occur when data "1" is written to memory cell MC. In other cases, the number of faulty cells that occur when data "1" is written to memory cell MC can be greater than the number of faulty cells that occur when data "0" is written to memory cell MC. Here, a faulty cell may refer to a memory cell that is programmed with specific data but is read as different data (i.e., the expected value to be written is read as another value). For example, when data with a specific logical value (e.g., 0) is written to memory cell MC, the written data may be read as different data (e.g., the read data may have the logical value 1).

[0073] According to some example embodiments, data read from the memory cell MC can be compared with data written to it, and when the number of faulty cells in the memory cell MC is greater than a reference value, the data to be written can be reversed and written.

[0074] In the following text, reference will be made to Figures 7 to 13This describes the process of programming third data D3, obtained by inverting first data D1, into non-volatile memory 200. Here, the programming operation may include write operations and erase operations. The inversion operation may include changing the logic value of a specific bit to 1 when the logic value of that specific bit is 0, or changing the logic value of that specific bit to 0 when the logic value of that specific bit is 1.

[0075] Reference Figure 7 According to some example embodiments, the first data D1 may include multiple bits. In some example embodiments, the first data D1 may include an inverted flag bit, one or more data bits, one or more ECC parity bits, etc. The inverted flag bit, data bits, and ECC parity bits are all shown as the same data (e.g., the same data string), but they may be data programmed in different memory units MC. The first data D1 may be transmitted to... Figure 2 The data of the read / write circuit 240.

[0076] The inversion flag bit indicates whether the first data D1 has been inverted. In some example embodiments, the inversion flag bit may have a logic value of 0 when the first data D1 has not been inverted. In some example embodiments, the inversion flag bit is also inverted when the first data D1 has been inverted, and the inversion flag bit may have a logic value of 1. The inversion flag bit may include a single bit, but the number of bits in the inversion flag bit may vary.

[0077] Data bits may include specific information. In some example embodiments, data bits may include information that host 10 wants to store in non-volatile memory 200. Data bits may include multiple bits. Data bits may also be inverted.

[0078] ECC parity bits can be used when correcting errors in the first data D1. ECC parity bits can be generated by the error correction code module 120. ECC parity bits can be used by the error correction code module 120 when correcting errors in the first data D1. ECC parity bits can include multiple bits. ECC parity bits can also be inverted.

[0079] Reference Figures 8 to 10 The memory cells MC (e.g., multiple memory cells MC) are programmable with first data D1 (S300). In some example embodiments, the controller 100 can control the first data D1 transmitted from the host 10 to be programmed in the memory cells MC included in the non-volatile memory 200.

[0080] A verification read can be performed on the memory cell MC programmed with the first data D1 (S301). The execution of the verification read can be controlled by the controller 100, or the verification read can be performed by, for example, the non-volatile memory 200 itself. When the verification read is performed, a second data D2 can be generated as the verification read result.

[0081] The result of the verification read (e.g., second data D2) may be provided to the controller 100 (S302). In some example embodiments, the second data D2, including the result of the verification read, may be transferred from the non-volatile memory 200 to the controller 100.

[0082] The controller 100 can use the provided verification read result to detect faulty units (S303). In some example embodiments, the inversion module 110 included in the controller 100 can use the transmitted second data D2 to detect faulty units. Therefore, the inversion module 110 can detect the number of bits with different logic values ​​by comparing the second data D2 with the first data D1. In some example embodiments, when the logic value of a specific bit of the first data D1 is "0" and the logic value of the corresponding bit of the second data D2 is "1", the inversion module 110 can detect the corresponding memory unit MC as a faulty unit.

[0083] Reference Figure 10 For example, when comparing first data D1 with second data D2, it can be checked whether two corresponding bits (e.g., a programming bit and a read bit at the same bit position) are different from each other. These two bits may be different and can be identified as faulty bits at the bit positions. In this case, the memory cell MC corresponding to the faulty bit can be detected as a faulty cell.

[0084] exist Figure 10 Although faulty bits are detected only for data bits, faulty bits can also be detected for inversion flag bits or ECC parity bits.

[0085] Refer to Figure 8 The controller 100 may determine whether the number of detected faulty cells is greater than a reference value (e.g., a reference number or a positive integer) (S304). In some example embodiments, the inversion module 110 of the controller 100 may determine whether the number of detected faulty cells in the memory cell MC is greater than a reference value.

[0086] The process can end when the number of faulty units is equal to or less than the reference value (S304 - No).

[0087] When the number of faulty cells is greater than the reference value (S304 - Yes), a reverse write can be performed (S305). In some example embodiments, a reverse write can be performed (S305) when the reference value is 3 and the number of faulty cells is 4.

[0088] Reference Figure 9 and Figure 10 Reverse write (S305) may include operations S306 and S307.

[0089] In some example embodiments, when the number of faulty units is greater than a reference value (S304 - Yes), the controller 100 may invert the first data D1 to generate the third data D3 (S306), such that, for example, if the logic value of a specific bit of the first data D1 is 0, the logic value of the corresponding specific bit of the third data D3 is inverted to 1. Therefore, the controller 100 may invert the first data D1 (instead of the second data D2) to generate the third data D3. In some example embodiments, each bit of the first data D1 may be inverted at the corresponding bit position in the third data D3.

[0090] The third data D3 can be programmed in the memory cell MC (S307). In some example embodiments, the third data D3, obtained by inverting the first data D1, can be programmed in the memory cell MC. In this case, an operation to erase the existing programmed first data D1 may be included. In some example embodiments, the erase command and address may be transmitted from the controller 100 to the non-volatile memory 200.

[0091] When the number of detected faulty cells exceeds a reference value, the write error rate (WER) of memory cell MC can be reduced by performing a reverse write (programming memory cell MC with third data D3 obtained by inverting first data D1). Therefore, when memory cell MC is written in a specific direction and the write error rate of that memory cell MC is high, the write error rate can be reduced by writing memory cell MC in the opposite direction to the specific direction.

[0092] Furthermore, by performing a reverse write only once, repeated write operations can be reduced or eliminated, and the power consumed by data programming can be reduced accordingly. As a result, the reliability and efficiency of the memory device 20, including the memory cell MC, can be improved.

[0093] Figure 11 This is a flowchart illustrating the operation of an electronic device according to some example embodiments. Figure 12 It is a diagram used to illustrate the operation of an electronic device according to some example embodiments. Figure 13 This is a diagram illustrating the operation of a non-volatile memory according to some example embodiments.

[0094] Reference Figures 11 to 13 The host 10 can provide the controller 100 with programming commands program CMD, first data D1 and address ADDR (S310).

[0095] The controller 100 may receive the programming command program CMD, the first data D1, and the address ADDR (S311). In some example embodiments, the buffer 130 may receive and temporarily store the programming command program CMD, the first data D1, and the address ADDR.

[0096] The controller 100 may provide the non-volatile memory 200 with a programming command (program CMD), first data (D1), and address (ADDR) (S312). In some example embodiments, the buffer 130 may provide the programming command (program CMD) to the control logic 250 of the non-volatile memory 200, provide the first data (D1) to the read / write circuitry 240, and provide the address (ADDR) to the address decoder 220.

[0097] The non-volatile memory 200 can be programmed based on the received programming command program CMD, first data D1, and address ADDR (S313). In some example embodiments, the word line WL connected to the memory cell array 210 is selected, a voltage is applied to the bit line BL, and the first data D1 can be programmed in the memory cell MC. The non-volatile memory 200 can program the first data D1 in the memory cell MC corresponding to the address ADDR.

[0098] The non-volatile memory 200 can perform a verification read on the programmed memory cell MC (S314). In some example embodiments, the read / write circuit 240 can provide the controller 100 with second data D2, which is a verification read result obtained by applying a verification voltage to the memory cell MC included in the memory cell array 210. In some example embodiments, the verification read can be performed by the memory cell MC itself. Therefore, the verification read can be performed without the control of the controller 100. However, the verification read of the non-volatile memory 200 can be performed by a verification read command provided from the controller 100. In addition, the verification read command can be sent together with the programming command.

[0099] The non-volatile memory 200 may provide the controller 100 with second data D2 as a verification of the read result (S315). In some example embodiments, the non-volatile memory 200 may provide the second data D2 to the buffer 130. The buffer 130 may temporarily store the second data D2.

[0100] The controller 100 can detect faulty cells and determine whether to perform a reverse write (S316). In some example embodiments, the detector 112 of the inversion module 110 can receive second data D2 and first data D1 from the buffer 130. The detector 112 can detect faulty cells by comparing the first data D1 with the second data D2. When the number of faulty cells in the memory cell MC is greater than a reference value, the detector 112 can provide the first data D1 to the inverter 114.

[0101] The controller 100 can invert the first data D1 to generate the third data D3 (S317). In some example embodiments, the inverter 114 of the inversion module 110 can invert the first data D1 to generate the third data D3.

[0102] The controller 100 may provide third data D3, programming command program CMD, and address ADDR to the non-volatile memory 200 (S318). In some example embodiments, the inverter 114 of the inversion module 110 may provide third data D3 to the non-volatile memory 200. Third data D3, programming command program CMD, and address ADDR may be provided to the non-volatile memory 200 from buffer 130.

[0103] The non-volatile memory 200 can be programmed on the memory cell MC based on the third data D3, the programming command program CMD, and the address ADDR (S319). In some example embodiments, a voltage is applied to the word line WL and bit line BL connected to the memory cell array 210, and the third data D3 (obtained by inverting the first data D1) can be programmed in the memory cell MC corresponding to the address ADDR.

[0104] The magnitude of the programming voltage provided by voltage generator 230 when the first data D1 is programmed may differ from the magnitude of the programming voltage provided by voltage generator 230 when the third data D3 is programmed. In some example embodiments, the magnitude of the programming voltage provided by voltage generator 230 when the third data D3 is programmed may be greater than the magnitude of the programming voltage provided by voltage generator 230 when the first data D1 is programmed. In some example embodiments, the power consumed when programming the memory cell MC with the third data D3 may be greater than the power consumed when programming the memory cell MC with the first data D1.

[0105] In the following text, reference will be made to Figures 14 to 16 The process of reversing the reading of the memory cell MC containing third data D3 is described according to some example embodiments.

[0106] Figure 14This is a flowchart illustrating the operation of an electronic device according to some example embodiments. Figure 15 This is a diagram illustrating data according to some example embodiments. Figure 16 This is a flowchart illustrating the operation of an electronic device according to some example embodiments.

[0107] Reference Figure 14 The controller 100 can control the non-volatile memory 200 to read data programmed into the memory cell MC (S330). In some example embodiments, the controller 100 can provide a read command to the non-volatile memory 200 to read the memory cell MC programmed with third data D3. In some example embodiments, refer to... Figure 15 The read result can be the fourth data D4. The fourth data D4 can be the same as the third data D3. The read / write circuit 240 can provide the fourth data D4 to the controller 100 in response to a voltage applied to the memory cell array 210.

[0108] Refer to Figure 14 The controller 100 can check whether the transmitted fourth data D4 is inverted data (S331). In some example embodiments, the detector 112 of the inversion module 110 included in the controller 100 can receive the fourth data D4 to check whether the fourth data D4 is inverted data.

[0109] The operation of checking whether the fourth data D4 is inverted data may include checking the inversion flag bit included in the fourth data D4. In some example embodiments, the fourth data D4 is not inverted data when the logic value of the inversion flag bit of the fourth data D4 is 0, and the fourth data D4 is inverted data when the logic value of the inversion flag bit of the fourth data D4 is 1.

[0110] When the fourth data D4 is not inverted data (S331-No), the controller 100 may perform a normal read (S333). In some example embodiments, the controller 100 may provide the fourth data D4 to the host 10 without conversion.

[0111] When the fourth data D4 is inverted data (S331-Yes), the controller 100 can perform an inverted read (S332). In some example embodiments, refer to Figure 15 The controller 100 can generate fifth data D5 obtained by inverting the fourth data D4. The controller 100 can provide the fifth data D5 to the host 10. The fifth data D5 can be the same as the first data D1 to be programmed. The host 10 can receive the data to be read by inversion. In addition, by inverting and programming the first data D1, the write error rate of the memory cell MC can be reduced.

[0112] Reference Figure 16 The host 10 can provide the read command CMD and the address ADDR to the controller 100 (S340). Here, the address ADDR can be the same as the address ADDR used during programming.

[0113] Controller 100 may receive a read command (read CMD) and an address (ADDR) (S341). In some example embodiments, a buffer 130 included in controller 100 may temporarily store the read command (read CMD) and the address (ADDR).

[0114] Controller 100 may provide read command (read CMD) and address (ADDR) to non-volatile memory 200 (S342). In some example embodiments, buffer 130 may provide the stored read command (read CMD) and address (ADDR) to non-volatile memory 200. In some example embodiments, buffer 130 may provide read command (read CMD) to control logic 250 and address (ADDR) to address decoder 220.

[0115] The non-volatile memory 200 can perform a read operation (S343). In some example embodiments, the non-volatile memory 200 can perform a read operation based on the provided read command read CMD and address ADDR. A read voltage can be applied to the bit line BL connected to the memory cell MC to read the result. In some example embodiments, the data read from the memory cell MC programmed with third data D3 can be fourth data D4. The fourth data D4 can be the same data as the third data D3.

[0116] The non-volatile memory 200 can provide the fourth data D4 (as a result of a read) to the controller 100 (S344). In some example embodiments, the read / write circuit 240 can provide the fourth data D4 to the buffer 130 of the controller 100.

[0117] The controller 100 can use the inversion flag bit of the fourth data D4 to determine whether the fourth data D4 is inverted data (S345). When the logic value of the inversion flag bit of the fourth data D4 is 0, the fourth data D4 may be uninverted data, and when the logic value of the inversion flag bit of the fourth data D4 is 1, the fourth data D4 may be inverted data.

[0118] When the fourth data D4 is inverted data, the controller 100 can invert the fourth data D4 to generate the fifth data D5 (S346). In some example embodiments, the inverter 114 of the inversion module 110 included in the controller 100 can invert the fourth data D4 to generate the fifth data D5.

[0119] Controller 100 may provide fifth data D5 to host 10 (S347). In some example embodiments, inverter 114 may provide fifth data D5 to host 10 via buffer 130. Fifth data D5 may be the same as first data D1 to be programmed.

[0120] In the following text, reference will be made to Figures 17 to 19 This describes the process of performing a reverse write after error correction, according to some example embodiments.

[0121] Figure 17 This is a flowchart illustrating the operation of an electronic device according to some example embodiments. Figure 18 This is a flowchart illustrating the operation of an electronic device according to some example embodiments. Figure 19 This is a diagram illustrating the operation of an electronic device according to some example embodiments. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 16 The repeated parts of the description.

[0122] Reference Figure 17 The memory cell MC can be programmed with first data D1 (S350). In some example embodiments, the controller 100 can control the non-volatile memory 200 to program the memory cells MC included in the memory cell array 210 with first data D1. In this case, the first data D1 may include ECC parity bits generated by the error correction code module 120. (Refer to reference...) Figures 1 to 16 The described process differs; this process may not require a verification read. Therefore, after programming the memory cell MC with the first data D1, a verification read may not be performed.

[0123] A read operation can be performed on the memory cell MC programmed with first data D1 (S351). In some example embodiments, the controller 100 can control the non-volatile memory 200 to read the memory cell MC. The sixth data D6 generated by the read operation can be provided to the controller 100.

[0124] The error correction code module 120 included in the controller 100 can perform error correction to detect faulty units (S352). In some example embodiments, the error correction code module 120 can use the ECC parity bit of the transmitted sixth data D6 to detect faulty bits.

[0125] The controller 100 can check whether the number of faulty cells in the detected memory cell MC is greater than a reference value (S353). In some example embodiments, the error correction code module 120 provides the detection result to the detector 112 of the inversion module 110, and the detector 112 can check whether the number of faulty cells is greater than the reference value. Furthermore, for example, first data D1 can be provided from the buffer 130 to the detector 112.

[0126] When the number of detected faulty cells is greater than a reference value (S353 - Yes), a reverse write can be performed (S354). In some example embodiments, a reverse write can be performed (S354) when the reference value is 3 and the number of detected faulty cells is 4. In some example embodiments, first data D1 is provided from detector 112 to inverter 114, and inverter 114 can reverse the first data D1 to generate seventh data D7. The generated seventh data D7 can be provided to non-volatile memory 200 and programmed in memory cell MC.

[0127] When the number of detected faulty units is less than or equal to the reference value (S353 - No), a read operation can be performed (S355); or when the number of detected faulty units is greater than the reference value (S353 - Yes), a read operation can be performed after the seventh data D7 is programmed into the unit MC (S355). In some example embodiments, when the number of detected faulty units is less than or equal to the reference value (S353 - No), a normal read can be performed. In some example embodiments, when the number of detected faulty units is greater than the reference value (S353 - Yes), a reverse read can be performed.

[0128] Reference Figure 18 and Figure 19 The host 10 can provide the controller 100 with programming commands program CMD, first data D1 and address ADDR (S360).

[0129] The controller 100 may receive the programming command program CMD, the first data D1, and the address ADDR (S361). In some example embodiments, the buffer 130 may receive and temporarily store the programming command program CMD, the first data D1, and the address ADDR.

[0130] The controller 100 may provide the non-volatile memory 200 with a programming command (program CMD), first data (D1), and address (ADDR) (S362). In some example embodiments, the buffer 130 may provide the programming command (program CMD) to the control logic 250 of the non-volatile memory 200, provide the first data (D1) to the read / write circuitry 240, and provide the address (ADDR) to the address decoder 220.

[0131] The non-volatile memory 200 can be programmed based on the received programming command program CMD, first data D1, and address ADDR (S363). In some example embodiments, voltage can be applied to the word line WL and bit line BL connected to the memory cell array 210 to program the memory cell MC using the first data D1. The non-volatile memory 200 can program the memory cell MC corresponding to the address ADDR with the first data D1.

[0132] The host 10 can provide the read command CMD and the address ADDR to the controller 100 (S364). The operation of providing the read command CMD and the address ADDR can be performed at any point in time after the memory cell MC is programmed with the first data D1.

[0133] Controller 100 may receive a read command (read CMD) and an address (ADDR) (S365). In some example embodiments, a buffer 130 included in controller 100 may temporarily store the read command (read CMD) and the address (ADDR).

[0134] Controller 100 may provide read command (read CMD) and address (ADDR) to non-volatile memory 200 (S366). In some example embodiments, buffer 130 may provide the stored read command (read CMD) and address (ADDR) to non-volatile memory 200. In some example embodiments, buffer 130 may provide read command (read CMD) to control logic 250 and address (ADDR) to address decoder 220.

[0135] The non-volatile memory 200 can perform a read operation (S367). In some example embodiments, the non-volatile memory 200 can perform a read operation based on the provided read command read CMD and address ADDR. A read voltage can be applied to the bit line BL connected to the memory cell MC to read the result. In some example embodiments, the data read from the memory cell MC programmed with first data D1 can be sixth data D6.

[0136] The non-volatile memory 200 may provide the controller 100 with sixth data D6 as a read result (S368). In some example embodiments, the read / write circuit 240 may provide the sixth data D6 to the buffer 130 of the controller 100.

[0137] Error correction module 120 performs error correction to detect faulty cells, and inversion module 110 determines that the write has been reversed (S369). In some example embodiments, sixth data D6 may be transmitted from buffer 130 to error correction module 120. Error correction module 120 performs error correction to detect faulty cells. Error correction module 120 may provide the detection result of the faulty cell to detector 112 of inversion module 110. Detector 112 may use the detection result of the faulty cell to check whether the number of faulty cells is greater than a reference value. When the number of faulty cells is greater than the reference value, detector 112 may provide first data D1 to inverter 114.

[0138] Controller 100 may generate seventh data D7 obtained by inverting first data D1 (S370). In some example embodiments, inverter 114 may generate seventh data D7 obtained by inverting the provided first data D1.

[0139] The controller 100 may provide the non-volatile memory 200 with the programming command program CMD, seventh data D7, and address ADDR (S371). In some example embodiments, the seventh data D7 may be transferred from the inverter 114 to the read / write circuit 240 via the buffer 130.

[0140] The non-volatile memory 200 can program the memory cell MC with the seventh data D7 based on the provided programming command program CMD, the seventh data D7, and the address ADDR (S372). The existing first data D1 that is to be programmed can be erased before programming the seventh data D7.

[0141] The controller 100 may provide the non-volatile memory 200 with a read command read CMD and an address ADDR (S373). Here, the address ADDR may be the same as the address ADDR used when programming the first data D1 and the seventh data D7.

[0142] The non-volatile memory 200 can perform a read operation (S374). In some example embodiments, the non-volatile memory 200 can perform a read operation based on the provided read command read CMD and address ADDR. A read voltage can be applied to the bit line BL connected to the memory cell MC to read the result. In some example embodiments, the data read from the memory cell MC programmed with seventh data D7 can be eighth data D8. The eighth data D8 can be the same data as the seventh data D7.

[0143] The non-volatile memory 200 may provide the controller 100 with eighth data D8 as a read result (S375). In some example embodiments, the read / write circuit 240 may provide the eighth data D8 to the buffer 130 of the controller 100. In some example embodiments, the eighth data D8 may be provided to the inverter 114.

[0144] The controller 100 can use the inversion flag bit of the eighth data D8 to determine whether the eighth data D8 is inverted data (S376). When the logic value of the inversion flag bit of the eighth data D8 is 0, the eighth data D8 can be uninverted data, and when the logic value of the inversion flag bit of the eighth data D8 is 1, the eighth data D8 can be inverted data.

[0145] When the eighth data D8 is inverted data, the controller 100 can invert the eighth data D8 to generate the ninth data D9 (S377). In some example embodiments, the inverter 114 of the inversion module 110 included in the controller 100 can invert the eighth data D8 to generate the ninth data D9.

[0146] Controller 100 may provide the ninth data D9 to host 10 (S378). In some example embodiments, inverter 114 may provide the ninth data D9 to host 10 via buffer 130. The ninth data D9 may be the same as the first data D1 to be programmed.

[0147] Error correction is performed using the error correction code module 120, and when the number of faulty cells in the memory cell MC exceeds a reference value, the memory cell MC can be programmed with inverted data. Therefore, the product reliability of the memory device 20, including the memory cell MC, can be improved.

[0148] Figure 20 This is a block diagram illustrating a non-volatile memory according to some example embodiments. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 16 The repeated parts of the description.

[0149] Reference Figure 20 The control logic 250 of the non-volatile memory 200' may include the inversion module 110. Therefore, although in Figures 1 to 16 The controller 100 includes an inversion module 110, but the controller 100 in this embodiment may not include an inversion module 110. Furthermore, the read / write circuitry 240 of the non-volatile memory 200' may include a buffer 130. Therefore, although in Figures 1 to 16 The controller 100 includes a buffer 130, but the controller 100 in this embodiment may not include a buffer 130.

[0150] Therefore, it can be performed in the non-volatile memory 200' Figures 1 to 16 The description includes verification reading, fault cell detection, determination of reverse write, reverse write operation, and reversal of read data. In some example embodiments, the controller 100 and the non-volatile memory 200' can operate without receiving or sending signals through an interface.

[0151] Figure 21 This is a block diagram illustrating a memory device according to some example embodiments. Figure 22 This is an example diagram illustrating a memory device according to some example embodiments. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 20 The repeated parts of the description.

[0152] Reference Figure 21 The memory device 201 may include a controller 100a and the memory device 201. The memory device 201 may include a plurality of memory chips 200a, 200b, and 200c. In some example embodiments, each of the plurality of memory chips 200a, 200b, and 200c may be a non-volatile memory 200. The controller 100a may be a controller 100.

[0153] Multiple memory chips 200a, 200b, and 200c can communicate with controller 100a through a single channel, or multiple memory chips 200a, 200b, and 200c can communicate with controller 100a through multiple channels.

[0154] Controller 100a can provide inverted or non-inverted data to the respective memory chips 200a, 200b, and 200c. In some example embodiments, controller 100a can use a reference... Figures 1 to 20 The described method detects faulty cells in memory chip 200a. Additionally, after detecting a faulty cell, controller 100a may provide data to memory chip 200a obtained by inverting the data to be programmed. In some example embodiments, controller 100a may use reference... Figures 1 to 20 The described method detects faulty cells in memory chip 200b. Furthermore, after detecting a faulty cell, controller 100a can provide memory chip 200b with data generated without reversing the data to be programmed.

[0155] Reference Figure 22 The memory device 20 may include a printed circuit board 30, a plurality of memory chips 200a, a buffer 40, a connector 50, and a controller 100a.

[0156] Multiple memory chips 200a can be assembled on a printed circuit board 30. A connector 50 can be electrically connected to the multiple memory chips 200a via wires. The connector 50 can be connected to a slot in the host 10, and the multiple memory chips 200a can be connected to the host 10.

[0157] The controller 100a can be connected to multiple memory chips 200a via the buffer 40 and can control multiple memory chips 200a.

[0158] Figure 23 This is an example diagram illustrating a memory chip according to some example embodiments.

[0159] Reference Figure 23 The memory chip 200a may include multiple semiconductor layers L1 to Ln. The memory chip 200a may be... Figure 21 and Figure 22 Each of the memory chips 200a, 200b and 200c.

[0160] Multiple semiconductor layers L1 to Ln can be electrically connected to each other via a through electrode 70 (e.g., a through-silicon via 70, TSV). Each of the semiconductor layers L1 to Ln may include a memory cell array 60, which includes non-volatile memory. In some example embodiments, the memory cell array 60 may include memory using… Figure 2 The memory cell array 210 is described.

[0161] As described above, the embodiments can provide a memory device with reduced write error rate and improved product reliability.

[0162] As described above, the embodiments may also provide an electronic device with a reduced write error rate and improved product reliability.

[0163] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A memory device, comprising: The first non-volatile memory includes resistive memory cells; as well as A controller configured to control the first non-volatile memory, in: The controller is configured to provide the first non-volatile memory with first data, a first programming command, and a first address. The controller is configured to receive second data from the first non-volatile memory in response to the first programming command, the second data being a verification read from a resistive memory cell programmed with the first data. The controller is configured to compare the first data with the second data to detect the number of faulty units. When the number of detected faulty units exceeds a reference value, the controller is configured to generate third data obtained by inverting the first data, and provide the third data to the first non-volatile memory. The first data includes the inverted flag bit. The resistive memory cell is configured to store data including a first state and a second state different from the first state. The first state has a logic value of 0, and the second state has a logic value of 1. The write error rate when data including the first state is stored in the resistive memory cell is greater than the write error rate when data including the second state is stored in the resistive memory cell.

2. The memory device according to claim 1, wherein, The resistive memory unit includes a magnetic random access memory.

3. The memory device according to claim 1, wherein: The first data includes data bits and error correction code parity bits, and The detected faulty unit includes a memory unit corresponding to the parity check bit of the error correction code.

4. The memory device according to claim 1, wherein, The controller is configured to provide the erase command and the third data together to the first non-volatile memory.

5. The memory device according to claim 1, wherein, The controller is configured to provide a verification read command for the first data to the first non-volatile memory, and to receive the second data in response to the verification read command.

6. The memory device according to claim 1, wherein: The controller is configured to provide a first read command and the first address to the first non-volatile memory. The controller is configured to receive, in response to the first read command, fourth data including the inverted flag bit from the first non-volatile memory, the fourth data being read from a resistive memory cell programmed with the third data, and The controller is configured to invert the fourth data when the logic value of the inverted flag bit of the provided fourth data is different from the logic value of the inverted flag bit of the first data.

7. The memory device according to claim 1, wherein: The controller includes an error correction code module. The controller is configured to provide the first non-volatile memory with fifth data, a second programming command, and a second address. The controller is configured to provide a second read command and the second address to the first non-volatile memory. The controller is configured to receive sixth data read from a resistive memory cell programmed with the fifth data in response to the second read command, and The error correction code module is configured to perform error correction on the sixth data to detect faulty units. When the number of detected faulty units is greater than the reference value, it generates seventh data by inverting the fifth data and provides the seventh data to the first non-volatile memory.

8. The memory device of claim 1, further comprising a second non-volatile memory different from the first non-volatile memory. in: The second non-volatile memory includes the resistive memory cell. The controller is configured to provide the first data, the third programming command, and the third address to the second non-volatile memory. The controller is configured to receive eighth data from the second non-volatile memory in response to the third programming command, the eighth data being a verification read from a resistive memory cell programmed with the first data. The controller is configured to compare the first data with the eighth data to detect the number of faulty units. The controller is configured to provide the first data to the second non-volatile memory, and The eighth data includes the inverted flag bit.

9. A memory device, comprising: A memory cell array, which includes resistive memory cells; A read / write circuit, which is connected to the memory cell array via bit lines; An address decoder is connected to the memory cell array via word lines; as well as Control logic, which is connected to the read / write circuit and the address decoder, in: The read / write circuit is connected to the controller. The read / write circuit is configured to receive first data including an inverted flag bit. The control logic is configured to receive a first programming command. The address decoder is configured to receive a first address. The read / write circuit, the control logic, and the address decoder are configured to program the resistive memory cell based on the first data, the first programming command, and the first address. The read / write circuit is configured to provide the controller with second data generated by applying a verification voltage to the bit line connected to the resistive memory cell. The read / write circuit is configured to, in response to the second data, receive third data obtained by inverting the first data from the controller when the number of faulty units detected by comparing the first data and the second data is greater than a reference value. The read / write circuit, the control logic, and the address decoder are configured to program the resistive memory cell based on the third data, the first programming command, and the first address. The resistive memory cell is configured to store data including a first state and a second state different from the first state. The first state has a logic value of 0, and the second state has a logic value of 1. The write error rate when data including the first state is stored in the resistive memory cell is greater than the write error rate when data including the second state is stored in the resistive memory cell.

10. The memory device according to claim 9, wherein, The control logic includes the controller.

11. The memory device of claim 9, further comprising a voltage generator configured to provide a first programming voltage and a second programming voltage to the address decoder. in, The magnitude of the first programming voltage used to program the resistive memory cell based on the first data is different from the magnitude of the second programming voltage used to program the resistive memory cell based on the third data.

12. The memory device according to claim 11, wherein, The power consumed when programming the resistive memory cell with the third data is greater than the power consumed when programming the resistive memory cell with the first data.

13. The memory device according to claim 9, wherein, The resistive memory unit includes a magnetic random access memory.

14. The memory device according to claim 9, wherein, The read / write circuit is configured to apply a read voltage to the bit line to receive fourth data, including the inverted flag bit, from a resistive memory cell programmed with the third data, and to provide the controller with fifth data obtained by inverting the received fourth data.

15. The memory device according to claim 14, wherein, The logical value of the inverted flag bit of the fourth data is different from the logical value of the inverted flag bit of the first data.

16. An electronic device comprising: Non-volatile memory, which includes resistive memory cells; A controller configured to control the non-volatile memory; as well as The host computer is configured to provide programming and reading commands to the controller. in: The controller is configured to provide the non-volatile memory with first data, the programming command, and an address. The controller is configured to receive second data from the non-volatile memory in response to the programming command, the second data being a verification read from a resistive memory cell programmed with the first data. The controller is configured to provide the non-volatile memory with third data obtained by inverting the first data when the number of faulty units detected by comparing the first data and the second data is greater than a reference value. The non-volatile memory is configured to program the resistive memory cell with the third data. The host is configured to provide the read command and the address to the controller. The controller is configured to provide the read command and the address to the non-volatile memory, and in response to the read command, receive fourth data obtained by reading the resistive memory cell from the non-volatile memory, and provide the host with fifth data obtained by inverting the fourth data. The first data includes the inverted flag bit. The resistive memory cell is configured to store data including a first state and a second state different from the first state. The logical value of the first state is 0, and the logical value of the second state is 1. The write error rate when data including the first state is stored in the resistive memory cell is greater than the write error rate when data including the second state is stored in the resistive memory cell.

17. The electronic device according to claim 16, wherein: The fourth data includes the inverted flag bit, and The logical value of the inverted flag bit of the first data is different from the logical value of the inverted flag bit of the fourth data.

18. The electronic device according to claim 16, wherein, The resistive memory unit includes a magnetic random access memory.

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