Preboosting scheme during programming operation in memory subsystem

Abstract

The present application relates to a preboost scheme during a programming operation in a memory subsystem. Control logic in a memory device initiates a programming operation on a memory array, the programming operation including a preboost phase that occurs prior to the programming phase. The control logic causes a first positive preboost voltage to be applied to a first plurality of word lines of a data block of the memory array during the preboost phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the programming operation. The control logic causes a second positive preboost voltage to be applied to a second plurality of word lines of the data block during the preboost phase, wherein the second plurality of word lines are adjacent to the first plurality of word lines, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage. The control logic further causes the second positive preboost voltage to be ramped down to the ground voltage before the first positive preboost voltage is ramped down to the ground voltage during the preboost phase.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to pre-boosting schemes during programming operations in memory subsystems. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] One aspect of the present disclosure provides a memory device, the memory device comprising: a memory array; and control logic operatively coupled to the memory array to perform operations comprising: initiating a programming operation on the memory array, the programming operation comprising a preboost phase occurring prior to the programming phase; causing a first positive preboost voltage to be applied to a first plurality of word lines of a data block of the memory array during the preboost phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the programming operation; causing a second positive preboost voltage to be applied to a second plurality of word lines of the data block during the preboost phase, wherein the second plurality of word lines are adjacent to the first plurality of word lines, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage; and causing the second positive preboost voltage to be ramped down to a ground voltage before the first positive preboost voltage is ramped down to the ground voltage during the preboost phase.

[0004] Another aspect of the disclosure provides a method comprising: initiating a programming operation on a memory array, the programming operation including a preboost phase occurring prior to the programming phase; causing a first positive preboost voltage to be applied to a first plurality of word lines of a data block of the memory array during the preboost phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the programming operation; causing a second positive preboost voltage to be applied to a second plurality of word lines of the data block during the preboost phase, wherein the second plurality of word lines are adjacent to the first plurality of word lines, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage; and causing the second positive preboost voltage to ramp down to a ground voltage before the first positive preboost voltage ramps down to the ground voltage during the preboost phase.

[0005] Another aspect of the present disclosure provides a memory device, the memory device comprising: a first memory cell string in a first sub-block of a memory cell block, the first sub-block comprising a selected sub-block, wherein the first memory cell string comprises a first plurality of memory cells coupled to a plurality of word lines; and a second memory cell string in a second sub-block of the memory cell block, the second sub-block comprising an unselected sub-block, wherein the second memory cell string comprises a second plurality of memory cells coupled to the plurality of word lines, wherein a first subset of the plurality of word lines is configured to receive a first positive pre-boost voltage signal during a pre-boost phase of a programming operation performed on the selected sub-block, wherein each of the first subset of the plurality of word lines is coupled to the second string of memory cells. and a second plurality of word lines configured to receive a second positive preboost voltage signal during the preboost phase, wherein the second subset of the plurality of word lines is adjacent to the first subset of the plurality of word lines, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second subset of the second plurality of memory cells in the second string, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage, and wherein the second positive preboost voltage will ramp down to the ground voltage during the preboost phase before the first positive preboost voltage ramps down to the ground voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 is a schematic diagram illustrating strings of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 is a timing diagram for operation of a memory device during a programming operation according to some embodiments of the present disclosure.

[0010] Figure 4 is a diagram illustrating the channel potential of a memory cell string during a pre-boosting phase of a programming operation according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of an example method of implementing a pre-boosting scheme during a programming operation in a memory subsystem according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Various aspects of the present disclosure are directed to a pre-boosting scheme during a programming operation in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include a high-density non-volatile memory device, where data retention is required when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Hereinafter, a data block refers to a cell of a memory device for storing data, and may include a memory cell group, a word line group, a word line, or an individual memory cell. Each data block may include several sub-blocks, each of which is defined by a set of associated pillars (e.g., vertical conductive traces) extending from a shared bit line. A memory page (also referred to herein as a "page") stores one or more bits of binary data corresponding to data received from a host system. To achieve high density, a string of memory cells in a nonvolatile memory device may be constructed to include several memory cells that at least partially surround a pillar of channel material. The memory cells may be coupled to access lines, often referred to as "word lines," that are often co-fabricated with the memory cells to form a string array in a memory block. The compactness of certain nonvolatile memory devices, such as 3D flash NAND memory, means that word lines are common to many memory cells within a memory block.

[0015] During a programming operation, a selected memory cell may be programmed by applying a programming voltage to a corresponding selected word line. Due to the word line being common to multiple memory cells, unselected memory cells may be subjected to the same programming voltage as the selected memory cells. If not otherwise preconditioned, the unselected memory cells may be affected by the programming voltage from the common word line. These programming voltage effects may include conditions where charge is stored in the unselected memory cells that are expected to maintain the stored data. This programming voltage effect is referred to as a "program disturbance" or "program disturb" effect. The program disturb effect may render the charge stored in the unselected memory cell completely unreadable, or, although still apparently readable, may read the contents of the memory cell as a data value different from the intended data value stored prior to the application of the programming voltage.

[0016] The presence of residual electrons, such as electrons trapped or otherwise left inside the polysilicon channel of the charge storage structure after an earlier operation (e.g., a previous programming operation) may contribute to a program disturb effect. At the end of a program verification operation, for example, the pass voltage (Vpass) applied to the word lines that are not being programmed is ramped down, and the word lines with high threshold voltages on the source side will be turned off before the word lines with lower threshold voltages. As a result, the electrons will be trapped inside the polysilicon channel at the word lines with lower threshold voltages (i.e., between the turned-off word lines) and become residual electrons. Because the polysilicon channel (i.e., the pillar channel region) in some non-volatile memory devices is a floating channel that may not be connected to a bulk grounded body, there is typically no path for the residual electrons in the channel region to discharge until the entire poly-Si channel reaches a new equilibrium state after some time. These residual electrons can contribute to program disturb in several ways. For example, a data word line can suffer from hot electron ("hot-e") disturbance, where a large voltage difference between the gate and source causes residual electrons to be injected from the drain depletion region into the floating gate. Additionally, this voltage difference can initiate an electrostatic field of sufficient magnitude to change the charge on the selected word line and cause the contents of the memory cell to be inadvertently programmed or incorrectly read. Furthermore, the electrostatic field can generate localized electron-hole pairs in the channel region, producing more electrons that can be injected into the selected word line.

[0017] During a programming operation on a non-volatile memory device, certain phases may be encountered, including programming, programming recovery, programming verification, and programming verification recovery. Since relatively high voltages are applied during the programming and programming verification phases, the programming recovery and programming verification recovery phases allow the device to recover from a high voltage mode to discharge internal nodes, etc. For example, a high programming voltage may be applied during the programming phase, followed by a programming recovery phase in which the nodes are discharged. Then, a verification voltage may be applied during the programming verification phase, followed by a verification recovery phase. During the recovery phase, all signals are ramped down to a certain lower voltage level. Because multiple programming operations may be performed in succession, typically, the programming verification and programming verification recovery phases of a previous programming operation are followed by the programming phase of a subsequent programming operation. The program disturb effect in a memory device is most severe during a programming operation, when a large amount of residual electrons from a previous programming operation remain on the source side of the channel (i.e., the residual electrons were not cleared during the programming verification recovery phase) and then flow to the drain side of the channel as the programming voltage is ramped up during the subsequent programming phase.

[0018] Aspects of the present disclosure address the above and other deficiencies by implementing a preboost scheme during programming operations on a memory array of a memory device in a memory subsystem. In some cases, between a program verify phase of one programming operation and a seeding phase of a subsequent programming operation, control logic in the memory device may initiate a preboost phase. Prior to the preboost phase, the control logic may cause the voltage applied to the word lines of the drain side select gate devices in the memory cell strings in the data block coupled to the memory array to be ramped down to the ground voltage after the program verify voltage applied to several data word lines is ramped down to the ground voltage at the end of the previous programming operation (e.g., program verify phase) on the memory array. This prevents any voltage present on the bit lines from flowing into the channel of the memory string and allows the channel potential at the selected word line (e.g., WLn) to reach 0V before the subsequent seeding phase. During the preboost phase, the control logic causes a first positive preboost voltage to be applied to a first set of word lines including the selected word line and any other data word lines on the drain side (e.g., closer to the bit lines), while a ground voltage or a slightly negative voltage is applied to a second set of data word lines farther down the memory string. In one embodiment, a second positive preboost voltage having a lower magnitude than the first positive preboost voltage is applied to two or more word lines between the first set of word lines and the second set of word lines. This reduces the electron barrier at those memory cells coupled to the respective word lines and forms a negative channel potential on the source side and a positive channel potential on the drain side of the selected word line (e.g., farther from the bit line), thereby allowing any residual electrons previously trapped on the source side to flow to the drain side. In one embodiment, the control logic further causes the second positive preboost voltage to ramp down to the ground voltage before the first positive preboost voltage ramps down to the ground voltage during the preboost phase. This can cause the memory cells coupled to those word lines to turn off and prevent residual electrons now on the drain side of the selected word line from flowing back to the source side. At the end of the preboost phase, the seeding phase is initiated and the select gate device is turned on, thereby allowing residual electrons to be cleared from the channel of the string via the bit line.

[0019] Advantages of the present disclosure include, but are not limited to, improved programming performance in a memory subsystem. Because the pre-boosting scheme moves most, if not all, residual electrons from the source side of the selected word line to the drain side, those electrons can be cleared from the channel during a subsequent seeding phase. Thus, when a high programming voltage is subsequently applied to the selected word line, the residual electrons are not present and are not injected into the selected word line. Accordingly, program disturb effects such as Fowler-Nordheim tunneling in a memory device can be significantly reduced.

[0020] Figure 1An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device including a memory and a processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0024] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0025] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory devices 130 may be grouped into pages that may refer to logical units of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] Although non-volatile memory components such as a 3D cross-point array of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, the memory device 130 may represent a single die with some control logic (e.g., the local media controller 135) embodied thereon. In some embodiments, one or more components of the memory subsystem 110 may be omitted.

[0036] In one embodiment, the memory device 130 includes a memory device programming management component 113 that can supervise, control and / or manage data access operations (e.g., programming operations) performed on a non-volatile memory device (e.g., memory device 130) of the memory subsystem 110. For example, a programming operation can include several phases, such as a pre-boost phase, a seeding phase, a programming phase, and a programming recovery phase. The programming management component 113 is responsible for causing specific voltages to be applied (or indicating which voltages are applied) to the memory device 130 during the programming operation. Prior to the pre-boost phase, the programming management component 113 can cause the voltage applied to the word lines of the drain side select gate devices in the strings of the memory cells in the data blocks coupled to the memory array of the memory device 130 to be ramped down to the ground voltage after the programming verification voltage applied to several data word lines was ramped down to the ground voltage at the end of the previous programming operation (e.g., the programming verification phase) on the memory array. During the preboost phase, the programming management component 113 may cause a first positive preboost voltage to be applied to a first plurality of word lines, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in a data block. The first plurality of word lines includes a selected word line associated with a programming operation. In addition, the programming management component 113 may cause a second positive preboost voltage to be applied to a second plurality of word lines of the data block during the preboost phase, wherein the second plurality of word lines are adjacent to the first plurality of word lines, and wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string of memory cells. In one embodiment, the second positive preboost voltage has a lower magnitude than the first positive preboost voltage. The programming management component 113 further causes the second positive preboost voltage to be ramped down to the ground voltage before the first positive preboost voltage is ramped down to the ground voltage during the preboost phase. In addition, the programming management component 113 can cause a third preboost voltage to be applied to a third plurality of word lines of the data block during the preboost phase, wherein the third plurality of word lines are adjacent to the second plurality of word lines, and wherein each of the third plurality of word lines is coupled to a respective memory cell of a third plurality of memory cells in the string of memory cells. In one embodiment, the third positive preboost voltage is at least one of a ground voltage or a negative voltage. Additional details regarding the operation of the programming management component 113 are described below.

[0037] In some embodiments, the memory subsystem controller 115 includes at least a portion of the programming management component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the programming management component 113 is part of the host system 120, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the programming management component 113 and is configured to perform the functionality described herein. In this embodiment, the programming management component 113 may be implemented using hardware or firmware stored on the memory device 130, which is executed by the control logic (e.g., the programming management component 113) to perform operations related to the pre-boosting scheme described herein.

[0038] Figure 2 is a schematic diagram illustrating a memory cell string 200 in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, the string 200 represents a portion of the memory device 130. The string 200 includes a number of memory cells 212 (i.e., charge storage devices), such as up to 32 memory cells (or more) in some embodiments. The string 200 includes a source-side select transistor, referred to as a source select gate 220 (SGS) (typically an n-channel transistor), coupled between the memory cells 212 at one end of the string 200 and a common source 226. The common source 226 may include, for example, a commonly doped semiconductor material and / or other conductive material. At the other end of the string 200, a drain-side select transistor referred to as a drain select gate 230 (i.e., drain-side select gate device SGD) (typically an n-channel transistor) and a gate induced drain leakage (GIDL) generator 240 (GG) (typically an n-channel transistor) are coupled between one of the memory cells 212 and a data line 234, which is commonly referred to in the art as a "bit line." The common source 226 may be coupled to a reference voltage (e.g., a ground voltage or simply "ground" [Gnd]) or a voltage source (e.g., a charge pump circuit or power supply, which may be selectively configured to a specific voltage suitable for optimizing programming operations, for example).

[0039] Each memory cell 212 may include, for example, a floating gate transistor or a charge trapping transistor, and may include a single level memory cell or a multi-level memory cell. The floating gate may be referred to as a charge storage structure 235. The memory cell 212, source select gate 220, drain select gate 230, and GIDL generator 240 may be controlled by signals on their respective control gates 250.

[0040] The control signal may be applied by or under the direction of the programming management component 113, for example, to a select line (not shown) to select a string, or to an access line (not shown) to select a memory cell 212. In some cases, the control gate may form part of a select line (for selecting a device) or an access line (for a cell). The drain select gate 230 receives a voltage that may cause the drain select gate 230 to select or deselect the string 200. In one embodiment, each respective control gate 250 is connected to a separate word line (i.e., an access line) so that each device or memory cell may be controlled individually. The string 200 may be one of a plurality of memory cell strings in a block of memory cells in the memory device 130. For example, when there are multiple memory cell strings, each memory cell 212 in the string 200 may be connected to a respective shared word line to which the respective memory cell in each of the plurality of strings is also connected. As such, if a selected memory cell in one of those multiple strings is being programmed, a corresponding unselected memory cell 212 in the string 200 connected to the same word line as the selected cell may experience the same programming voltage, thereby potentially causing a program disturb effect. Accordingly, in one embodiment, the program management component 113 causes the word line driver to apply a first positive preboost voltage to be applied to a first plurality of word lines during a preboost phase, wherein each of the first plurality of word lines is coupled to a control gate 250 of a corresponding memory cell 212 in the string 200 that includes a selected word line associated with a programming operation. The program management component 113 further causes a second positive preboost voltage to be applied to a second plurality of word lines during a preboost phase, wherein the second plurality of word lines are adjacent to the first plurality of word lines, wherein each of the second plurality of word lines is coupled to a control gate of a corresponding memory cell 212 in the string 200, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage to effectively push residual electrons from the source side to the drain side. The program management component 113 further causes the second positive preboost voltage to be ramped down to the ground voltage before the first positive preboost voltage is ramped down to the ground voltage during the preboost phase to keep the residual electrons on the drain side. Thus, most, if not all, of the residual electrons can be cleared from the channel of the string during the seeding phase so that when a high programming voltage is subsequently applied to the selected word line, the residual electrons are not present and are not injected into the selected word line.

[0041] Figure 33 is a timing diagram 300 for the operation of a memory device during a programming operation according to some embodiments of the present disclosure. During a programming operation performed on a non-volatile memory device such as memory device 130, certain phases may be encountered, including a programming verification phase 310 of a previous programming operation, pre-boost phases 320a, 320b, and 320c, and a seeding phase 330. For example, the programming operation may also include other phases not shown in timing diagram 300, such as a programming phase, or various recovery phases. Timing diagram 300 illustrates various phases of programming operation 300 according to one embodiment. In this embodiment, different signals are applied to various devices in memory device 130 in each of the phases shown. In one embodiment, programming management component 113 sends a signal to a corresponding driver (or some other component) instructing the driver to apply the associated signal.

[0042] During the program verify phase 310, a program verify voltage is applied to a word line (e.g., a selected word line WLn) to read the charge level stored at the selected memory cell to confirm that the desired value was properly programmed during the previous programming operation. In addition, a signal 301 representing the bit line voltage is applied to the bit line (BL), and a signal 302 is applied to the drain side select gate device SGD 230. The signal 302 (e.g., 7V) activates the drain side select gate device 230 (e.g., turns it "on"), thereby allowing the bit line voltage to flow from the bit line 234 through the drain side select gate device 230 to the various data word lines connected to the string 200. In one embodiment, the data word lines include one or more word lines connected to the remaining memory cells 212 of the string 200. These cells 212 are typically used to store data, such as data from the host system 120. In one embodiment, the program management component 113 may cause the signal 302 applied to the word line coupled to the drain side select gate device SGD in the string 200 to ramp down to a ground voltage (e.g., 0V) after the signal 303 representing the program verify voltage applied to the first plurality of word lines (i.e., WLn and above) and the second plurality of word lines (i.e., WLn-1 and WLn-2) ramps down to the ground voltage at the end of the previous program verify phase 310. This prevents any voltage present on the bit line from flowing into the channel of the memory string 200 and allows the channel potential at the selected word line (e.g., WLn) to reach 0V prior to the subsequent seeding phase 330. The signals 301 and 302 remain at the ground voltage during the pre-boost phases 320a, 320b, 320c.

[0043] In one embodiment, during the preboost phase 320a, the program management component 113 causes a signal 303 having a first positive preboost voltage (e.g., 4V) to be applied to a first plurality of word lines (e.g., WLn and above), including a selected word line associated with a programming operation. In one embodiment, the first plurality of word lines includes the selected word line WLn and all word lines on the drain side of the selected word line (e.g., data word lines or dummy word lines). This may include any word line between the selected word line and the bit line 234 in the memory string 200. In another embodiment, the first positive preboost voltage is only applied to a threshold number of word lines (e.g., 5 word lines, 10 word lines, etc.). Any additional word lines on the drain side of the selected word line may actually receive a ground voltage.

[0044] In addition, the programming management component 113 causes a signal 304 having a second positive pre-boost voltage (e.g., 2V) to be applied to a second plurality of word lines (e.g., WLn-1 and WLn-2) adjacent to the first plurality of word lines. The second positive pre-boost voltage is typically of a lower magnitude than the first positive pre-boost voltage, although different values ​​may be used in different implementations. This makes the channel potential gradient from the source side to the drain side less severe, thereby preventing any electron injection during the pre-boost phase 320a. In one embodiment, the same pre-boost voltage is applied to both WLn-1 and WLn-2. In another embodiment, different voltages are applied to WLn-1 (e.g., 2V) and WLn-2 (e.g., 1V). In one embodiment, the second plurality of word lines may include more than two word lines.

[0045] In one embodiment, during the preboost phase 320a, the program management component 113 further causes a signal 305 having a third preboost voltage (e.g., -1V) to be applied to a third plurality of word lines (e.g., WLn-3 and below) adjacent to the second plurality of word lines. Depending on the embodiment, the third positive preboost voltage may be at least one of a ground voltage or a negative voltage. This forms a negative channel potential on the source side of the selected word line and a positive channel potential on the drain side, thereby allowing any residual electrons previously trapped on the source side to flow to the drain side. In one embodiment, during the preboost phase 320b, the program management component 113 causes a signal 304 having a second positive preboost voltage to be ramped down to a ground voltage (e.g., 0V) before the first positive preboost voltage is ramped down. Thus, the signal 303 remains at the first positive preboost voltage during the preboost phase 320b. This may cause the memory cells coupled to WLn-1 and WLn-2 to be turned off and prevent residual electrons now on the drain side of the selected word line from flowing back to the source side.

[0046] In one embodiment, during the pre-boost phase 320c, the programming management component 113 causes the signal 303 having the first positive pre-boost voltage to ramp down to the ground voltage, and the signal 305 having the negative voltage to ramp up to the ground voltage. In another embodiment, the signal 305 remains at the ground voltage throughout the pre-boost phases 320a, 320b, 320c.

[0047] During the seeding phase 330, the program management component 113 causes a signal 301 having a seeding voltage (e.g., 3 volts) to be applied to the bit line 234 of the string 200. In one embodiment, the program management component 113 sends a signal to a bit line driver (or some other component) instructing the driver to apply the signal 301 to the bit line 234. In one embodiment, the program management component 113 causes a signal 302 having a positive voltage to be applied to the drain side select gate device 230 during the seeding phase 330, and signals 303, 304, and 305, each having a ground voltage, to be applied to the respective word lines. When the select gate devices are activated during the seeding phase 330, the residual electrons now on the drain side of the selected word line can flow out of the channel via the bit line.

[0048] Figure 4 is a diagram illustrating the channel potential 400 of a string of memory cells during a pre-boosting phase of a programming operation according to some embodiments of the present disclosure. In one embodiment, the string 200 corresponds to Figure 2 The string 200 shown in FIG. 1 and the inoculation scheme used corresponds to Figure 3300 is shown in the timing diagram 300 shown in . As described above, string 200 includes a GIDL generator (GG) device, a drain select gate (SGD) device, a number of memory cells (each connected to a separate word line (WL)), and a source select gate (SGS) device. In one embodiment, one or more of the memory cells are connected to a dummy word line layer (DWL) and are generally not used to store data. At least one of the memory cells in string 200 may be connected to a selected word line (i.e., the word line being programmed (WLn)), and each remaining memory cell on the source side of the selected word line may be connected to a word line referred to as a data word line (WLn-1, WLn-2, ​​..., WLn-17). In one embodiment, there may be one or more memory cells connected to a word line (e.g., WLn+1) on the drain side of the selected word line, which word line may be a dummy word line or a data word line. Depending on the embodiment, there may be any number of data word lines. In one embodiment, string 200 represents an unselected sub-block of a data block of memory cells of memory device 130. As described above, a data block may include additional sub-blocks having additional strings of memory cells. For example, string 450 may represent a selected sub-block of the same data block and may similarly include several memory cells and / or other devices coupled to the same word line as corresponding memory cells and / or other devices of string 200.

[0049] In one embodiment, each of the devices in string 200 has an associated threshold voltage (Vt) that represents the voltage at which each device switches from an "off" state to an "on" state (or vice versa). For example, SGD may have a threshold voltage of 3V, memory cells connected to WLn+1 and the selected word line WLn may have a threshold voltage of -2V, memory cells connected to WLn-1 and WLn-2 may have a threshold voltage of 5V, memory cells connected to WLn-3 to WLn-15 may have a threshold voltage of -1V, and memory cells connected to WLn-16 and WLn-17 may have a threshold voltage of 5V. In one embodiment, the channel potential 400 of string 200 represents the difference between the voltage applied at the control gate of each device (i.e., the gate voltage (Vg)) and a representative threshold voltage. In one embodiment, there is a first representative threshold voltage on the drain side of the selected word line (WLn), and there is a second representative threshold voltage on the source side of the selected word line (WLn). Each representative threshold voltage may be the highest threshold voltage on the drain side and the source side, respectively. Thus, in the illustrated embodiment, the first representative threshold voltage on the drain side may be -2V associated with the selected word lines WLn and WLn+1 (excluding SGD), and the second representative threshold voltage on the source side may be 5V associated with the memory devices connected to WLn-1, WLn-2, ​​WLn-16, and WLn-17. Since WLn-1 has the highest threshold voltage on the source side of the selected word line, the highest number of source side residual electrons are trapped there. This represents the worst case scenario in terms of program disturb effects, so the corresponding threshold voltages may be used as representative threshold voltages.

[0050] As mentioned above about Figure 3 As described, in one embodiment, the programming management component 113 may cause different voltage signals to be applied to the gate terminals of different devices during the pre-boost phase of the programming operation. These voltage signals may be referred to as corresponding gate voltages (Vg). Figure 4As shown in , in one embodiment, the program management component 113 can cause a first positive preboost voltage to be applied to a first plurality of word lines of the string 200, where a positive voltage can be experienced at the control gate 250 of the corresponding memory cell 212. For example, the program management component 113 can cause a first positive preboost voltage (e.g., 4V) to be applied to a selected word line (i.e., WLn) and any word lines above the selected word line in the string (e.g., WLn+1), and can cause a second positive preboost voltage (e.g., 2V) to be applied to a second plurality of word lines of the data block adjacent to the first plurality of word lines (e.g., WLn-1 and WLn-2) on the source side during the preboost phase. These positive voltages can reduce the electron barrier at the corresponding memory cell, allowing any residual electrons 420 trapped on the source side to flow through the barrier and to the drain (i.e., bit line 234). In addition, the program management component 113 can cause a third pre-boost voltage to be applied to the third plurality of word lines of the string 200 during the pre-boost phase. For example, the program management component 113 can cause a negative voltage (e.g., -1V) to be applied to the word lines WLn-3 to WLn-17. This negative voltage can effectively push the residual electrons 420 from the source side to the drain side.

[0051] Therefore, the channel potential 400 on the drain side of the selected word line (WLn) is 6V (i.e., gate voltage 4V minus the first representative threshold voltage -2V), and the channel potential 400 on the source side of the selected word line (WLn) is -6V (i.e., gate voltage -1V minus the second representative threshold voltage 5V). Therefore, the difference in channel potential 400 from the drain side to the source side is -12V. It should be noted that if a ground voltage (0V) is applied on the word lines, the drain side channel potential will be 2V, the source side channel potential will be -5V, and the difference will only be -7V. Therefore, applying positive voltages to certain word lines and negative voltages to other word lines increases the potential gradient between the drain side and the source side of the selected word line (WLn). Because the source side of the selected word line (WLn) has a lower channel potential, the residual electrons 420 trapped on the source side tend to flow toward the drain side during the pre-boost phase and flow through the lowered potential barriers at WLn-1 and WLn-2, ​​where they can be cleared via the bit line 234 once SGD is activated during the seeding phase. In the worst case mode, the electron barrier on WLn-1 and WLn-2 seen by the residual electrons 420 is 5V in a conventional seeding scheme and can be reduced to less than 2V using the techniques described herein. This indicates that more than 60% of the residual electrons can be cleared during the seeding phase, and therefore, program disturb from hot electron injection during the programming phase can also be expected to be reduced by approximately 60%.

[0052] Figure 5is a flow chart of an example method for implementing a pre-boosting scheme during a programming operation in a memory subsystem according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by Figure 1 The programming management component 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] At operation 505, the previous programming operation ends. For example, at the end of the previous programming operation, once a program verify phase occurs in which the results of the previous programming operation are confirmed (e.g., read), the processing logic may ramp down various voltages applied to the word lines of the memory string 200 in anticipation of the start of a subsequent programming operation. In one embodiment, the processing logic causes the voltage applied to the word line coupled to the drain side select gate devices (SGD) in the string 200 of memory cells 212 to be ramped down to a ground voltage (e.g., 0V) after the program verify voltage applied to the first plurality of word lines (e.g., WLn and WLn+1) and the second plurality of word lines (e.g., WLn-1 and WLn-2) are ramped down to a ground voltage at the end of the previous programming operation.

[0054] At operation 510, a subsequent programming operation is initiated. For example, processing logic (e.g., processor 117 or local media controller 135) may initiate a programming operation on a memory device (e.g., memory device 130). In one embodiment, the programming operation includes a pre-boost phase, a seeding phase, a programming phase, and a programming verification phase. In certain embodiments, each of these phases may be repeated multiple times in a cycle during a single programming operation. The seeding phase typically includes a global boosting of the channel voltage of the inhibited strings in the memory device 130 in an attempt to counteract program disturbances resulting from the use of high voltage programming pulses. During the programming phase, a programming voltage is applied to a selected word line (e.g., WLn) of the memory device 130 in order to program a specific charge level representing a desired value to a selected memory cell on the word line. During the programming verification phase, a programming verification voltage is applied to the selected word line in order to read the charge level programmed during the programming phase and verify that it is correct. However, prior to those phases, a pre-boost phase may be performed, as described below.

[0055] At operation 515, a first positive preboost voltage is applied to a particular word line. For example, processing logic may cause a first positive preboost voltage to be applied to a first plurality of word lines of a data block of a memory array during a preboost phase, wherein each of the first plurality of word lines is coupled to a respective memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with a programming operation. In one embodiment, program management component 113 may cause a first positive preboost voltage (e.g., 4V) to be applied to particular word lines (e.g., WLn and WLn+1) of string 200 during preboost phase 320a, wherein the voltage may be experienced at control gate 250 of respective memory cell 212. The first positive preboost voltage may form a positive channel potential on the drain side of the selected word line.

[0056] At operation 520, a second positive preboost voltage is applied to specific word lines. For example, processing logic may cause a second positive preboost voltage to be applied to a second plurality of word lines of a data block during a preboost phase, wherein the second plurality of word lines are adjacent to the first plurality of word lines, wherein each of the second plurality of word lines is coupled to a respective memory cell of a second plurality of memory cells in a string of memory cells, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage. In one embodiment, program management component 113 may cause a second positive preboost voltage (e.g., 2V) to be applied to specific word lines (e.g., WLn-1 and WLn-2) of string 200 during preboost phase 320a, wherein the voltage may be experienced at control gates 250 of respective memory cells 212. The second positive preboost voltage may reduce the electron barrier at those specific word lines, thereby allowing any residual electrons trapped on the source side to flow through the barrier and to the drain (i.e., bit line 234). Generally, the second positive pre-boost voltage is less than the first positive pre-boost voltage. For example, in the embodiment shown in the timing diagram 300, the second positive pre-boost voltage is 2V.

[0057] At operation 525, a negative voltage or a ground voltage is applied to other word lines. For example, processing logic may cause a third preboost voltage to be applied to a third plurality of word lines of a data block during a preboost phase, wherein the third plurality of word lines are adjacent to the second plurality of word lines, wherein each of the third plurality of word lines is coupled to a respective memory cell of a third plurality of memory cells in a string of memory cells, and wherein the third positive preboost voltage comprises at least one of a ground voltage or a negative voltage. For example, in the embodiment shown in timing diagram 300, programming management component 113 causes a negative voltage (e.g., -1V) to be applied to WLn-3 to WLn-17. In other embodiments, programming management component 113 causes a ground voltage (i.e., 0V) to be applied to WLn-3 to WLn-17. This negative voltage or ground voltage may form a negative channel potential on the source side of the selected word line, which may effectively push residual electrons from the source side to the drain side.

[0058] At operation 530, the preboost voltage is ramped down. For example, processing logic may cause the second positive preboost voltage to be ramped down to the ground voltage before the first positive preboost voltage is ramped down to the ground voltage during the preboost phase. In one embodiment, the programming management component 113 causes the second positive preboost voltage to be ramped down during the preboost phase 320b, while the first positive preboost voltage is not ramped down until the preboost phase 320c. This may cause the memory cells 212 coupled to the word lines WLn-1 and WLn-2 to be turned off and prevent the residual electrons 420 now on the drain side of the selected word line WLn from flowing back to the source side. At the end of the preboost phase 320c, the seeding phase 330 is initiated and the select gate device (e.g., SGD) is turned on, allowing the residual electrons 420 to be cleared from the channel of the string via the bit line 234.

[0059] In one embodiment, the programming management component 113 may selectively implement the pre-boost phase described above only in certain circumstances. Otherwise, a subsequent programming operation may begin with an inoculation phase without the pre-boost phase having occurred. Thus, the programming management component 113 may perform a pre-boost phase only during a specific programming operation or during a specific iteration of a single programming operation. For example, a programming operation may include a plurality of inoculation phases, a programming phase, and a programming verification phase that are repeated sequentially. In one embodiment, the pre-boost phase is implemented only before a subset of the plurality of inoculation phases that occur after a threshold number of the plurality of programming phases have occurred. For example, if the threshold is four, the pre-boost phase will not occur before the first four inoculation phases, but will occur before any inoculation phase thereafter. In another embodiment, if the total number of inoculation phases to be performed is known in advance, the programming management component 113 may cause the pre-boost phase to be performed only during the last few inoculation phases (e.g., during the last five inoculation phases).

[0060] Figure 6 An example machine of computer system 600 is shown, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the embodiment of the present invention may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a client-server network environment.

[0061] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is illustrated, the term "machine" should also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0062] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0063] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 602 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate via a network 620.

[0064] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, in whole or in part, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0065] In one embodiment, the instructions 626 include instructions for implementing the Figure 1 The functional instructions of the programming management component 113 of the present invention. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding an instruction set for machine execution and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should accordingly be understood to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0066] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that leads to a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Mainly for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0067] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0068] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0069] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0070] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, and the instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory component, etc.

[0071] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A memory device, comprising: Memory array; as well as control logic operatively coupled to the memory array to perform operations including: initiating a programming operation on the memory array, the programming operation including a pre-boosting phase occurring prior to a programming phase; causing a first positive preboost voltage to be applied to a first plurality of word lines of a data block of the memory array during the preboost phase, wherein each of the first plurality of word lines is coupled to a respective memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the programming operation; causing a second positive preboost voltage to be applied to a second plurality of word lines of the data block during the preboost phase, wherein the second plurality of word lines are adjacent to the first plurality of word lines, wherein each of the second plurality of word lines is coupled to a respective memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage; as well as The second positive pre-boost voltage is caused to ramp down to the ground voltage before the first positive pre-boost voltage ramps down to the ground voltage during the pre-boost stage.

2. The memory device of claim 1 , wherein the selected word line is coupled to a first memory cell of the first plurality of memory cells, and wherein causing the first positive pre-boost voltage to be applied to the first plurality of word lines comprises: The first positive pre-boost voltage is caused to be applied to the first plurality of word lines coupled to the first plurality of memory cells on the drain side of the first memory cell in the string of memory cells.

3. The memory device of claim 2, wherein the first plurality of word lines comprises one or more word lines coupled to a threshold number of the first plurality of memory cells on a drain side of the first memory cell in the string of memory cells.

4. The memory device of claim 2, wherein causing the second positive pre-boost voltage to be applied to the second plurality of word lines comprises: The second positive pre-boost voltage is caused to be applied to the second plurality of word lines coupled to the second plurality of memory cells on a source side of the first memory cell in the string of memory cells.

5. The memory device of claim 1 , wherein the control logic is to perform further operations comprising: A plurality of positive pre-boosting voltages are caused to be respectively applied to the second plurality of word lines, each of the plurality of positive pre-boosting voltages having a different magnitude.

6. The memory device of claim 1 , wherein the control logic is to perform further operations comprising: Causes a voltage applied to word lines coupled to drain side select gate devices in the memory cell string to be ramped down to the ground voltage after a program verify voltage applied to the first and second word lines is ramped down to the ground voltage at the end of a previous programming operation on the memory array.

7. The memory device of claim 1 , wherein the control logic is to perform further operations comprising: causing a third preboost voltage to be applied to a third plurality of word lines of the data block during the preboost phase, wherein the third plurality of word lines are adjacent to the second plurality of word lines, wherein each of the third plurality of word lines is coupled to a respective memory cell of a third plurality of memory cells in the string of memory cells, and wherein the third preboost voltage comprises at least one of the ground voltage or a negative voltage.

8. The memory device of claim 1, wherein the programming operation comprises a plurality of programming phases, and wherein the control logic initiates the preboost phase only before a subset of the plurality of programming phases that occurs after a threshold number of the plurality of programming phases have occurred.

9. A method comprising: initiating a programming operation on a memory array, the programming operation including a pre-boosting phase occurring prior to a programming phase; causing a first positive preboost voltage to be applied to a first plurality of word lines of a data block of the memory array during the preboost phase, wherein each of the first plurality of word lines is coupled to a respective memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the programming operation; causing a second positive preboost voltage to be applied to a second plurality of word lines of the data block during the preboost phase, wherein the second plurality of word lines are adjacent to the first plurality of word lines, wherein each of the second plurality of word lines is coupled to a respective memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage; as well as The second positive pre-boost voltage is caused to ramp down to the ground voltage before the first positive pre-boost voltage ramps down to the ground voltage during the pre-boost stage.

10. The method of claim 9, wherein the selected word line is coupled to a first memory cell of the first plurality of memory cells, and wherein causing the first positive pre-boost voltage to be applied to the first plurality of word lines comprises: The first positive pre-boost voltage is caused to be applied to the first plurality of word lines coupled to the first plurality of memory cells on the drain side of the first memory cell in the string of memory cells.

11. The method of claim 10, wherein the first plurality of word lines comprises one or more word lines coupled to a threshold number of the first plurality of memory cells on a drain side of the first memory cell in the string of memory cells.

12. The method of claim 10, wherein causing the second positive pre-boost voltage to be applied to the second plurality of word lines comprises: The second positive pre-boost voltage is caused to be applied to the second plurality of word lines coupled to the second plurality of memory cells on a source side of the first memory cell in the string of memory cells.

13. The method according to claim 9, further comprising: A plurality of positive pre-boosting voltages are caused to be respectively applied to the second plurality of word lines, each of the plurality of positive pre-boosting voltages having a different magnitude.

14. The method according to claim 9, further comprising: Causes a voltage applied to word lines coupled to drain side select gate devices in the memory cell string to be ramped down to the ground voltage after a program verify voltage applied to the first and second word lines is ramped down to the ground voltage at the end of a previous programming operation on the memory array.

15. The method according to claim 9, further comprising: causing a third preboost voltage to be applied to a third plurality of word lines of the data block during the preboost phase, wherein the third plurality of word lines are adjacent to the second plurality of word lines, wherein each of the third plurality of word lines is coupled to a respective memory cell of a third plurality of memory cells in the string of memory cells, and wherein the third preboost voltage comprises at least one of the ground voltage or a negative voltage.

16. The method of claim 9, wherein the programming operation comprises a plurality of programming phases, and wherein the pre-boost phase is initiated only before a subset of the plurality of programming phases that occur after a threshold number of the plurality of programming phases have occurred.

17. A memory device comprising: a first memory cell string in a first sub-block of a memory cell block, the first sub-block comprising a selected sub-block, wherein the first memory cell string comprises a first plurality of memory cells coupled to a plurality of word lines; and a second memory cell string in a second sub-block of the memory cell block, the second sub-block comprising unselected sub-blocks, wherein the second memory cell string comprises a second plurality of memory cells coupled to the plurality of word lines, wherein a first subset of the plurality of word lines is configured to receive a first positive preboost voltage signal during a preboost phase of a programming operation performed on the selected sub-block, wherein each of the first subset of the plurality of word lines is coupled to a respective memory cell of a first subset of the second plurality of memory cells in the second string of memory cells, the first subset of the plurality of word lines comprising a selected word line associated with the programming operation, wherein a second subset of the plurality of word lines is configured to receive a second positive preboost voltage signal during the preboost phase, wherein the second subset of the plurality of word lines is adjacent to the first subset of the plurality of word lines, wherein each of the second plurality of word lines is coupled to a respective memory cell of a second subset of the second plurality of memory cells in the second memory cell string, and wherein the second positive preboost voltage has a lower magnitude than the first positive preboost voltage, and The second positive pre-boost voltage will ramp down to the ground voltage during the pre-boost phase before the first positive pre-boost voltage ramps down to the ground voltage.

18. The memory device of claim 17, wherein the selected word line is coupled to a first memory cell of the first subset of the plurality of memory cells, and wherein the first subset of the plurality of memory cells comprises one or more memory cells on the drain side of the first memory cell in the second string of memory cells.

19. The memory device of claim 18, wherein the second subset of the plurality of memory cells comprises two or more memory cells on a source side of the first memory cell in the string of memory cells.

20. A memory device according to claim 17, wherein the second memory cell string includes a drain side selection gate device coupled to a word line, and the word line is configured to receive a voltage signal that is ramped down to the ground voltage after the programming verification voltage applied to the first subset of the multiple word lines and the second subset of the multiple word lines is ramped down to the ground voltage at the end of a previous programming operation.

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