Fast replication via controller

Abstract

A device, controller, and system for storing data for rapid copying via a controller, wherein the modification and subsequent encoding affects only a small portion of the metadata associated with the copied data. By modifying and re-encoding only this small portion of the metadata, a small portion of the parity data of the copied data needs to be updated. In embodiments where there are no errors in the read data to be copied (e.g., from the SLC portion of the NAND), the decoding, modification, and encoding can be performed in parallel. Because such a small number of metadata bits are modified, in some embodiments, all possible codewords for the parity bits can be pre-determined and combined (e.g., by XOR) to update the metadata parity bits.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to replicating data within a NAND array, and more particularly to encoding the replicated data. Background Art

[0002] In solid-state drives (SSDs), copying data from one location to another is a common operation for data folding, garbage collection, read grooming, and similar operations. To perform the copy, SSDs typically employ on-chip copying, which copies from one location in the NAND to another without going through a controller, or copy through controller (CTC), which copies the data to the SSD controller and writes to the new location.

[0003] In CTC, data is typically decoded, edited, re-encoded, and then copied back to NAND. CTC is a complex and expensive (i.e., in terms of time and power) operation. For many CTC operations, the host data being copied remains unedited; only the metadata associated with the host data being copied is modified. However, in previous methods, although only a small portion of the total data is manipulated, all data (i.e., host data and metadata) is decoded and re-encoded, and the only benefit is the movement of data. Because so little data is usefully re-encoded (i.e., metadata), decoding and re-encoding all data wastes valuable time and processing resources that could have been used for more valuable operations.

[0004] Systems and methods are needed to address the shortcomings of previous approaches in order to more efficiently decode and encode data in a manner that uses less time and power than previous approaches. Summary of the invention

[0005] The present disclosure is generally directed to methods and systems for CTC data copy operations, where the modification and subsequent encoding affects only a small portion of the metadata associated with the copied data. By modifying and re-encoding only this small portion of the metadata, a small portion of the parity data of the copied data needs to be updated. In embodiments where there are no errors in the read data to be copied (e.g., from the SLC portion of the NAND), the decoding, modification, and encoding can be performed in parallel. Because such a small number of metadata bits are modified, in some embodiments, all possible codewords for the parity bits can be pre-determined and combined (e.g., by XOR) to update the metadata parity bits.

[0006] In one embodiment, a data storage device is disclosed, comprising one or more memory devices and a controller configured to perform a method for encoding data. In an embodiment, the method comprises receiving data from the one or more memory devices, the data comprising parity check matrix data and stored data; modifying a portion of the parity check matrix data corresponding to metadata associated with the data; and encoding the stored data with the modified parity check matrix data.

[0007] In another embodiment, a controller for a data storage device is disclosed, comprising an I / O to one or more memory devices, and a processor configured to perform a method for encoding data. In an embodiment, the method comprises receiving a request to move a portion of data, the portion of data comprising data and metadata comprising a first variable and a last variable; retrieving the portion of data; modifying the last variable; and writing the portion of data to the one or more memory devices.

[0008] In another embodiment, a system for storing data is disclosed, the system comprising one or more memory components, and a controller component configured to implement a method for encoding data. In an embodiment, the method comprises reading a data segment from the one or more memory components, wherein the data segment comprises metadata and data, the metadata comprising a beginning and an end; modifying a portion of the metadata adjacent to the end of the metadata; and writing the data segment to the one or more memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order that the above-mentioned features of the present disclosure may be understood in detail, a more specific description of the present disclosure briefly summarized above may be understood by reference to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and are therefore not to be considered as limiting the scope of the present disclosure, as the present disclosure may admit that other equally effective embodiments exist.

[0010] Figure 1 Depicted is a schematic block diagram showing a storage system having a storage device that can function as a storage device for a host device, in accordance with one or more techniques of this disclosure.

[0011] Figure 2 Depicted is a graph showing the cascading effect of computing parity bits for metadata in accordance with a disclosed embodiment.

[0012] Figure 3 Depicted is a graph describing the re-encoding process with respect to time in accordance with a disclosed embodiment.

[0013] Figure 4Depicted is a graph showing calculation of parity bits for changed portions of metadata in accordance with disclosed embodiments.

[0014] Figure 5 Depicted is a graph depicting an improved re-encoding process with respect to time in accordance with the disclosed embodiments.

[0015] Figure 6 Depicted is a graph describing an opportunistic re-encoding process with respect to time in accordance with a disclosed embodiment.

[0016] Figure 7 Depicted is a graph depicting an improved re-encoding process utilizing parallel operations with respect to time in accordance with the disclosed embodiments.

[0017] Figure 8 A method of encoding data according to the disclosed embodiments is described.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0019] Hereinafter, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. In fact, it is contemplated that any combination of the following features and elements (regardless of whether they are related to different embodiments) is used to implement and practice the present disclosure. In addition, although the embodiments of the present disclosure may achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a particular advantage is achieved by a given embodiment does not limit the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative and are not considered to be elements or limitations of the appended claims unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a generalization of any inventive subject matter disclosed herein, and should not be considered to be an element or limitation of the appended claims unless explicitly stated in the claims.

[0020] The present disclosure is generally directed to methods and systems such that modification and subsequent encoding in a CTC data copy operation affects only a small portion of the metadata associated with the copied data. By modifying and re-encoding only this small portion of the metadata, a small portion of the parity data of the copied data needs to be updated. In embodiments where there are no errors in the read data to be copied (e.g., from the SLC portion of the NAND), decoding, modification, and encoding can be performed in parallel. Because such a small number of metadata bits are modified, in some embodiments, all possible codewords for the parity bits can be pre-determined and combined (e.g., by XOR) to update the metadata parity bits.

[0021] Figure 1 1 is a schematic block diagram illustrating a storage system 100 in accordance with one or more techniques of this disclosure, wherein a data storage device 106 can act as a storage device for a host device 104. For example, the host device 104 can utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138. In some examples, the storage system 100 can include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 can include multiple data storage devices 106 configured as an inexpensive / redundant array of independent disks (RAID), which together act as a large-capacity storage device for the host device 104.

[0022] The storage system 100 includes a host device 104 that can store data to and / or retrieve data from one or more storage devices, such as data storage device 106. Figure 1 , host device 104 may communicate with data storage device 106 via interface 114. Host device 104 may include any of a wide range of devices, including computer servers, network attached storage (NAS) units, desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, telephone handsets such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, and the like.

[0023] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, a volatile memory 112, an interface 114, and a write buffer 116. In some examples, the data storage device 106 may include Figure 1106 for clarity. For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached and the printed circuit board includes conductive traces or the like that electrically interconnect the components of the data storage device 106. In some examples, the physical size and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some example standard form factors include (but are not limited to) 3.5" data storage device (e.g., HDD or SSD), 2.5" data storage device, 1.8" data storage device, peripheral component interconnect (PCI), PCI extension (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device 106 may be directly coupled (e.g., directly soldered) to a motherboard of the host device 104.

[0024] The interface 114 of the data storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), or the like. The electrical connection of the interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of interface 114 may also permit data storage device 106 to receive power from host device 104. Figure 1 As shown in , power supply 111 may receive power from host device 104 via interface 114 .

[0025] The data storage device 106 includes an NVM 110, which may include a plurality of memory devices or memory cells. The NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of the NVM 110 may receive data and a message indicating that the memory cell stores data from the controller 108. Similarly, a memory cell of the NVM 110 may receive a message indicating that the memory cell retrieves data from the controller 108. In some instances, each of the memory cells may be referred to as a die. In some instances, a single physical chip may include a plurality of dies (i.e., a plurality of memory cells). In some instances, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0026] In some examples, each memory cell of NVM 110 may include any type of nonvolatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of nonvolatile memory device.

[0027] NVM 110 may include multiple flash memory devices or memory cells. Flash memory devices may include NAND or NOR based flash memory devices, and may store data based on the charge contained in the floating gate of the transistor for each flash memory cell. In NAND flash memory devices, the flash memory device may be divided into multiple blocks that may be divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NAND cells. The rows of NAND cells may be electrically connected using word lines to define one page of multiple pages. The corresponding cells in each of the multiple pages may be electrically connected to the corresponding bit lines. In addition, the NAND flash memory device may be a 2D or 3D device, and may be a single-level cell (SLC), a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). The controller 108 may write data to the NAND flash memory device at the page level and read data from the NAND flash memory device at the page level, and erase data from the NAND flash memory device at the block level.

[0028] The data storage device 106 includes a power supply 111, which can provide power to one or more components of the data storage device 106. When operating in standard mode, the power supply 111 can use power provided by an external device such as the host device 104 to provide power to the one or more components. For example, the power supply 111 can use power received from the host device 104 via the interface 114 to provide power to the one or more components. In some examples, the power supply 111 may include one or more power storage components configured to provide power to the one or more components when operating in the shutdown mode (e.g., when power is stopped from being received from the external device). In this way, the power supply 111 can act as an onboard backup power supply. Some examples of the one or more power storage components include (but are not limited to) capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that the one or more power storage components can store can vary with the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, when the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0029] The data storage device 106 also includes a volatile memory 112 that can be used by the controller 108 to store information. The volatile memory 112 can include one or more volatile memory devices. In some examples, the controller 108 can use the volatile memory 112 as a cache memory. For example, the controller 108 can store cached information in the volatile memory 112 until the cached information is written to the non-volatile memory 110. Figure 1 As shown in , volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)).

[0030] The data storage device 106 includes a controller 108 that can manage one or more operations of the data storage device 106. For example, the controller 108 can manage data reading from and / or data writing to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110.

[0031] The data storage device 106 includes a low-density parity-check code (LDPC) encoder 118 and an LDPC decoder 120. The LDPC encoder 118 and the LDPC decoder 120 may each include an internal memory to store several matrices including multiple error correction codes (ECCs), wherein the internal memory of the LDPC encoder 118 and the LDPC decoder 120 are the same. The one or more matrices of the internal memory of the LDPC encoder 118 and the LDPC decoder 120 may allow for fast switching between matrices to avoid any firmware (FW) intervention or performance loss due to the time to switch between matrices. In the description herein, the LDPC encoder 118 may handle encoding operations, and the LDPC decoder 120 may handle decoding operations.

[0032] Figure 2 1 is a graph showing the cascading effect of computing parity bits of metadata according to the disclosed embodiments. Each point represents a data bit, such as host data (e.g., user data), metadata, and parity data. The host data can be from a host (e.g., Figure 1 host 104) which is programmed into, for example, Figure 1 The NVM of the data storage device 106 or the like (e.g., Figure 1The one or more flash management units (FMUs) in the NVM 110 may each be approximately 4,096B of physical memory. Each of the one or more FMUs may be further segmented into logical block addresses (LBAs), wherein each LBA may be approximately 512B of physical memory. In addition, a flash translation layer (FTL) of the data storage device may logically store the physical location of each of the plurality of LBAs and / or each of the plurality of FMUs to easily access the associated memory location in the data storage device. In some embodiments, host data may be programmed into the MRAM. The listed memory locations are not intended to be limiting, but rather provide examples of possible embodiments. Each FMU may also include metadata and parity data.

[0033] The controller generates metadata, such as a firmware header, scrambling seed, cyclic redundancy check (CRC), and FTL management information, for each FMU programmed into the NVM. In the description herein, for exemplary purposes, the FMU may be described as a codeword. Compared to host data, the size of metadata may be significantly smaller, such as about a few dozen bytes per 4KB of host data. In addition, when host data and metadata are passed to the controller (e.g., Figure 1 When the host data and metadata are transmitted to the controller 108, the host data and metadata may be passed through a parity check engine (e.g., an exclusive OR (XOR) engine) to generate parity check data. The parity check data may be used to correct an associated failed codeword, where the failed codeword contains one or more bit errors. The parity check data may be encoded using a diagonal or semi-diagonal parity check matrix, such as Figure 2 . In the diagonal parity check matrix shown in. In a diagonal or semi-diagonal parity check matrix, each group of parity check equations depends on the parity check equations of the previous group. For example, by changing the position (for example, top position 202) connected to the top variable, each subsequent parity check bit is affected. Each affected parity check bit is shown by the bold outline of the position. The matrix listed is not intended to be restrictive, but provides an example of a possible embodiment. In one embodiment, the first matrix or H matrix can be used for decoding, and the second matrix or G matrix can be used for encoding. Because the H matrix is ​​more sparse than the G matrix, the manipulation of the H matrix may be more feasible. Therefore, the LDPC code can be designed to operate the H matrix column by column, so that the LDPC code can change the one or more columns from the last column of the H matrix, rather than starting to make changes from the first column of the H matrix and all / most of the columns after the first column as in the previous method. By only starting to make changes from the last column of the H matrix, the change to the code word can be reduced to a minimum.

[0034] Common examples of flash management operations are folding, garbage collection, and memory cleaning. The listed flash management operations are not intended to be limiting, but rather provide examples of possible embodiments. Folding may include writing data to SLC memory, copying one or more SLC data to a controller, and programming the one or more SLC data to MLC memory, TLC memory, or QLC memory. Garbage collection may include writing related data (e.g., current data) from a block of NAND to a controller, deallocating the related block, and programming the related data to another block of NAND. Garbage collection may free up space in the NAND that is utilized by obsolete data and recover available memory space. Memory cleaning may include decoding data from a block of NAND at a controller, correcting any bit errors in the decoded data using an error correction code (ECC), encoding the corrected data, and programming the encoded data to the related block of NAND.

[0035] In order to copy data from one location in a NAND array (e.g., a first erase block of a first die) to another location in the NAND array (e.g., a first erase block of a second die), during a flash management operation, the data may be passed to a controller before being programmed to the other location in the NAND array. In other words, the flash management operation may be referred to as copy via controller (CTC). In another embodiment, data may be copied from a first type of memory cell including SLC, MLC, TLC, and QLC to a second type of memory cell including SLC, MLC, TLC, and QLC. Other iterations of memory cells are contemplated and may be applicable to the disclosed embodiments. When data is copied from one location in the NAND array to another location in the NAND array via the controller, bit errors may be corrected and not propagated to the copied data that is programmed to the other location in the NAND array.

[0036] Figure 3 is a graph describing a recoding process with respect to time according to the disclosed embodiment. At time A, a flash management operation of a controller of a storage device is started. The relevant one or more codewords are passed from one or more blocks of NAND to the controller. The one or more codewords are decoded by a decoder of the controller.

[0037] At time B, the one or more codewords are successfully decoded and the controller begins editing the one or more codewords. Editing the one or more codewords may include garbage collection operations, memory defragmentation, etc. The editing operation may affect metadata without affecting host data. In addition, the location of the metadata in each codeword may be fixed.

[0038] After successfully editing the one or more codewords, the plurality of parity data are re-encoded into the codewords at time C. When encoding the plurality of parity data into the one or more codewords, using, for example, Figure 2 Each set of parity check data of the one or more codewords is encoded using a diagonal or semi-diagonal parity check matrix such as the diagonal parity check matrix shown in . In the diagonal or semi-diagonal parity check matrix, each set of parity check equations depends on the parity check equations of the previous set.

[0039] Figure 4 is a graph illustrating calculation of parity bits of a changed portion of metadata according to the disclosed embodiments. Figure 4 The aspects can be similar to Figure 2 The embodiment described in . Aspects of LDPC codes can be designed to include fast coding segments to correspond to the same equations where the last parity check variables are connected. For example, the fast coding segments may be subject to Figure 4 The location of the metadata shown in FIG.

[0040] LDPC codes can edit the last bit of the metadata so that changes to the parity bit matrix are minimized. Therefore, when re-encoding the one or more codewords, most of the parity bits in the matrix are unchanged, and only the changed parity bits in the matrix need to be re-encoded. For example, because the parity check equation is connected to the last parity check variable, most of the parity check bits may not change when editing the metadata. The modified portion of the parity check data may include a trailing portion of the parity check data. Figure 4 In the example, the parity bits with a bold outline may be the only parity bits of the plurality of parity bits that need to be recalculated. In addition, the encoding process may encode only the portion of the stored data that is related to the trailing portion of the parity data. Since there are fewer parity bits that have changed, the editing process and the encoding process may be faster.

[0041] Figure 5 is a graph depicting an improved re-encoding process with respect to time according to the disclosed embodiments. Figure 4 Aspects applicable to Figure 5 In addition, process 1 can be represented by Figure 3 Process 2 can be represented by Figure 4 The embodiments described in .

[0042] Regarding process 2, at time A, a flash management operation of a controller of a storage device is started. The relevant one or more codewords are passed from one or more blocks of NAND to the controller. In one embodiment, the one or more blocks are from SLC memory. The one or more codewords are decoded by a decoder of the controller.

[0043] Regarding process 2, at time B, the one or more code words are successfully decoded and the controller begins editing the one or more code words. Editing the one or more code words may include garbage collection operations, memory tidying, etc. The editing operation may affect metadata without affecting host data. In addition, the location of the metadata in each code word may be fixed. Because the fast encoding segment of the LDPC code affects the parity check equation associated with the last parity check variable, the editing process of the one or more code words ends at time C, and the process 2 editing process ends before the process 1 editing process, wherein the process 1 editing process is completed at time C'.

[0044] With respect to process 2, at time C, a portion of the stored data associated with the trailing portion of the parity data is encoded. Because most of the parity bits remain unchanged, the encoding process may only affect the parity bits that have been changed or updated. Since there are few parity bits to be encoded, the encoding process ends at time D. In various embodiments, the encoded one or more codewords may be programmed into an SLC memory, an MLC memory, a TLC memory, or a QLC memory. In one embodiment, the encoding time may be shortened by approximately 50% to approximately 75%. When process 2 ends at time D, process 1 is still encoding the multiple parity bits. Therefore, the gain of process 2 may be the time between time D and time E.

[0045] Figure 6 is a graph depicting an opportunistic re-encoding process with respect to time according to the disclosed embodiments. Figure 4 Aspects applicable to Figure 6 In addition, process 1 can be represented by Figure 3 Flow 2 describes the opportunistic re-encoding process for flash management operations (eg, folding).

[0046] At time A, a flash management operation of a controller of a storage device is started. The relevant one or more codewords are passed from one or more blocks of NAND to the controller. In one embodiment, the one or more blocks are from SLC memory. Referring to flow 1, the one or more codewords are decoded by a decoder of the controller. Referring to flow 2, when decoding the one or more codewords, the controller performs an editing process and an encoding process in parallel with the decoding. Because programming to SLC memory typically exhibits little or zero flip bit counts (FBC), programming to SLC memory typically does not cause errors. Therefore, decoding of the data may not be required.

[0047] Thus, the opportunistic editing and encoding process (wherein the data is first edited and then encoded) and the decoding process can be started simultaneously at time A. If an error or flipped bit is found during the decoding process of process 1, the opportunistic process 2 is stopped and the process of process 1 is continued. During process 2, the LDPC code can edit the last bit of the metadata so that the change to the parity bit is minimized. Therefore, when re-encoding the one or more code words, most of the parity bits are unchanged, and only the parity bits that have been changed need to be re-encoded. The potential time gain in the case where no error is found by utilizing the opportunistic parallel editing and encoding process during the decoding process of process 1 is from about time B to about time D. In one embodiment, the encoding operation delay can be avoided because the encoding operation is performed in parallel with the decoding operation.

[0048] Figure 7 is a graph depicting an improved re-encoding process with respect to time utilizing parallel decoding and encoding operations in accordance with the disclosed embodiments. Figure 4 Aspects applicable to Figure 7 In addition, process 1 can be represented by Figure 3 Flow 2 describes the parallel encoding and decoding process of the flash management operation.

[0049] Regarding process 2, at time A, the flash management operation of the controller of the storage device is started. The relevant one or more code words are transferred from one or more blocks of NAND to the controller. In one embodiment, the one or more blocks are from SLC memory. The LDPC code can edit the last bit of the metadata so that the change to the parity bit is minimized. Therefore, when re-encoding the one or more code words, most of the parity bits in the matrix remain unchanged, and only the parity bits that have changed need to be re-encoded. When the controller decodes the one or more code words, the controller uses the linear characteristics of LDPC to combine two or more LDPC code words to form a legal code word. The controller can generate a subset of the multiple legal code words, each of which can represent a single bit change. For example, if 8 bits change, the controller can generate a subset of 8 legal code words, each of which reflects one of the 8 bits that changed. The subsets of 8 legal code words can each be a candidate for encoding parity. Multiple forms of parity matrix data are used to calculate each of the subsets of the multiple legal code words.

[0050] With regard to process 2, at time B, the decoding of the one or more codewords and the generation of the subgroups of the multiple codewords are all completed. At time B, the decoded codeword is combined with each of the coding parity check candidates. In one embodiment, two or more parity check candidates may be selected and combined. For example, in the case of 8 coding parity check candidates, there are about 256 combinations of the decoded codewords and coding parity check candidates combined. In about 256 combinations, the one or more coding parity check candidates containing the coefficient 1 reflecting the change relative to the original data are combined with the original decoded parity check data using the XOR function due to the linear characteristics of the LDPC. The resulting XOR parity check data is the coded parity check data of the relevant part (i.e., the edited data bit). The potential time gain generated by utilizing parallel decoding and encoding operations is the time from about time C to about time D. In one embodiment, the coding operation delay can be avoided because the coding operation is performed in parallel with the decoding operation.

[0051] Figure 8 is a method of encoding data according to the disclosed embodiments. At block 802, for example Figure 1 The controller 108 of the embodiment of the present invention receives a request to move data from a first type of memory cell to a second type of memory cell. In one embodiment, the first type of memory cell may be any one of an SLC memory, an MLC memory, a TLC memory, a TLC memory, etc. The second type of memory may be any one of an SLC memory, an MLC memory, a TLC memory, a TLC memory, etc.

[0052] At block 804 , the controller receives data from the one or more memory devices, where the one or memory devices may be SLC memory, MLC memory, TLC memory, TLC memory, etc. When the controller receives the data, the controller begins a decoding process by checking for errors in the received data at block 806 .

[0053] At block 808, the controller modifies a portion of the parity check matrix data with the updated data. In one embodiment, the modified portion of the parity check matrix data is a trailing portion of the parity check data. At block 810, the controller encodes the stored data with the modified parity check matrix data.

[0054] In one embodiment, the modified portion of the parity check matrix data is obtained by Figure 5 In another embodiment, the controller may be encoded by the process described in Figure 6 The parity check matrix data is edited and encoded while the process described in the above is decoding the data. In another embodiment, Figure 7The process described in is to complete the decoding and encoding of the parity check matrix data in parallel when no error is found. When the parity check matrix data is decoded and encoded in parallel, multiple types of parity check matrix data are calculated for each bit changed in the modified parity check matrix data. The controller selects at least one of the multiple types of parity check matrix data types and updates the parity check matrix data with the selected one of the multiple check matrix data types. The updating of the parity check matrix data may include XORing the parity check matrix data with a selected one of the multiple types of parity check matrix data. In one embodiment, the selected type of the parity check matrix data includes two or more types of the multiple types of parity check matrix data.

[0055] By utilizing an editing process to implement more flexible replication via a controller, a storage device may improve performance, achieve greater power savings during operation, and reduce firmware complexity.

[0056] In one embodiment, a data storage device is disclosed, comprising one or more memory devices and a controller configured to perform a method for encoding data. In an embodiment, the method comprises receiving data from the one or more memory devices, the data comprising parity check matrix data and stored data; modifying a portion of the parity check matrix data corresponding to metadata associated with the data; and encoding the stored data with the modified parity check matrix data.

[0057] The method comprising modifying the portion of parity data comprises modifying a trailing portion of the parity data. The method comprising encoding the stored data comprises encoding only a portion of the stored data associated with the trailing portion of the parity data. The method further comprises receiving a request to move data from a first type of memory cell of the one or more memory devices to a second type of memory cell of the one or more memory devices, checking for errors in the data, and decoding and encoding the data in parallel when no errors are found. The first type of memory cell is one of a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC). The second type of memory cell is one of a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC). The method comprising modifying parity check matrix data comprises calculating a plurality of patterns of parity check matrix data, selecting at least one of the plurality of patterns, and updating the parity check matrix data with the selected one of the plurality of patterns. Each of the plurality represents a pattern of parity check matrix data having a different single bit modified.

[0058] In another embodiment, a controller for a data storage device is disclosed, comprising an I / O to one or more memory devices, and a processor configured to perform a method for encoding data. In an embodiment, the method comprises receiving a request to move a portion of data, the portion of data comprising data and metadata comprising a first variable and a last variable; retrieving the portion of data; modifying the last variable; and writing the portion of data to the one or more memory devices.

[0059] The method further includes encoding the data with the modified last variable. The first variable and the last variable include parity bits. The method further includes generating a basis of codewords for the last variable including a plurality of codewords representing at least two variations of the modified last variable, and selecting at least two of the at least two variations based on the modified last variable. The method further includes combining the at least two variations. The method including the combining includes combining using an XOR function. The method further includes error checking the portion of the data, and performing at least a portion of encoding and decoding in parallel after no errors are found. The method further includes retrieving the portion of the data from a single-level unit of the one or more memory devices.

[0060] In another embodiment, a system for storing data is disclosed, the system comprising one or more memory components, and a controller component configured to implement a method for encoding data. In an embodiment, the method comprises reading a data segment from the one or more memory components, wherein the data segment comprises metadata and data, the metadata comprising a beginning and an end; modifying a portion of the metadata adjacent to the end of the metadata; and writing the data segment to the one or more memory components.

[0061] The method further includes encoding data of the data segment with the modified portion of the metadata. The method further includes decoding the data segment after reading from at least one single-layer unit of the one or more memory components, and encoding the data segment with the modified portion of the metadata in parallel with the decoding. The method further includes generating a plurality of codewords, each of the plurality of codewords corresponding to a one-bit modified version of the portion of the metadata; editing the data of the data segment; determining a subset of the plurality of codewords from the editing; and combining the subset of the plurality of codewords. The modifying includes combining the subset of the plurality of codewords.

[0062] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, which is determined by the claims that follow.

Claims

1. A data storage device, comprising: one or more memory devices; as well as A controller configured to perform a method for encoding data, the method comprising: receiving data from the one or more memory devices, the data comprising parity check matrix data and stored data; modifying a portion of the parity-check matrix data corresponding to metadata associated with the data; and The stored data is encoded with modified parity-check matrix data.

2. The data storage device of claim 1, wherein said modifying said portion of said parity-check matrix data comprises modifying a trailing portion of said parity-check matrix data.

3. The data storage device of claim 2, wherein the encoding the stored data comprises encoding only a portion of the stored data associated with the trailing portion of the parity check matrix data.

4. The data storage device according to claim 1, the method further comprising: receiving a request to move the data from a first type of memory cell of the one or more memory devices to a second type of memory cell of the one or more memory devices; checking said data for errors; as well as The data is decoded and encoded in parallel when no errors are found.

5. The data storage device of claim 4, the method further comprising wherein the first type of memory cell is one of a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

6. The data storage device of claim 5, wherein the second type of memory cell is one of a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

7. The data storage device of claim 2, wherein modifying the parity check matrix data comprises: calculating a plurality of versions of the parity-check matrix data; selecting at least one of the plurality of patterns; as well as The parity check matrix data is updated using a selected one of the plurality of patterns.

8. The data storage device of claim 7, wherein each of the plurality represents a version of the parity check matrix data having a different single bit modified.

9. A controller for a data storage device, comprising: I / O to one or more storage devices; as well as A processor configured to perform a method for encoding data, the method comprising: receiving a request to move a portion of data, the portion of data comprising the data and metadata including a first variable and a last variable; retrieving the portion of the data; Modifying the last variable, wherein modifying the last variable comprises: modifying a portion of a parity check matrix corresponding to the last variable, wherein the parity check matrix comprises a plurality of parity check bits; and encoding a modified portion of the parity check matrix corresponding to the last variable; and The portion of data is written to the one or more memory devices.

10. The controller of claim 9, the method further comprising encoding the data with a modified final variable.

11. The controller of claim 10, wherein the first variable and the last variable include parity bits.

12. A controller for a data storage device, comprising: I / O to one or more storage devices; as well as A processor configured to perform a method for encoding data, the method comprising: receiving a request to move a portion of data, the portion of data comprising data and metadata, the metadata comprising a first variable and a last variable; retrieving the portion of the data; modifying said last variable; generating a basis of codewords for the last variable comprising a plurality of codewords representing at least two variations of the modified last variable; selecting at least two of said at least two variations based on said modification of said last variable; and The portion of data is written to the one or more memory devices.

13. The controller of claim 12, the method further comprising combining the at least two variations.

14. The controller of claim 13, wherein the combining comprises combining using an exclusive-OR function.

15. A controller for a data storage device, comprising: I / O to one or more storage devices; as well as A processor configured to perform a method for encoding data, the method comprising: receiving a request to move a portion of data, the portion of data comprising data and metadata, the metadata comprising a first variable and a last variable; retrieving the portion of the data; modifying said last variable; writing a portion of the data to the one or more memory devices; performing error checking on the portion of the data; and At least a portion of the encoding and decoding is performed in parallel after no errors are found.

16. The controller of claim 15, the method further comprising retrieving the portion of data from a single level cell of the one or more memory devices.

17. A system for storing data, comprising: one or more memory components; as well as A controller coupled to the one or more memory components, the controller being configured to perform a method for encoding data, the method comprising: reading a data sector from the one or more memory components, wherein the data sector comprises metadata and data, the metadata comprising a beginning and an end; modifying a portion of the metadata adjacent to the end of the metadata; and The data sectors are written to the one or more memory components.

18. The system of claim 17, the method further comprising encoding the data of the data segment with the modified portion of the metadata.

19. The system of claim 17, the method further comprising: decoding the data sector after reading from at least one single level cell of the one or more memory components; as well as The data segments are encoded with the modified portions of the metadata in parallel with the decoding.

20. The system of claim 17, the method further comprising: generating a plurality of codewords, each of the plurality of codewords corresponding to a one-bit modified version of the portion of the metadata; Editing the data of the data section; determining a subset of the plurality of codewords from the compilation; as well as combining the subsets of the plurality of codewords; Wherein the modifying comprises replacing the portion of the metadata with a combined subset of the plurality of codewords.

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