Semiconductor device with a flexible reinforcement structure

Abstract

This application relates to semiconductor devices with a flexible reinforcement structure. Methods for manufacturing semiconductor devices with a flexible reinforcement structure, as well as associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die may include a first surface connected to the redistribution structure and a second surface spaced apart from the redistribution structure. The method further includes reducing the thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of at least one semiconductor die.

Description

Technical Field

[0001] The present technology generally relates to semiconductor devices, and more particularly, to semiconductor devices having a flexible reinforcement structure coupled to a semiconductor die. Background Art

[0002] Encapsulated semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and packaged in a protective cover. The semiconductor die may include functional features such as memory cells, processor circuitry, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads may be electrically connected to terminals external to the protective cover to allow the semiconductor die to be connected to a higher-level circuit system.

[0003] During the manufacturing process, the semiconductor die may be thinned (e.g., by backgrinding) to reduce the overall thickness of the semiconductor package. However, a thinner semiconductor die may be more prone to cracking, chipping, or other damage during subsequent processing steps. A semiconductor package having a thinner semiconductor die may also be more prone to failure due to thermomechanical stress (e.g., chip-package interaction (CPI) stress). Summary of the Invention

[0004] In one aspect, the present application provides a method of manufacturing a semiconductor device, the method comprising: electrically coupling at least one semiconductor die to a redistribution structure on a first carrier, the semiconductor die including a first surface connected to the redistribution structure and a second surface spaced apart from the redistribution structure; reducing the thickness of the semiconductor die to no greater than 10 μm; and coupling a flexible reinforcement structure to the second surface of the semiconductor die.

[0005] In another aspect, the present application provides a semiconductor device, comprising: a semiconductor die having a first surface and a second surface, wherein the semiconductor die has a thickness less than or equal to 10 μm; a flexible reinforcement structure permanently fixed to the first surface of the semiconductor die; and a redistribution structure electrically coupled to the second surface of the semiconductor die. Brief Description of the Drawings

[0006] Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, the emphasis is placed on clearly illustrating the principles of the present technology.

[0007] Figure 1A is a side cross-sectional view of a redistribution structure formed on a first carrier and configured according to an embodiment of the present technology.

[0008] Figure 1B is coupled to Figure 1ASide cross-sectional view of a semiconductor die having a redistribution structure and configured according to an embodiment of the present technology.

[0009] Figure 1C is a side cross-sectional view of a semiconductor die encapsulated in a molding material and configured according to an embodiment of the present technology Figure 1B of a semiconductor die.

[0010] Figure 1D is a side cross-sectional view of a semiconductor die thinned according to an embodiment of the present technology Figure 1C of a semiconductor die.

[0011] Figure 1E is a side cross-sectional view of a reinforcement structure attached to Figure 1D a thinned semiconductor die and configured according to an embodiment of the present technology.

[0012] Figure 1F is a side cross-sectional view of a second carrier attached to Figure 1E a reinforcement structure and configured according to an embodiment of the present technology.

[0013] Figure 1G is a side cross-sectional view of a semiconductor die after separation from a first carrier, according to an embodiment of the present technology Figure 1F of a semiconductor die.

[0014] Figure 1H is a side cross-sectional view of a semiconductor die coupled to an array of electrical connectors and configured according to an embodiment of the present technology Figure 1G of a semiconductor die.

[0015] Figure 1I is a side cross-sectional view of a plurality of semiconductor devices produced by singulating a Figure 1H semiconductor die according to an embodiment of the present technology.

[0016] Figure 2 is a side cross-sectional view of a semiconductor device configured according to an embodiment of the present technology.

[0017] Figure 3 is a schematic diagram of a system including a semiconductor device or package configured according to an embodiment of the present technology. Detailed Description

[0018] Details of several embodiments of semiconductor devices and associated systems and methods are described below. Those skilled in the relevant art will recognize that suitable stages of the methods described herein can be performed at the wafer level or die level. Thus, depending on the context in which it is used, the term "substrate" can refer to a wafer-level substrate or a singulated die-level substrate. Additionally, unless the context dictates otherwise, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. For example, materials can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, electroless plating, spin coating, and / or other suitable techniques. Similarly, for example, materials can be removed using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0019] In several embodiments described below, a method of fabricating a semiconductor device includes electrically coupling one or more semiconductor dies to a redistribution structure on a first carrier. Each semiconductor die can have a first surface (e.g., an active side or surface) connected to the redistribution structure and a second surface (e.g., a back side or surface) spaced apart from the redistribution structure. The method can also include reducing the thickness of each semiconductor die, such as by grinding or otherwise removing material from the second surface of the semiconductor die. After the thinning process, a flexible reinforcement structure can be coupled to the second surface of the semiconductor die, and the flexible reinforcement structure can remain attached to the semiconductor die during subsequent manufacturing steps and / or with the final semiconductor device. It is desired that this technology reduces chipping, cracking, or other damage or failures in the semiconductor die that cause yield loss during the manufacturing process. Additionally, the embodiments described herein can be used to reliably produce very thin semiconductor dies (e.g., no greater than 10 μm thick), suitable for single die packages (SDPs) or system-in-packages (SiPs), for flexible electronics applications or other applications that require thin dies. In some embodiments, the techniques described herein can be used to produce substrate-less semiconductor packages (e.g., packages in which the semiconductor die is directly mounted to a printed circuit board or flexible circuit without any intermediate package substrate).

[0020] Numerous specific details are set forth herein to provide a thorough and practicable description of embodiments of the technology. However, those skilled in the art will understand that the technology can have additional embodiments and that the technology can be practiced without several details of the embodiments described below. For example, some details of semiconductor devices and / or packages that are well known in the art are omitted so as not to obscure the technology. In general, it should be understood that, in addition to the specific embodiments disclosed herein, various other devices and systems can also be within the scope of the technology. Figures 1A to 3

[0021] ​As used herein, the terms "vertical", "lateral", "upper", "lower", "above", and "below" may refer to the relative directions or positions of features in a semiconductor device according to the orientation shown in the figures. For example, "upper" or "uppermost" may refer to a feature that is closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, above / below, over / under, up / down, and left / right may be interchanged according to the orientation.

[0022] Figures 1A to 1I is a side cross-sectional view showing various stages of a method of manufacturing a semiconductor device according to an embodiment of the present technology. The semiconductor device may be manufactured as, for example, a discrete device or as part of a larger wafer or panel. In wafer-level or panel-level manufacturing, multiple semiconductor die are encapsulated on the wafer or panel before being singulated into multiple individual devices. Although Figures 1A to 1I shows a manufacturing process involving five semiconductor die, in practice, the process may be scaled or otherwise adapted to any suitable number of semiconductor die (e.g., a single semiconductor die, dozens or hundreds of semiconductor die, etc.).

[0023] Referring Figure 1A , a redistribution structure 100 (schematically shown) is formed on a first carrier 102. The redistribution structure 100 includes a first surface 103a (e.g., a lower surface) connected to the first carrier 102 and a second surface 103b (e.g., an upper surface) remote from the first carrier 102. The redistribution structure 100 may be fabricated directly on the first carrier 102 using any suitable additive manufacturing process, such as sputtering, physical vapor deposition (PVD), electroplating, lithography, etc.

[0024] In some embodiments, according to techniques known to those skilled in the art, the redistribution structure 100 is or includes a redistribution layer (RDL) configured for fan-out wafer-level packaging. The redistribution structure 100 may include one or more layers of insulating material 104 and one or more layers of conductive elements 106 (e.g., contacts, traces, pads, vias, etc.). The insulating material 104 may separate and electrically isolate the conductive elements 106 from each other. The insulating material 104 may be made of any suitable non-conductive dielectric material, such as parylene, polyimide, or low-temperature chemical vapor deposition (CVD) materials (e.g., tetraethyl orthosilicate (TEOS), silicon nitride, silicon oxide). The conductive elements 106 may be made of any suitable conductive material, such as one or more metals (e.g., copper, silver, titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the redistribution structure 100 is configured to be flexible and can undergo a certain amount of deformation (e.g., elastic deformation and / or plastic deformation) while remaining fully operational. For example, the insulating material 104 may be made of a flexible polyimide dielectric material, and the conductive elements 106 may be made of thin copper or flexible silver paste.

[0025] The first carrier 102 may be a wafer or other structure that temporarily provides mechanical support for the redistribution structure 100 and / or other semiconductor components for subsequent processing stages. The first carrier 102 may be formed of any suitable material, such as silicon, silicon-on-insulator, compound semiconductor materials (e.g., gallium nitride), glass, or quartz. In some embodiments, the first carrier 102 is temporarily coupled to the redistribution structure 100 via a release layer 108. The release layer 108 may be configured to selectively dissolve, peel, or otherwise separate from the redistribution structure 100 upon application of a suitable stimulus (e.g., heat, light) or reagent (e.g., solvent, acid, water), such that the redistribution structure 100 can be removed from the first carrier 102, as described in more detail below. The release layer 108 may be made of any suitable material, such as adhesives, polymers, epoxies, films, tapes, pastes, etc.

[0026] Reference Figure 1B, a plurality of semiconductor dies 110 are mechanically and electrically coupled to the redistribution structure 100. The semiconductor dies 110 may be spaced apart from each other on the surface of the redistribution structure 100, for example, distributed according to a wafer-level or panel-level manufacturing process. Each semiconductor die 110 includes a semiconductor substrate 112 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.), which has a first side or surface 114a (e.g., a lower surface) and a second side or surface 114b (e.g., an upper surface). Each semiconductor die 110 may be relatively thick, e.g., the initial thickness T of the semiconductor die 110 1 may be greater than or equal to 750 μm.

[0027] In some embodiments, the first surface 114a of each semiconductor die 110 is connected to the second surface 103b of the redistribution structure 100, while the second surface 114b is away from the redistribution structure 100. The first surface 114a may be an active side, surface or region, which includes various types of semiconductor components, such as memory circuits (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), flash memory or other types of memory circuits), controller circuits (e.g., DRAM controller circuits), logic circuits, processing circuits, circuit elements (e.g., wires, traces, interconnects, transistors, etc.), imaging components and / or other semiconductor features. In some embodiments, the first surface 114a includes contacts (e.g., bonding pads—not shown) for electrically coupling the semiconductor die 110 to the conductive elements 106 of the redistribution structure 100. The first surface 114a may be electrically coupled to the redistribution structure 100 using any suitable bonding technique known to those skilled in the art (e.g., thermocompression bonding, flip-chip bonding, etc.). The second surface 114b may be the back side or surface of the semiconductor die 110, which does not include electrically or optically active semiconductor components or features.

[0028] Reference Figure 1C , a molding material 116 may be disposed over the semiconductor die 110 and a portion of the second surface 103b of the redistribution structure 100. The molding material 116 may cover the second surface 114a and the lateral surface 114c of each semiconductor die 110, and fill the space between the individual semiconductor dies 110. The molding material 116 may be a resin, an epoxy resin, a silicone-based material, a polyimide or any other material suitable for encapsulating at least a portion of the semiconductor die 110 and / or the redistribution structure 100 to protect these components from contaminants and / or physical damage. Once deposited, the molding material 116 may optionally be cured by ultraviolet light, chemical hardeners, heat or other suitable curing methods known in the art.

[0029] Figure 1DAn assembly is shown after reducing the thickness of each semiconductor die 110 by removing material from the semiconductor substrate 112. In some embodiments, the thinning process may involve removing portions of the semiconductor substrate 112 that do not include any active semiconductor components (e.g., portions at or near the second surface 114b), leaving portions of the semiconductor substrate 112 that include active components (e.g., portions at or near the first surface 114a). The thinning process may also involve removing some of the molding material 116. For example, portions above the second surface 114b of the molding material 116 may be removed such that the second surface 114b is exposed for thinning the semiconductor die 110 and subsequent manufacturing processes. Thinning of the semiconductor die 110 may be achieved via techniques known to those skilled in the art, such as grinding (e.g., back grinding of the second surface 114b), dry etching, chemical etching, or chemical mechanical polishing (CMP).

[0030] The final thickness T of the semiconductor die 110 2 can be significantly less than the initial thickness T 1 . For example, the final thickness T 2 can be less than or equal to 50 μm, 40 μm, 30 μm, 20 μm, 15 μm, 10 μm, 5 μm, 4 μm, 3 μm, 2 μm, or 1 μm. In some embodiments, the final thickness T 2 is less than or equal to 10%, 5%, 4%, 3%, 2%, 1.5%, 1%, or 0.5% of the initial thickness T 1 . Optionally, the final thickness T 2 can be thin enough such that the semiconductor die 110 can be bent or flexed for flexible electronics applications, non-TSV die stacking techniques, and / or other applications that require a very thin semiconductor die, as further described below.

[0031] Reference Figure 1E, at least one reinforcing structure 118 is coupled to the second surface 114b of each semiconductor die 110. The reinforcing structure 118 includes a first surface 120a (e.g., the lower surface) that contacts the semiconductor die 110 and a second surface 120b (e.g., the upper surface) that is away from the semiconductor die 110. In some embodiments, the second surface 114b of each semiconductor die 110 contacts and is covered by the reinforcing structure 118, while the side surface 114c is surrounded by the molding material 116. The reinforcing structure 118 can be configured as a layer, sheet, film, or any other structure having a large enough surface area to cover multiple semiconductor dies 110 in a wafer-level or panel-level manufacturing process. The reinforcing structure 118 can also cover the exposed area of the molding material 116. The reinforcing structure 118 can be configured to support and protect the semiconductor die 110 after thinning, e.g., to reduce or prevent cracking or chipping and mitigate the likelihood of failure due to thermo-mechanical stress, etc. As previously mentioned, thin semiconductor dies (e.g., having a thickness less than or equal to 50 μm, 35 μm, 10 μm, or 5 μm) may be particularly prone to chipping or cracking at the molding edge during subsequent manufacturing processes. Additionally, thermo-mechanical stress (e.g., CPI stress) during subsequent manufacturing processes and / or operation can also have a significant impact on thin semiconductor dies. Thus, the reinforcing structure 118 can protect the semiconductor die 110 to reduce yield loss due to chipping, cracking, and other failures.

[0032] In some embodiments, the reinforcing structure 118 is flexible and can accommodate a certain degree of elastic and / or plastic deformation (e.g., bending) without breaking, separating from the semiconductor die 110, or other mechanical failures. Thus, the reinforcing structure 118 can have a thickness T 3 that is less than or equal to 50 μm, 40 μm, 30 μm, 20 μm, 15 μm, 10 μm, 5 μm, 4 μm, 3 μm, 2 μm, or 1 μm, a relatively thin structure. In some embodiments, the thickness T 3 is less than or equal to the thickness T of the thinned semiconductor die 110 2 , e.g., the thickness T 3 is less than or equal to 100%, 90%, 80%, 70%, 60%, 50%, 40%, 30%, 20%, or 10% of the thickness T 2 . The reinforcing structure 118 can be configured to be more flexible than a silicon layer having an equal thickness.

[0033] The reinforcing structure 118 can be made of many different types of materials, such as polymeric materials (e.g., polyimide, polytetrafluoroethylene (PTFE)), resins (e.g., epoxy resins), laminates, films (e.g., die attach films), metallic materials (e.g., copper, aluminum), or combinations thereof. Optionally, the reinforcing structure 118 can be a composite material including at least one structural element (e.g., fabric, fiber, particles, etc.) embedded in a matrix material (e.g., polymer, resin, etc.). The structural element can provide mechanical strength and support, while the matrix material can surround and / or impregnate the structural elements to connect them to each other and / or provide flexibility. For example, the matrix material can be polyimide or epoxy resin, and the structural element can be a carbon-based material (e.g., carbon fabric or carbon fiber) or a glass-based material (e.g., glass fabric or glass fiber). Optionally, the reinforcing structure 118 can be made of the same or substantially similar materials as those used in the substrate for semiconductor devices (e.g., the core material used in printed circuit boards). Optionally or in combination, the reinforcing structure 118 can be made of the same or substantially similar materials as the metals or metal alloys used in semiconductor package and lead frame manufacturing (e.g., metal layers attached via a thin adhesive layer).

[0034] The reinforcing structure 118 can be coupled to the semiconductor die 110 in various ways. For example, the reinforcing structure 118 can be provided as a prefabricated layer or sheet that is laminated or otherwise joined to the semiconductor die 110 (e.g., via heating, curing, adhesive, etc.). As another example, the reinforcing structure 118 can be provided as a liquid or semi-solid material coated onto the semiconductor die 110 (e.g., by spin coating, spraying, etc.). In a further example, the reinforcing structure 118 can be molded onto the semiconductor die 110. The reinforcing structure 118 can optionally be attached to the semiconductor die 110 in an uncured state and then subsequently cured (e.g., by heat, light, chemical agents, etc.). Suitable adhesion promoters can also be used to facilitate the coupling of the reinforcing structure 118 to the semiconductor die 110. In some embodiments, the second surface 114b of the semiconductor substrate 112 includes a native oxide layer, and the reinforcing structure 118 is attached to the oxide layer. In other embodiments, the native oxide layer can be removed such that the reinforcing structure 118 is directly attached to the silicon of the semiconductor substrate 112. Other techniques known to those skilled in the art for fabricating thin layer materials on semiconductor die 110 can also be used.

[0035] Although the illustrated embodiment shows a single stiffening structure 118, in other embodiments, a different number of stiffening structures 118 (e.g., two, three, four, five, or more) may be used. The stiffening structures 118 may each be made of the same material, or some or all of the stiffening structures 118 may be made of different materials to impart different properties (e.g., strength, flexibility, heat transfer, etc.) to the composite stiffening structure. Similarly, the stiffening structures 118 may each have the same thickness, or some or all of the stiffening structures 118 may have different thicknesses. In some embodiments, the combined thickness of all the stiffening structures 118 is thin enough to maintain flexibility, e.g., less than or equal to 50 μm, 40 μm, 30 μm, 20 μm, 15 μm, 10 μm, 5 μm, 4 μm, 3 μm, 2 μm, or 1 μm.

[0036] Reference Figure 1F , the second carrier 122 may be coupled to the stiffening structure 118. The second carrier 122 may be coupled to the second surface 120b of the stiffening structure 118 that is remote from the semiconductor die 110. The second carrier 122 may be the same as or substantially similar to the first carrier 102, such as a wafer or other structure that temporarily provides mechanical support for subsequent processing stages. According to techniques known to those skilled in the art, the second carrier 122 may be directly coupled to the flexible stiffening structure 118, or may be indirectly coupled via a release layer (e.g., the same as or substantially similar to the release layer 108—not shown).

[0037] Reference Figure 1G , the first carrier 102 may be separated from the redistribution structure 100. In some embodiments, the first carrier 102 is separated by, for example, using a suitable stimulus (e.g., heat, light) or reagent (e.g., solvent, water) to dissolve, peel, or otherwise decouple the release layer 108 from the redistribution structure 100. After the first carrier 102 is removed, the semiconductor die 110 and the redistribution structure 100 remain coupled to the second carrier 122 via the stiffening structure 118, while the first surface 103a of the redistribution structure 100 is exposed for subsequent manufacturing stages.

[0038] Figure 1HShows the components after an array of electrical connectors 124 (e.g., ball grid array) has been mechanically and electrically coupled to the redistribution structure 100. According to techniques known to those skilled in the art, the electrical connectors 124 can include solder balls, conductive bumps, conductive posts, conductive epoxy, and / or other suitable conductive elements configured to electrically and mechanically couple the semiconductor die 110 to a substrate or another device. In some embodiments, the electrical connectors 124 are electrically coupled to the conductive elements 106 of the redistribution structure 100 such that signals from the semiconductor die 110 can be routed via the redistribution structure 100 to the electrical connectors 124. For example, the first surface 103a of the redistribution structure 100 can include contacts (e.g., bond pads—not shown) for receiving and coupling to the electrical connectors 124, and the contacts can be electrically coupled via the conductive elements 106 to corresponding contacts on the semiconductor die 110.

[0039] Reference Figure 1I , the semiconductor die 110 can be singulated or otherwise separated from each other to form a plurality of individual semiconductor devices 150. The singulation process can involve separating the reinforcement structure 118 from the second carrier 122 (e.g., using techniques similar to those described previously with respect to the first carrier 102 and Figure 1G described). Subsequently, the semiconductor die 110 can be mounted on a tape or film 126 (e.g., dicing tape) supported by a frame 128. In the illustrated embodiment, the second surface 120b of the reinforcement structure 118 is coupled to the tape 126 while the first surface 103a of the redistribution structure 100 is exposed. A dicing mechanism (e.g., blade, saw, laser, etc.) can be used to cut through the portions of the redistribution structure 100, the molding material 116, and the reinforcement structure 118 between the individual semiconductor die 110 to separate them from each other. According to techniques known to those skilled in the art, the resulting singulated devices 150 can subsequently be separated from the tape 126.

[0040] Optionally, during the singulation process, a film layer (e.g., anisotropic conductive film (ACF)—not shown) can be coupled between the tape 126 and the reinforcement structure 118, for example to facilitate adhesion. The film layer can extend continuously across all the devices 150 or can be pre-cut into individual segments corresponding to the size of the individual devices 150.

[0041] In some embodiments, after singulation, one or more additional reinforcement structures (not shown) can be coupled around the lateral surface 152 of each device 150 to provide further support and protection. The additional reinforcement structures can be the same as or substantially similar to the reinforcement structure 118 and can be attached via lamination, coating, molding, or any other suitable technique.

[0042] Figure 2is a side cross-sectional view of a semiconductor device 200 configured according to an embodiment of the present technology. The device 200 may use any embodiment of the methods provided herein, such as those Figures 1A to 1I described methods to manufacture. The device 200 includes a semiconductor die 110 mounted on a substrate 202. The components of the device 200 may be the same as or substantially similar to the corresponding components previously described with respect to Figures 1A to 1I described. For example, the semiconductor die 110 may be relatively thin (e.g., having a thickness less than or equal to 10 μm or 5 μm) and may have a first surface 114a (e.g., an active side or surface) coupled to a redistribution structure 100 and a second surface 114b (e.g., a back side or surface) coupled to a reinforcement structure 118 (e.g., a flexible reinforcement structure). The semiconductor die 110 may be electrically coupled to the substrate 202 via the redistribution structure 100 and an array of electrical connectors 124, thereby allowing signal transmission between the semiconductor die 110 and the substrate 202. Optionally, the semiconductor die 110 may be at least partially encapsulated by a molding material 116 between the reinforcement structure 118 and the redistribution structure 100.

[0043] The substrate 202 may be any structure or component suitable for supporting the semiconductor die 110. For example, the substrate 202 may be or include an interposer, such as a printed circuit board, a dielectric spacer, another semiconductor die (e.g., a logic die), or another suitable substrate. In some embodiments, the substrate 202 is a flexible circuit or other suitable flexible substrate. Thus, the device 200 may be used in flexible electronic product applications. In such embodiments, the device 200 may be configured to bend or otherwise deform while remaining fully operational (e.g., without mechanical and / or electrical failures). Optionally, the device 200 may be a "chip - on - board" package, where the substrate 202 is a board - level substrate (e.g., a printed circuit board or a flexible circuit) and the device 200 does not include any intermediate substrate (e.g., a package - level substrate) between the semiconductor die 110 and the board - level substrate.

[0044] Although embodiments of the present disclosure describe semiconductor devices having a single semiconductor die, the techniques herein can also be applied to semiconductor devices having multiple semiconductor dice vertically arranged in a die stack. Some or all of the semiconductor dice in the die stack can be relatively thin (e.g., having a thickness less than or equal to 10 μm or 5 μm). For example, some or all of the semiconductor dice can be thin enough to accommodate non-TSV die stack technology. In such embodiments, as previously described, one or more reinforcement structures can be coupled to the uppermost semiconductor die in the stack to provide protection against fragmentation, cracking, and / or thermo-mechanical stress. According to techniques known to those skilled in the art, the reinforcement structure can be attached to the uppermost semiconductor die (e.g., the semiconductor die farthest from the redistribution structure) after the die stack is assembled on the redistribution structure. Accordingly, the corresponding semiconductor device can include a first semiconductor die coupled to the reinforcement structure and at least one second semiconductor die between the first semiconductor die and the redistribution structure.

[0045] Any of the semiconductor devices and / or packages having the features described above with reference to Figures 1A to 2 can be incorporated into any of a wide variety of larger and / or more complex systems, representative examples of which are Figure 3 the system 300 schematically shown in. The system 300 can include a processor 302, a memory 304 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 306, and / or other subsystems or components 308. The semiconductor dice and / or packages described above with reference to Figures 1A to 2 can be included in any of the Figure 3 elements shown. The resulting system 300 can be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Accordingly, representative examples of the system 300 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, Internet appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Other representative examples of the system 300 include lights, cameras, vehicles, etc. With respect to these and other examples, the system 300 can be housed in a single unit or distributed over multiple interconnected units, e.g., via a communication network. The components of the system 300 can accordingly include local and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0046] It will be understood from the foregoing that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without departing from the disclosure. Accordingly, the invention is not limited except as by the appended claims. In addition, certain aspects of the new technology described in the context of specific embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to exhibit such advantages to fall within the scope of the technology. Accordingly, the present disclosure and the associated technology may embrace other embodiments not expressly shown or described herein.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: electrically coupling at least one semiconductor die to a redistribution structure on a first carrier, the semiconductor die including a first surface connected to the redistribution structure and a second surface spaced apart from the redistribution structure; reducing the thickness of the semiconductor die to no greater than 10 μm; and directly coupling a flexible reinforcement structure to the second surface of the semiconductor die.

2. The method according to claim 1, wherein the flexible reinforcement structure comprises a polymeric material, a resin, a laminate, a film, or a combination thereof.

3. The method according to claim 1, wherein the flexible reinforcement structure comprises at least one structural element embedded in a matrix material.

4. The method according to claim 3, wherein the at least one structural element comprises a fabric or a fiber.

5. The method according to claim 1, wherein the flexible reinforcement structure has a thickness of no greater than 10 μm.

6. The method according to claim 1, wherein the flexible reinforcement structure is configured to protect the semiconductor die from one or more of chipping, cracking, or thermo-mechanical stress.

7. The method according to claim 1, wherein coupling the flexible reinforcement structure to the second surface comprises laminating, coating, or molding the flexible reinforcement structure onto the second surface.

8. The method according to claim 1, further comprising: coupling the flexible reinforcement structure to a second carrier; separating the redistribution structure from the first carrier; and electrically coupling the redistribution structure to an array of electrical connectors.

9. The method according to claim 8, further comprising: separating the flexible reinforcement structure from the second carrier; and electrically coupling the semiconductor die to a flexible circuit via the array of electrical connectors.

10. The method according to claim 1, wherein the at least one semiconductor die comprises a plurality of semiconductor dies.

11. The method according to claim 10, further comprising singulating the semiconductor dies into a plurality of individual semiconductor devices.

12. A semiconductor device, comprising: a semiconductor die having a first surface and a second surface, wherein the semiconductor die has a thickness less than or equal to 10 μm; a flexible reinforcement structure directly fixed to the first surface of the semiconductor die; and a redistribution structure electrically coupled to the second surface of the semiconductor die.

13. The semiconductor device according to claim 12, further comprising a flexible circuit, wherein the semiconductor die and the redistribution structure are mounted on the flexible circuit.

14. The semiconductor device according to claim 13, further comprising an array of electrical connectors for electrically coupling the semiconductor die and the redistribution structure to the flexible circuit.

15. The semiconductor device according to claim 12, wherein the thickness of the semiconductor die is less than or equal to 5 μm.

16. The semiconductor device according to claim 12, wherein the semiconductor die is a first semiconductor die, and further comprises at least one second semiconductor die between the first semiconductor die and the redistribution structure, the second semiconductor die having a thickness less than or equal to 10 μm.

17. The semiconductor device according to claim 12, wherein the flexible reinforcement structure comprises a polymeric material, a resin, a laminate, or a combination thereof.

18. The semiconductor device according to claim 12, wherein the flexible reinforcement structure comprises at least one structural element embedded in a matrix material.

19. The semiconductor device according to claim 18, wherein the at least one structural element comprises a fabric or a fiber.

20. The semiconductor device according to claim 18, wherein the at least one structural element is made of carbon or glass, and wherein the matrix material is a polymer or a resin.

21. The semiconductor device according to claim 12, further comprising a molding material surrounding at least a portion of the semiconductor die, wherein at least a portion of the flexible reinforcement structure is attached to the molding material.

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