A CIS chip special-shaped gate structure and a manufacturing method thereof

Abstract

The application discloses a CIS chip special-shaped gate structure and a manufacturing method thereof. The CIS chip special-shaped gate structure comprises a photo clamping diode (PPD) and a floating diffusion (FD) arranged on a substrate. A first polysilicon gate with a width of L1 and a height of h1 is arranged on one side close to the photo clamping diode (PPD), and a second polysilicon gate with a width of L2 and a height of h2 is arranged on one side close to the floating diffusion (FD). The special-shaped gate is formed through a photoetching and etching process. Then, P-type doping is performed on one side close to the PPD through ion implantation, and N-type doping is performed on one side close to the FD, so that different threshold voltages are obtained on two sides of the gate. The stepped channel structure increases the channel length, and the potential distribution from high to low at the stepped connection effectively reduces the backflow of channel electrons to the PPD after the gate is turned off.

Description

Technical Field

[0001] This invention relates to a CIS (CMOS image sensor) chip process and application simulation, and more particularly to a CIS chip irregular gate structure and fabrication method. Background Technology

[0002] Large-size CMOS image sensors (CIS), due to their high sensitivity and short exposure time, are often used in high-speed motion capture and are now widely used in broadcasting, sports, machine vision, and scientific research. However, image lag is one of the challenges in high-speed CIS pixel design. To reduce image lag, past research has mainly focused on suppressing the potential barrier or well around the transmission gate edge. Although signal charge is transferred from the PPD to the FD via the transmission channel when the gate is turned on, there is another potential source of image lag. When the gate turns from on to off, charge in the channel region moves to the PD side or the FD side. This charge flowing back to the PD will produce image lag.

[0003] like Figure 1-A As shown, the gate structure connecting the photodiode (PD) and the floating diffusion region (FD) in the CIS (CMOS image sensor) chip serves as a valve channel for the transfer of photogenerated electrons from the PD to the FD, affecting various important parameters of the chip such as electron transfer efficiency and image hysteresis.

[0004] In summary, traditional CIS chips have a flat channel potential below the gate. However, due to structural and process issues, they may have problems such as potential barriers and potential traps, which reduce the transfer efficiency of photogenerated charges. In particular, when there is a high potential barrier near the pinned photodiode (PPD) side channel, electrons may flow back into the PPD, resulting in image trailing.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a non-circular gate structure for a CIS chip and a method for fabricating it, so as to solve the above-mentioned technical problems existing in the prior art.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] The irregular gate structure of the CIS chip of the present invention includes a photodiode PPD and a floating diffusion region FD disposed on a substrate. A first polysilicon gate with a width of L1 and a height of h1 is provided on the side near the photodiode PPD, and a second polysilicon gate with a width of L2 and a height of h2 is provided on the side near the floating diffusion region FD.

[0009] The first polysilicon gate is P-type doped, and the second polysilicon gate is N-type doped;

[0010] The widths L1 and L2 may be the same or different, and the heights h1 and h2 may be different.

[0011] The above-mentioned method for fabricating the irregular gate structure of a CIS chip includes the following steps:

[0012] A. A trench is obtained by photolithography and etching on the side near the photodiode PPD, then a gate oxide layer is deposited, followed by polysilicon deposition, and P-type doping is performed at the position corresponding to the trench by photolithography and ion implantation.

[0013] B. N-type doping is performed on the side near the floating diffusion region FD by photolithography and ion implantation;

[0014] C. For the polysilicon and oxide layer in the non-gate region, they are removed by photolithography and etching, respectively, and then polysilicon is obtained by chemical mechanical planarization.

[0015] D. After oxide layer deposition and silicon nitride deposition, the surface silicon nitride and oxide layers are removed by etching, leaving the sidewall silicon oxide-silicon nitride structure, and finally the irregular gate structure is obtained.

[0016] Compared with the prior art, the irregular gate structure and fabrication method of CIS chip provided by the present invention form an irregular gate through photolithography and etching processes, and then perform P-type doping on the side near PPD and N-type doping on the side near FD through ion implantation to obtain different threshold voltages on both sides of the gate. The stepped channel structure increases the channel length, and the potential distribution from high to low at the stepped connection effectively reduces the backflow of channel electrons to PPD after the gate is turned off. Attached Figure Description

[0017] Figure 1-A This is a schematic diagram of a traditional gate structure.

[0018] Figure 1-B This is a schematic diagram of the gate structure according to an embodiment of the present invention.

[0019] Figure 2-A 2-B, 2-C, and 2-D are schematic diagrams of the cross-sectional morphology obtained according to the process steps provided in the embodiments of the present invention.

[0020] Figure 3 This is a schematic diagram of the simulation results of the potential distribution when the gate is turned off, according to an embodiment of the present invention.

[0021] Figure 4-A This is a schematic diagram of 20 horizontal lines cut at equal intervals within the range of Y = 0 to 0.03 μm when the gate is turned off, according to an embodiment of the present invention.

[0022] Figure 4-B This is a schematic diagram of the electrostatic potential distribution of 20 horizontal lines in the X direction according to an embodiment of the present invention.

[0023] Figure 5 A schematic diagram of the process steps is provided for embodiments of the present invention.

[0024] In the picture:

[0025] 100 Oxide

[0026] 110 FD

[0027] 120 P-sub

[0028] 130 polysilicon

[0029] 140 SIN

[0030] 150 PPD

[0031] 160 Pinning P+

[0032] 170 P+polysilicon

[0033] 180 N+polysilicon Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0035] First, the following explanations are provided for the terms that may be used in this article:

[0036] The term "and / or" means that either or both can be achieved simultaneously. For example, X and / or Y means that it includes both "X" or "Y" as well as the three cases of "X and Y".

[0037] The terms “including,” “comprising,” “containing,” “having,” or other similar semantic descriptions should be interpreted as non-exclusive inclusion. For example, “including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction conditions, processing conditions, parameter, algorithm, signal, data, product or article of manufacture, etc.)” should be interpreted as including not only the expressly listed technical feature element, but also other technical feature elements that are not expressly listed and are well-known in the art.

[0038] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.

[0039] The term "parts by mass" indicates the mass ratio between multiple components. For example, if component X is described as x parts by mass and component Y as y parts by mass, then the mass ratio of component X to component Y is x:y. One part by mass can represent any mass; for example, one part by mass can be expressed as 1 kg or 3.1415926 kg, etc. The sum of the parts by mass of all components is not necessarily 100 parts; it can be greater than 100 parts, less than 100 parts, or equal to 100 parts. Unless otherwise stated, parts, proportions, and percentages mentioned herein are all measured by mass.

[0040] Unless otherwise explicitly specified or limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this document according to the specific circumstances.

[0041] When concentration, temperature, pressure, size, or other parameters are expressed as numerical ranges, such ranges should be understood to specifically disclose all ranges formed by any pairing of upper limits, lower limits, or preferred values ​​within that range, regardless of whether the range is explicitly stated; for example, if the numerical range "2 to 8" is stated, then that range should be interpreted to include ranges such as "2 to 7", "2 to 6", "5 to 7", "3 to 4 and 6 to 7", "3 to 5 and 7", "2 and 5 to 7", etc. Unless otherwise stated, the numerical ranges described herein include both their endpoints and all integers and fractions within that range.

[0042] The terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” and “counterclockwise” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience and simplification of description and do not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this document.

[0043] The contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Where the manufacturers of the reagents or instruments used in the embodiments of this invention are not specified, they are all conventional products that can be purchased commercially.

[0044] A CIS chip irregular gate structure includes a photodiode PPD and a floating diffusion region FD disposed on a substrate, characterized in that a first polysilicon gate with a width of L1 and a height of h1 is provided on the side near the photodiode PPD, and a second polysilicon gate with a width of L2 and a height of h2 is provided on the side near the floating diffusion region FD.

[0045] The first polysilicon gate is P-type doped, and the second polysilicon gate is N-type doped;

[0046] The widths L1 and L2 may be the same or different, and the heights h1 and h2 may be different.

[0047] The upper surfaces of the first polysilicon gate and the second polysilicon gate are flush, the lower surface of the second polysilicon gate is flush with the upper surface of the floating diffusion region FD, and the lower surface of the first polysilicon gate extends downward into the trench.

[0048] The fabrication method of the irregular gate structure of the CIS chip described above is shown in Figures 2A to 2D. Figure 5 As shown, the steps include:

[0049] A. A trench is obtained by photolithography and etching on the side near the photodiode PPD, then a gate oxide layer is deposited, followed by polysilicon deposition, and P-type doping is performed at the position corresponding to the trench by photolithography and ion implantation.

[0050] B. N-type doping is performed on the side near the floating diffusion region FD by photolithography and ion implantation;

[0051] C. For the polysilicon and oxide layer in the non-gate region, they are removed by photolithography and etching, respectively, and then polysilicon is obtained by chemical mechanical planarization.

[0052] D. After oxide layer deposition and silicon nitride deposition, the surface silicon nitride and oxide layers are removed by etching, leaving the sidewall silicon oxide-silicon nitride structure, and finally the irregular gate structure is obtained.

[0053] In step A, the trench depth is 0.02 μm, the oxide layer thickness is 71.5 Å, and the polysilicon thickness is 2000 Å.

[0054] In step C, the polycrystalline silicon thickness obtained by the chemical mechanical planarization treatment is 1450 Å.

[0055] To more clearly demonstrate the technical solution and its effects provided by the present invention, the embodiments of the present invention will be described in detail below with reference to specific examples.

[0056] Example 1

[0057] One embodiment of the present invention relates to the formation of a gate, gate P+N+ doping, and a corresponding comparison of simulated gate channel potentials.

[0058] like Figure 1-B As shown, this invention, starting from the gate structure, provides an irregular gate structure. A polysilicon gate with a first height h1 is formed in the L1 broadband area near the PPD side, and a polysilicon gate with a second height h2 with a width L2 is formed on the other side near the FD side. Different threshold voltages are obtained by different gate heights and doping. When the gate is turned off, the channel electrons are effectively controlled to flow back to the PPD, thereby improving the imaging quality.

[0059] The manufacturing method of a specific embodiment, such as Figures 2-A to 2-D and Figure 5 As shown:

[0060] 1. Gate trench formation: First, at the position L1, which is half the width of the gate closest to the PPD, a trench with a depth of 0.02um is obtained through photolithography and etching. Then, a gate oxide layer with a thickness of 71.5A is deposited, followed by the deposition of 2000A polysilicon.

[0061] 2. P-type doping is performed at the corresponding position of the gate trench by photolithography and ion implantation, and N-type doping is performed in the L2 width range on the other side of the gate position by photolithography and ion implantation.

[0062] 3. Gate formation: The polysilicon and oxide layers in the non-gate regions are removed by photolithography and etching, respectively, and then chemical-mechanical planarization (CMP) is performed to obtain a polysilicon thickness of 1450 Å.

[0063] 4. After oxide deposition and silicon nitride deposition, the surface silicon nitride and oxide layers are removed by over-etching, leaving the sidewall silicon oxide-silicon nitride structure, and finally this irregular gate structure is obtained.

[0064] According to the definition in semiconductor physics, the Fermi level of P-type doped polysilicon is higher than that of N-type doped polysilicon. The work function difference of the N-type doped polysilicon on the right is smaller than that of the P-type doped polysilicon on the left. Therefore, the threshold voltage on the left side of the gate is greater than that on the right side, which can form a gradient potential distribution from small to large in the transmission channel, reducing channel electron backflow and effectively suppressing image hysteresis. Figure 3 As shown, this is the simulation result of the potential distribution after the gate is turned off in this embodiment. When the gate is turned off, the potential under the deep channel on the left is significantly smaller than that under the channel on the right. Specifically, the potential distribution of the gate is obtained by taking values ​​in the horizontal direction in the channel (Figures 4A to 4B).

[0065] As shown in Figure 4A, 20 horizontal lines are equally divided in the vertical direction of the left and right channels from 0.03 to 0 in the Y direction. Figure 4B shows the magnitude of the electrostatic potential of these horizontal lines at different positions in the X direction. The dashed line is the position of the gate trench near the right step. It can be clearly seen from the figure that when the gate is turned off, the channel electrostatic potential at the deep trench is significantly smaller than the electrostatic potential at the normal channel on the right.

[0066] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A method for fabricating an irregularly shaped gate structure for a CIS chip, characterized in that: The irregular gate structure of the CIS chip includes a photodiode (PPD) and a floating diffusion region (FD) disposed on the substrate. A first polysilicon gate with a width of L1 and a height of h1 is provided on the side near the photodiode (PPD), and a second polysilicon gate with a width of L2 and a height of h2 is provided on the side near the floating diffusion region (FD). The first polysilicon gate is P-type doped, and the second polysilicon gate is N-type doped; The widths L1 and L2 may be the same or different, and the heights h1 and h2 may be different. The upper surfaces of the first polysilicon gate and the second polysilicon gate are flush, the lower surface of the second polysilicon gate is flush with the upper surface of the floating diffusion region (FD), and the lower surface of the first polysilicon gate extends downward into the trench. The method for fabricating the irregular gate structure of the CIS chip includes the following steps: A. A trench is obtained by photolithography and etching on the side near the photodiode (PPD), then a gate oxide layer is deposited, followed by the deposition of polysilicon with a thickness of 2000 Å. P-type doping is performed at the position corresponding to the trench by photolithography and ion implantation. The depth of the trench is 0.02 μm, and the thickness of the gate oxide layer is 71.5 Å. B. N-type doping is performed on the side near the floating diffusion region (FD) by photolithography and ion implantation; C. The polysilicon and oxide layer in the non-gate region are removed by photolithography and etching, respectively, and then chemical mechanical planarization is performed to obtain polysilicon with a thickness of 1450 Å. D. After oxide layer deposition and silicon nitride deposition, the surface silicon nitride and oxide layers are removed by etching, leaving the sidewall oxide-silicon nitride structure, and finally the irregular gate structure is obtained.

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