Display device and method of manufacturing the same

Abstract

The present invention relates to a display device including a light emitting diode and a method for manufacturing the display device. A display device according to an embodiment of the present invention has pixels arranged in a display area. The pixel includes: a first partition wall and a second partition wall, which are arranged on a base layer to be separated from each other; a first electrode and a second electrode, which are respectively arranged on the first partition wall and the second partition wall to be separated from each other; a light emitting diode, which is arranged between the first electrode and the second electrode and includes a first end connected to the first electrode and a second end connected to the second electrode; and at least one insulating layer, which is arranged on at least one of the first electrode and the second electrode and the light emitting diode. The at least one insulating layer includes at least one opening portion of a first opening portion adjacent to the first end of the light emitting diode and a second opening portion adjacent to the second end of the light emitting diode.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device and a method of manufacturing the same. Background Art

[0002] Recently, a technology for manufacturing an ultra-small light-emitting element using a material having a reliable inorganic crystal structure and manufacturing a light-emitting device using the light-emitting element has been developed. For example, a technology for manufacturing a plurality of ultra-small light-emitting elements each having a small size ranging from the nanometer level to the micrometer level and forming a light source of various light-emitting devices including pixels of a display device using the ultra-small light-emitting elements has been developed. Summary of the invention

[0003] Technical issues

[0004] An object of the present disclosure is to provide a display device including a light emitting element and a method of manufacturing the same.

[0005] Technical Solution

[0006] A display device according to an embodiment of the present disclosure includes a pixel arranged in a display area. The pixel includes: a first partition wall and a second partition wall, which are arranged on a base layer and spaced apart from each other; a first electrode and a second electrode, which are respectively arranged on the first partition wall and the second partition wall and spaced apart from each other; a light-emitting element, which is arranged between the first electrode and the second electrode and includes a first end connected to the first electrode and a second end connected to the second electrode; and at least one insulating layer, which is arranged on the light-emitting element and at least one of the first electrode and the second electrode and includes at least one of a first opening adjacent to the first end of the light-emitting element and a second opening adjacent to the second end of the light-emitting element.

[0007] In an embodiment, the first opening may be provided in a region corresponding to a space between a first end of the light emitting element and the first partition wall. The second opening may be provided in a region corresponding to a space between a second end of the light emitting element and the second partition wall.

[0008] In an embodiment, the first opening may be disposed on the first partition wall. The second opening may be disposed on the second partition wall.

[0009] In an embodiment, the first opening may have a width that is the same as or smaller than the width of the first partition wall and is arranged to overlap the first partition wall. The second opening may have a width that is the same as or smaller than the width of the second partition wall and is arranged to overlap the second partition wall.

[0010] In an implementation, the first opening and the second opening may be spaced apart from the light emitting element by the same horizontal distance.

[0011] In an embodiment, each of the first opening and the second opening vertically passes through the at least one insulating layer at an angle in a range of 80° to 100° relative to a plane on which the light emitting element is disposed.

[0012] In an embodiment, the first partition wall may include an inclined surface or a curved surface facing the first end of the light emitting element. The second partition wall may include an inclined surface or a curved surface facing the second end of the light emitting element.

[0013] In an implementation, each of the first electrode and the second electrode may include an inclined surface or a curved surface corresponding to a shape of a corresponding one of the first partition wall and the second partition wall, and may include a reflective electrode layer.

[0014] In an embodiment, the display device may further include at least one of the following items: a first insulating layer, disposed on the first electrode and the second electrode and exposing an area of ​​the first electrode and an area of ​​the second electrode; and a second insulating layer, disposed on the light emitting element and exposing the first end and the second end of the light emitting element.

[0015] In an embodiment, the pixel may include: a third electrode, which is disposed on the first end of the light-emitting element and the first electrode and is configured to electrically connect the first end of the light-emitting element to the first electrode; and a fourth electrode, which is disposed on the second end of the light-emitting element and the second electrode and is configured to electrically connect the second end of the light-emitting element to the second electrode.

[0016] In an implementation, at least one insulating layer may be directly disposed on at least one of the third electrode and the fourth electrode.The first opening and the second opening may expose a region of the third electrode and a region of the fourth electrode, respectively.

[0017] In an embodiment, at least one insulating layer may include at least one of the following items: a third insulating layer disposed on the third electrode and an area including the first end of the light-emitting element and configured to cover one end of the third electrode on the light-emitting element; and a fourth insulating layer disposed on the entire surface of the display area, the display area including a space throughout the light-emitting element, the third electrode and the fourth electrode.

[0018] In an implementation, the first opening may pass through the third insulating layer and the fourth insulating layer. The second opening may pass through the fourth insulating layer.

[0019] In an embodiment, the display device may further include an upper substrate disposed over the pixels, and include a light conversion layer overlapping the pixels.

[0020] In an embodiment, the light conversion layer may include at least one of: a color filter layer disposed on the upper substrate to face the pixel; and a color conversion layer disposed between the color filter layer and the pixel and including color conversion particles.

[0021] A method for manufacturing a display device according to an embodiment of the present disclosure includes: forming a first partition wall and a second partition wall spaced apart from each other on a base layer; forming a first electrode and a second electrode on the first partition wall and the second partition wall, respectively; providing and aligning a light-emitting element between the first electrode and the second electrode; forming a third electrode and a fourth electrode, the third electrode and the fourth electrode being configured to connect a first end and a second end of the light-emitting element to the first electrode and the second electrode, respectively; forming at least one insulating layer on the light-emitting element and at least one of the third electrode and the fourth electrode; and forming at least one opening in the at least one insulating layer in a region adjacent to at least one of the first end and the second end of the light-emitting element.

[0022] In an implementation, forming the at least one opening may include dry etching at least one insulating layer in a vertical direction.

[0023] In an embodiment, the method may include continuously forming a third electrode and a fourth electrode. Forming at least one insulating layer may include at least one of the following: after forming the third electrode, forming an insulating layer configured to cover the third electrode and a region including the first end of the light emitting element; and after forming the fourth electrode, forming an insulating layer configured to cover the entire surface of a display region, the display region including a space throughout the light emitting element, the third electrode, and the fourth electrode.

[0024] In an embodiment, forming at least one opening may include: forming a first opening by etching at least one insulating layer in a region corresponding to a space between a first partition wall and a first end of the light emitting element, and forming a second opening by etching at least one insulating layer in a region corresponding to a space between a second partition wall and a second end of the light emitting element.

[0025] In an implementation, forming the at least one opening may include forming the first opening by etching at least one insulating layer in a region over the first partition wall, and forming the second opening by etching at least one insulating layer in a region over the second partition wall.

[0026] Beneficial Effects

[0027] In the display device and the method of manufacturing the display device according to various embodiments of the present disclosure, light efficiency of a pixel including a light emitting element may be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0029] Figure 2a and Figure 2b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0030] Figure 3a and Figure 3b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 4a and Figure 4b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0032] Figure 5 is a plan view showing a display device according to an embodiment of the present disclosure.

[0033] Figures 6a to 6e are circuit diagrams each showing a pixel according to an embodiment of the present disclosure.

[0034] Figure 7 is a plan view showing a pixel according to an embodiment of the present disclosure.

[0035] Figure 8a and Figure 8b are cross-sectional views each showing a pixel according to an embodiment of the present disclosure.

[0036] Fig. 9 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure.

[0037] Fig.10 as well as Figures 11a to 11c are cross-sectional views each showing a display device according to an embodiment of the present disclosure.

[0038] Fig.12 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure.

[0039] Fig.13 and Fig.14 are cross-sectional views each showing a display device according to an embodiment of the present disclosure.

[0040] Figures 15a to 15i are cross-sectional views sequentially illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0041] Fig.16 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure.

[0042] Fig.17 and Fig.18are cross-sectional views each showing a display device according to an embodiment of the present disclosure.

[0043] Fig.19 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure.

[0044] Fig. 20 and Fig.21 are cross-sectional views each showing a display device according to an embodiment of the present disclosure.

[0045] Figures 22a to 22g are cross-sectional views sequentially illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0046] Fig.23 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure.

[0047] Fig.24 and Fig.25 are cross-sectional views each showing a display device according to an embodiment of the present disclosure.

[0048] Figures 26a to 26c are cross-sectional views sequentially illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0049] Fig. 27 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure.

[0050] Fig.28 and Fig.29 are cross-sectional views each showing a display device according to an embodiment of the present disclosure.

[0051] Fig.30a and Fig.30b are cross-sectional views sequentially illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0052] Figure 31 to Figure 34 are cross-sectional views each showing a pixel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Reference will now be made in detail to various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below, but which may be modified in many different forms. However, the present disclosure is not limited to the following embodiments and may be modified in various forms.

[0054] In order to clearly explain the present disclosure, some elements in the drawings that are not directly related to the features of the present disclosure may be omitted. In addition, the sizes, proportions, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that in all the drawings, the same reference numerals are used to represent the same or similar elements, and repeated explanations will be omitted.

[0055] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It should also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the features, wholes, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. In addition, when a first component or part is disposed on a second component or part, the first component or part may not only be directly on the second component or part, but a third component or part may also be interposed between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they may change to opposite positions or directions depending on the viewing angle or direction. In addition, the singular form may include the plural form as long as it is not specifically mentioned in the sentence.

[0056] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 and 2 are a perspective view and a cross-sectional view each showing a light emitting element LD according to an embodiment of the present disclosure. Figures 1a to 3b A cylindrical rod-type light emitting element LD is illustrated, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0057] refer to Figure 1a and Figure 1b , the light emitting element LD according to the embodiment of the present disclosure may include a first conductive type semiconductor layer (or first semiconductor layer) 11, a second conductive type semiconductor layer (or second semiconductor layer) 13, and an active layer 12 interposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting element LD may include the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13 continuously stacked in a longitudinal direction.

[0058] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end EP1 and a second end EP2 in the longitudinal direction.

[0059] In an embodiment, one of the first and second conductive type semiconductor layers 11 and 13 may be disposed on the first end EP1 of the light emitting element LD. The other of the first and second conductive type semiconductor layers 11 and 13 may be disposed on the second end EP2 of the light emitting element LD.

[0060] In an embodiment, the light emitting element LD may be a rod-type light emitting element (also referred to as a "rod-type light emitting diode") manufactured in the form of a rod by an etching scheme or the like. In this specification, the term "rod-like shape" includes a rod-like shape and a bar-like shape, such as a cylindrical shape and a prism shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0061] In an embodiment, the light emitting element LD may have a small size in the range from nanometer level to micrometer level. For example, each light emitting element LD may have a diameter D (or width) and / or a length L in the range from nanometer level to micrometer level. However, in the present disclosure, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (e.g., display devices), and various devices (e.g., display devices) use light emitting devices using the light emitting element LD as light sources.

[0062] The first conductive type semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For example, the first conductive type semiconductor layer 11 may include an N-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material used to form the first conductive type semiconductor layer 11 is not limited thereto, and the first conductive type semiconductor layer 11 may be formed of various other materials.

[0063] The active layer 12 may be disposed on the first conductive type semiconductor layer 11 and have a single quantum well structure or a multiple quantum well (MQW) structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0064] The second conductive type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a type different from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a P-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a second conductive dopant such as Mg. However, the material for forming the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0065] When a voltage equal to or greater than a threshold voltage is applied to opposite ends of the light emitting element LD, the light emitting element LD can emit light by recombination of electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for various light emitting devices and pixels of a display device.

[0066] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12, and may also surround regions (or portions) of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose the first end EP1 and the second end EP2 disposed on the corresponding opposite ends of the light emitting element LD in the longitudinal direction (for example, the insulating film INF may expose the light emitting element LD and the like). Figure 1a and Figure 1b The top and bottom surfaces corresponding to the two base sides of the cylinder shown in FIG. 1 ) are not covered by the first end EP1 and the second end EP2 .

[0067] In an embodiment, the insulating film INF may include silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and titanium dioxide (TiO 2 ) at least one insulating material, but is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0068] In an embodiment, in addition to the first conductive type semiconductor layer 11, the active layer 12, the second conductive type semiconductor layer 13 and / or the insulating film INF, the light emitting element LD may further include additional other components. For example, the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers and / or one or more electrode layers disposed on one end of the first conductive type semiconductor layer 11, the active layer 12 and / or the second conductive type semiconductor layer 13.

[0069] For example, Figure 2a and Figure 2b As shown in FIG. 1 , the light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive type semiconductor layer 13. For example, the light emitting element LD may further include an electrode layer 14 disposed on the first end EP1.

[0070] In an embodiment, if Figure 3a and Figure 3b As shown in FIG. 1 , the light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive type semiconductor layer 11. For example, the light emitting element LD may include electrode layers 14 and 15 disposed on the first end EP1 and the second end EP2, respectively.

[0071] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. Each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, each of the electrode layers 14 and 15 may be formed of a transparent electrode material (alone or in combination) of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), an oxide or alloy thereof, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO). In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15.

[0072] In an embodiment, the insulating film INF may at least partially surround the peripheral surface of the electrode layers 14 and 15, or may not surround the peripheral surface thereof. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different conductivity types (e.g., P-type and N-type, respectively). For example, the insulating film INF may expose at least one region of the electrode layers 14 and 15 on the first end EP1 and the second end EP2 of the light emitting element LD. Alternatively, in an embodiment, the insulating film INF may not be provided in the light emitting element LD.

[0073] If the insulating film INF is provided to cover the surface of the light-emitting element LD (specifically, the peripheral surface of the active layer 12), the active layer 12 can be prevented from being short-circuited with at least one electrode not shown (for example, the first electrode or the second electrode of the pixel). Therefore, the electrical stability of the light-emitting element LD can be ensured. In the description of each embodiment of the present disclosure, the term "connecting (or connection)" may comprehensively refer to physical and / or electrical connection (connecting) (or connection). In addition, the term "connecting (or connection)" may comprehensively refer to direct or indirect connection (connecting) (or connection) and integral or non-integral connection (connecting) (or connection).

[0074] In addition, by forming the insulating film INF on the surface of the light emitting element LD, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In addition, if the insulating film INF is formed on the surface of each light emitting element LD, even in the case where a plurality of light emitting elements LD are arranged adjacent to each other, the light emitting element LD can be prevented from being unexpectedly short-circuited.

[0075] In an embodiment of the present disclosure, a surface treatment process may be performed to manufacture the light emitting element LD. For example, each light emitting element LD may be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and then provided to each emission region (e.g., the emission region of each pixel), the light emitting element LD may be uniformly dispersed in the solution rather than being unevenly aggregated.

[0076] In a non-limiting embodiment related hereto, the insulating film INF itself may be formed of a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed of a hydrophobic material may be formed on the insulating film INF. In an embodiment, the hydrophobic material may be a fluorine-containing material to exhibit hydrophobicity. In an embodiment, the hydrophobic material may be applied to the light emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available fluorine-containing material such as Teflon. TM or Cytop TM or corresponding materials.

[0077] The above-mentioned light-emitting element LD can be used as a light source in different types of light-emitting devices including pixels of a display device. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD each having a size ranging from nanometers to micrometers) can be arranged in each pixel area of ​​a display panel for forming a screen of a display device, and form a light source (or light source unit) of the corresponding pixel. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in other types of devices (such as lighting devices) that require a light source.

[0078] Figure 4a and Figure 4b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element LD according to an embodiment of the present disclosure. Figure 4a and Figure 4b Shows that with Figures 1a to 3b The structure of the light emitting element LD shown in the figure is different from that of the light emitting element LD, and for example, a light emitting element LD having a core-shell structure is shown. In other words, the type, structure and / or shape of the light emitting element LD according to the embodiment of the present disclosure may be changed in various ways. Figure 4a and Figure 4b In the description of the embodiments of the present invention, the same reference numerals are used to represent Figures 1a to 3b Components similar or identical (or corresponding) to those of the embodiments of the present invention, and their detailed description will be omitted.

[0079] refer to Figure 4a and Figure 4b , the light emitting element LD according to an embodiment of the present disclosure may include a first conductive type semiconductor layer 11, a second conductive type semiconductor layer 13, and an active layer 12 interposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. In an embodiment, the first conductive type semiconductor layer 11 may be disposed in a central region of the light emitting element LD, and the active layer 12 may be disposed on a surface of the first conductive type semiconductor layer 11 to surround at least one region of the first conductive type semiconductor layer 11. The second conductive type semiconductor layer 13 may be disposed on a surface of the active layer 12 to surround at least one region of the active layer 12.

[0080] The light emitting element LD may further selectively include an electrode layer 14 and / or an insulating film INF, the electrode layer 14 being configured to surround at least one region of the second conductive type semiconductor layer 13, and the insulating film INF being disposed on the outermost surface of the light emitting element LD. For example, the light emitting element LD may further include an electrode layer 14 disposed on the surface of the second conductive type semiconductor layer 13 to surround at least one region of the second conductive type semiconductor layer 13, and an insulating film INF disposed on the surface of the electrode layer 14 to surround at least one region of the electrode layer 14.

[0081] In an implementation, an insulating film INF may be disposed on the surface of the light emitting element LD to cover a portion of the outer peripheral surface of the first conductive type semiconductor layer 11 and the outer peripheral surface of the electrode layer 14. The insulating film INF may include a transparent insulating material.

[0082] In an embodiment, after the insulating film INF is formed to cover the entire peripheral surface of the electrode layer 14 included in the light emitting element LD, the insulating film INF can be partially removed to expose a region of the electrode layer 14 for electrical connection to an unillustrated electrode (e.g., a first electrode of a pixel).

[0083] The light emitting element LD according to the aforementioned embodiment may be a core-shell light emitting element (also referred to as a "core-shell light emitting diode") manufactured by a growth scheme, etc. For example, the light emitting element LD may have a core-shell structure including a first conductive type semiconductor layer 11, an active layer 12, a second conductive type semiconductor layer 13, an electrode layer 14, and an insulating film INF that are continuously arranged in a direction from the center to the periphery. In an embodiment, the light emitting element LD may not include at least one of the electrode layer 14 and the insulating film INF.

[0084] In an embodiment, the light emitting element LD may have a polygonal pyramid shape extending in one direction. For example, at least one region of the light emitting element LD may have a hexagonal pyramid shape. However, the shape of the light emitting element LD may be changed in various ways.

[0085] If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end EP1 and a second end EP2 in the longitudinal direction. In an embodiment, one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 (or an electrode layer configured to surround any one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13) is disposed on the first end EP1 of the light emitting element LD. The other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 (or an electrode layer configured to surround the other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13) may be disposed on the second end EP2 of the light emitting element LD.

[0086] In an embodiment of the present disclosure, the light emitting element LD may be a light emitting diode having a core-shell structure and having an ultra-small size, wherein the first end EP1 protrudes in a polygonal pyramid shape (e.g., a hexagonal pyramid shape). For example, the light emitting element LD may have a shape corresponding to a combination of a hexagonal pyramid and a hexagonal prism, and may have a small size ranging from nanometer level to micrometer level (e.g., a width W and / or a length L corresponding to nanometer level or micrometer level). Here, the size and shape of the light emitting element LD may be changed according to the design conditions of various devices (e.g., display devices) that employ the light emitting element LD as a light source.

[0087] In an embodiment, the opposite ends of the first conductive type semiconductor layer 11 may have a shape that protrudes in the longitudinal direction of the light emitting element LD. The shapes of the opposite ends of the first conductive type semiconductor layer 11 that protrude outward may be different from each other. For example, the first end of the opposite ends of the first conductive type semiconductor layer 11 that is disposed at an upper position may have a pyramid shape (e.g., a hexagonal pyramid shape), the width of which decreases upward to form a vertex. In addition, the second end of the opposite ends of the first conductive type semiconductor layer 11 that is disposed at a lower position may have a prism shape (e.g., a hexagonal prism shape) having a constant width, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first conductive type semiconductor layer 11 may have a polygonal or stepped cross-section, the width of which gradually decreases downward. The shapes of the opposite ends of the first conductive type semiconductor layer 11 may be changed in various ways according to the embodiment.

[0088] The first conductive type semiconductor layer 11 may be disposed in the core of the light emitting element LD, that is, in the central (or middle) portion of the light emitting element LD. In addition, the light emitting element LD may have a shape corresponding to the shape of the first conductive type semiconductor layer 11. For example, if the first conductive type semiconductor layer 11 has a hexagonal pyramid shape on its upper end, the light emitting element LD may have a hexagonal pyramid shape on its upper end (e.g., the first end EP1).

[0089] The active layer 12 may be disposed and / or formed in a shape surrounding the outer peripheral surface of the first conductive type semiconductor layer 11. For example, the active layer 12 may be disposed and / or formed in a shape surrounding a region of the first conductive type semiconductor layer 11 except for one end (e.g., the next end) of the first conductive type semiconductor layer 11 relative to the longitudinal direction of the light emitting element LD.

[0090] The second conductive type semiconductor layer 13 may be disposed and / or formed in a shape surrounding the outer peripheral surface of the active layer 12, and include a semiconductor layer having a type different from that of the first conductive type semiconductor layer 11. For example, in the case where the first conductive type semiconductor layer 11 includes an N-type semiconductor layer, the second conductive type semiconductor layer 13 may include a P-type semiconductor layer.

[0091] In an embodiment, the light emitting element LD may further include an electrode layer 14 surrounding the outer peripheral surface of the second conductive type semiconductor layer 13. The electrode layer 14 may be an ohmic contact electrode electrically connected to the second conductive type semiconductor layer 13, but the present disclosure is not limited thereto.

[0092] As described above, the light emitting element LD may have a core-shell structure whose opposite ends protrude outward, and may include a first conductive type semiconductor layer 11 disposed in a central portion thereof, an active layer 12 surrounding the first conductive type semiconductor layer 11, and a second conductive type semiconductor layer 13 surrounding the active layer 12. In addition, the light emitting element LD may further selectively include an electrode layer 14 surrounding the second conductive type semiconductor layer 13. One end of the electrode layer 14 may be disposed on the first end EP1 of the light emitting element LD, and one end of the first conductive type semiconductor layer 11 may be disposed on the second end EP2 of the light emitting element LD.

[0093] The above-mentioned light-emitting element LD can be used as a light source in different types of light-emitting devices including pixels. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD each having a size ranging from nanometers to micrometers) can be arranged in each pixel area of ​​the display panel to form a light source (or light source unit) of the corresponding pixel. In an embodiment, each pixel may include at least one rod-type light-emitting element LD or at least one core-shell light-emitting element LD, or a combination of a rod-type light-emitting element LD and a core-shell light-emitting element LD. In an embodiment, each pixel may include other light-emitting elements having a type and / or shape different from the type and / or shape of the rod-type light-emitting element LD or the core-shell light-emitting element LD.

[0094] Figure 5 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 5 A display device (specifically, a display panel PNL provided in the display device) is shown as a display device that can be used Figures 1a to 4b The light emitting element LD described in the embodiment is an example of a device as a light source. For example, each pixel unit PXU of the display panel PNL and each pixel used to form the pixel unit PXU may include a plurality of light emitting elements LD. However, the present disclosure is not limited thereto. For example, in an embodiment, at least one pixel may include a single light emitting element LD.

[0095] For the sake of explanation, Figure 5 The structure of the display panel PNL according to the embodiment is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided in the display panel PNL.

[0096] refer to Figure 5 , the display panel PNL according to an embodiment of the present disclosure may include a base layer BSL and a plurality of pixels disposed on the base layer BSL. The pixels may include a first color pixel PXL1, a second color pixel PXL2, and / or a third color pixel PXL3. In the following embodiments, the term "pixel (pixel) PXL" or "pixels (pixels) PXL" will be used to collectively designate any one pixel or two or more types of pixels among the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3.

[0097] In detail, the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA except the display area DA. The pixels PXL may be disposed in the display area DA on the base layer BSL.

[0098] In an embodiment, the display area DA may be disposed in a central area of ​​the display panel PNL, and the non-display area NDA may be disposed in a peripheral area of ​​the display panel PNL in a manner surrounding the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed. The display area DA may form a screen on which an image is displayed.

[0099] The base layer BSL may form a substrate of the display panel PNL. In an embodiment, the base layer BSL may be a rigid substrate or a rigid film or a flexible substrate or a flexible film, and its material or properties are not particularly limited. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and its material and / or properties are not particularly limited.

[0100] In addition, the base layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the base layer BSL may be a transparent, translucent, opaque or reflective substrate.

[0101] One area of ​​the base layer BSL may be defined as a display area DA in which the pixels PXL are disposed, and another area thereof may be defined as a non-display area NDA. For example, the base layer BSL may include a display area DA including a plurality of pixel areas in which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuits connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0102] A plurality of pixels PXL are dispersed and arranged in the display area DA. For example, the plurality of pixels PXL may be regularly arranged in the display area DA in a stripe or PenTile arrangement, etc. The arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in the display area DA in various structures and / or schemes.

[0103] In an embodiment, two or more types of pixels PXL emitting light of different colors may be provided in the display area DA. For example, a first color pixel PXL1 configured to emit light of a first color, a second color pixel PXL2 configured to emit light of a second color, and a third color pixel PXL3 configured to emit light of a third color may be regularly arranged in the display area DA. At least one first color pixel PXL1, at least one second color pixel PXL2, and at least one third color pixel PXL3 disposed adjacent to each other may form one pixel unit PXU that may emit light of different colors.

[0104] In an embodiment, each first color pixel PXL1 may be a red pixel configured to emit red light, each second color pixel PXL2 may be a green pixel configured to emit green light, and each third color pixel PXL3 may be a blue pixel configured to emit blue light. In an embodiment, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may respectively include a light emitting element LD associated with the first color, a light emitting element LD associated with the second color, and a light emitting element LD associated with the third color as a light source, so that the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may respectively emit light of the first color, light of the second color, and light of the third color. In an embodiment, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may respectively include a light emitting element LD having the same color, and a color filter and / or a light conversion layer having different colors may be provided on each light emitting element LD, so that the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may respectively emit light of the first color, light of the second color, and light of the third color.

[0105] The color, type, and / or number of the pixels PXL forming each pixel unit PXU are not particularly limited. For example, the color of light emitted from each pixel PXL may be changed in various ways.

[0106] Each pixel PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first power source and a second power source). Figures 1a to 3b At least one light emitting element LD of any one of the embodiments of the present invention, for example, at least one ultra-small rod-type light emitting element LD having a small size corresponding to the nanometer level or the micrometer level. In an embodiment, each of the pixels PXL may include a Figure 4a and Figure 4b The at least one light emitting element LD of the embodiment of the present invention may be, for example, at least one ultra-small core-shell light emitting element LD having a small size corresponding to the nanometer level or the micrometer level. In addition, different types of light emitting elements LD may be used as the light source of the pixel PXL.

[0107] In an embodiment, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving scheme of the pixel PXL applicable to the display device according to the present disclosure is not particularly limited. For example, each pixel PXL may have the same structure as a pixel for a passive or active light-emitting display device, and the passive or active light-emitting display device has various known structures and / or may operate with various known driving schemes.

[0108] Figures 6a to 6e are circuit diagrams each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figures 6a to 6e Various embodiments of the pixel PXL applicable to an active display device are shown. However, the types of the pixel PXL and the display device to which the embodiments of the present disclosure can be applied are not limited thereto.

[0109] In an embodiment, Figures 6a to 6e The pixel PXL shown in FIG. 1 may be arranged in Figure 5 Any one of the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 in the display panel PNL. In addition, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may have substantially the same or similar structures.

[0110] refer to Figure 6a The pixel PXL according to an embodiment of the present disclosure may include a light source unit LSU configured to generate light having brightness corresponding to a data signal. The pixel PXL may further selectively include a pixel circuit PXC configured to drive the light source unit LSU.

[0111] The light source unit LSU may include a first electrode ELT1 (also referred to as a "first pixel electrode" or a "first alignment electrode"), a second electrode ELT2 (also referred to as a "second pixel electrode" or a "second alignment electrode"), and at least one light emitting element LD connected between the first electrode ELT1 and the second electrode ELT2, for example, a plurality of light emitting elements LD. In an embodiment, the first electrode ELT1 may be connected to a first power source VDD through a pixel circuit PXC and a first power line PL1. In other words, the light emitting elements LD may be connected in parallel with each other in the same direction between the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first electrode ELT1 may be an anode electrode, and the second electrode ELT2 may be a cathode electrode, but the present disclosure is not limited thereto.

[0112] Each of the light emitting elements LD may include a P-type terminal connected to a first power source VDD through a first electrode ELT1 and / or a pixel circuit PXC and an N-type terminal connected to a second power source VSS through a second electrode ELT2. In other words, the light emitting element LD may be connected in parallel between the first electrode ELT1 and the second electrode ELT2 in a forward direction. In this way, each of the light emitting elements LD connected between the first power source VDD and the second power source VSS in a forward direction may form an effective light source. A group of effective light sources may form a light source unit LSU of a pixel PXL.

[0113] In an embodiment, the first power supply VDD and the second power supply VSS may provide voltages having different potentials so that the light emitting element LD may emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, at least during the emission period of the pixel PXL, the difference between the voltages of the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting element LD or a voltage greater than that.

[0114] In an embodiment, a first end (e.g., a P-type end) of the light emitting element LD forming each light source unit LSU may be commonly connected to the pixel circuit PXC through one electrode of the light source unit LSU (e.g., the first electrode ELT1 of each pixel PXL), and connected to the first power source VDD through the pixel circuit PXC and the first power line PL1. A second end (e.g., an N-type end) of the light emitting element LD may be commonly connected to the second power source VSS through another electrode of the light source unit LSU (e.g., the second electrode ELT2 of each pixel PXL) and the second power line PL2.

[0115] The light emitting element LD of the light source unit LSU may emit light having a brightness corresponding to the driving current supplied thereto by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply the light source unit LSU with a driving current corresponding to the grayscale value of the data of the corresponding frame. The driving current supplied to the light source unit LSU may be divided into a portion flowing to the light emitting element LD connected in the forward direction. Therefore, each of the light emitting elements LD may emit light having a brightness corresponding to the current applied thereto, so that the light source unit LSU may emit light having a brightness corresponding to the driving current.

[0116] Despite Figure 6a , the illustration of the light source unit LSU focuses on the light emitting element LD forming each effective light source, but in an embodiment, in addition to the light emitting element LD, the light source unit LSU may also include at least one invalid light source. For example, the light source unit LSU may also include at least one light emitting element (hereinafter, referred to as "invalid light source") connected between the first electrode ELT1 and the second electrode ELT2 in opposite directions or not completely connected between the first electrode ELT1 and the second electrode ELT2. Even in the case where a predetermined driving voltage (e.g., a driving voltage in the forward direction) is applied between the first electrode ELT1 and the second electrode ELT2, each invalid light source remains disabled. Therefore, current does not substantially flow through the invalid light source.

[0117] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed on the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0118] The first transistor T1 (also referred to as a "driving transistor") is connected between the first power source VDD and the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0119] The second transistor T2 (also referred to as a "switching transistor") is connected between the data line Dj and the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is provided from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj.

[0120] During each frame period, a data signal of a corresponding frame is supplied to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged in the storage capacitor Cst.

[0121] One electrode of the storage capacitor Cst is connected to the first power source VDD, and the other electrode thereof is connected to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to a data signal supplied to the first node N1 during each frame period.

[0122] Despite Figure 6a The transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are shown as P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0123] For example, Figure 6b As shown in , both the first transistor T1 and the second transistor T2 may be formed of N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the data line Dj to the pixel PXL in each frame period may be a high-level voltage (also referred to as a "gate high voltage"). Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage having a voltage with a value similar to that of the gate high voltage. Figure 6a The voltage level of the embodiment is opposite to the level of the voltage level. For example, in Figure 6b In an embodiment, as the grayscale value to be expressed increases, a data signal with a higher voltage may be provided.

[0124] In an embodiment, the interconnection position between the pixel circuit PXC and the light source unit LSU may be changed. Figure 6b As shown in , in the case where both the first transistor T1 and the second transistor T2 forming the pixel circuit PXC are N-type transistors, the pixel circuit PXC may be connected between the light source unit LSU and the second power supply VSS, and the storage capacitor Cst may be connected between the first node N1 and the second power supply VSS. However, the present disclosure is not limited thereto. For example, in an embodiment, even if the pixel circuit PXC is formed by an N-type transistor, the pixel circuit PXC may be connected between the first power supply VDD and the light source unit LSU, and the storage capacitor Cst may be connected between the first node N1 and the first power supply VDD.

[0125] In addition to the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) that vary according to the transistor types, Figure 6b The pixel PXL shown in FIG. 1 is similar in configuration and operation to the Figure 6a The pixels PXL are basically similar. Therefore, Figure 6b A detailed description of the pixel PXL.

[0126] The structure of the pixel circuit PXC is not limited to Figure 6a and Figure 6b In other words, the pixel circuit PXC may be formed by a well-known pixel circuit that may have various structures and / or be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a well-known pixel circuit that may have various structures and / or be operated by various driving schemes. Figure 6c The embodiment shown in FIG. 1 is configured in the same manner.

[0127] refer to Figure 6c , the pixel circuit PXC can be connected not only to the scan line Si of the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL arranged in the i-th row of the display area DA can also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to the third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0128] The first transistor T1 is connected between the first power source VDD and the light source unit LSU. For example, the first electrode (e.g., source electrode) of the first transistor T1 may be connected to the first power source VDD via the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., drain electrode) of the first transistor T1 may be connected to the first electrode ELT1 of the light source unit LSU (e.g., the first pixel electrode of the corresponding pixel PXL) via the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control the driving current to be provided to the light source unit LSU in response to the voltage of the first node N1.

[0129] The second transistor T2 is connected between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is provided from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the data line Dj may be transmitted to the first transistor T1.

[0130] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is provided from the scan line Si, the third transistor T3 can be turned on to connect the first transistor T1 in a diode form.

[0131] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When the scan signal of the gate-on voltage is provided to the i-1th scan line Si-1, the fourth transistor T4 can be turned on so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. In an embodiment, when the first transistor T1 is a P-type transistor, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 can be equal to or less than the lowest voltage of the data signal.

[0132] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having a gate cut-off voltage (for example, a high level voltage) is provided to the emission control line Ei, the fifth transistor T5 can be turned off, and the fifth transistor T5 can be turned on in other cases.

[0133] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having the gate-off voltage is provided to the emission control line Ei, the sixth transistor T6 may be turned off, and the sixth transistor T6 may be turned on in other cases.

[0134] The seventh transistor T7 is connected between the first electrode ELT1 of the light source unit LSU and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage (subsequent horizontal pixel row), for example, to the i+1th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode ELT1 of the light source unit LSU. In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode ELT1 of the light source unit LSU may be initialized. The control signal for controlling the operation of the seventh transistor T7 may be changed in various ways. For example, in an embodiment, the gate electrode of the seventh transistor T7 may be connected to the corresponding scan line, that is, the i-th scan line Si. In this case, when a scan signal having a gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode ELT1 of the light source unit LSU.

[0135] The storage capacitor Cst may be connected between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0136] Despite Figure 6c , the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC are shown as being formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0137] although Figures 6a to 6c 1 shows an embodiment in which all effective light sources (i.e., light emitting elements LD in the forward direction) constituting each light source unit LSU are connected in parallel to each other, but the present disclosure is not limited thereto. Figure 6d and Figure 6e As shown in , the light source unit LSU of each pixel PXL may be configured to include a series structure. Figure 6d and Figure 6e In the following description of the implementation method of Figures 6a to 6c Detailed description of components similar or identical to those of the embodiments of the present invention (e.g., pixel circuit PXC).

[0138] refer to Figure 6d, the light source unit LSU may include at least two light emitting elements connected in series with each other. For example, the light source unit LSU may include a first-level light emitting element LDs1, a second-level light emitting element LDs2, and a third-level light emitting element LDs3 connected in series between a first power source VDD and a second power source VSS in a forward direction and thus forming each effective light source. Hereinafter, in the case of specifying a specific light emitting element among the first-level light emitting element LDs1, the second-level light emitting element LDs2, and the third-level light emitting element LDs3, the corresponding light emitting element will be referred to as "first-level light emitting element LDs1", "second-level light emitting element LDs2", or "third-level light emitting element LDs3". The term "light emitting element LD" or "light emitting elements LD" will be used to arbitrarily specify at least one of the first-level light emitting element LDs1, the second-level light emitting element LDs2, and the third-level light emitting element LDs3, or collectively specify the first-level light emitting element LDs1, the second-level light emitting element LDs2, and the third-level light emitting element LDs3.

[0139] The P-type end of the first-stage light emitting element LDs1 may be connected to the first power source VDD through the first electrode ELT1 of the light source unit LSU, the pixel circuit PXC, and / or the first power line PL1. The N-type end of the first-stage light emitting element LDs1 may be connected to the P-type end of the second-stage light emitting element LDs2 through the first intermediate electrode IET1. The P-type end of the second-stage light emitting element LDs2 may be connected to the N-type end of the first-stage light emitting element LDs1. The N-type end of the second-stage light emitting element LDs2 may be connected to the P-type end of the third-stage light emitting element LDs3 through the second intermediate electrode IET2. The P-type end of the third-stage light emitting element LDs3 may be connected to the N-type end of the second-stage light emitting element LDs2. The N-type end of the third-stage light emitting element LDs3 may be connected to the second power source VSS through the second electrode ELT2 of the light source unit LSU and the second power line PL2. In this way, the first-stage light emitting element LDs1, the second-stage light emitting element LDs2, and the third-stage light emitting element LDs3 may be continuously connected in series between the first electrode ELT1 and the second electrode ELT2 of the light source unit LSU.

[0140] Despite Figure 6d , the light emitting elements LD are connected to form a three-stage series structure, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, two light emitting elements LD may be connected to form a two-stage series structure, or four or more light emitting elements LD may be connected to form a four-stage or more series structure.

[0141] When it is assumed that the same brightness is expressed using light emitting elements LD having the same conditions (e.g., the same size and / or number), in the light source unit LSU having a structure in which the light emitting elements LD are connected in series, the voltage applied between the first electrode ELT1 and the second electrode ELT2 can be increased, and the amount of driving current flowing to the light source unit LSU can be reduced, compared to the light source unit LSU having a structure in which the light emitting elements LD are connected in parallel. Therefore, in the case where the series connection structure of the light emitting elements LD is used for the light source unit LSU forming each pixel PXL, when the display device is driven, the panel current flowing through the display panel PNL can be reduced.

[0142] In an embodiment, at least one series stage may include a plurality of light emitting elements LD connected in parallel to each other. In this case, the light source unit LSU may be formed by a series / parallel combination structure. For example, the light source unit LSU may be as follows: Figure 6e Configured as shown in the embodiment.

[0143] refer to Figure 6e , at least one series connection stage forming the light source unit LSU may include a plurality of light emitting elements LD connected in parallel with each other in the forward direction. For example, the light source unit LSU may include a plurality of first-stage light emitting elements LDs1 arranged in a first series connection stage (also referred to as a "first stage" or a "first row"), a plurality of second-stage light emitting elements LDs2 arranged in a second series connection stage (also referred to as a "second stage" or a "second row") after the first series connection stage, and at least one third-stage light emitting element LDs3 arranged in a third series connection stage (also referred to as a "third stage" or a "third row") after the second series connection stage.

[0144] Although already Figure 6e , a light source unit LSU formed of light emitting elements LD arranged in three series stages is shown, but the present disclosure is not limited thereto. For example, the light source unit LSU may include a plurality of light emitting elements LD arranged in only two series stages or may include a plurality of light emitting elements LD dispersed in four or more series stages. In addition, the number of light emitting elements LD connected in the forward direction in each series stage may be one or more and may be changed to various values. In an embodiment, the light source unit LSU is arranged in the display area ( Figure 5The number of light-emitting elements LD included in the pixels PXL in the DA) may be the same or similar to each other. For example, in the step of providing the light-emitting element LD to each pixel area (specifically, the emission area of ​​each pixel PXL) for forming each pixel PXL, the light-emitting element ink (also referred to as "light-emitting element solution") including the light-emitting element LD may be controlled to be uniformly applied to the emission area of ​​each pixel PXL, and the electric field may be controlled to be applied to each pixel PXL under the same conditions, so that the light-emitting element LD may be aligned. Therefore, the pixel PXL may be formed so that the pixel PXL includes the same or similar number of light-emitting elements LD, thereby making the emission characteristics of the corresponding pixel PXL uniform.

[0145] In an embodiment, each pixel PXL may further include at least one reverse light emitting element LDrv disposed in at least one series stage. For example, at least one of the plurality of series stages may further include at least one reverse light emitting element LDrv connected in a direction opposite to that of the light emitting element LD.

[0146] Even in the case where the reverse light-emitting element LDrv is connected to at least one series stage, if at least one effective light source (e.g., the first-stage light-emitting element LDs1, the second-stage light-emitting element LDs2, and / or the third-stage light-emitting element LDs3) connected to the series stage in the forward direction is provided, the driving current of the pixel PXL can flow continuously via the series stage. Therefore, the light source unit LSU can emit light with a brightness corresponding to the driving current.

[0147] As described in the foregoing embodiments, each light source unit LSU may include a plurality of light emitting elements LD connected between a first power source VDD and a second power source VSS in a forward direction and forming a corresponding effective light source. In addition, the connection structure between the light emitting elements LD may be changed in various ways according to the embodiments. For example, the light emitting elements LD may be connected only in series with each other or only in parallel with each other or in a series / parallel combination structure.

[0148] As described above, the pixel PXL may include a pixel circuit PXC and / or a light source unit LSU that may have various structures. The structure of the pixel PXL that may be applied to the present disclosure is not limited to Figures 6a to 6e, and each pixel PXL may have various well-known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a well-known pixel circuit that may have various structures and / or be operated by various driving schemes. In an embodiment of the present disclosure, each pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode ELT1 and the second electrode ELT2 may be directly connected to the scan line Si, the data line Dj, the power line and / or the control line.

[0149] Figure 7 is a plan view showing a pixel PXL according to an embodiment of the present disclosure. In the embodiment, Figure 7 The structure of the pixel PXL is shown with the light source unit LSU focused on the pixel PXL. In an embodiment, each pixel PXL may further selectively include a circuit element connected to the light source unit LSU (eg, a plurality of circuit elements forming each pixel circuit PXC).

[0150] In an embodiment, Figure 7 The pixel PXL shown in FIG. 1 may be Figures 5 to 6e Any one of the pixels PXL shown in , but the present disclosure is not limited thereto. For example, Figure 7 Each pixel PXL shown in FIG. 1 may include Figures 6a to 6c . However, the present disclosure is not limited thereto. For example, in an embodiment, a light source unit LSU having a series / parallel combination structure may be formed by changing the arrangement and / or connection structure of the electrodes and the light emitting elements LD forming each light source unit LSU. Alternatively, in an embodiment, at least one pixel PXL provided in the display area DA may include only one light emitting element LD connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction.

[0151] also, Figure 7 An embodiment in which each light source unit LSU is connected to a predetermined power line (e.g., a first power line PL1 and / or a second power line PL2), a circuit element (e.g., at least one circuit element forming a pixel circuit PXC), and / or a signal line (e.g., a scan line Si and / or a data line Dj) through a first contact hole CH1 and a second contact hole CH2 is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the first electrode ELT1 and the second electrode ELT2 of each pixel PXL may be directly connected to a predetermined power line and / or a signal line without using a contact hole and / or an intermediate line.

[0152] refer to Figures 5 to 7, the pixel PXL according to the embodiment of the present disclosure may include a first electrode ELT1 and a second electrode ELT2 disposed in each emission area EMA and at least one light emitting element LD disposed between the first electrode ELT1 and the second electrode ELT2 (for example, a plurality of light emitting elements LD connected in parallel between the first electrode ELT1 and the second electrode ELT2). In addition, the pixel PXL may also selectively include a first electrode line ELI1 (also referred to as a "first connection electrode" or a "first alignment line") and a first contact hole CH1 configured to connect the first electrode ELT1 to the first power line PL1, a second electrode line ELI2 (also referred to as a "second connection electrode" or a "second alignment line") and a second contact hole CH2 configured to connect the second electrode ELT2 to the second power line PL2, a first partition wall (or a first bank pattern) PW1 and a second partition wall (or a second bank pattern) PW2 respectively overlapping the first electrode ELT1 and the second electrode ELT2, and at least one of a first contact electrode CNE1 (also referred to as a "third electrode") and a second contact electrode CNE2 (also referred to as a "fourth electrode") configured to electrically connect the light emitting element LD between the first electrode ELT1 and the second electrode ELT2. In an embodiment, first and second partition walls PW1 and PW2 , first and second electrodes ELT1 and ELT2 , light emitting elements LD and / or first and second contact electrodes CNE1 and CNE2 , etc. may form a light source unit LSU of a pixel PXL according to an embodiment of the present disclosure.

[0153] The first electrode ELT1 and the second electrode ELT2 may be arranged at positions spaced apart from each other in each pixel region in which the corresponding pixel PXL is arranged and / or formed, and specifically, may be arranged in the emission region EMA of the corresponding pixel PXL. In an embodiment, each pixel region may comprehensively represent a pixel circuit region in which a circuit element for forming the corresponding pixel PXL is arranged and an emission region EMA in which the light source unit LSU of the pixel PXL is arranged. The emission region EMA may be a region in which a light emitting element LD (specifically, an effective light source effectively connected between the first electrode ELT1 and the second electrode ELT2) of the light source unit LSU forming each pixel PXL is arranged. In addition, a predetermined electrode (e.g., the first electrode ELT1 and the second electrode ELT2 and / or the first contact electrode CNE1 and the second contact electrode CNE2) connected to the light emitting element LD or an area of ​​the electrode may be arranged in the emission region EMA. The emission region EMA may be surrounded by a light shielding dam and / or a reflective dam (also referred to as a "pixel defining layer"), which is formed between the pixels PXL to define each pixel region and the emission region EMA formed in the pixel region. For example, a dam surrounding the emission area EMA may be provided around the emission area EMA.

[0154] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed in parallel in each emission area EMA at positions spaced apart from each other by a predetermined distance in the first direction DR1.

[0155] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a rod shape extending in any one direction. For example, each of the first electrode ELT1 and the second electrode ELT2 may have a rod shape extending in a second direction DR2 intersecting with the first direction DR1 (e.g., perpendicular to the first direction DR1). However, the present disclosure is not limited thereto. For example, the shape, orientation, and / or relative arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0156] In addition, one or more first electrodes ELT1 and second electrodes ELT2 may be disposed in each emission area EMA, and the number of first electrodes ELT1 and second electrodes ELT2 disposed in the emission area EMA is not particularly limited. For example, a plurality of first electrodes ELT1 extending in the second direction DR2 and parallel to each other may be disposed in each emission area EMA. At least one second electrode ELT2 facing each first electrode ELT1 may be disposed in each emission area EMA. For example, in each emission area EMA, one second electrode ELT2 may be disposed between two first electrodes ELT1, and a plurality of second electrodes ELT2 may be disposed to correspond to the plurality of first electrodes ELT1, respectively.

[0157] In an embodiment, the first electrode ELT1 may be electrically connected to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., a first power line PL1) and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line) through a first electrode line ELI1 and / or a first contact hole CH1. In an embodiment, the first electrode ELT1 may be electrically connected to a predetermined circuit element disposed thereunder through the first electrode line ELI1 and the first contact hole CH1, and electrically connected to the first line through the circuit element. The first line may be a first power line PL1 for supplying a voltage of a first power supply VDD, but the present disclosure is not limited thereto. For example, in an embodiment, the first line may be a signal line through which a predetermined first drive signal (e.g., a scan signal, a data signal, or a predetermined control signal) may be provided.

[0158] Alternatively, in an embodiment, the first electrode ELT1 may be directly connected to a predetermined power line or signal line without passing through the first electrode line ELI1, the first contact hole CH1 and / or the circuit element. In this case, the first electrode ELT1 may be integrally or non-integrally connected to the predetermined power line or signal line.

[0159] In an embodiment, the first electrode ELT1 and the first electrode line ELI1 may extend in different directions in each pixel region. For example, when the first electrode line ELI1 extends in a first direction DR1, the first electrode ELT1 may extend in a second direction DR2 intersecting the first direction DR1.

[0160] In an embodiment, the first electrode ELT1 and the first electrode line ELI1 may be integrally connected to each other. For example, the first electrode ELT1 may branch from the first electrode line ELI1 in at least one manner. In the case where the first electrode ELT1 and the first electrode line ELI1 are integrally connected to each other, the first electrode line ELI1 may be considered as a region of the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in an embodiment, the first electrode ELT1 and the first electrode line ELI1 may be formed separately from each other and connected to each other through at least one contact hole, a through hole, or the like.

[0161] In an embodiment, the second electrode ELT2 may be electrically connected to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., a second power line PL2) and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line) through a second electrode line ELI2 and / or a second contact hole CH2. For example, the second electrode ELT2 may be electrically connected to a second line disposed thereunder through a second electrode line ELI2 and a second contact hole CH2. The second line may be a second power line PL2 for providing a voltage of a second power supply VSS, but the present disclosure is not limited thereto. For example, in an embodiment, the second line may be a signal line through which a predetermined second drive signal (e.g., a scan signal, a data signal, or a predetermined control signal) is provided.

[0162] In an embodiment, the second electrode ELT2 may be directly connected to a predetermined power line or signal line without passing through the second electrode line ELI2 and / or the second contact hole CH2. In this case, the second electrode ELT2 may be integrally or non-integrally connected to the predetermined power line or signal line.

[0163] In an embodiment, the second electrode ELT2 and the second electrode line ELI2 may extend in different directions. For example, when the second electrode line ELI2 extends in the first direction DR1, the second electrode ELT2 may extend in the second direction DR2 intersecting the first direction DR1.

[0164] In an embodiment, the second electrode ELT2 and the second electrode line ELI2 may be integrally connected to each other. For example, the second electrode ELT2 may branch from the second electrode line ELI2 in at least one manner. In the case where the second electrode ELT2 and the second electrode line ELI2 are integrally connected to each other, the second electrode line ELI2 may be considered as a region of the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in an embodiment, the second electrode ELT2 and the second electrode line ELI2 may be formed separately from each other and connected to each other through at least one contact hole, a through hole, etc.

[0165] Here, during the process of forming the pixel PXL, specifically, before the alignment of the light emitting element LD is completed, the first electrodes ELT1 of the pixels PXL disposed in the display area DA may be connected to each other, and the second electrodes ELT2 of the pixels PXL may be connected to each other. In the step of aligning the light emitting element LD, a first alignment signal (or a first alignment voltage) and a second alignment signal (or a second alignment voltage) may be provided to the first electrode ELT1 and the second electrode ELT2, respectively. For example, an AC alignment signal may be provided to any one of the first electrode ELT1 and the second electrode ELT2, and an alignment voltage having a constant voltage level (e.g., a ground voltage) may be provided to the other of the first electrode ELT1 and the second electrode ELT2.

[0166] In other words, in the step of aligning the light emitting element LD, a predetermined alignment signal may be applied to the first electrode ELT1 and the second electrode ELT2, so that an electric field may be formed between the first electrode ELT1 and the second electrode ELT2. The light emitting element LD provided to each pixel region (specifically, the emission region EMA of each pixel PXL) may be self-aligned between the first electrode ELT1 and the second electrode ELT2 by the electric field. After the alignment of the light emitting element LD is completed, the connection between the first electrode ELT1 and / or the connection between the second electrode ELT2 may be disconnected between the pixels PXL, so that the pixels PXL may be driven individually.

[0167] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer or multi-layer structure. For example, each first electrode ELT1 may include at least one reflective electrode layer, and may also selectively include at least one transparent electrode layer and / or a conductive capping layer. Similarly, each second electrode ELT2 may include at least one reflective electrode layer, and may also selectively include at least one transparent electrode layer and / or a conductive capping layer.

[0168] The first partition wall PW1 may be disposed under or below each first electrode ELT1 to overlap with the first electrode ELT1. For example, the width of the first partition wall PW1 may be smaller than the width of each first electrode ELT1 and may be disposed under or below the first electrode ELT1. If the first partition wall PW1 is disposed under or below the first electrode ELT1, the first electrode ELT1 may protrude upward in the region in which the first partition wall PW1 is disposed. The first partition wall PW1 may form a reflective partition wall together with the first electrode ELT1. Therefore, light emitted from the first end EP1 of the light emitting element LD facing the first electrode ELT1 may be controlled to travel more efficiently in the forward direction of the display device.

[0169] The second partition wall PW2 may be disposed below or under the second electrode ELT2 to overlap with an area of ​​the second electrode ELT2. For example, the width of the second partition wall PW2 may be less than the width of the second electrode ELT2 and may be disposed below or under the second electrode ELT2. If the second partition wall PW2 is disposed below or under the second electrode ELT2, the second electrode ELT2 may protrude upward in an area in which the second partition wall PW2 is disposed. The second partition wall PW2 may form a reflective partition wall together with the second electrode ELT2. Therefore, the light emitted from the second end EP2 of the light emitting element LD facing the second electrode ELT2 may be controlled to travel more efficiently in the forward direction of the display device.

[0170] The light emitting elements LD may be disposed in parallel between the first and second electrodes ELT1 and ELT2. For example, each light emitting element LD may be disposed between the first and second electrodes ELT1 and ELT2 in a first direction DR1 (eg, in a horizontal direction) and electrically connected therebetween.

[0171] although Figure 7 The light emitting elements LD are shown to be uniformly oriented in any one direction, for example, in the first direction DR1, but the present disclosure is not limited thereto. For example, at least one of the light emitting elements LD may be oriented in a diagonal direction between the first electrode ELT1 and the second electrode ELT2. Figure 7 Not shown, but at least one light emitting element (ie, an ineffective light source) that is not completely connected between the first electrode ELT1 and the second electrode ELT2 may be further disposed in each emission area EMA and / or a peripheral area thereof.

[0172] In an embodiment, each of the light emitting elements LD may be a light emitting element made of a material having an inorganic crystal structure and having an ultra-small size (e.g., a size ranging from nanometer to micrometer). For example, each light emitting element LD may be an ultra-small light emitting element (e.g., Figures 1a to 4b However, the type and / or size of the light emitting element LD may be changed in various ways according to the design conditions of each light emitting device (eg, pixel PXL) using the light emitting element LD as a light source, or the like.

[0173] In an embodiment, each light emitting element LD may include a first end EP1 and a second end EP2, the first end EP1 being arranged to face the adjacent first electrode ELT1, and the second end EP2 being arranged to face the adjacent second electrode ELT2. In an embodiment, each of the light emitting elements LD may overlap with the adjacent first electrode ELT1 and / or the second electrode ELT2, or may not overlap with the adjacent first electrode ELT1 and / or the second electrode ELT2. For example, the first end EP1 of the light emitting element LD may overlap with the adjacent first electrode ELT1 or may not overlap with it. Similarly, the second end EP2 of the light emitting element LD may overlap with the adjacent second electrode ELT2 or may not overlap with it.

[0174] In an embodiment, the corresponding first end EP1 of the light emitting element LD may be connected to the first electrode ELT1. The corresponding second end EP2 of the light emitting element LD may be connected to the second electrode ELT2. For example, the corresponding first end EP1 of the light emitting element LD may be electrically connected to the first electrode ELT1 via the first contact electrode CNE1. The corresponding second end EP2 of the light emitting element LD may be electrically connected to the second electrode ELT2 via the second contact electrode CNE2. In an embodiment, at least one of the first end EP1 and the second end EP2 of each of the light emitting elements LD may directly contact the first electrode ELT1 and / or the second electrode ELT2, and be electrically connected to the first electrode ELT1 and / or the second electrode ELT2. In this case, the first contact electrode CNE1 and / or the second contact electrode CNE2 may be selectively omitted.

[0175] In an embodiment, the light emitting element LD may be prepared in a predetermined solution in a diffused form, and then provided to each pixel area (specifically, the emission area EMA of each pixel PXL) by various methods (such as an inkjet scheme or a slit coating scheme). For example, the light emitting element LD may be mixed with a volatile solvent and provided to the emission area EMA of each pixel PXL. Here, if a predetermined alignment voltage (or alignment signal) is applied to the first electrode ELT1 and the second electrode ELT2 of the pixel PXL, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD has been aligned, the solvent may be removed by a volatilization method or other methods. In this way, the light emitting element LD may be reliably disposed between the first electrode ELT1 and the second electrode ELT2. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed on opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting element LD, respectively. Therefore, the light emitting element LD may be more reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0176] For example, the first contact electrode CNE1 may be disposed on each corresponding first electrode ELT1 and the first end EP1 of the light emitting element LD adjacent thereto, so that the first contact electrode CNE1 overlaps the first electrode ELT1 and the first end EP1 of the light emitting element LD. The first contact electrode CNE1 may electrically connect the first electrode ELT1 to the first end EP1 of the light emitting element LD. In addition, the first contact electrode CNE1 may reliably fix the first end EP1 of the light emitting element LD, thereby preventing the light emitting element LD from being moved from the aligned position. In an embodiment, without forming the first contact electrode CNE1, the first end EP1 of the light emitting element LD may be disposed to overlap the adjacent first electrode ELT1 and be directly connected to the first electrode ELT1.

[0177] The second contact electrode CNE2 may be disposed on each corresponding second electrode ELT2 and the second end EP2 of the light emitting element LD adjacent thereto, so that the second contact electrode CNE2 overlaps the second electrode ELT2 and the second end EP2 of the light emitting element LD. The second contact electrode CNE2 may electrically connect the second electrode ELT2 to the second end EP2 of the light emitting element LD. In addition, the second contact electrode CNE2 may stably fix the second end EP2 of the light emitting element LD, thereby preventing the light emitting element LD from moving away from the aligned position. In an embodiment, without forming the second contact electrode CNE2, the second end EP2 of the light emitting element LD may be disposed to overlap with the adjacent second electrode ELT2 and be directly connected to the second electrode ELT2.

[0178] Each light emitting element LD connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction may form an effective light source of the corresponding pixel PXL. Such effective light sources may be gathered to form a light source unit LSU of the corresponding pixel PXL.

[0179] For example, when the voltage of the first power source VDD (or a predetermined first control signal, such as a scan signal or a data signal) is applied to the first end EP1 of the light emitting element LD via the first power line PL1, the first electrode ELT1 and / or the first contact electrode CNE1 and the voltage of the second power source VSS (or a predetermined second control signal, such as a scan signal or a data signal) is applied to the second end EP2 of the light emitting element LD via the second power line PL2, the second electrode ELT2 and / or the second contact electrode CNE2, at least one light emitting element LD connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction may emit light. Thus, the pixel PXL may emit light.

[0180] Figure 8a , Figure 8b and Fig. 9 are cross-sectional views each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figure 8a and Figure 8b Shows the corresponding Figure 7 Different embodiments of the cross section of line II', and Fig. 9 Shows the corresponding Figure 7 An embodiment of a cross section of line II-II'.

[0181] In an embodiment, Figure 8a and Figure 8b Any one transistor T among the circuit elements forming the pixel circuit PXC is shown, and Fig. 9 The storage capacitor Cst and the transistor (eg, Figure 6a and Figure 6b Hereinafter, in the case where the first transistor T1 does not need to be specified separately, the term “transistor T” may be used to specify the first transistor T1 comprehensively.

[0182] In an embodiment, the transistor T forming each pixel circuit PXC may have a substantially identical or similar structure, but the present disclosure is not limited thereto. In addition, the structure and / or position of the transistor T and the storage capacitor Cst may be changed in various ways according to the embodiment, without limitation. Figures 8a to 9 The structure and / or location of an embodiment of the present invention.

[0183] refer to Figures 5 to 9According to an embodiment of the present disclosure, the pixel PXL may include a display element layer DPL disposed on one surface of the base layer BSL and including a plurality of light emitting elements LD. In addition, the pixel PXL may further selectively include a pixel circuit layer PCL disposed between the base layer BSL and the display element layer DPL.

[0184] In an embodiment, the pixel circuit layer PCL may include at least one circuit element forming each pixel circuit PXC. For example, the pixel circuit layer PCL may include a plurality of transistors T and a storage capacitor Cst forming the pixel circuit PXC, and also include at least one power line and / or signal line connected to the pixel circuit PXC and / or the light source unit LSU. Here, in the case where the pixel circuit PXC is omitted and the light source unit LSU of each pixel PXL is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the pixel circuit layer PCL may be omitted.

[0185] In addition, the pixel circuit layer PCL may include a plurality of insulating layers disposed between the respective electrodes and / or lines. In an embodiment, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the base layer BSL. The pixel circuit layer PCL may also selectively include at least one light shielding pattern (not shown) disposed below or under at least some of the transistors T.

[0186] Each transistor T may include a semiconductor layer SCL, a gate electrode GE, and first and second transistor electrodes TE1 and TE2. Figures 8a to 9 An embodiment in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 provided in at least one transistor T provided in each pixel region may be formed integrally with the corresponding semiconductor layer SCL.

[0187] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with each first transistor electrode TE1, a second region in contact with each second transistor electrode TE2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0188] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first and second regions of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0189] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap a region of the semiconductor layer SCL.

[0190] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on each semiconductor layer SCL and the corresponding gate electrode GE, with at least one interlayer insulating layer ILD interposed therebetween. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to the first region and the second region of each semiconductor layer SCL through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD. In an embodiment, any one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0191] At least one transistor T provided in the pixel circuit PXC may be connected to any one electrode of the light source unit LSU. Figure 6a and Figure 6b Any one of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 shown in FIG. 4 may be electrically connected to the first electrode ELT1 and / or the first electrode line ELI1 of the light source unit LSU disposed over the passivation layer PSV through a first contact hole CH1 passing through the passivation layer PSV.

[0192] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2 that overlap each other. In an embodiment, each of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be formed of a single layer or multiple layers. In addition, at least one of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be disposed on the same layer as at least one electrode of the first transistor T1 or a layer of the semiconductor layer SCL.

[0193] For example, the first capacitor electrode CE1 may be formed of a multilayer electrode including a lower electrode LE disposed on the same layer as that of the semiconductor layer SCL of the first transistor T1 and an upper electrode UE disposed on the same layer as that of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 and electrically connected to the lower electrode LE. The second capacitor electrode CE2 may be formed of a single-layer electrode disposed on the same layer as that of the gate electrode GE of the first transistor T1 and disposed between the lower electrode LE and the upper electrode UE of the first capacitor electrode CE1.

[0194] Here, the present disclosure is not limited thereto. The structure and / or position of each of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be changed in various ways. For example, in an embodiment, any one of the first capacitor electrode CE1 and the second capacitor electrode CE2 may include at least one conductive pattern layer disposed on a layer different from the layer forming the electrode of the first transistor T1 (e.g., the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2) and the semiconductor layer SCL.

[0195] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be arranged on the same layer as the layer of one electrode of each of the circuit elements forming the pixel circuit PXC. For example, the scan line Si of each pixel PXL may be arranged on the same layer as the layer of the gate electrode GE. The data line Dj of each pixel PXL may be arranged on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T. In addition, the first power line PL1 and / or the second power line PL2 may be arranged on the same layer as the gate electrode GE of the transistor T or the first transistor electrode TE1 and the second transistor electrode TE2. For example, the second power line PL2 for providing the voltage of the second power supply VSS may be arranged on the same layer as the gate electrode GE of the transistor T, and is electrically connected to the second electrode ELT2 and / or the second electrode line ELI2 of the light source unit LSU through the bridge pattern BRP arranged on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T and through the second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the second power line PL2, etc., may be changed in various ways.

[0196] In an embodiment, the display element layer DPL may include a light source unit LSU for each of the pixels PXL. For example, the display element layer DPL may include at least one pair of first electrodes ELT1 and second electrodes ELT2 disposed in the emission area EMA of each pixel PXL and at least one light emitting element LD electrically connected between the first electrode ELT1 and the second electrode ELT2, and may further include at least one conductive layer and / or insulating layer, etc.

[0197] In an embodiment, if Figures 6a to 7 As shown in the embodiment of FIG. 1 , each pixel PXL may include a plurality of light emitting elements LD connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction. However, the number of light emitting elements LD provided in each pixel PXL is not limited thereto, and this may be changed in various ways. For the purpose of explanation, Figures 8a to 9 In the description of the embodiment and other embodiments to be described below, each embodiment will be explained assuming that each pixel PXL includes a plurality of light emitting elements LD. Here, it should be noted that the light emitting element LD provided in the pixel PXL according to each embodiment may be changed to a single light emitting element LD.

[0198] In an embodiment, in each pixel area, the display element layer DPL may include a first partition wall PW1, a second partition wall PW2, a first electrode ELT1, a second electrode ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, a first contact electrode CNE1, a third insulating layer INS3, a second contact electrode CNE2 and a fourth insulating layer INS4, which are sequentially arranged and / or formed on the base layer BSL and / or the pixel circuit layer PCL.

[0199] The first partition wall PW1 and the second partition wall PW2 may be disposed at positions spaced apart from each other on one surface of the base layer BSL on which the pixel circuit layer PCL is selectively formed. For example, at least one pair of the first partition wall PW1 and the second partition wall PW2 spaced apart from each other may be disposed in each pixel region (specifically, each emission region EMA) on the base layer BSL.

[0200] The first and second partition walls PW1 and PW2 may protrude from the base layer BSL and / or the pixel circuit layer PCL in a height direction toward the front surface of the display panel PNL. In an embodiment, the first and second partition walls PW1 and PW2 may have substantially the same shape and / or height, but the present disclosure is not limited thereto.

[0201] In an embodiment, the first partition wall PW1 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and each first electrode ELT1. The first partition wall PW1 may be disposed adjacent to the first end EP1 of the light emitting element LD. For example, one side surface of the first partition wall PW1 may be located adjacent to the first end EP1 of the light emitting element LD and disposed to face the first end EP1.

[0202] In an embodiment, the second partition wall PW2 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and the second electrode ELT2. The second partition wall PW2 may be disposed adjacent to the second end EP2 of the light emitting element LD. For example, one side surface of the second partition wall PW2 may be positioned adjacent to the second end EP2 of the light emitting element LD and disposed to face the second end EP2.

[0203] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may have various shapes. Figure 8a and Fig. 9 As shown in , the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross-section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side. For example, the first partition wall PW1 may include an inclined surface facing the first end EP1 of the light emitting element LD, and the second partition wall PW2 may have an inclined surface facing the second end EP2 of the light emitting element LD. In an embodiment, the inclined surface of each of the first partition wall PW1 and the second partition wall PW2 (specifically, the inclined surface of one end facing the adjacent light emitting element LD) may be formed to have an inclination angle θ1, θ2 (e.g., an initial inclination angle) in the range from about 15° to about 80° relative to the plane on which the light emitting element LD is disposed.

[0204] In an embodiment, if Figure 8b As shown in , the first partition wall PW1 and the second partition wall PW2 may have a semicircular or semi-elliptical cross-section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side. For example, the first partition wall PW1 may include a curved surface facing the first end EP1 of the light emitting element LD, and the second partition wall PW2 may have a curved surface facing the second end EP2 of the light emitting element LD. In an embodiment, the curved surface of each of the first partition wall PW1 and the second partition wall PW2 (specifically, the curved surface of one end facing the adjacent light emitting element LD) may be formed to have an initial inclination angle θ1', θ2' in the range of about 15° to about 80° relative to the plane on which the light emitting element LD is disposed.

[0205] Here, the shapes of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways according to the embodiment. For example, in the embodiment, the first partition wall PW1 and the second partition wall PW2 may each have a stepped structure on at least one side thereof.

[0206] In an embodiment, the shape (e.g., inclination angle), size (e.g., height), and / or position of the first partition wall PW1 and the second partition wall PW2 may be designed in various ways in consideration of the light efficiency of each pixel PXL, etc. In other words, the shape, size, and / or position of the first partition wall PW1 and the second partition wall PW2 are not particularly limited, and these may be changed in various ways in consideration of the design conditions or light efficiency of each pixel PXL, etc. In an embodiment, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted or the position may be changed.

[0207] Each of the first partition wall PW1 and the second partition wall PW2 may include an insulating material including at least one inorganic material and / or an organic material. For example, the first partition wall PW1 and the second partition wall PW2 may include at least one inorganic layer including various known inorganic insulating materials such as silicon nitride (SiN x ) or silicon oxide (SiO x ). Alternatively, the first partition wall PW1 and the second partition wall PW2 may include at least one organic layer and / or a photoresist layer including various known organic insulating materials, or may form a single-layer or multi-layer insulator including a combination of organic / inorganic materials. In the embodiment of the present disclosure, the constituent materials of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways.

[0208] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may be used as a reflector. For example, the first partition wall PW1 and the second partition wall PW2 together with the first electrode ELT1 and the second electrode ELT2 disposed on the first partition wall PW1 and the second partition wall PW2 may be used as a reflector that guides light emitted from each light emitting element LD in a desired direction, thereby enhancing (or improving) the light efficiency of the pixel PXL. For example, the first partition wall PW1 together with the first electrode ELT1 disposed thereon may form a first reflective partition wall, and the second partition wall PW2 together with the second electrode ELT2 disposed thereon may form a second reflective partition wall.

[0209] The first electrode ELT1 and the second electrode ELT2 may be disposed on the first partition wall PW1 and the second partition wall PW2, respectively. The first electrode ELT1 and the second electrode ELT2 may be disposed at positions spaced apart from each other in each emission area EMA.

[0210] In an embodiment, the first electrode ELT1 and the second electrode ELT2 respectively disposed on the first partition wall PW1 and the second partition wall PW2 may have shapes corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2. For example, the first electrode ELT1 and the second electrode ELT2 may have inclined surfaces or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, respectively, and may protrude in the height direction of the base layer BSL. Similarly, at least one conductive layer and / or insulating layer disposed on the first electrode ELT1 and the second electrode ELT2 may have a shape corresponding to the shapes of the first electrode ELT1 and the second electrode ELT2.

[0211] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one metal among various metal materials, at least one material among conductive oxides and conductive polymers, the metal material includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or their alloys, and the conductive oxide is such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), tin oxide (SnO 2 ), a conductive polymer such as PEDOT, but the present disclosure is not limited thereto. For example, each of the first electrode ELT1 and the second electrode ELT2 may include other conductive materials such as carbon nanotubes and graphene. In other words, each of the first electrode ELT1 and the second electrode ELT2 may include at least one of various conductive materials to have conductivity, and its constituent materials are not particularly limited. In addition, each of the first electrode ELT1 and the second electrode ELT2 may have the same conductive material or at least one different conductive material.

[0212] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer or multi-layer structure. For example, each of the first electrode ELT1 and the second electrode ELT2 may include a reflective electrode layer. In addition, each of the first electrode ELT1 and the second electrode ELT2 may also selectively include at least one of a transparent electrode layer disposed above and / or below or below the reflective electrode layer and a conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0213] In an embodiment, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of a conductive material having a uniform reflectivity. For example, the reflective electrode layer may include at least one of various metal materials, and the various metal materials include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc. or their alloys, but the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials. Each of the first electrode ELT1 and the second electrode ELT2 including the reflective electrode layer may enable light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting elements LD to travel in the direction of displaying an image (e.g., in the forward direction). Specifically, if the first electrode ELT1 and the second electrode ELT2 have inclined surfaces or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, respectively, and are disposed to face the first end EP1 and the second end EP2 of the light emitting element LD, respectively, light emitted from the first end EP1 and the second end EP2 of each light emitting element LD can be reflected by the first electrode ELT1 and the second electrode ELT2, and thus more reliably travel in the forward direction of the display panel PNL (e.g., in the upward direction of the base layer BSL). Thus, the efficiency of light emitted from the light emitting element LD can be improved.

[0214] In addition, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ELT1 and the second electrode ELT2 are each formed of a multilayer structure of at least two layers, the voltage drop caused by the signal delay (RC delay) may be minimized. Therefore, the desired voltage may be effectively transmitted to the light emitting element LD.

[0215] In addition, if each of the first electrode ELT1 and the second electrode ELT2 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the first electrode ELT1 and the second electrode ELT2 can be prevented from being damaged due to defects caused in the manufacturing process of the pixel PXL. However, the conductive capping layer may be selectively included in the first electrode ELT1 and the second electrode ELT2, and the conductive capping layer may be omitted according to the embodiment. In addition, the conductive capping layer may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or as a separate component disposed on the first electrode ELT1 and the second electrode ELT2.

[0216] The first insulating layer INS1 may be disposed on a region of each of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed to cover a region of the first electrode ELT1 and the second electrode ELT2, and may include an opening exposing other regions of the first electrode ELT1 and the second electrode ELT2 (for example, the first contact portion CNP1 and the second contact portion CNP2).

[0217] In an embodiment, the first insulating layer INS1 may be first formed to cover the entire surface of the first electrode ELT1 and the second electrode ELT2. After providing the light emitting element LD and aligning the light emitting element LD on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose the first electrode ELT1 and the second electrode ELT2 in the first contact portion CNP1 and the second contact portion CNP2, respectively. In an embodiment, the first insulating layer INS1 may be patterned in the form of a separate pattern, which is segmentedly disposed below or under the light emitting element LD after the provision and alignment of the light emitting element LD are completed.

[0218] In other words, the first insulating layer INS1 may be interposed between the first and second electrodes ELT1 and ELT2 and the light emitting element LD, and may expose at least one region of each of the first and second electrodes ELT1 and ELT2. After forming the first and second electrodes ELT1 and ELT2, the first insulating layer INS1 may be formed to cover the first and second electrodes ELT1 and ELT2, thereby preventing the first and second electrodes ELT1 and ELT2 from being damaged during subsequent processes. In addition, the first insulating layer INS1 may stably support each light emitting element LD.

[0219] The first insulating layer INS1 may be selectively provided according to an embodiment. For example, in an embodiment, the first insulating layer INS1 may be omitted. In this case, the light emitting element LD may be directly provided on the passivation layer PSV between the first electrode ELT1 and the second electrode ELT2 to contact the passivation layer PSV, or the light emitting element LD may be provided between the first electrode ELT1 and the second electrode ELT2 so that the first end EP1 and / or the second end EP2 of the light emitting element LD are directly provided on the first electrode ELT1 and / or the second electrode ELT2, respectively.

[0220] A plurality of light emitting elements LD may be provided to each emission region EMA in which the first insulating layer INS1 is formed and aligned in the emission region EMA. For example, a plurality of light emitting elements LD may be provided to each emission region EMA by an inkjet scheme, a slit coating scheme, etc., and the light emitting elements LD may be aligned between the first electrode ELT1 and the second electrode ELT2 by a predetermined alignment voltage (or alignment signal) applied to the first electrode ELT1 and the second electrode ELT2.

[0221] The second insulating layer INS2 may be disposed over the light emitting element LD (specifically, the light emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2), and may expose the first end EP1 and the second end EP2 of the light emitting element LD. For example, the second insulating layer INS2 may be disposed only partially over a region including a central region of the light emitting element LD without covering the first end EP1 and the second end EP2 of the light emitting element LD. The second insulating layer INS2 may be formed as an independent pattern in each emission region EMA; however, the present disclosure is not limited thereto.

[0222] The second insulating layer INS2 can reliably fix the light emitting element LD. For example, after the alignment of the light emitting element LD is completed, the second insulating layer INS2 is formed on the light emitting element LD, so that the light emitting element LD can be prevented from moving from the aligned position. If there is a space between the first insulating layer INS1 and the light emitting element LD before the second insulating layer INS2 is formed, the space can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. Therefore, the light emitting element LD can be supported more stably.

[0223] The second insulating layer INS2 may be selectively provided according to an embodiment. For example, in an embodiment, the second insulating layer INS2 may be omitted. In this case, one end of each of the first contact electrode CNE1 and the second contact electrode CNE2 may be directly provided on the light emitting element LD.

[0224] The first contact electrode CNE1 may be disposed on a region of the first electrode ELT1 and the light emitting element LD. For example, the first contact electrode CNE1 may be formed on the first electrode ELT1 and the first end EP1 of the light emitting element LD to cover at least one region of the first electrode ELT1 including the first contact portion CNP1 and the first end EP1 of the light emitting element LD. The first contact electrode CNE1 may contact each of the first electrodes ELT1 through the first contact portion CNP1 and contact the first end EP1 of the light emitting element LD exposed from the second insulating layer INS2. Therefore, the first end EP1 of the light emitting element LD may be electrically connected to the first electrode ELT1 through the first contact electrode CNE1.

[0225] The third insulating layer INS3 may be disposed on the first contact electrode CNE1. For example, the third insulating layer INS3 may be disposed directly on the first contact electrode CNE1 to cover at least the first contact electrode CNE1. For example, the third insulating layer INS3 may be disposed on the first contact electrode CNE1 and a region of the light emitting element LD including the first end EP1, and cover an end of the first contact electrode CNE1 on the light emitting element LD.

[0226] The third insulating layer INS3 may be interposed between the first contact electrode CNE1 and the second contact electrode CNE2 and reliably insulate the first contact electrode CNE1 and the second contact electrode CNE2. In other words, when the third insulating layer INS3 is formed, a short circuit defect between the first contact electrode CNE1 and the second contact electrode CNE2 may be effectively prevented. The third insulating layer INS3 may be formed only on a partial region of the light emitting element LD so that the second end EP2 of the light emitting element LD is not covered by the third insulating layer INS3.

[0227] The second contact electrode CNE2 may be disposed on a region of the second electrode ELT2 and the light emitting element LD. For example, the second contact electrode CNE2 may be formed on the second electrode ELT2 and the second end EP2 of the light emitting element LD to cover at least one region of the second electrode ELT2 including the second contact portion CNP2 and the second end EP2 of the light emitting element LD. The second contact electrode CNE2 may contact each second electrode ELT2 through the second contact portion CNP2, and contact the second end EP2 of the light emitting element LD exposed from the second insulating layer INS2 and the third insulating layer INS3. Therefore, the second end EP2 of the light emitting element LD may be electrically connected to the second electrode ELT2 through the second contact electrode CNE2.

[0228] The fourth insulating layer INS4 may be disposed on the first contact electrode CNE1 and the second contact electrode CNE2. For example, the fourth insulating layer INS4 may be formed and / or disposed on the entire surface of the display area DA of the base layer BSL, and the display area DA of the base layer BSL includes the first partition wall PW1 and the second partition wall PW2, the first electrode ELT1 and the second electrode ELT2, the light emitting element LD, and the first contact electrode CNE1 and the second contact electrode CNE2 throughout each pixel PXL. When the fourth insulating layer INS4 is formed, the pixel PXL formed in the display area DA may be protected from the external environment. For example, when the fourth insulating layer INS4 is formed, foreign substances such as water may be prevented from being introduced into the pixel PXL, or the pixel PXL may be prevented from being damaged by an external impact. The fourth insulating layer INS4 may include at least one inorganic layer and / or an organic layer.

[0229] In an embodiment, the fourth insulating layer INS4 may include a thin film encapsulation layer having a multi-layer structure, but the present disclosure is not limited thereto. In some embodiments, at least one outer coating layer and / or an upper substrate (eg, an encapsulation substrate) not shown, etc. may be further disposed on the fourth insulating layer INS4.

[0230] In an embodiment, each of the first to fourth insulating layers INS1 to INS4 may have a single-layer or multi-layer structure and include at least one inorganic insulating material and / or organic insulating material. For example, each of the first to fourth insulating layers INS1 to INS4 may include various well-known organic / inorganic insulating materials (including silicon nitride (SiN x )), and the constituent material of each of the first to fourth insulating layers INS1 to INS4 is not particularly limited. The first to fourth insulating layers INS1 to INS4 may include different insulating materials, or at least some of the first to fourth insulating layers INS1 to INS4 may include the same insulating material.

[0231] Fig.10 and Figures 11a to 11c are cross-sectional views each showing a display device according to an embodiment of the present disclosure. For example, Fig.10 and Figures 11a to 11c Shown including according to Fig. 9 Different embodiments of a cross section of a region of a display panel PNL of a pixel PXL of an embodiment. In an embodiment, Fig.10 and Figures 11a to 11c The cross sections of the display panel PNL are each shown focusing on a region in which any one pixel unit PXU formed of the first color pixel PXL1 , the second color pixel PXL2 , and the third color pixel PXL3 adjacent to each other is disposed.

[0232] Since the illustrative structure of each pixel PXL has been described in detail through the above-mentioned embodiments, Fig.10 and Figures 11a to 11c Each of the diagrams schematically shows the structure of each pixel PXL with one light emitting element LD as the center. Fig.10 and Figures 11a to 11c In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and a detailed description thereof will be omitted.

[0233] refer to Figures 5 to 10 , the light source unit LSU of each pixel PXL may be disposed in the display element layer DPL above the base layer BSL and / or the pixel circuit layer PCL. For example, in each emission area EMA of the display element layer DPL, the light source unit LSU of the corresponding pixel PXL may be disposed. A bank BNK for defining each emission area EMA may be disposed between adjacent emission areas EMA.

[0234] The light source unit LSU, which may have various configurations according to the embodiment, may be formed in the emission area EMA of each pixel PXL. For example, in each emission area EMA, a Figures 7 to 9 1 and 2 , first and second partition walls PW1 and PW2 , first and second electrodes ELT1 and ELT2 , a light emitting element LD, first and second contact electrodes CNE1 and CNE2 , and first to fourth insulating layers INS1 to INS4 are shown in FIG.

[0235] In an embodiment, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may include a light emitting element LD configured to emit light of different colors. For example, each first color pixel PXL1 may include a first color light emitting element LD1, each second color pixel PXL2 may include a second color light emitting element LD2, and each third color pixel PXL3 may include a third color light emitting element LD3. In an embodiment, the first color light emitting element LD1, the second color light emitting element LD2, and the third color light emitting element LD3 may be a red light emitting element, a green light emitting element, and a blue light emitting element, respectively, but the present disclosure is not limited thereto.

[0236] The bank BNK may be a structure that defines an emission area EMA of each pixel PXL, and is, for example, a pixel defining layer. For example, the bank BNK may be disposed in a boundary area of ​​a first pixel area PXA1, a second pixel area PXA2, and a third pixel area PXA3 in which first color pixels PXL1, second color pixels PXL2, and third color pixels PXL3 are disposed, respectively, so that the emission area EMA of each pixel PXL is surrounded by the bank BNK. The bank BNK may also be disposed on the periphery of the display area DA to surround the display area DA in which the pixel PXL is disposed. Hereinafter, the term "pixel area (pixel area) PXA" or "pixel area (pixel areas) PXA" will be used to specify any pixel area in the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3, or to specify two or more types of pixel areas together.

[0237] The bank BNK may include at least one light shielding material and / or a reflective material to prevent light leakage between adjacent pixels PXL. For example, the bank BNK may include at least one black matrix material (e.g., at least one known light shielding material) of different types of black matrix materials and / or a color filter material having a specific color. For example, the bank BNK may be formed of a black opaque pattern to block the transmission of light. In an embodiment, a reflective layer not shown may be formed on a surface (e.g., a sidewall) of the bank BNK to increase the light efficiency of the pixel PXL.

[0238] In an embodiment, during a process of forming the first partition wall PW1 and the second partition wall PW2 of the pixel PXL, the bank BNK may be formed on the same layer as the layer of the first partition wall PW1 and the second partition wall PW2. In an embodiment, during a process separate from the process of forming the first partition wall PW1 and the second partition wall PW2, the bank BNK may be formed on the same layer as or different from the layer of the first partition wall PW1 and the second partition wall PW2. In other words, the position of the bank BNK (e.g., the position in the layer in the cross-sectional view), its formation step, etc. may be changed in various ways according to the embodiment. In addition, the shape, size and / or constituent material of the bank BNK may be changed in various ways according to the design conditions of the display panel PNL, etc. For example, the bank BNK may be a single-layer or multi-layer pattern, which may have various shapes including a trapezoidal shape, a semicircular shape, an elliptical shape, etc., and its size (e.g., width and / or height) or constituent material may be changed in various ways.

[0239] In an embodiment, an upper substrate ENC may be disposed over the pixel PXL. For example, an upper substrate ENC (also referred to as an "encapsulation substrate" or a "color filter substrate") encapsulating at least the display area DA may be disposed on one surface of the base layer BSL on which the pixel PXL is disposed.

[0240] In an implementation, the upper substrate ENC may include a light conversion layer LCP overlapping the pixel PXL. For example, the light conversion layer LCP may include a color filter layer CFL disposed on one surface of the upper substrate ENC to face the pixel PXL.

[0241] The color filter layer CFL may include a color filter corresponding to the color of each pixel PXL. For example, the color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, the first color filter CF1 being disposed on each first color pixel PXL1 and allowing light generated from the first color pixel PXL1 to selectively pass therethrough, the second color filter CF2 being disposed on each second color pixel PXL2 and allowing light generated from the second color pixel PXL2 to selectively pass therethrough, and the third color filter CF3 being disposed on each third color pixel PXL3 and allowing light generated from the third color pixel PXL3 to selectively pass therethrough. In an embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red color filter, a green color filter, and a blue color filter, respectively, but the present disclosure is not limited thereto. Hereinafter, the term "color filter CF" or "color filters CF" will be used to designate any color filter among the first color filter CF1, the second color filter CF2, and the third color filter CF3 or to designate two or more color filters in combination.

[0242] The first color filter CF1 may be disposed between each first color pixel PXL1 (specifically, the light source unit LSU of the first color pixel PXL1) and the upper substrate ENC, and include a color filter material that allows light of a first color generated from the first color pixel PXL1 to selectively pass therethrough. For example, in the case where the first color pixel PXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0243] The second color filter CF2 may be disposed between each second color pixel PXL2 (specifically, the light source unit LSU of the second color pixel PXL2) and the upper substrate ENC, and include a color filter material that allows light of a second color generated from the second color pixel PXL2 to selectively pass therethrough. For example, in the case where the second color pixel PXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0244] The third color filter CF3 may be disposed between each third color pixel PXL3 (specifically, the light source unit LSU of the third color pixel PXL3) and the upper substrate ENC, and include a color filter material that allows light of a third color generated from the third color pixel PXL3 to selectively pass therethrough. For example, in the case where the third color pixel PXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0245] In an embodiment, the black matrix BM may be disposed between the color filters CF. For example, the black matrix BM may be disposed on one surface of the upper substrate ENC to face the bank BNK. In an embodiment, the black matrix BM may be disposed in a boundary region of the pixel region PXA so as not to cover each emission region EMA.

[0246] In an embodiment, the black matrix BM may include at least one black matrix material (e.g., at least one well-known light shielding material) of different types of black matrix materials and / or a color filter material having a specific color. The black matrix BM may be formed of the same material as the material of the bank BNK, but the present disclosure is not limited thereto. In other words, the black matrix BM and the bank BNK may include the same material or different materials.

[0247] In an embodiment, the black matrix BM may be formed of a black light shielding pattern including a black matrix material. In an embodiment, the black matrix BM may be formed of a blue light shielding pattern including a blue color filter material. In this case, the number of masks used to form the color filter layer CFL can be reduced, and the process can be simplified.

[0248] In an embodiment, the black matrix BM may have a multi-layer structure. For example, the black matrix BM may have a multi-layer structure including a black light shielding pattern including a black matrix material and a blue light shielding pattern including a blue color filter material.

[0249] For example, the black matrix BM may be a single-layer or multi-layer pattern, may have various shapes including a trapezoidal shape, a semicircular shape, an elliptical shape, etc., and its size (eg, width and / or height) or constituent material may be changed in various ways.

[0250] In an embodiment, an air layer may be formed in a space between a lower plate of the display panel PNL including a base layer BSL, a display element layer DPL, etc. and an upper plate of the display panel PNL including an upper substrate ENC, a light conversion layer LCP, etc. In an embodiment, the space between the lower plate and the upper plate of the display panel PNL may be filled with a predetermined filler having a relatively low refractive index in a range from about 1 to about 1.5.

[0251] although Fig.10An embodiment in which the upper substrate ENC is disposed on the base layer BSL on which the pixel PXL is disposed is shown, but the present disclosure is not limited thereto. For example, in the case where the fourth insulating layer INS4 includes a thin film encapsulation layer sufficient to protect the pixel PXL, the upper substrate ENC may be omitted. In this case, the color filter CF and / or the black matrix BM may be disposed on a window (not shown) disposed above the display panel PNL.

[0252] refer to Fig.11a The upper substrate ENC may include a light conversion layer LCP overlapping the pixel PXL. The light conversion layer LCP may include a color filter layer CFL disposed on the upper substrate ENC to face the pixel PXL and a color conversion layer CCL disposed between the color filter layer CFL and the pixel PXL and including color conversion particles.

[0253] although Fig.11a An embodiment in which there is a gap (e.g., an air layer) between the color conversion layer CCL and the fourth insulating layer INS4 is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the color conversion layer CCL may be formed so that the space between the color filter layer CFL and the fourth insulating layer INS4 is completely filled with the color conversion layer CCL.

[0254] The light conversion layer LCP may include a first light conversion layer LCP1 disposed on the first color pixel PXL1, a second light conversion layer LCP2 disposed on the second color pixel PXL2, and a third light conversion layer LCP3 disposed on the third color pixel PXL3. Hereinafter, the term "light conversion layer (light conversion layer) LCP" or "light conversion layers (light conversion layers) LCP" will be used to specify any one of the first light conversion layer LCP1, the second light conversion layer LCP2 and the third light conversion layer LCP3 or to specify two or more types of light conversion layers in combination.

[0255] In an embodiment, at least some of the first light conversion layer LCP1, the second light conversion layer LCP2, and the third light conversion layer LCP3 may include a color conversion layer CCL and / or a color filter layer CFL corresponding to a predetermined color. For example, the first light conversion layer LCP1 may include a first color conversion layer CCL1 and a first color filter CF1, the first color conversion layer CCL1 including first color conversion particles corresponding to the first color, and the first color filter CF1 is configured to allow light of the first color to selectively pass therethrough. Similarly, the second light conversion layer LCP2 may include a second color conversion layer CCL2 and a second color filter CF2, the second color conversion layer CCL2 including second color conversion particles corresponding to the second color, and the second color filter CF2 is configured to allow light of the second color to selectively pass therethrough. The third light conversion layer LCP3 may include at least one of a light scattering layer LSL and a third color filter CF3, the light scattering layer LSL including light scattering particles SCT, and the third color filter CF3 is configured to allow light of a third color to selectively pass therethrough.

[0256] In an embodiment, at least one insulating layer not shown may be disposed on the surface of each of the first color conversion layer CCL1, the second color conversion layer CCL2, and / or the light scattering layer LSL. Each insulating layer (e.g., a cover layer, a buffer layer, and / or a barrier layer) may be disposed between the first color conversion layer CCL1, the second color conversion layer CCL2, and / or the light scattering layer LSL and each color filter CF and on the surface of each of the first color conversion layer CCL1, the second color conversion layer CCL2, and / or the light scattering layer LSL to protect the first color conversion layer CCL1, the second color conversion layer CCL2, and / or the light scattering layer LSL. In an embodiment, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may include a light emitting element LD configured to emit light of the same color. For example, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may include a third color light emitting element LD3, which is configured to emit light of a third color belonging to a wavelength band in the range from about 400 nm to about 500 nm, such as blue light. A color conversion layer CCL including at least one color conversion particle may be disposed on at least some of the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3. Therefore, the display device according to an embodiment of the present disclosure may display a full-color image.

[0257] The first color conversion layer CCL1 may be disposed on one surface of the upper substrate ENC to face the first color pixel PXL1, and include first color conversion particles that convert light of a third color emitted from a third color light emitting element LD3 disposed in the first color pixel PXL1 into light of a first color. For example, in the case where the third color light emitting element LD3 disposed in the first color pixel PXL1 is a blue light emitting element configured to emit blue light and the first color pixel PXL1 is a red pixel, the first color conversion layer CCL1 may include red quantum dots QDr that convert blue light emitted from the blue light emitting element into red light.

[0258] For example, the first color conversion layer CCL1 may include a plurality of red quantum dots QDr dispersed in a predetermined matrix material such as a transparent resin. The red quantum dots QDr may absorb blue light and convert the wavelength of the light according to energy conversion, thereby emitting red light having a wavelength band in the range of 620 nm to 780 nm. In the case where the first color pixel PXL1 is one of the pixels having other colors, the first color conversion layer CCL1 may include a first quantum dot corresponding to the color of the first color pixel PXL1.

[0259] In an embodiment, the second color conversion layer CCL2 may be disposed on one surface of the upper substrate ENC to face the second color pixel PXL2, and include second color conversion particles that convert light of a third color emitted from a third color light emitting element LD3 disposed in the second color pixel PXL2 into light of a second color. For example, in the case where the third color light emitting element LD3 disposed in the second color pixel PXL2 is a blue light emitting element configured to emit blue light and the second color pixel PXL2 is a green pixel, the second color conversion layer CCL2 may include green quantum dots QDg that convert blue light emitted from the blue light emitting element into green light.

[0260] For example, the second color conversion layer CCL2 may include a plurality of green quantum dots QDg dispersed in a predetermined matrix material such as a transparent resin. The green quantum dots QDg may absorb blue light and convert the wavelength of the light according to energy conversion, thereby emitting green light having a wavelength band in the range of 500 nm to 570 nm. In the case where the second color pixel PXL2 is one of the pixels having other colors, the second color conversion layer CCL2 may include a second quantum dot corresponding to the color of the second color pixel PXL2.

[0261] Each of the first quantum dot and the second quantum dot (eg, red quantum dot QDr and green quantum dot QDg) may be selected from group II-VI compounds, group IV-VI compounds, group III-V compounds, group IV elements, group IV compounds, and combinations thereof.

[0262] The II-VI compound can be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, wherein the binary compound is selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; the ternary compound is selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS , CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; the quaternary compound is selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0263] The III-V compound can be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, wherein the binary compound is selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; the ternary compound is selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb and mixtures thereof; the quaternary compound is selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0264] The IV-VI compound may be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, wherein the binary compound is selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; the ternary compound is selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; the quaternary compound is selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe and mixtures thereof.

[0265] The first quantum dot and the second quantum dot may have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less, and light emitted by the first quantum dot and the second quantum dot may be emitted in all directions. Therefore, the viewing angle of the display device may be enhanced.

[0266] Each of the first quantum dot and the second quantum dot can be in the form of a nanoparticle, a nanotube, a nanowire, a nanofiber, a planar nanoparticle having a spherical shape, a pyramid shape, a multi-arm shape or a cubic shape, but is not limited thereto. In other words, the shapes of the first quantum dot and the second quantum dot can be changed in various ways.

[0267] In an embodiment of the present disclosure, when blue light having a relatively short wavelength in the visible light region is incident on each of the red quantum dot QDr and the green quantum dot QDg, the absorption coefficient of the red quantum dot QDr and the green quantum dot QDg can be increased. Thus, ultimately, the efficiency of light emitted from each of the first color pixel PXL1 and the second color pixel PXL2 can be enhanced, and satisfactory color reproducibility can be ensured. In addition, since the light source unit LSU of the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 is formed using the light emitting element LD of the same color, the efficiency of manufacturing the display device can be improved.

[0268] In an implementation, the light scattering layer LSL may be disposed on one surface of the upper substrate ENC to face the third color pixel PXL3. For example, the light scattering layer LSL may be disposed between the third color pixel PXL3 and the third color filter CF3.

[0269] In an embodiment, when the third color light emitting element LD3 provided in the third color pixel PXL3 is a blue light emitting element configured to emit blue light and the third color pixel PXL3 is a blue pixel, a light scattering layer LSL may be selectively provided to effectively use the light emitted from the third color light emitting element LD3. The light scattering layer LSL may include at least one light scattering particle SCT.

[0270] For example, the light scattering layer LSL may include a plurality of light scattering particles SCT dispersed in a predetermined matrix material (such as a transparent resin). For example, the light scattering layer LSL may include light scattering particles SCT, such as titanium dioxide (TiO 2 ) or silicon dioxide. In the present disclosure, the material of the light scattering particles SCT is not particularly limited, and the light scattering layer LSL may be formed of various well-known materials. Here, the light scattering particles SCT may be disposed in an area other than the third pixel area PXA3 in which the third color pixel PXL3 is formed. For example, the light scattering particles SCT may also be selectively included in the first color conversion layer CCL1 and / or the second color conversion layer CCL2.

[0271] refer to Fig.11b , the black matrix BM may extend at least in the thickness (or height) direction, so that the black matrix BM may also be disposed between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL. For example, the black matrix BM may extend at least in the thickness direction to have a thickness corresponding to the entire thickness of the light conversion layer LCP including the color filter layer CFL and the color conversion layer CCL (e.g., a thickness substantially equal to or similar to the entire thickness of the light conversion layer LCP).

[0272] In an embodiment, the black matrix BM may be disposed between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL, so that the black matrix BM defines an area in which the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL are formed. In this case, the first color conversion layer CCL1, the second color conversion layer CCL2, and / or the light scattering layer LSL may be formed by an inkjet scheme, etc. For example, the color conversion layer CCL may be formed by forming a black matrix BM on one surface of the upper substrate ENC before forming the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL, and then applying the first color conversion layer CCL1, the second color conversion layer CCL2, and / or the light scattering layer LSL on one surface of the upper substrate ENC on which the black matrix BM is formed.

[0273] refer to Fig.11cThe black matrix BM may have a multi-layer structure including a first black matrix BM1 disposed in the color filter layer CFL and a second black matrix BM2 disposed in the color conversion layer CCL. In other words, in an embodiment, the black matrix BM may have an integrated or separated structure in the light conversion layer LCP.

[0274] In an embodiment, the second black matrix BM2 may be formed before or after forming the first color conversion layer CCL1, the second color conversion layer CCL2, and / or the light scattering layer LSL. In an embodiment, in the case where the second black matrix BM2 is formed after the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL are formed on one surface of the upper substrate ENC, the second black matrix BM2 may have a shape corresponding to the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL, and the second black matrix BM2 may be inserted between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL.

[0275] according to Figures 11a to 11c In the embodiment of the present invention, the pixel PXL and the display device including the pixel PXL can be easily manufactured using the single-color light-emitting element LD (for example, the third color light-emitting element LD3). In addition, since the color conversion layer CCL is provided on at least some of the pixels PXL, the full-color pixel unit PXU and the display device including the full-color pixel unit PXU can be manufactured.

[0276] Fig.12 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and for example shows a pixel PXL corresponding to Figure 7 An embodiment of a cross section of line II-II'. Fig.13 and Fig.14 are cross-sectional views each showing a display device according to an embodiment of the present disclosure, and for example show a display device including Fig.12 The embodiment of the cross section of a region of the pixel PXL of the display panel PNL is different from the embodiment of the embodiment. Fig.13 and Fig.14 Each shows the Fig.10 and Fig.11a The upper plate of the display panel PNL of the embodiment of the present invention may be modified in various ways. Fig.11b or Fig.11c As shown in the embodiment of FIG. 1 , the upper panel may include a black matrix BM disposed between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL. Figure 12 to Figure 14 In the description of the embodiments of the present invention, the same reference numerals are used to represent the same embodiments as those described above (for example, Figures 8a to 11c) are similar or identical components to the components of the embodiment, and their detailed description will be omitted.

[0277] refer to Figure 12 to Figure 14 , can be omitted according to the implementation Figures 9 to 11c For example, the first contact electrode CNE1 may be directly covered with the fourth insulating layer INS4 without forming the third insulating layer INS3 on the first contact electrode CNE1. Figures 8a to 11c Compared with the embodiment of the present invention, the mask process of forming the third insulating layer INS3 can be omitted, so that the manufacturing process can be further simplified. In addition, since the third insulating layer INS3 is not formed, the light efficiency of each pixel PXL can be improved. For example, in the case where the third insulating layer INS3 is not provided on the path where the light generated from the light emitting element LD is emitted from each pixel PXL, the amount of light that is confined in the optical waveguide formed by the transparent electrode and / or the insulating layer provided in the pixel PXL and is thus dissipated and cannot be emitted from the pixel PXL can be reduced. Therefore, the amount of light emitted from each pixel PXL within a viewing angle (for example, a viewing angle within a range of 0° to ±180°) having a predetermined angle including the forward direction of the display panel PNL (for example, a direction within a viewing angle range of 0° to ±2° based on a normal direction perpendicular to the display panel PNL) is increased, so that the light efficiency of each pixel PXL can be increased compared with the light efficiency of the structure including the third insulating layer INS3.

[0278] Figures 15a to 15i are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.12 An embodiment of the method of a display device of a pixel PXL.

[0279] refer to Figure 12 to Figure 15a , a pixel circuit layer PCL is formed in each pixel area PXA on the base layer BSL, and a first partition wall PW1 and a second partition wall PW2 spaced apart from each other may be formed in each pixel area PXA on the base layer BSL on which the pixel circuit layer PCL is formed. Here, in the case where the pixel circuit layer PCL is omitted, the first partition wall PW1 and the second partition wall PW2 may be directly formed on one surface of the base layer BSL (or the base layer BSL on which the buffer layer BFL is formed).

[0280] In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be formed by a process of forming an insulating layer including an inorganic material and / or an organic material and / or a patterning process (e.g., a photolithography process), and may be formed by various types of known processes. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be simultaneously formed on the same layer (or the same plane) on the base layer BSL using the same material, but the present disclosure is not limited thereto.

[0281] In addition, a first contact hole CH1 for connecting a predetermined circuit element (e.g., a first transistor T1 of each pixel PXL) provided in the pixel circuit layer PCL and any one electrode of the display element layer DPL (e.g., a first electrode ELT1 of each pixel PXL) and / or a second contact hole CH2 for connecting a predetermined line (e.g., a second power line PL2) provided in the pixel circuit layer PCL and another electrode of the display element layer DPL (e.g., a second electrode ELT2 of each pixel PXL) are formed. In an embodiment, the first contact hole CH1 and the second contact hole CH2 may be formed before or after forming the first partition wall PW1 and the second partition wall PW2, or may be formed during at least one etching process for forming the first partition wall PW1 and the second partition wall PW2.

[0282] refer to Fig.15b , the first electrode ELT1 and the second electrode ELT2 are formed on the first partition wall PW1 and the second partition wall PW2. In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be formed by a process of forming a conductive layer including at least one conductive material and / or a patterning process, and may be formed by various types of known processes. Each of the first electrode ELT1 and the second electrode ELT2 may be formed of a single layer or a multilayer. For example, each of the first electrode ELT1 and the second electrode ELT2 may be formed of a conductive pattern having a single-layer structure, or a conductive pattern having a multilayer structure including a corresponding reflective electrode layer and a corresponding conductive capping layer. In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be simultaneously formed on the same layer (or the same plane) on the base layer BSL using the same material, but the present disclosure is not limited thereto.

[0283] refer to Fig.15c , a first insulating layer INS1 is formed on the base layer BSL including the first and second electrodes ELT1 and ELT2. In an embodiment, the first insulating layer INS1 may be formed on one surface of the base layer BSL to cover at least the first and second electrodes ELT1 and ELT2.

[0284] In an embodiment, the first insulating layer INS1 may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. In an embodiment, the pixel PXL may not include the first insulating layer INS1. In this case, the process of forming the first insulating layer INS1 may be omitted.

[0285] refer to Fig.15d , at least one light emitting element LD, for example, a plurality of light emitting elements LD may be provided and aligned between the first electrode ELT1 and the second electrode ELT2 of each pixel PXL. For example, a plurality of light emitting elements LD may be provided to each pixel area PXA (for example, the emission area EMA of each pixel PXL) on a base layer BSL on which the first electrode ELT1 and the second electrode ELT2, the first insulating layer INS1, etc. are formed, and the light emitting elements LD may be aligned between the first electrode ELT1 and the second electrode ELT2 by applying a predetermined alignment voltage to the first electrode ELT1 and the second electrode ELT2.

[0286] In an embodiment, the light emitting element LD may be provided to each pixel region PXA in such a manner that a solution in which a plurality of light emitting elements LD are dispersed (also referred to as "light emitting element ink (LED ink)") is applied to each emission region EMA of the base layer BSL by an inkjet printing scheme or a slit coating scheme, etc. However, the scheme for providing the light emitting element LD is not limited to the above scheme, and the light emitting element LD may be provided to each pixel region PXA in various other ways.

[0287] In an embodiment, by providing an AC alignment voltage or a constant voltage having a reference potential to each of the first electrode ELT1 and the second electrode ELT2, an electric field for self-alignment of the light emitting element LD may be formed between the first electrode ELT1 and the second electrode ELT2. For example, by applying an AC alignment voltage to the second electrode ELT2 of each of the pixels PXL and providing a constant voltage having a reference potential (e.g., a ground potential) to the first electrode ELT1 of each of the pixels PXL, the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 of each pixel PXL.

[0288] In an embodiment, each light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 of the corresponding pixel PXL in the horizontal direction. For example, the first end EP1 of each of the light emitting elements LD may be disposed to face the first electrode ELT1. The second end EP2 of each of the light emitting elements LD may be disposed to face the second electrode ELT2.

[0289] refer to Fig.15e, a second insulating layer INS2 is formed on the light emitting element LD. In an embodiment, the second insulating layer INS2 may be formed by a deposition process and a patterning process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. For example, by depositing an insulating layer for forming the second insulating layer INS2 on the base layer BSL on which the light emitting element LD is aligned and then patterning the insulating layer, the second insulating layer INS2 may be formed only on a local area outside the first end EP1 and the second end EP2 of the light emitting element LD. In this way, the second insulating layer INS2 may be formed so that the light emitting element LD may be reliably fixed at the aligned position. In an embodiment, the pixel PXL may not include the second insulating layer INS2. In this case, the process of forming the second insulating layer INS2 may be omitted.

[0290] refer to Fig.15f , the first insulating layer INS1 is etched so that a region of each of the first electrode ELT1 and the second electrode ELT2 is exposed. Thus, a first contact portion CNP1 may be formed on the first electrode ELT1, and a second contact portion CNP2 may be formed on the second electrode ELT2. In an embodiment, the first contact portion CNP1 may refer to a region where the first electrode ELT1 is exposed by partially removing the first insulating layer INS1, and refers to a region where the first electrode ELT1 and the first contact electrode CNE1 formed by a subsequent process contact each other. Similarly, the second contact portion CNP2 may refer to a region where the second electrode ELT2 is exposed by partially removing the first insulating layer INS1, and refers to a region where the second electrode ELT2 and the second contact electrode CNE2 formed by a subsequent process contact each other.

[0291] refer to Figure 15g and Fig.15h , a first contact electrode CNE1 is formed on the first end EP1 of the light emitting element LD and the first electrode ELT1, and a second contact electrode CNE2 is formed on the second end EP2 of the light emitting element LD and the second electrode ELT2. For example, the first contact electrode CNE1 may be formed to cover at least one region of the first electrode ELT1 including the first contact portion CNP1 and the first end EP1 of the light emitting element LD. The second contact electrode CNE2 may be formed to cover at least one region of the second electrode ELT2 including the second contact portion CNP2 and the second end EP2 of the light emitting element LD. Due to the formation of the first contact electrode CNE1 and the second contact electrode CNE2, the first end EP1 of each of the light emitting elements LD may be connected to the first electrode ELT1, and the second end EP2 of each of the light emitting elements LD may be connected to the second electrode ELT2.

[0292] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be sequentially formed by different processes. However, the present disclosure is not limited thereto. For example, in an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed simultaneously.

[0293] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed by a process of forming a conductive layer including at least one same or different conductive material and / or a patterning process, and may be formed by various types of known processes. In an embodiment, each of the first contact electrode CNE1 and the second contact electrode CNE2 may be formed to be substantially transparent using at least one transparent electrode material. Therefore, light emitted from the light emitting element LD through the first end EP1 and the second end EP2 may pass through the first contact electrode CNE1 and the second contact electrode CNE2.

[0294] refer to Fig.15i , a fourth insulating layer INS4 is formed on one surface of the base layer BSL on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed. Fig.12 In an embodiment, the fourth insulating layer INS4 may be formed by a deposition process of at least one insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes.

[0295] After forming the pixel PXL in the display area DA through the above-mentioned process, a pixel PXL according to the embodiment of the present invention may be selectively provided on the pixel PXL. Fig.13 or Fig.14 An upper plate of the display panel PNL of an embodiment.

[0296] Fig.16 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and for example shows a pixel PXL corresponding to Figure 7 An embodiment of a cross section of line II-II'. Fig.17 and Fig.18 are cross-sectional views each showing a display device according to an embodiment of the present disclosure, and for example show a display device including Fig.16 The embodiment of the cross section of a region of the pixel PXL of the display panel PNL is different from the embodiment of the embodiment. Fig.17 and Fig.18 Each shows the Fig.10 and Fig.11a The upper plate of the display panel PNL of the embodiment of the present invention may be modified in various ways. Fig.11b or Fig.11cAs shown in the embodiment of FIG. 1 , the upper panel may include a black matrix BM disposed between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL. Figures 16 to 18 In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and a detailed description thereof will be omitted.

[0297] refer to Figures 16 to 18 , can also be omitted according to the implementation method Figure 12 to Figure 14 For example, according to the fourth insulating layer INS4 shown in FIG. Figure 12 to Figure 14 The pixel PXL of the embodiment and the display device including the pixel PXL are different, according to Figures 16 to 18 The pixel PXL and the display device including the pixel PXL according to the embodiment of the present invention may not include the fourth insulating layer INS4, and Figures 8a to 11c The pixel PXL of the embodiment and the display device including the pixel PXL are different, according to Figures 16 to 18 The pixel PXL of the embodiment and the display device including the pixel PXL may not include all of the third insulating layer INS3 and the fourth insulating layer INS4.

[0298] In this case, an additional mask process for forming the fourth insulating layer INS4 can be omitted, so that the manufacturing process can be further simplified. In addition, since the fourth insulating layer INS4 is not formed, the light efficiency of each pixel PXL can be further improved. For example, in the case where all of the third insulating layer INS3 and the fourth insulating layer INS4 are not arranged on the path where the light generated from the light emitting element LD is emitted from each pixel PXL, the amount of light that is confined in the optical waveguide formed by the transparent electrode and / or the insulating layer arranged in the pixel PXL and is therefore dissipated and cannot be emitted from each pixel PXL can be further reduced. Therefore, the amount of light emitted from each pixel PXL within a viewing angle having a predetermined angle including the forward direction of the display panel PNL (for example, a viewing angle in the range of 0° to ±180°) increases, so that the light efficiency of each pixel PXL can be further increased compared with the light efficiency of the structure including the third insulating layer INS3 and / or the fourth insulating layer INS4.

[0299] In the case where the fourth insulating layer INS4 is not provided, an upper substrate ENC or the like may be provided on the pixel PXL so that the display area DA may be encapsulated. Therefore, even in the case where the fourth insulating layer INS4 is not included, the pixel PXL may be protected from the external environment.

[0300] In an embodiment, the Figure 15a to Figure 15h Described process manufacturing Fig.16The pixels PXL and the display device including the pixels PXL (eg, the lower plate of the display panel PNL including the pixels PXL). Therefore, detailed description related thereto will be omitted.

[0301] Fig.19 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and for example shows a pixel PXL corresponding to Figure 7 An embodiment of a cross section of line II-II'. Fig. 20 and Fig.21 are cross-sectional views each showing a display device according to an embodiment of the present disclosure, and for example show a display device including Fig.19 The embodiment of the cross section of a region of the pixel PXL of the display panel PNL is different from the embodiment of the embodiment. Fig. 20 and Fig.21 Each shows the Fig.10 and Fig.11a The upper plate of the display panel PNL of the embodiment of the present invention may be modified in various ways. Fig.11b or Fig.11c As shown in the embodiment of FIG. 1 , the upper panel may include a black matrix BM disposed between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL. Figures 19 to 21 In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and a detailed description thereof will be omitted.

[0302] refer to Figures 19 to 21 , can be omitted according to the implementation Figures 9 to 11c For example, the display area DA may be encapsulated by disposing an upper substrate ENC or the like over the pixel PXL without forming the fourth insulating layer INS4 on the first contact electrode CNE1 and the second contact electrode CNE2. Therefore, even without including the fourth insulating layer INS4, the pixel PXL may be protected from the external environment.

[0303] In this case, with Figures 8a to 11cCompared with the embodiment of the present invention, the mask process of forming the fourth insulating layer INS4 can be omitted, so that the manufacturing process can be further simplified. In addition, since the fourth insulating layer INS4 is not formed, the light efficiency of each pixel PXL can be improved. For example, in the case where the fourth insulating layer INS4 is not provided on the path where the light generated from the light emitting element LD is emitted from each pixel PXL, the amount of light that is confined in the optical waveguide formed by the transparent electrode and / or the insulating layer provided in each pixel PXL and is therefore dissipated and cannot be emitted from the pixel PXL can be reduced. Therefore, the amount of light emitted from each pixel PXL within a viewing angle having a predetermined angle including the forward direction of the display panel PNL (for example, a viewing angle in a range from 0° to ±180°) increases, so that the light efficiency of each pixel PXL can be increased compared with the light efficiency of the structure including the fourth insulating layer INS4.

[0304] Figures 22a to 22g are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.19 Embodiments of the method for displaying a pixel PXL. Figures 22a to 22g In the description of the embodiments of the present invention, the same reference numerals are used to represent the same embodiments as those described above (for example, Figures 15a to 15i ) are similar or identical components to the components of the embodiment, and their detailed description will be omitted.

[0305] refer to Figure 19 to Figure 22a , first and second partition walls PW1 and PW2, first and second electrodes ELT1 and ELT2, and a first insulating layer INS1 are formed in each pixel area PXA on a base layer BSL on which a pixel circuit layer PCL is selectively formed. At least one light emitting element LD, for example, a plurality of light emitting elements LD may be provided and aligned between the first and second electrodes ELT1 and ELT2.

[0306] In an embodiment, the first and second partition walls PW1 and PW2, the first and second electrodes ELT1 and ELT2, and the first insulating layer INS1 may be formed by referring to Figures 15a to 15c The light emitting element LD can be manufactured by referring to Fig.15d The described process is provided to each emission area EMA and aligned in each emission area EMA. Therefore, a detailed description related thereto will be omitted.

[0307] refer to Figure 22b, a second insulating layer INS2 is formed on the first insulating layer INS1 on the second electrode ELT2 and the region other than the first end EP1 of the light emitting element LD. In an embodiment, the second insulating layer INS2 may be formed by a deposition process and a patterning process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. The second insulating layer INS2 may be patterned so that the first electrode ELT1 and the first end EP1 of the light emitting element LD are not covered thereby.

[0308] refer to Fig.22c , the first insulating layer INS1 is etched to expose a region of the first electrode ELT1, thereby forming a first contact portion CNP1 on the first electrode ELT1.

[0309] refer to Fig.22d , a first contact electrode CNE1 is formed on the first electrode ELT1 and the first end EP1 of the light emitting element LD. For example, the first contact electrode CNE1 may be formed to cover the first end EP1 of the light emitting element LD and at least one region of the first electrode ELT1 including the first contact portion CNP1. Since the first contact electrode CNE1 is formed, the first end EP1 of each of the light emitting elements LD may be connected to the first electrode ELT1. In an embodiment, the first contact electrode CNE1 may be formed by a process of forming a conductive layer including at least one conductive material and / or a patterning process, and may be formed by various types of known processes. In an embodiment, the first contact electrode CNE1 may be formed to be substantially transparent using at least one transparent electrode material.

[0310] refer to Fig.22e , a third insulating layer INS3 may be disposed on the first contact electrode CNE1 and the light emitting element LD to cover the first contact electrode CNE1 and a region of the light emitting element LD including the first end EP1. In addition, the second insulating layer INS2 is etched and removed on the second electrode ELT2 and the second end EP2 of the light emitting element LD. Therefore, the second insulating layer INS2 may be disposed only on a partial region of the light emitting element LD except the first end EP1 and the second end EP2.

[0311] refer to Figure 22f , the first insulating layer INS1 is etched so that a region of the second electrode ELT2 is exposed, thereby forming a second contact portion CNP2 on the second electrode ELT2.

[0312] refer to Figure 22g, a second contact electrode CNE2 is formed on the second electrode ELT2 and the second end EP2 of the light emitting element LD. For example, the second contact electrode CNE2 may be formed to cover the second end EP2 of the light emitting element LD and at least one region of the second electrode ELT2 including the second contact portion CNP2. Since the second contact electrode CNE2 is formed, the second end EP2 of each of the light emitting elements LD may be connected to the second electrode ELT2. In an embodiment, the second contact electrode CNE2 may be formed by a process of forming a conductive layer including at least one conductive material and / or a patterning process, and may be formed by various types of known processes. In an embodiment, the second contact electrode CNE2 may be formed to be substantially transparent using at least one transparent electrode material.

[0313] After forming the pixel PXL in the display area DA through the aforementioned process, the pixel PXL may be provided with a Fig. 20 or Fig.21 The upper plate of the display panel PNL of the embodiment can thereby encapsulate the pixels PXL.

[0314] Fig.23 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and for example shows a pixel PXL corresponding to Figure 7 An embodiment of a cross section of line II-II'. Fig.24 and Fig.25 are cross-sectional views each showing a display device according to an embodiment of the present disclosure, and for example show a display device including Fig.23 The embodiment of the cross section of a region of the pixel PXL of the display panel PNL is different from the embodiment of the embodiment. Fig.24 and Fig.25 Each shows the Fig.10 and Fig.11a The upper plate of the display panel PNL of the embodiment of the present invention may be modified in various ways. Fig.11b or Fig.11c As shown in the embodiment of FIG. 1 , the upper panel may include a black matrix BM disposed between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL. Figure 23 to Figure 25 In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and a detailed description thereof will be omitted.

[0315] refer to Figure 23 to Figure 25 ,like Figures 9 to 11cAs shown in the embodiment of the present invention, all of the third insulating layer INS3 and the fourth insulating layer INS4 are formed, and the corresponding regions of the third insulating layer INS3 and the fourth insulating layer INS4 around the light emitting element LD can be opened, so that the light efficiency of each pixel PXL can be improved. For example, the first opening OPN1 (also referred to as the "first light-transmitting hole") can be formed by opening the corresponding regions of the third insulating layer INS3 and the fourth insulating layer INS4 in the region adjacent to the first end EP1 of the light emitting element LD. The second opening OPN2 (also referred to as the "second light-transmitting hole") can be formed by opening a region of the fourth insulating layer INS4 in the region adjacent to the second end EP2 of the light emitting element LD.

[0316] In an embodiment, the first opening OPN1 may be disposed in a region corresponding to a space between the first end EP1 of the light emitting element LD and the first partition wall PW1 adjacent thereto. Similarly, the second opening OPN2 may be disposed in a region corresponding to a space between the second end EP2 of the light emitting element LD and the second partition wall PW2 adjacent thereto. In an embodiment, the first opening OPN1 and the second opening OPN2 may be disposed so as not to overlap with the first partition wall PW1 and the second partition wall PW2, respectively, but the present disclosure is not limited thereto. For example, in an embodiment, the first opening OPN1 and / or the second opening OPN2 may at least partially overlap with a corresponding region of the first partition wall PW1 and / or the second partition wall PW2 (e.g., an inclined surface adjacent to the light emitting element LD).

[0317] In an embodiment, the first opening OPN1 and the second opening OPN2 may be spaced apart from the first end EP1 and the second end EP2 of the light emitting element LD by substantially the same horizontal distances d1 and d2, respectively, and may have substantially the same horizontal widths w1 and w2, but the present disclosure is not limited thereto. In this case, the light output characteristics of each pixel PXL may be further uniformized. In the description of the embodiments of the present disclosure, the term "substantially the same" may refer to the term "exactly the same", and may also refer to the term "similar within a predetermined allowable error tolerance" in combination with consideration of process conditions, etc.

[0318] In addition, the first opening OPN1 and the second opening OPN2 may have a thickness and / or depth corresponding to the thickness of the third insulating layer INS3 and the fourth insulating layer INS4. For example, the first opening OPN1 may have a thickness corresponding to the sum of the thicknesses of the third insulating layer INS3 and the fourth insulating layer INS4 (for example, the same thickness as the sum of the thicknesses of the third insulating layer INS3 and the fourth insulating layer INS4), or may have a depth corresponding to the contour of the peripheral conductive layer and / or insulating layer surrounding the first opening OPN1. The second opening OPN2 may have a thickness corresponding to the thickness of the fourth insulating layer INS4 (for example, the same thickness as the thickness of the fourth insulating layer INS4), or may have a depth corresponding to the contour of the conductive layer and / or insulating layer surrounding the second opening OPN2.

[0319] In an embodiment, the first opening OPN1 and the second opening OPN2 are manufactured by a dry etching scheme capable of performing a vertical etching operation, so that the first opening OPN1 and the second opening OPN2 can pass through the third insulating layer INS3 and / or the fourth insulating layer INS4 in a direction substantially perpendicular to the plane on which the light emitting element LD is disposed (for example, a plane parallel to the base layer BSL). For example, each of the first opening OPN1 and the second opening OPN2 can vertically pass through the third insulating layer INS3 and / or the fourth insulating layer INS4, so that the first opening OPN1 and the second opening OPN2 have angles θ3 and θ4 in the range from about 80° to about 100° (for example, an angle of substantially 90° within a predetermined allowable error range) relative to the plane on which the light emitting element LD is disposed. Therefore, the amount of light dissipated in each pixel PXL can be reduced, and its light efficiency can be improved.

[0320] In an embodiment, the first opening OPN1 and the second opening OPN2 may completely pass through the third insulating layer INS3 and / or the fourth insulating layer INS4 in the corresponding region. For example, the first opening OPN1 may pass through the third insulating layer INS3 and the fourth insulating layer INS4 so that a region of the first contact electrode CNE1 is exposed. Similarly, the second opening OPN2 may pass through the fourth insulating layer INS4 so that a region of the second contact electrode CNE2 is exposed.

[0321] However, the present disclosure is not limited thereto. For example, in an embodiment, each of the first opening OPN1 and the second opening OPN2 may be formed in a shape in which the third insulating layer INS3 and / or the fourth insulating layer INS4 is partially etched in the thickness direction, in other words, in the form of a groove formed in the third insulating layer INS3 and / or the fourth insulating layer INS4. Alternatively, in an embodiment, the depth of the first opening OPN1 and the second opening OPN2 may be increased by partially etching the first contact electrode CNE1 and / or the second contact electrode CNE2 disposed below or under the third insulating layer INS3 and / or the fourth insulating layer INS4. As another alternative, in an embodiment, the first opening OPN1 may be formed only in the fourth insulating layer INS4, but not in the third insulating layer INS3.

[0322] In an embodiment, the horizontal width (eg, relative to the horizontal width of each of the first partition wall PW1 and the second partition wall PW2) is Figure 7 The width in the first direction DR1) may be in the range of 3 μm to 12 μm, the height thereof may be in the range of 0.5 μm to 3.5 μm, and the inclination angles θ1 and θ2 thereof may be in the range of 15° to 80°. The thickness of each of the first electrode ELT1 and the second electrode ELT2, the thickness of the first insulating layer INS1, the thickness of the second insulating layer INS2, the thickness of the first contact electrode CNE1, the thickness of the third insulating layer INS3, the thickness of the second contact electrode CNE2, and the thickness of the fourth insulating layer INS4 may be in the range of 0.01 μm to 2 μm, in the range of 0.01 μm to 2 μm, in the range of 0.05 μm to 1 μm, in the range of 0.005 μm to 2 μm, in the range of 0.05 μm to 3 μm, in the range of 0.005 μm to 2 μm, and in the range of 0.05 μm to 3 μm, respectively. In this case, each of the first and second openings OPN1 and OPN2 may have a horizontal width w1 , w2 in the range of 0.005 μm to 3 μm, and a thickness in the range of 0.005 μm to 6 μm.

[0323] Here, the size (e.g., horizontal width w1, w2, thickness and / or depth) and position (e.g., horizontal distance d1, d2 from the light emitting element LD) of each of the first opening OPN1 and the second opening OPN2, etc. may be changed in various ways according to the embodiment. For example, the size and / or position of each of the first opening OPN1 and the second opening OPN2 may be determined by experiments according to the light output characteristics of the pixel PXL.

[0324] In an embodiment, the first opening OPN1 and the second opening OPN2 may have different horizontal widths w1 and w2, or may be spaced apart from the first end EP1 and the second end EP2 of the light emitting element LD by different horizontal distances d1 and d2. In addition, the size of each of the first opening OPN1 and the second opening OPN2 may be changed in various ways depending on the size of a space that can be ensured at the position where the first opening OPN1 and the second opening OPN2 are to be provided (for example, a space between the light emitting element LD and the inclined surfaces of the first partition wall PW1 and the second partition wall PW2 adjacent thereto) and the thickness or profile of the peripheral insulating layer and / or the conductive layer including the third insulating layer INS3 and the fourth insulating layer INS4 and / or the first contact electrode CNE1 and the second contact electrode CNE2.

[0325] According to the above-described embodiment, since the third insulating layer INS3 and the fourth insulating layer INS4 are partially removed in the middle portion of the optical waveguide formed by the transparent electrode (e.g., the first contact electrode CNE1 and / or the second contact electrode CNE2) and / or the insulating layer (e.g., the third insulating layer INS3 and / or the fourth insulating layer INS4) provided in each pixel PXL, a refractive index difference between the first opening OPN1 and the second opening OPN2 and their peripheral areas can be given. Figures 9 to 11c In the pixel PXL of the embodiment of the present invention, at least some of the light confined in the optical waveguide and dissipated can be guided to travel through the optical waveguide according to Figure 23 to Figure 25 The first opening OPN1 and the second opening OPN2 of the embodiment change the light path. Therefore, the amount of light emitted from the pixel PXL may be increased, so that the light efficiency of each pixel PXL may be improved.

[0326] Figures 26a to 26c are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig.23 Embodiments of the method for displaying a pixel PXL. Figures 26a to 26c In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and a detailed description thereof will be omitted.

[0327] refer to Figure 23 to Figure 26a On the base layer BSL on which the pixel circuit layer PCL is selectively formed, first partition walls PW1 and second partition walls PW2, first electrodes ELT1 and second electrodes ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, a first contact electrode CNE1, a third insulating layer INS3 and a second contact electrode CNE2 are sequentially formed and / or arranged in each pixel area PXA. In an embodiment, the first and second partition walls PW1 and PW2, first electrodes ELT1 and ELT2, first insulating layer INS1, light emitting element LD, second insulating layer INS2, first contact electrode CNE1, third insulating layer INS3 and second contact electrode CNE2 are sequentially formed and / or arranged in each pixel area PXA. Figures 22a to 22gThe described process sequentially forms and / or disposes first and second partition walls PW1 and PW2, first and second electrodes ELT1 and ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, a first contact electrode CNE1, a third insulating layer INS3, and a second contact electrode CNE2.

[0328] refer to Figure 26b , a fourth insulating layer INS4 is formed on one surface of the base layer BSL on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed. For example, the fourth insulating layer INS4 for covering the entire surface of the display area DA (including each pixel area PXA) may be formed on one surface of the base layer BSL on which the first partition wall PW1 and the second partition wall PW2 of each pixel PXL are formed, the first electrode ELT1 and the second electrode ELT2, the first insulating layer INS1, the light emitting element LD, the second insulating layer INS2, the first contact electrode CNE1, the third insulating layer INS3, and the second contact electrode CNE2.

[0329] refer to Fig.26c , the first opening OPN1 and the second opening OPN2 may be formed by etching the third insulating layer INS3 and the fourth insulating layer INS4 in the region adjacent to the first end EP1 and the second end EP2 of the light emitting element LD. For example, the first opening OPN1 passing through the third insulating layer INS3 and the fourth insulating layer INS4 may be formed by etching the third insulating layer INS3 and the fourth insulating layer INS4 in the region corresponding to the space between the first end EP1 of the light emitting element LD and the first partition wall PW1 adjacent thereto. The second opening OPN2 passing through the fourth insulating layer INS4 may be formed by etching the fourth insulating layer INS4 in the region corresponding to the space between the second end EP2 of the light emitting element LD and the second partition wall PW2 adjacent thereto.

[0330] In an embodiment, the first opening OPN1 and the second opening OPN2 may be formed by vertically dry-etching the third insulating layer INS3 and the fourth insulating layer INS4. Therefore, the first opening OPN1 and the second opening OPN2 may be formed so that the first opening OPN1 and the second opening OPN2 vertically pass through the third insulating layer INS3 and the fourth insulating layer INS4 at angles θ3 and θ4 in the range of about 80° to about 100° (e.g., an angle of about 90°) relative to the plane on which the light emitting element LD is disposed.

[0331] Through the above process, it is possible to manufacture Fig.23In the embodiment, the pixel PXL and the display device including the pixel PXL (for example, the lower plate of the display panel PNL including the pixel PXL) are provided. In addition, in the embodiment, after the pixel PXL is formed in the display area DA, the pixel PXL may be selectively provided with a plurality of pixels. Fig.24 or Fig.25 An upper plate of the display panel PNL of an embodiment.

[0332] Fig. 27 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and for example shows a pixel PXL corresponding to Figure 7 An embodiment of a cross section of line II-II'. Fig.28 and Fig.29 are cross-sectional views each showing a display device according to an embodiment of the present disclosure, and for example show a display device including Fig. 27 The embodiment of the cross section of a region of the pixel PXL of the display panel PNL is different from the embodiment of the embodiment. Fig.28 and Fig.29 Each shows the Fig.10 and Fig.11a The upper plate of the display panel PNL of the embodiment of the present invention may be modified in various ways. Fig.11b or Fig.11c As shown in the embodiment of FIG. 1 , the upper panel may include a black matrix BM disposed between the first color conversion layer CCL1, the second color conversion layer CCL2, and the light scattering layer LSL. Figure 27 to Figure 29 In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and a detailed description thereof will be omitted.

[0333] refer to Figure 27 to Figure 29 ,like Figure 23 to Figure 25 As shown in the embodiment of the present invention, the third insulating layer INS3 and the fourth insulating layer INS4 are formed in their entirety, and the corresponding regions of the third insulating layer INS3 and the fourth insulating layer INS4 around the light emitting element LD may be opened, thereby improving the light efficiency of each pixel PXL. Figure 27 to Figure 29 In the embodiment of the present invention, the first opening OPN1′ and the second opening OPN2′ may be formed at the same position as that of the Figure 23 to Figure 25 In the embodiment, the first opening OPN1 and the second opening OPN2 are located at different positions.

[0334] For example, the first opening OPN1' may be disposed on the first partition wall PW1 adjacent to the first end EP1 of the light emitting element LD, and the second opening OPN2' may be disposed on the second partition wall PW2 adjacent to the second end EP2 of the light emitting element LD. For example, the first opening OPN1' may have a horizontal width w1' smaller than the width of the first partition wall PW1, and be disposed to overlap the first partition wall PW1. The second opening OPN2' may have a horizontal width w2' smaller than the width of the second partition wall PW2, and be disposed to overlap the second partition wall PW2.

[0335] In an embodiment, the first opening OPN1' and the second opening OPN2' may be spaced apart from the first end EP1 and the second end EP2 of the light emitting element LD by substantially the same horizontal distances d1' and d2', respectively, and may have substantially the same horizontal widths w1' and w2'. Therefore, the light output characteristics of each pixel PXL may be further uniformized. However, the present disclosure is not limited thereto. For example, in an embodiment, the first opening OPN1' and the second opening OPN2' may have different horizontal widths w1' and w2', or may be spaced apart from the light emitting element LD by different horizontal distances d1' and d2'.

[0336] In addition, the first opening OPN1' and the second opening OPN2' may have a thickness and / or depth corresponding to the thickness of the third insulating layer INS3 and the fourth insulating layer INS4. For example, the first opening OPN1' may have a thickness and / or depth corresponding to the sum of the thicknesses of the third insulating layer INS3 and the fourth insulating layer INS4 (for example, the same thickness as the sum of the thicknesses of the third insulating layer INS3 and the fourth insulating layer INS4). The second opening OPN2 may have a thickness and / or depth corresponding to the thickness of the fourth insulating layer INS4 (for example, the same thickness as the thickness of the fourth insulating layer INS4).

[0337] In an embodiment, the first opening OPN1' and the second opening OPN2' are manufactured by a dry etching scheme capable of performing a vertical etching operation, so that the first opening OPN1' and the second opening OPN2' can pass through the third insulating layer INS3 and / or the fourth insulating layer INS4 in a direction substantially perpendicular to the plane on which the light emitting element LD is disposed (e.g., a plane parallel to the base layer BSL). For example, each of the first opening OPN1' and the second opening OPN2' can vertically pass through the third insulating layer INS3 and / or the fourth insulating layer INS4, so that the first opening OPN1' and the second opening OPN2' have angles θ3' and θ4' in the range of about 80° to about 100° relative to the plane on which the light emitting element LD is disposed (e.g., an angle of substantially 90° within a predetermined allowable error margin). Therefore, light emitted from each pixel PXL can be guided to travel more reliably in the forward direction of the display panel PNL.

[0338] In an embodiment, the first opening OPN1' and the second opening OPN2' may completely pass through the third insulating layer INS3 and / or the fourth insulating layer INS4. For example, the first opening OPN1' may pass through the third insulating layer INS3 and the fourth insulating layer INS4, so that a region of the first contact electrode CNE1 above the first partition wall PW1 is exposed. Similarly, the second opening OPN2' may pass through the fourth insulating layer INS4, so that a region of the second contact electrode CNE2 above the second partition wall PW2 is exposed.

[0339] However, the present disclosure is not limited thereto. For example, in an embodiment, each of the first opening OPN1' and the second opening OPN2' may be formed in a shape in which the third insulating layer INS3 and / or the fourth insulating layer INS4 is partially etched in the thickness direction, in other words, in the form of a groove formed in the third insulating layer INS3 and / or the fourth insulating layer INS4. Alternatively, in an embodiment, the depth of the first opening OPN1' and the second opening OPN2' may be increased by partially etching the first contact electrode CNE1 and / or the second contact electrode CNE2 disposed below or under the third insulating layer INS3 and / or the fourth insulating layer INS4. As another alternative, in an embodiment, the first opening OPN1' may be formed only in the fourth insulating layer INS4, but not in the third insulating layer INS3.

[0340] In an embodiment, the horizontal width (eg, relative to the horizontal width of each of the first partition wall PW1 and the second partition wall PW2) is Figure 7The width in the first direction DR1) may be in the range of 3 μm to 12 μm, the height thereof may be in the range of 0.5 μm to 3.5 μm, and the inclination angles θ1 and θ2 thereof may be in the range of 15° to 80°. The thickness of each of the first electrode ELT1 and the second electrode ELT2, the thickness of the first insulating layer INS1, the thickness of the second insulating layer INS2, the thickness of the first contact electrode CNE1, the thickness of the third insulating layer INS3, the thickness of the second contact electrode CNE2, and the thickness of the fourth insulating layer INS4 may be in the range of 0.01 μm to 2 μm, in the range of 0.01 μm to 2 μm, in the range of 0.05 μm to 1 μm, in the range of 0.005 μm to 2 μm, in the range of 0.05 μm to 1 μm, in the range of 0.005 μm to 2 μm, and in the range of 0.05 μm to 1 μm, respectively. In this case, each of the first opening OPN1 ′ and the second opening OPN2 ′ may have a horizontal width w1 ′, w2 ′ in the range of 2 μm to 8 μm, and a thickness thereof may be in the range of 0.005 μm to 6 μm.

[0341] Here, the size (e.g., horizontal width w1', w2', thickness and / or depth) and position (e.g., horizontal distance d1', d2' from the light emitting element LD) of each of the first opening OPN1' and the second opening OPN2', etc. may be changed in various ways according to the embodiment. For example, the size and / or position of each of the first opening OPN1' and the second opening OPN2' may be determined by experiments according to the light output characteristics of the pixel PXL.

[0342] In an embodiment, the first opening OPN1' and the second opening OPN2' may have different horizontal widths w1' and w2', or may be spaced apart from the first end EP1 and the second end EP2 of the light emitting element LD by different horizontal distances d1' and d2'. In addition, the size of each of the first opening OPN1' and the second opening OPN2' may be changed in various ways depending on the size of a space (e.g., a space formed above the first partition wall PW1 and the second partition wall PW2) that may be ensured at the position where the first opening OPN1' and the second opening OPN2' are to be provided, the thickness or profile of the peripheral insulating layer and / or the conductive layer including the third insulating layer INS3 and the fourth insulating layer INS4 and / or the first contact electrode CNE1 and the second contact electrode CNE2, etc.

[0343] According to the above-described embodiment, since the third insulating layer INS3 and the fourth insulating layer INS4 are partially removed in the middle portion of the optical waveguide formed by the transparent electrode (e.g., the first contact electrode CNE1 and / or the second contact electrode CNE2) and / or the insulating layer (e.g., the third insulating layer INS3 and / or the fourth insulating layer INS4) provided in each pixel PXL, a refractive index difference between the first opening OPN1' and the second opening OPN2' and the peripheral area thereof can be given. Figures 9 to 11c In the pixel PXL of the embodiment of the present invention, at least some of the light confined in the optical waveguide and dissipated may travel through the optical waveguide according to Figure 27 to Figure 29 The first opening OPN1' and the second opening OPN2' of the embodiment change the light path. Therefore, the amount of light emitted from the pixel PXL may be increased, so that the light efficiency of each pixel PXL may be improved.

[0344] Fig.30a and Fig.30b are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Fig. 27 Embodiments of the method for displaying a pixel PXL. Figure 30a to Figure 30b In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and a detailed description thereof will be omitted.

[0345] refer to Figure 27 to Figure 30a , a first partition wall PW1 and a second partition wall PW2, a first electrode ELT1 and a second electrode ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, a first contact electrode CNE1, a third insulating layer INS3, a second contact electrode CNE2, and a fourth insulating layer INS4 are sequentially formed and / or arranged in each pixel area PXA on a base layer BSL on which a pixel circuit layer PCL is selectively formed. In an embodiment, the first and second partition walls PW1 and PW2, the first and second electrodes ELT1 and ELT2, the first insulating layer INS1, the light emitting element LD, the second insulating layer INS2, the first contact electrode CNE1, the third insulating layer INS3, the second contact electrode CNE2, and the fourth insulating layer INS4 may be sequentially formed and / or arranged in each pixel area PXA. Figure 26a to Figure 26b The described process sequentially forms and / or arranges first and second partition walls PW1 and PW2, first and second electrodes ELT1 and ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, a first contact electrode CNE1, a third insulating layer INS3, a second contact electrode CNE2, and a fourth insulating layer INS4.

[0346] refer to Fig.30b, a first opening OPN1' and a second opening OPN2' passing through the third insulating layer INS3 and the fourth insulating layer INS4 may be formed on the first partition wall PW1 adjacent to the first end EP1 of the light emitting element LD and on the second partition wall PW2 adjacent to the second end EP2 of the light emitting element LD. For example, the first opening OPN1' may be formed by etching the third insulating layer INS3 and the fourth insulating layer INS4 on the first partition wall PW1 adjacent to the first end EP1 of the light emitting element LD. The second opening OPN2' may be formed by etching the fourth insulating layer INS4 on the second partition wall PW2 adjacent to the second end EP2 of the light emitting element LD.

[0347] In an embodiment, the first opening OPN1' and the second opening OPN2' may be formed by vertically dry-etching the third insulating layer INS3 and the fourth insulating layer INS4. Therefore, the first opening OPN1' and the second opening OPN2' may be formed so that the first opening OPN1' and the second opening OPN2' vertically pass through the third insulating layer INS3 and the fourth insulating layer INS4 at angles θ3' and θ4' in the range of about 80° to about 100° (e.g., an angle of about 90°) relative to the plane on which the light emitting element LD is disposed.

[0348] Through the above process, it is possible to manufacture Fig. 27 In the embodiment, the pixel PXL and the display device including the pixel PXL (for example, the lower plate of the display panel PNL including the pixel PXL) are provided. In addition, in the embodiment, after the pixel PXL is formed in the display area DA, the pixel PXL may be selectively provided with a plurality of pixels. Fig.28 or Fig.29 An upper plate of the display panel PNL of an embodiment.

[0349] Figure 31 to Figure 34 Each is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and shows, for example, a pixel PXL corresponding to Figure 7 Different embodiments of the cross section of line II-II'. Figure 31 to Figure 34 In the description of the embodiments of the present invention, the same reference numerals will be used to refer to components similar to or identical to those of the previous embodiments, and a detailed description thereof will be omitted.

[0350] refer to Fig.31 ,and Fig.23 Compared with the pixel PXL of FIG. 1 , each pixel PXL may not include the third insulating layer INS3. For example, the pixel PXL may include only the third insulating layer INS3 disposed at Fig.23In addition, the fourth insulating layer INS4 may include a first opening OPN1 and a second opening OPN2, the first opening OPN1 being disposed in a region corresponding to a space between the first end EP1 of the light emitting element LD and the first partition wall PW1 adjacent thereto, and the second opening OPN2 being disposed in a region corresponding to a space between the second end EP2 of the light emitting element LD and the second partition wall PW2 adjacent thereto.

[0351] refer to Fig.32 ,and Fig.31 Similar to the pixels PXL, each pixel PXL may not include the third insulating layer INS3, and may include a layer formed between Fig.31 The first opening OPN1 and the second opening OPN2 of the pixel PXL are located at different positions. For example, the pixel PXL may include only the first opening OPN1′ and the second opening OPN2′ provided at Fig. 27 In addition, the fourth insulating layer INS4 may include a first opening OPN1' disposed on the first partition wall PW1 and a second opening OPN2' disposed on the second partition wall PW2.

[0352] refer to Fig.33 ,and Fig.23 Compared with the pixel PXL of FIG. 1 , each pixel PXL may not include the fourth insulating layer INS4. For example, the pixel PXL may include only the fourth insulating layer INS4 disposed at Fig.23 In an embodiment, the third insulating layer INS3 may include a first opening OPN1 disposed in a region corresponding to a space between the first end EP1 of the light emitting element LD and the first partition wall PW1 adjacent thereto.

[0353] refer to Fig.34 ,and Fig.33 Similar to the pixels PXL, each pixel PXL may not include the fourth insulating layer INS4, and may include a layer formed between Fig.33 The pixel PXL may include a first opening OPN1′ at a position different from the first opening OPN1 of the pixel PXL. For example, the pixel PXL may include only the first opening OPN1′ disposed at Fig. 27 The third insulating layer INS3 in the pixel PXL and the third insulating layer INS3 in the fourth insulating layer INS4 may include a first opening OPN1 ′ disposed on the first partition wall PW1 .

[0354] As shown in the above-mentioned embodiments, the pixel PXL and the display device including the pixel PXL according to the embodiments of the present disclosure may have various structures. For example, at least one pixel PXL disposed in the display area DA may have an application Figures 7 to 34 A structure of only any one embodiment among the embodiments or a structure to which a combination of at least two embodiments among the aforementioned embodiments is applied.

[0355] In an embodiment, if Figures 7 to 11c As shown in the embodiment, each pixel PXL and the display device including the pixel PXL may include a third insulating layer INS3 covering the first end EP1 of the light emitting element LD and the first contact electrode CNE1, and a fourth insulating layer INS4 covering the space above the light emitting element LD and the first contact electrode CNE1 and the second contact electrode CNE2 and each pixel area PXA and / or the display area DA including the pixel area PXA.

[0356] In an embodiment, if Figure 7 as well as Figure 12 to Figure 22g As shown in the embodiment, each pixel PXL and the display device including the pixel PXL may not include at least one of the third insulating layer INS3 and the fourth insulating layer INS4, so that Figures 8a to 11c Compared with the light output characteristics of the embodiment of the present invention, the light output characteristics can be enhanced.

[0357] In an embodiment, if Figure 7 as well as Figure 23 to Figure 30b As shown in the embodiment of the present invention, each pixel PXL and the display device including the pixel PXL may include all of the third insulating layer INS3 and the fourth insulating layer INS4, and include first openings OPN1, OPN1' and second openings OPN2, OPN2' formed in the third insulating layer INS3 and the fourth insulating layer INS4 on opposite sides of the light emitting element LD, so that Figures 8a to 11c For example, each pixel PXL and a display device including the pixel PXL may include each first opening OPN1, OPN1' provided in a region corresponding to a space between a first end EP1 of the light emitting element LD and a first partition wall PW1 adjacent thereto or provided on the first partition wall PW1, and each second opening OPN2, OPN2' provided in a region corresponding to a space between a second end EP2 of the light emitting element LD and a second partition wall PW2 adjacent thereto or provided on the second partition wall PW2.

[0358] In an embodiment, if Figure 31 to Figure 34 As shown in the embodiment, each pixel PXL and the display device including the pixel PXL may have Figure 7as well as Figure 12 to Figure 22g At least one of the embodiments and Figure 7 as well as Figure 23 to Figure 30b The combined structure of at least one embodiment of the embodiments of Figures 8a to 11c Compared with the light output characteristics of the embodiment of the present invention, the light output characteristics can be enhanced (or improved). For example, each pixel PXL and the display device including the pixel PXL may include only the fourth insulating layer INS4 of the third insulating layer INS3 and the fourth insulating layer INS4. The fourth insulating layer INS4 may include first openings OPN1, OPN1' and second openings OPN2, OPN2' arranged on opposite sides of the light emitting element LD. In addition, each pixel PXL and the display device including the pixel PXL may include only the third insulating layer INS3 of the third insulating layer INS3 and the fourth insulating layer INS4. The third insulating layer INS3 may include each first opening OPN1, OPN1' arranged on one side of the light emitting element LD (for example, around the first end EP1).

[0359] As described above, in each pixel PXL, a display device including the pixel PXL, and a method of manufacturing the display device according to various embodiments of the present disclosure, light efficiency of the pixel PXL including each light emitting element LD may be enhanced (or improved).

[0360] Although the scope of the present disclosure is described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and replacements may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0361] The scope of the present disclosure is not limited by the detailed description of this specification, and should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A display device comprising pixels arranged in a display area, in, The pixels include: a first partition wall and a second partition wall disposed on the base layer and spaced apart from each other; A first electrode and a second electrode are respectively disposed on the first partition wall and the second partition wall and are spaced apart from each other; a light emitting element disposed between the first electrode and the second electrode and including a first end connected to the first electrode and a second end connected to the second electrode; and at least one insulating layer disposed on the light emitting element and at least one of the first electrode and the second electrode, and including at least one of the first opening and the second opening; wherein the first opening is disposed in a region corresponding to a space between the first end of the light emitting element and a side wall of the first partition wall away from the light emitting element, and The second opening is disposed in a region corresponding to a space between the second end of the light emitting element and a side wall of the second partition wall away from the light emitting element.

2. The display device according to claim 1, in, The first opening is provided in a region corresponding to a space between the first end of the light emitting element and a side wall of the first partition wall adjacent to the light emitting element, and The second opening is disposed in a region corresponding to a space between the second end of the light emitting element and a side wall of the second partition wall adjacent to the light emitting element.

3. The display device according to claim 1, in, The first opening is disposed on the first partition wall, and Wherein, the second opening is arranged on the second partition wall.

4. The display device according to claim 3, in, The first opening has a width that is the same as or smaller than a width of the first partition wall and is disposed to overlap with the first partition wall, and The second opening has a width that is the same as or smaller than a width of the second partition wall, and is disposed to overlap with the second partition wall.

5. The display device according to claim 1, wherein: The first opening and the second opening are spaced apart from the light emitting element by the same horizontal distance.

6. The display device according to claim 1, wherein: Each of the first opening and the second opening vertically penetrates the at least one insulating layer at an angle in a range of 80° to 100° relative to a plane on which the light emitting element is disposed.

7. The display device according to claim 1, in, The first partition wall includes an inclined surface or a curved surface facing the first end of the light emitting element, and The second partition wall includes an inclined surface or a curved surface facing the second end of the light emitting element.

8. The display device according to claim 7, wherein: Each of the first electrode and the second electrode includes an inclined surface or a curved surface corresponding to a shape of a corresponding one of the first partition wall and the second partition wall, and includes a reflective electrode layer.

9. The display device according to claim 1, further comprising at least one of the following: a first insulating layer disposed on the first electrode and the second electrode and exposing a region of the first electrode and a region of the second electrode; and A second insulating layer is disposed on the light emitting element and exposes the first end and the second end of the light emitting element.

10. The display device according to claim 1, wherein: The pixels include: a third electrode disposed on the first end of the light emitting element and the first electrode and configured to electrically connect the first end of the light emitting element to the first electrode; and The fourth electrode is disposed on the second end of the light emitting element and the second electrode and is configured to electrically connect the second end of the light emitting element to the second electrode.

11. The display device according to claim 10, in, The at least one insulating layer is directly disposed on at least one of the third electrode and the fourth electrode, and The first opening and the second opening expose a region of the third electrode and a region of the fourth electrode respectively.

12. The display device according to claim 10, wherein: The at least one insulating layer comprises at least one of the following: a third insulating layer, disposed on the third electrode and a region including the first end of the light emitting element, and configured to cover an end of the third electrode on the light emitting element; as well as A fourth insulating layer is provided on the entire surface of the display region, wherein the display region includes a space extending over the light emitting element, the third electrode, and the fourth electrode.

13. The display device according to claim 12, in, The first opening passes through the third insulating layer and the fourth insulating layer, and Wherein, the second opening passes through the fourth insulating layer. 14 . The display device according to claim 1 , further comprising an upper substrate disposed over the pixels and comprising a light conversion layer overlapping the pixels.

15. The display device according to claim 14, wherein: The light conversion layer includes at least one of the following: a color filter layer disposed on the upper substrate to face the pixels; as well as The color conversion layer is disposed between the color filter layer and the pixels and includes color conversion particles.

16. A method for manufacturing a display device, comprising: forming a first partition wall and a second partition wall spaced apart from each other on the base layer; forming a first electrode and a second electrode on the first partition wall and the second partition wall respectively; providing and aligning a light emitting element between the first electrode and the second electrode; forming a third electrode and a fourth electrode, wherein the third electrode and the fourth electrode are configured to connect the first end and the second end of the light emitting element to the first electrode and the second electrode, respectively; forming at least one insulating layer on the light emitting element and at least one of the third electrode and the fourth electrode; as well as forming at least one opening in the at least one insulating layer; Wherein, forming the at least one opening comprises: forming a first opening by etching the at least one insulating layer in a region corresponding to a space between a side wall of the first partition wall away from the light emitting element and the first end of the light emitting element; and A second opening is formed by etching the at least one insulating layer in a region corresponding to a space between a side wall of the second partition wall away from the light emitting element and the second end of the light emitting element.

17. The method according to claim 16, wherein: Forming the at least one opening includes dry etching the at least one insulating layer in a vertical direction.

18. The method according to claim 16, comprising: continuously forming the third electrode and the fourth electrode, Wherein, forming the at least one insulating layer comprises at least one of the following items: After forming the third electrode, forming an insulating layer configured to cover the third electrode and a region including the first end of the light emitting element; and After forming the fourth electrode, an insulating layer configured to cover the entire surface of a display region including a space extending over the light emitting element, the third electrode, and the fourth electrode is formed.

19. The method according to claim 16, wherein: Forming the at least one opening comprises: forming a first opening by etching the at least one insulating layer in a region corresponding to a space between a side wall of the first partition wall adjacent to the light emitting element and the first end of the light emitting element, and A second opening is formed by etching the at least one insulating layer in a region corresponding to a space between a side wall of the second partition wall adjacent to the light emitting element and the second end of the light emitting element.

20. The method according to claim 16, wherein: Forming the at least one opening comprises: forming a first opening by etching the at least one insulating layer in a region above the first partition wall, and A second opening is formed by etching the at least one insulating layer in a region above the second partition wall.

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