Spin-orbit torque magnetic memory array and its fabrication

Abstract

A magnetic memory device (300) includes a spin-orbit torque magnetic random access memory (SOT-MRAM) device (104) and a write circuit at a grid intersection of first conductive lines (102) extending along a first direction and second conductive lines (314) extending along a second direction, the write circuit including a first transistor (116) and a second transistor (118), the first transistor being coupled to each corresponding first conductive line to apply a first write current (120) along the first conductive line in the first direction, and the second transistor (118) being used to select a separate SOT-MRAM device and apply a second write current (122) to the separate SOT-MRAM device along an axis perpendicular to the layers of the separate SOT-MRAM device. A corresponding manufacturing method includes different instances of depositing a common layer and electrically isolating the respective common layers.

Description

Technical Field

[0001] The present invention relates generally to the field of magnetic memory applications, and more particularly to spin-orbit torque (SOT) based magnetic memory. Background Art

[0002] Magnetoresistive random access memory (MRAM) is a non-volatile memory technology that stores data through magnetic storage elements. MRAM devices store information by changing the torque orientation of the storage layer. For example, a "1" or "0" can be stored in each MRAM cell based on whether the storage layer is aligned parallel or anti-parallel relative to the reference layer.

[0003] The memory application space is becoming more challenging as the performance requirements for memory-based devices increase.MRAM-based memory systems have performance advantages over traditional memory systems due to many useful properties of MRAM (e.g., data retention, error resistance, and longevity of memory cells). Summary of the invention

[0004] There is a need for systems and / or devices with more efficient, accurate and effective methods for manufacturing and / or operating memory systems. Such systems, devices and methods optionally supplement or replace conventional systems, devices and methods for manufacturing and / or operating memory systems.

[0005] This disclosure describes various implementations of MRAM systems and devices.

[0006] (A1) A magnetic memory device is provided. The magnetic memory device includes a plurality of first wires extending along a first direction and a plurality of second wires extending along a second direction different from the first direction, and the plurality of second wires form a grid with the plurality of first wires. The device includes a plurality of spin-orbit torque magnetic random access memory (SOT-MRAM) devices, each of the plurality of SOT-MRAM devices being arranged at a corresponding position on the grid. The device includes a write circuit, the write circuit including a transistor coupled to each corresponding first wire of the plurality of first wires, for applying a first write current along the corresponding first wire in a first direction. The device also includes a readout circuit for reading a data value stored by the corresponding SOT-MRAM device.

[0007] (A2) In some embodiments of (A1), the write circuit further includes a second transistor for selecting an individual SOT-MRAM device and applying a second write current to the individual SOT-MRAM device. The second write current is along an axis of the individual SOT-MRAM device.

[0008] (A3) In some embodiments of any one of (A1)-(A2), a first write current applied in a first direction along a corresponding first conductive line provides a first magnetic torque to the individual SOT-MRAM device; and the first magnetic torque is lower than a threshold for switching the magnetic orientation of the individual SOT-MRAM device.

[0009] (A4) In some embodiments of (A3), a second write current applied along the axis of the separate SOT-MRAM device provides a second magnetic torque to the separate SOT-MRAM device, and the sum of the first magnetic torque and the second magnetic torque is above a threshold for switching the magnetic orientation of the separate SOT-MRAM device.

[0010] (A5) In some embodiments of any of (A1)-(A4), each of the plurality of SOT-MRAM devices includes a different instance of a common set of layers.

[0011] (A6) In some embodiments of (A5), the common set of layers includes: a magnetic storage layer, a magnetic reference layer, and a spacer layer separating the magnetic storage layer from the magnetic reference layer. The data value is encoded in the relative magnetic orientation of the magnetic storage layer and the magnetic reference layer.

[0012] (A7) In some embodiments of (A6), the magnetic storage layer is disposed closer to the corresponding first conductive line than the magnetic reference layer is to the corresponding first conductive line.

[0013] (A8) In some embodiments of any one of (A6)-(A7), the magnetic storage layer and the magnetic reference layer exhibit perpendicular magnetic anisotropy.

[0014] (A9) In some embodiments of any of (A1)-(A8), each first conductive line is a different instance of the first conductive material layer.

[0015] (A10) In some embodiments of any of (A1)-(A9), each second conductive line is a different instance of the second conductive material layer.

[0016] (A11) In some embodiments of any of (A1)-(A10), the plurality of first conductive lines include wires and the plurality of second conductive lines include wires.

[0017] (A12) In some embodiments of any of (A1)-(A11), the first direction and the second direction differ by substantially 90 degrees.

[0018] (B1) A magnetic memory device is provided. The magnetic memory device includes a first wire extending along a first direction and a plurality of spin-orbit torque magnetic random access memory (SOT-MRAM) devices, each of the plurality of SOT-MRAM devices being arranged at a corresponding position along the first wire. The device includes a write circuit, the write circuit including: a first transistor coupled to the first wire to apply a first write current along the first wire in a first direction; and a second transistor for selecting a separate SOT-MRAM device and applying a second write current to the separate SOT-MRAM device simultaneously with the application of the first write current. The second write current is along the axis of the separate SOT-MRAM device. The device also includes a readout circuit for reading a data value stored by the separate SOT-MRAM device.

[0019] (B2) In some embodiments of (B1), a first write current applied along a first conductive line in a first direction provides a first magnetic torque to the separate SOT-MRAM device, and the first magnetic torque from the first write current applied along the first conductive line in the first direction is lower than a threshold for switching the magnetic orientation of the separate SOT-MRAM device.

[0020] (B3) In some embodiments of (B2), a second write current applied along the axis of the separate SOT-MRAM device provides a second magnetic torque to the separate SOT-MRAM device, and the sum of the first magnetic torque and the second magnetic torque is higher than a threshold for switching the magnetic orientation of the separate SOT-MRAM device.

[0021] (B4) In some embodiments of (B3), the individual SOT-MRAM devices exhibit voltage-controlled magnetic anisotropy.

[0022] (B5) In some embodiments of any of (B1)-(B3), each of the plurality of SOT-MRAM devices includes a different instance of a common group layer.

[0023] (B6) In some embodiments of (B5), the common set of layers includes a magnetic storage layer, a magnetic reference layer, and a spacer layer separating the magnetic storage layer from the magnetic reference layer. The data value is encoded in the relative magnetic orientation of the magnetic storage layer and the magnetic reference layer.

[0024] (B7) In some embodiments of (B6), the magnetic storage layer is disposed closer to the corresponding first conductive line than the magnetic reference layer is to the corresponding first conductive line.

[0025] (B8) In some embodiments of any one of (B6)-(B7), the magnetic storage layer and the magnetic reference layer exhibit perpendicular magnetic anisotropy.

[0026] (C1) A method for manufacturing a magnetic memory device is provided. The method includes: depositing a first conductive material layer; electrically isolating multiple different instances of the first conductive material layer to form multiple first wires extending along a first direction; and depositing a common group device layer on the multiple different instances of the first conductive material layer. The method also includes electrically isolating different instances of the common group device layer to form multiple spin-orbit torque magnetic random access memory (SOT-MRAM) devices. Each of the multiple SOT-MRAM devices is located on a different instance of the first conductive material layer. The method also includes depositing a second conductive material layer on different instances of the common group device layer, and electrically isolating multiple different instances of the second conductive material layer to form multiple second wires, which extend along a second direction, wherein the second direction is different from the first direction.

[0027] (C2) In some embodiments of (C1), electrically isolating different instances of the common set of device layers includes etching the common set of device layers into lines extending in the second direction.

[0028] (C3) In some embodiments of (C2), electrically isolating different instances of the common set of device layers further comprises: destroying conductivity of portions of each line without etching the portions of each line to form conductive pillars from each line. Each SOT-MRAM device includes a conductive pillar.

[0029] (C4) In some embodiments of (C3), before destroying the conductivity of multiple portions of each line without etching the multiple portions of each line, the method includes depositing a protective layer on the line and patterning the protective layer to expose the multiple portions of the line.

[0030] (C5) In some embodiments of any of (C2)-(C4), each different instance of the second conductive material layer coincides with a corresponding line extending in the second direction.

[0031] (C6) In some embodiments of any of (C1)-(C2), or (C5), electrically isolating different instances of a common set of device layers includes etching the common set of device layers into lines extending in a first direction.

[0032] (C7) In some embodiments of (C6), each different instance of the first conductive material layer coincides with a corresponding line extending in the first direction.

[0033] (C8) In some embodiments of any one of (C2)-(C7), the etching comprises reactive ion etching (eg, any one of the etching operations described in (C2)-(C7)).

[0034] (C9) In some embodiments of (C8), the reactive ion etching is based on carbonyl chemistry.

[0035] (C10) In some embodiments of any of (C1)-(C9), a common set of device layers is deposited after electrically isolating the multiple different instances of the first conductive material layer.

[0036] (C11) In some embodiments of any of (C1)-(C10), the second conductive material layer is deposited after electrically isolating the multiple different instances of the first conductive material layer.

[0037] (C12) In some embodiments of any of (C1)-(C11), electrically isolating the multiple different instances of the first conductive material layer includes removing portions of the first conductive material layer.

[0038] (C13) In some embodiments of any one of (C1)-(C11), electrically isolating the multiple different instances of the first conductive material layer includes destroying conductivity of multiple portions of the first conductive material layer without removing the multiple portions of the first conductive material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] For a better understanding of the various described embodiments, reference should be made to the following description of the embodiments in conjunction with the following drawings, in which like reference numerals designate corresponding parts throughout the several views.

[0040] Figure 1 A diagram illustrating a magnetic memory device according to some embodiments.

[0041] Figure 2 FIG. 2 shows the relationship between different magnetic torques applied during a write operation according to some embodiments. Figure 1 The effect of the switching threshold of the device shown in .

[0042] Figure 3 A diagram of a magnetic memory device according to some embodiments is illustrated.

[0043] Figure 4 A diagram illustrating a magnetic memory device according to some embodiments.

[0044] Figure 5 A block diagram of a magnetic memory device according to some embodiments is shown.

[0045] Figure 6 A schematic diagram of a magnetic memory device according to some embodiments is shown.

[0046] 7A to 7F A process for fabricating an array of SOT-MRAM devices according to some embodiments is schematically illustrated.

[0047] FIG. 8A to FIG. 8B A flow chart is shown of a process for fabricating an array of SOT-MRAM devices according to some embodiments. DETAILED DESCRIPTION

[0048] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the various described embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other cases, well-known methods, processes, components, circuits, and networks are not described in detail to avoid unnecessarily obscuring aspects of the embodiments.

[0049] As used herein, the term "torque" refers to magnetic torque (eg, a measure of the tendency to change the direction of a magnetic moment). In some embodiments, magnetic torque has units of energy.

[0050] Figure 1 A magnetic memory device 100 according to some embodiments is shown. In some embodiments, the magnetic memory device 100 is a spin-orbit torque magnetic memory device that uses spin transfer torque (STT) and / or voltage controlled magnetic anisotropy (VCMA) to help reverse the torque of the magnetic bit storage layer.

[0051] To this end, the device 100 includes a first conductive line (e.g., a SOT conductive line) 102 and a plurality of spin-orbit torque magnetic random access memory (SOT-MRAM) devices 104 (e.g., devices 104a to 104c) disposed at corresponding positions along the first conductive line 102. The first conductive line 102 extends along a first direction (e.g., a direction along a plane of a substrate 124 on which the device 100 is fabricated).

[0052] In some embodiments, the SOT-MRAM device 104 includes different instances of the common set of layers 106. For example, in some embodiments, different instances of the layer are formed by depositing the layer on a portion of a chip and patterning the layer (by etching and / or electrically isolating portions of the layer) to form different instances (as described below with reference to 7A to 7F The process 700 and FIG. 8A to FIG. 8B In some embodiments, each SOT-MRAM device 104 forms a pillar.

[0053] In some embodiments, the common group of layers 106 includes a magnetic storage layer 108, a magnetic reference layer 112, and a spacer layer 110 separating the magnetic storage layer from the magnetic reference layer. In some embodiments, the common group of layers 106 includes a top electrode layer 114 (the top electrode layer includes a conductive material). One or more data values ​​are encoded in the relative magnetic orientation of the magnetic storage layer and the magnetic reference layer. For example, in some embodiments, the magnetic storage layer 108 and the magnetic reference layer 112 exhibit perpendicular magnetic anisotropy (e.g., each of the layers 108 / 112 exhibits a preferential axis of its respective torque, which is perpendicular to the plane of the layers 108 / 112). In some embodiments, the anti-parallel alignment of the torque of the magnetic storage layer relative to the torque of the magnetic reference layer corresponds to a first data value (e.g., a "0" value), and the parallel alignment of the torque of the magnetic storage layer relative to the torque of the magnetic reference layer corresponds to a second data value different from the first data value (e.g., a "1" value). In some embodiments, the torque of the magnetic reference layer 112 is substantially fixed (e.g., in either an up or down direction).

[0054] Note that in some embodiments, the SOT-MRAM device 104b has the same layers, torque characteristics, and anisotropy as the SOT-MRAM devices 104a and 104c. However, the arrows representing torque shown in the SOT-MRAM devices 104a and 104c are not shown in the SOT-MRAM device 104b to make room for the arrows representing the second write current 122 described below.

[0055] In some embodiments, the spacer layer 110 is a tunnel barrier. In some embodiments, the spacer layer 110 includes an insulating material. In some embodiments, the spacer layer 110 includes a material selected from the group consisting of MgO, SiOx, AlOx, or alloys thereof. In some embodiments, the spacer layer 110 has a thickness of 0.2 to 2 nanometers (nm), which may depend on the target resistance. In some embodiments, the spacer layer 110 is deposited using a sputtering method (e.g., from a MgO sintered target or by sputtering Mg metal and oxidizing it).

[0056] In some embodiments, the magnetic storage layer 108 (sometimes also referred to as a "free layer") includes a plurality of sublayers (e.g., separately deposited sublayers). In some embodiments, the sublayers include a metal buffer layer used as a perpendicular magnetic anisotropy (PMA) enhancement portion. In some embodiments, the sublayers include one or more sublayers, the one or more sublayers comprising a material selected from the group consisting of Ta, Cr, W, V, Mo, Pt, Ru, Pd, Cu, Ag, Rh, or alloys thereof. In some embodiments, the thickness of the magnetic storage layer 108 is 1 to 10 nm, preferably 1 to 5 nm.

[0057] In some embodiments, the magnetic reference layer 112 (sometimes also referred to as a "fixed layer") includes a plurality of sublayers (e.g., separately deposited sublayers). In some embodiments, the sublayers include one or more sublayers comprising a material from the group consisting of CoFeB, CoFe, CoFeNi, FeNi, FeB, or alloys thereof. In some embodiments, the sublayers include a plurality of Co / (Pt, Pd) multilayers. In some embodiments, the sublayers include one or more sublayers comprising a Heusler Alloy (e.g., a material selected from the group consisting of CoMnSi, CoMnGe, CoMnAl, CoMnFeSi, CoFeSi, CoFeAl, CoCrFeAl, CoFeAlSi). In some embodiments, the sublayers include a capping layer as a PMA enhancement. In some embodiments, the capping layer includes a material selected from the group consisting of Ta, Cr, W, V, Pt, Ru, Pd, Cu, Ag, Rh, or alloys thereof. In some embodiments, the capping layer includes MgO. In some embodiments, the capping layer has a thickness in the range of 1 to 10 nm. In some embodiments, the magnetic reference layer 112 has a thickness (eg, total thickness) in a range of 1 to 20 nm, preferably 1 to 10 nm, and more preferably 1 to 5 nm.

[0058] In some embodiments, the first wire 102 includes a first conductive material. In some embodiments, the first wire 102 includes a material exhibiting a strong spin Hall effect (SHE). In some embodiments, the first wire 102 includes a heavy metal. In some embodiments, the first wire 102 includes Pt, Ta, W, or an alloy thereof. In some embodiments, the thickness of the first wire 102 is in the range of 2 to 100 nm, preferably 5 to 80 nm, and more preferably 8 to 50 nm. In some embodiments, the thickness depends on the target resistance.

[0059] The device 100 also includes a write circuit. In some embodiments, the write circuit is configured to set the relative magnetic orientation of the magnetic storage layer 108 and the magnetic reference layer 112 (e.g., by setting the direction of the magnetic orientation of the magnetic storage layer). The write circuit includes a first transistor 116 coupled to the first wire 102 for applying a first write current 120 along the first wire in a first direction (e.g., along the plane of the substrate 124). The write circuit also includes a second transistor 118 for selecting a separate SOT-MRAM device 104 (e.g., a single SOT-MRAM device) and applying a second write current 122 to the separate SOT-MRAM device while applying the first write current 120. The second write current is along an axis of the separate SOT-MRAM device (e.g., an axis perpendicular to the layers and along the same direction as the torque of the magnetic layer, e.g., the second write current is perpendicular to the first write current). For example, second transistor 118a activates SOT-MRAM device 104a (e.g., applies a vertical current to SOT-MRAM device 104a); second transistor 118b activates SOT-MRAM device 104b (e.g., applies a vertical current to SOT-MRAM device 104b); and second transistor 118c activates SOT-MRAM device 104c (e.g., applies a vertical current to SOT-MRAM device 104c). In some embodiments, second transistor 118 is fabricated below SOT-MRAM device 104 (e.g., fabricated closer to substrate 124 on which SOT-MRAM device 104 is fabricated and / or fabricated partially within substrate 124). In some embodiments, second transistor 118 is fabricated directly below SOT-MRAM device 104 (e.g., such that there is at least some overlap between SOT-MRAM device 104 and its corresponding second transistor 118).

[0060] In some embodiments, as described below with reference Figure 2 Described in more detail, the first write current 120 applied along the first conductive line 102 in the first direction provides a first magnetic torque to the individual SOT-MRAM devices 104. In some embodiments, the first write current 120 applies a magnetic torque to each of the plurality of SOT-MRAM devices 104 arranged along the first conductive line 102. In some embodiments, the first magnetic torque from the first write current 120 applied along the first conductive line 102 in the first direction is below a threshold for switching the magnetic orientation of the individual SOT-MRAM devices (e.g., insufficient to switch the relative magnetic orientation from parallel to antiparallel or from antiparallel to parallel). In some embodiments, the first torque is in the range of 70-90% of the threshold.

[0061] In some embodiments, the second write current 122 applied along the axis of the individual SOT-MRAM device 104 provides a second magnetic torque to the individual SOT-MRAM device 104. In some embodiments, the second magnetic torque from the second write current 122 is below a threshold for switching the magnetic orientation of the individual SOT-MRAM device (e.g., insufficient to switch the relative magnetic orientation from parallel to antiparallel or from antiparallel to parallel). However, the sum of the first magnetic torque and the second magnetic torque is above a threshold for switching the magnetic orientation of the individual SOT-MRAM device 104. For example, during a write operation for setting a data value of the SOT-MRAM device 104b, a first write current 120 is applied along the first conductive line 102 (e.g., which provides a magnetic torque to each of the SOT-MRAM devices 104), and a second write current 122 is applied along the SOT-MRAM device 104b alone (e.g., without applying a write current perpendicular to the other SOT-MRAM devices 104, e.g., by activating the transistor 118b). Since the net sum of the magnetic torques from the first write current 120 and the second write current 122 is above the threshold for switching the magnetic orientation of the SOT-MRAM device 104b, the magnetic orientation of the SOT-MRAM device 104b is switched under these two currents. However, since the remaining SOT-MRAM devices 104 are only subjected to the effects of the first write current 120 (which has a corresponding magnetic torque below the threshold), the remaining SOT-MRAM devices 104 are not switched. Therefore, Figure 1 A magnetic memory device is provided in which the SOT-MRAM devices 104 are individually addressable.

[0062] Thus, in some embodiments, during a write operation, the first write current 120 applies a SOT torque to the plurality of SOT-MRAM devices. The second write current 122 applies a magnetic torque to a subset of less than all of the plurality of SOT-MRAM devices. Less than all of the subset of SOT-MRAM devices are written in a write operation, and the remaining SOT-MRAM devices in the plurality of SOT-MRAM devices are not written in a write operation.

[0063] The device 100 includes a readout circuit for reading a data value stored by the individual SOT-MRAM devices 104. In some embodiments, the readout circuit is configured to read the data value without changing the torque of any layer. In some embodiments, the readout circuit also includes a second transistor 118. For example, during a read operation of the corresponding SOT-MRAM device 104, a small current (e.g., less than the second current 122 applied during a write operation) is applied perpendicular to the corresponding SOT-MRAM device 104. The small current is used to detect the resistance of the corresponding SOT-MRAM device 104, which is used to determine the data value stored by the corresponding SOT-MRAM device 104 (e.g., due to magnetoresistance, the parallel arrangement of the torque of the magnetic storage layer 108 and the magnetic reference layer 112 has a different resistance than its anti-parallel arrangement).

[0064] Note that the first write current 120 and the second write current 122 apply magnetic torques based on different physical phenomena. In some embodiments, the first write current 120 applies a spin-orbit torque and the second write current 122 applies a spin-transfer torque. Because the spin-orbit torque acts over a short distance relative to an appropriately selected wire, in some embodiments, the magnetic storage layer 108 is disposed closer to the first wire 102 than the magnetic reference layer 112 is to the first wire 102 (e.g., the magnetic storage layer 108 is adjacent to the first wire 102, perhaps with the exception of optional thin layers (layers less than 1 nanometer in thickness), such as adhesion layers and other layers included for manufacturing purposes).

[0065] In some embodiments, the second write current 122 is applied by applying a voltage between the top electrode 114 on the corresponding SOT-MRAM device 104 and the second transistor 118 corresponding to the corresponding SOT-MRAM device 104. In some cases, the effect of the voltage is multi-peaked. For example, in some embodiments, the corresponding SOT-MRAM device 104 exhibits a voltage-controlled magnetic anisotropy (e.g., the magnetic storage layer exhibits a voltage-controlled magnetic anisotropy). This has the effect of reducing the switching threshold of the corresponding SOT-MRAM device 104 without reducing the switching threshold of other SOT-MRAM devices 104, and the other SOT-MRAM devices 104 act in synergy with the spin transfer torque from the second write current 122. The spin-orbit torque from the first write current 120, the spin transfer torque from the second write current 122, and the effect of the reduced threshold are sufficient to switch the corresponding SOT-MRAM device 104 without switching the remaining SOT-MRAM devices 104.

[0066] It should also be noted that in some embodiments, rather than writing to a single SOT-MRAM device 104 in a corresponding write operation, multiple (less than all) SOT-MRAM devices 104 disposed on the first conductive line 102 are written in a write operation. To this end, a first write current 120 is applied along the first conductive line 102, and a second write current 122 is applied to each of the SOT-MRAM devices 104 being written (e.g., by activating the corresponding second transistor 118). No vertical current is applied to the SOT-MRAM devices 104 that are not being written.

[0067] Figure 2 FIG. 2 shows the relationship between different magnetic torques applied during a write operation according to some embodiments. Figure 1 The effect of the switching threshold of the device shown in .

[0068] As described above, the device 100 uses spin transfer torque and / or voltage controlled magnetic anisotropy (VCMA) to assist spin-orbit torque to write data values ​​to the individual SOT-MRAM devices 104, which in some embodiments constitutes the dominant effect (e.g., the majority of the torque on the free layer of the SOT-MRAM device 104). To this end, Figure 2 The SOT torque is shown to be less than the threshold for switching positions. In some embodiments, the SOT torque is between 70-90% of the threshold for switching positions. In addition, the VCMA effect (which can be viewed as reducing the threshold, or equivalently as reducing its own torque) is less than the threshold and less than the effect of the SOT torque (e.g., the VCMA is equivalent to providing a torque of 10-50% of the threshold). In some embodiments, the STT torque is less than the threshold and less than the SOT torque (e.g., the STT torque is between 10-50% of the threshold).

[0069] Furthermore, different effects (SOT, STT, and VCMA) result in different switching times. For example, a device based only on SOT torque has a switching time of about 0.7 nanoseconds (ns). A device based on VCMA has a switching time of about 2.1ns. A device based on STT has a switching time of about 7.8ns. However, by using primarily SOT with a small amount of STT and / or VCMA assistance, as shown in reference Figure 1 As described, the devices described herein can be made to switch at about 1.1 ns, which is very close to the switching time of a separate SOT. Thus, the described embodiments benefit from the fast switching of SOT devices, but allow such devices to be individually addressed using SOT / VCMA assistance, as described above with reference to Figure 1 described.

[0070] Figure 3A diagram of a magnetic memory device 300 according to some embodiments is shown. In some embodiments, the magnetic memory device 300 is an MRAM array (e.g., similar to Figure 5 ). Various aspects of the magnetic memory device 300 are similar to those of the MRAM array 502 shown in FIG. Figure 1 For the sake of brevity, these details are not repeated here. For example, features of the magnetic memory device 300 that are given the same reference numerals as similar features of the magnetic memory device 100 may share any characteristics of those features described above.

[0071] To this end, the magnetic memory device 300 includes a plurality of first wires 102. For example, the magnetic memory device 300 includes two first wires 102 (e.g., first wires 102a and 102b), but it should be understood that in some embodiments, the magnetic memory device 300 may include tens or hundreds of first wires 102. In some embodiments, the first wire 102 is a SOT wire that exhibits a strong spin Hall effect. The first wire 102 extends along a first direction (e.g., in the plane of the substrate 124 on which the magnetic memory device 300 is manufactured). For example, each corresponding first wire 102 in the plurality of first wires 102 has a first end and a second end, and the first direction is from the first end toward the second end.

[0072] The magnetic memory device 300 includes a plurality of second conductive lines 314 extending along a second direction different from the first direction. For example, the magnetic memory device 300 includes three second conductive lines 314 (e.g., second conductive lines 314a to 314c), but it should be understood that in some embodiments, the magnetic memory device 300 includes dozens or hundreds of second conductive lines 314 (e.g., in a single MRAM array 502, as described with respect to Figure 5 The plurality of second conductors 314 form a grid (e.g., a matrix) with the plurality of first conductors 102. For example, at corresponding positions on the grid, corresponding second conductors 314 overlap corresponding first conductors 102. In some embodiments, the first direction and the second direction differ by substantially 90 degrees (e.g., the first conductors 102 and the second conductors 314 form a rectangular "xy" matrix).

[0073] The magnetic memory device 300 includes a plurality of spin-orbit torque magnetic random access memory (SOT-MRAM) devices 104. For example, Figure 3As shown, the magnetic memory device 300 includes SOT-MRAM devices 104a to 104f. Each of the plurality of SOT-MRAM devices 104 is disposed at a corresponding position on the grid. In some embodiments, each SOT-MRAM device 104 is a column formed between the corresponding first wire 102 and the corresponding second wire 314 at a position where the corresponding first wire 102 and the second wire 314 overlap, so that the axis of the SOT-MRAM device 104 extends from the corresponding first wire 102 to the corresponding second wire 314. For example, the SOT-MRAM device 104b is a column formed between the first wire 102a and the second wire 102a at a position where the first wire 102a and the second wire 314b overlap, so that the axis of the SOT-MRAM device 104b extends from the first wire 102a to the corresponding second wire 314b (e.g., perpendicular to the substrate 124).

[0074] Note that as used herein, the term "column" does not mean a circular cross-section, an elliptical cross-section, or a cross-section of any other shape. Instead, a column only means a vertical structure (e.g., relative to a substrate). In some embodiments, a column is a tall vertical structure (e.g., taller than it is wide). In addition, in some embodiments, the column is formed by depositing layers on a substrate and patterning these layers. In some cases, patterning includes electrically isolating the column (e.g., by ion bombardment to destroy conductivity) without physically removing material. Therefore, in some embodiments, the column is a vertical conductive path.

[0075] The magnetic memory device 300 includes a write circuit. The write circuit includes a first transistor 116 coupled to each corresponding first wire 102 of the plurality of first wires 102. For example, the first transistor 116a is coupled to the first wire 102a, and the first transistor 116b is coupled to the first wire 102b. The first transistor 116 is configured to apply a first write current 120 along the corresponding first wire 102 in a first direction (e.g., from the first end of the corresponding first wire 102 toward the second end of the corresponding first wire 102). For example, in some embodiments, the corresponding first wire 102 is selected by activating the corresponding transistor 116, and the corresponding transistor 116 applies the first write current 110 to the first wire 102.

[0076] In some embodiments, the write circuit further includes a second transistor 118 for selecting a separate SOT-MRAM device 104 (eg, a single SOT-MRAM device) and transmitting the second write current 122 ( Figure 1) is applied to the individual SOT-MRAM device 104. As described above, the second write current 122 is along the axis of the individual SOT-MRAM device 104. In some embodiments, the write circuit includes a second transistor 118 for each individual SOT-MRAM device 104 (e.g., the write circuit includes a plurality of second transistors 118). In some embodiments, the second transistor is disposed below the SOT-MRAM device.

[0077] In some embodiments, each second transistor 118 is a field effect transistor (FET) having a gate, a source, and a drain. In some embodiments, the gate of each second transistor 118 along a corresponding row of second transistors 118 (e.g., a row of a grid) is connected to the same word line 304. The source (or drain) of each second transistor along a corresponding column of second transistors is connected to the same bit line (not shown). Thus, the individual SOT-MRAM device 104 can be selected by, for example, activating the gate (using the word line) and pulling the voltage on the source line to a suitable level to cause a voltage difference across the individual SOT-MRAM devices 104.

[0078] In some embodiments, the write circuit also includes a bit line 302. In some embodiments, the bit line 302 is activated (eg, a voltage is applied to the bit line 302) to activate the entire magnetic memory device 300. Transistors 116 / 118 are then used to address one or more individual SOT-MRAM devices 104.

[0079] The magnetic memory device 300 also includes a readout circuit for reading the data value stored by the corresponding SOT-MRAM device 104. The readout circuit is similar to the reference Figure 1 For example, in some embodiments, the readout circuit includes a second transistor 118. The data value is read out by activating the corresponding second transistor 118 to select the corresponding SOT-MRAM device 104 and measuring the resistance of the SOT-MRAM device 104 (e.g., between the bit line 302 and the corresponding second transistor 118).

[0080] As mentioned above Figure 1 As described, in some embodiments, a first write current 120 applied along a corresponding first conductive line 102 in a first direction provides a first magnetic torque to an individual SOT-MRAM device 104. In some embodiments, a write current applied along a corresponding first conductive line 102 in a first direction provides a magnetic torque to two or more SOT-MRAM devices 104 (e.g., all devices along the first conductive line 102). The first magnetic torque is below a threshold for switching the magnetic orientation of the individual SOT-MRAM device 104.

[0081] The second write current 122 applied along the axis of the individual SOT-MRAM device 104 provides a second magnetic torque to the individual SOT-MRAM device 104. The sum of the first magnetic torque and the second magnetic torque is above a threshold for switching the magnetic orientation of the individual SOT-MRAM device 104. In some embodiments, the individual SOT-MRAM device 104 exhibits a voltage-controlled magnetic anisotropy that lowers the threshold for switching the magnetic orientation of the individual SOT-MRAM device 104 when the second write current 122 (and thus the voltage) is applied along the axis of the individual SOT-MRAM device 104.

[0082] In some embodiments, each of the plurality of SOT-MRAM devices includes the Figure 1 Various examples of common set of layers 106 are depicted, including: a magnetic storage layer 108; a magnetic reference layer 112; and a spacer layer 110 separating the magnetic storage layer from the magnetic reference layer. Data values ​​are encoded in the relative magnetic orientations of the magnetic storage layer and the magnetic reference layer.

[0083] In some embodiments, each first conductive line 102 is a different instance of a first conductive material layer. In some embodiments, the first conductive material includes a reference Figure 1 Any conductive material described for the first conductive line 102 .

[0084] In some embodiments, each second conductive line is a different instance of the second conductive material layer.

[0085] In some embodiments, the second conductive material includes Cu, Au, Ag, or alloys thereof.

[0086] In some embodiments, the plurality of first conductive lines 102 include lines (e.g., straight lines). In some embodiments, the plurality of second conductive lines 314 include lines (e.g., straight lines). In some embodiments, as described below with reference to method 800, a SOT-MRAM device of the magnetic memory device 300 can be fabricated entirely or almost entirely in a grid (e.g., a matrix) using a lined photolithography mask (e.g., rather than a more complex shape). When combined with the etching techniques described herein, the structure can achieve a pitch of approximately 2-4F, with a 2-3F bit-to-bit spacing, and with a 4-12F 2 Very high bit density.

[0087] Figure 4 FIG. 4 is a diagram of a magnetic memory device 400 according to some embodiments. In particular, the magnetic memory device 400 is similar to the magnetic memory device 300 ( Figure 3), except that the first conductive line 102 (e.g., SOT conductive line) is disposed above the SOT-MRAM device 104 (e.g., relative to the substrate 124). Since the magnetic storage layer should generally be disposed closer to the first conductive line 102 (e.g., SOT conductive line) than the magnetic reference layer (e.g., the magnetic storage layer is adjacent to the SOT conductive line), the SOT-MRAM device 104 in the magnetic storage device 400 is substantially flipped compared to those of the magnetic storage device 300. That is, in the magnetic storage device 400, the magnetic reference layer is disposed closer to the substrate than the magnetic storage layer.

[0088] Another difference between the magnetic memory device 400 and the magnetic memory device 300 is that the bit line 302 of the magnetic memory device 400 is disposed at the side of the SOT-MRAM device 104 , rather than being disposed at the top of the SOT-MRAM device 104 as in the case of the magnetic memory device 300 .

[0089] For visual clarity, Figure 4 The word lines and source lines are not shown.

[0090] Figure 5 A block diagram of a magnetic memory device 500 according to some embodiments is shown. In some embodiments, the magnetic memory device 500 is formed on a single die.

[0091] In some embodiments, the magnetic memory device 500 includes a plurality of MRAM arrays 502 (eg, MRAM arrays 502a-502d). In some embodiments, each MRAM array 502 is Figure 3 The magnetic storage device 300 or Figure 4 4. In some embodiments, the MRAM array 502 is formed into rows and columns.

[0092] In some embodiments, the magnetic memory device 500 includes a word line (WL) decoder 504. For example, the magnetic memory device 500 includes a word line decoder 504 for each row of the MRAM array 502. In some embodiments, the word line decoder 504 is part of a read circuit of the magnetic memory device 500.

[0093] In some embodiments, the magnetic memory device 500 includes a SOT amplifier 508 for each column of the MRAM array 502. The SOT amplifier 508 provides an amplified current (eg, Figure 1 The first current 120), such as Figure 3 In some embodiments, the SOT amplifier 508 is a part of the write circuit of the magnetic memory device 500 .

[0094] In some embodiments, the magnetic memory device 500 includes a sense amplifier 506 for each column of the MRAM array 502. The sense amplifier 506 amplifies a read signal (eg, based on magnetoresistance) of the SOT-MRAM device 104 being read.

[0095] In some embodiments, the magnetic memory device 500 is coupled to one or more peripheral devices 510 , such as a memory controller or a processor.

[0096] Figure 6 Schematic diagram of a magnetic memory device 600 according to some embodiments is shown. The magnetic memory device 600 includes an MRAM array 502 (eg, as shown in FIG. Figure 5 ). The magnetic memory device 600 also includes a plurality of bit lines 302. Each bit line is used to activate (e.g., select) a separate MRAM array 502 (e.g., for a read or write operation). The magnetic memory device 600 includes word lines 304 and source lines 604, which are used to activate (e.g., select) a separate SOT-MRAM device in a corresponding MRAM array 502, as described elsewhere in this document.

[0097] 7A to 7F A process 700 for manufacturing a magnetic memory device (eg, a SOT-MRAM device array) according to some embodiments is illustrated. In some embodiments, the process 700 is used to manufacture any device described herein (eg, Figure 1 A magnetic storage device 100, Figure 3 The magnetic memory device 300 and / or Figure 4 In some embodiments, 7A to 7F The steps shown in FIG. 8 are used to illustrate process 800 ( FIG. 8A to FIG. 8B ). In some embodiments, the following operations are shown in order 7A to 7F The operations shown in Fig. 7A The operations shown in Figure 7B Before the operations shown in Figure 7B The operations shown in Figure 7C In some cases, the order of the operations is not important, and those skilled in the art will recognize how to reorder certain operations.

[0098] In some cases, process 700 produces an array of SOT-MRAM devices having a pitch of about 2-4F, a bit-to-bit spacing of 2-3F, and a 4-12F 2 Very high bit density.

[0099] In operation 702 ( Fig. 7A), a word line 304 is formed. In some embodiments, by Figure 3 Word lines 304 (only some of the word lines, such as word lines 304a-304c, are labeled) are formed by depositing a conductive material on a substrate 124 (e.g., a substrate 124) and patterning the conductive material (e.g., so that each word line 304 is a different instance of the conductive material). In some embodiments, multiple word lines 304 are formed in this manner. In some embodiments, word lines 304 are lines (e.g., straight lines). In some embodiments, word lines 304 extend in a first direction (e.g., along the surface of the substrate).

[0100] It should be noted that the various operations in process 700 include depositing and patterning conductive materials. For any of these operations, in some embodiments, patterning the conductive material includes etching multiple portions of the conductive material to remove the multiple portions of the conductive material. In some embodiments, patterning the conductive material includes destroying (e.g., by ion bombardment) the conductivity of multiple portions of the conductive material to form different instances of the conductive material. In some embodiments, the conductive material is a metal. In some embodiments, the conductive material is deposited by sputtering, chemical deposition techniques, physical deposition techniques, evaporation and / or epitaxial growth techniques. In some embodiments, photolithography can be used to perform any patterning operation described herein.

[0101] It should also be noted that 7A to 7F Any physical gaps shown in (e.g., between different instances of a layer) are typically filled with an inert material (e.g., a non-magnetic, insulating material). In some embodiments, after a layer is patterned and the gaps are filled, the layer is planarized, thereby providing a flat surface for the next layer to be deposited thereon.

[0102] In operation 704, source lines 604 are formed. In some embodiments, source lines 604 are formed by depositing a conductive material on top of word lines 304 (only some of the source lines are labeled, e.g., source lines 604a-604c) and patterning the conductive material (e.g., such that each source line 604 is a different instance of the conductive material). In some embodiments, multiple source lines 604 are formed in this manner. In some embodiments, source lines 604 are lines (e.g., straight lines). In some embodiments, source lines 604 extend in a second direction (e.g., perpendicular to the first direction and along the surface of the substrate).

[0103] In some embodiments, source line 604 is electrically isolated from word line 304. In some embodiments, a thin layer of insulating material is deposited between the layer forming word line 304 and the layer forming source line 604. In some embodiments (not shown), the transistor grid is fabricated so that each transistor has a terminal connected to a source line and a terminal connected to a word line. For example, in some embodiments, the transistor is a field effect transistor (FET) having a gate, a source, and a drain. The gate of each transistor is electrically coupled to a corresponding word line, and the source (or drain) of each transistor is electrically coupled to a corresponding source line. In some embodiments, each transistor on the grid is coupled to a different combination of source lines and word lines.

[0104] For visual clarity, FIG. 7B to FIG. 7F The word lines 304 and source lines 604 are not shown in the rest of the process 700. However, it should be understood that the word lines 304 and source lines 604 and the transistors described above are formed below the rest of the structures fabricated in the process 700 (eg, close to the substrate).

[0105] In operation 706 ( Figure 7B ), forming a plurality of first conductive lines 102 (e.g., SOT conductive lines) (only some of which are shown, such as first conductive lines 102a-102c). In some embodiments, the plurality of first conductive lines 102 are formed by electrically isolating a plurality of different instances of a first conductive material layer to form a plurality of first conductive lines 102 extending along a first direction (e.g., such that the first conductive lines 102 are parallel to the word lines, as described above). In some embodiments, electrically isolating the first conductive lines 102 includes forming a non-magnetic material 707 between the first conductive lines 102. In some embodiments, the first conductive lines 102 include a first conductive material. In some embodiments, the first conductive line 102 includes a material exhibiting a strong spin Hall effect (SHE). In some embodiments, the first conductive line 102 includes a heavy metal. In some embodiments, the first conductive line 102 includes Pt, Ta, W, or alloys thereof. In some embodiments, the first conductive line 102 has a thickness 709 in the range of 2 to 100 nm, preferably 5 to 80 nm, and more preferably 8 to 50 nm (this value may depend on the target resistance).

[0106] In operation 708 ( Figure 7C ), depositing a common set of device layers. In some embodiments, the common set of device layers includes a magnetic storage layer 108, a spacer layer 110, and a magnetic reference layer 112. In some embodiments, the magnetic storage layer 108 is deposited first (e.g., adjacent to the SOT wire). In some embodiments, the common set of device layers is applied on (e.g., on top of) the SOT wire (e.g., applied on a layer forming the first wire 102).

[0107] In some embodiments, the spacer layer 110 is a tunnel barrier. In some embodiments, the spacer layer 110 includes an insulating material. In some embodiments, the spacer layer 110 includes a material selected from the group consisting of MgO, SiOx, AlOx, or alloys thereof. In some embodiments, the spacer layer 110 has a thickness of 0.2 to 2 nanometers (nm), which may depend on the target resistance. In some embodiments, the spacer layer 110 is deposited using a sputtering method (e.g., from a MgO sintered target or by depositing Mg metal to oxidize it).

[0108] In some embodiments, the magnetic storage layer 108 (sometimes also referred to as a "free layer") includes a plurality of sublayers (e.g., separately deposited sublayers). In some embodiments, the sublayers include a metal buffer layer used as a perpendicular magnetic anisotropy (PMA) enhancement portion. In some embodiments, the sublayers include one or more sublayers, the one or more sublayers including a material selected from the group consisting of Ta, Cr, W, V, Mo, Pt, Ru, Pd, Cu, Ag, Rh, or alloys thereof. In some embodiments, the thickness of the magnetic reference layer 108 is 1 to 10 nm, preferably 1 to 5 nm.

[0109] In some embodiments, the magnetic reference layer 112 (sometimes also referred to as a "fixed layer") includes multiple sublayers (e.g., separately deposited sublayers). In some embodiments, the sublayers include one or more sublayers that include a material in the group consisting of CoFeB, CoFe, CoFeNi, FeNi, FeB, or alloys thereof. In some embodiments, the sublayers include multiple Co / (Pt, Pd) multilayers. In some embodiments, the sublayers include one or more sublayers that include a Heusler alloy (e.g., a material selected from the group consisting of CoMnSi, CoMnGe, CoMnAl, CoMnFeSi, CoFeSi, CoFeAl, CoCrFeAl, CoFeAlSi). In some embodiments, the sublayers include a capping layer that is a PMA enhancement. In some embodiments, the sublayers include a synthetic ferrimagnet that includes at least two magnetic sublayers separated by a non-magnetic sublayer. In some embodiments, the non-magnetic layer includes a material selected from the group consisting of Ru, Cr, Ir, V, Au, Ag, or alloys thereof. In some embodiments, the capping layer comprises a material selected from the group consisting of Ta, Cr, W, V, Pt, Ru, Pd, Cu, Ag, Rh, or alloys thereof. In some embodiments, the capping layer comprises MgO. In some embodiments, the capping layer has a thickness in the range of 1 to 10 nm. In some embodiments, the magnetic reference layer 112 has a thickness (e.g., total thickness) in the range of 1 to 20 nm, preferably 1 to 10 nm, and more preferably 1 to 5 nm.

[0110] Note that the thickness mentioned above refers to the same dimension as thickness 709, but for visual clarity, the thickness of the device layer is not marked in the figure.

[0111] Operations 710-716 ( FIG. 7D to FIG. 7E ) illustrates different instances of electrically isolating a common group of device layers to form a plurality of spin-orbit torque magnetic random access memory (SOT-MRAM) devices. Each of the plurality of SOT-MRAM devices is located on a different instance of a first conductive material layer. In some embodiments, each SOT-MRAM device stores one or more bits. Therefore, in some embodiments, operations 710-716 are used to isolate bits of a magnetic memory device.

[0112] To this end, in operation 710, trenches 711 are formed to form lines of a common set of device layers.

[0113] In some embodiments, the lines of the common set of device layers are perpendicular to the SOT conductive line 102. In some embodiments, the lines of the common set of device layers are parallel to the SOT conductive line 102.

[0114] In some embodiments, forming groove 711 includes etching a common group device layer. In some embodiments, etching of the common group device layer is performed using ion beam milling, reactive ion etching, oxidation, nitridation, ion implementation or any combination of these techniques. In some embodiments, etching of the common group device layer is performed using reactive ion etching utilizing carbonyl chemistry. In some embodiments, reactive ion etching is performed using a reactive ion beam incident on the surface at an angle. In some embodiments, the angle is between 45-80 degrees, and preferably between 60-80 degrees. Below 45 degrees, the device size becomes too large and the density / capacity is low. Using an angle greater than 80 degrees will result in a lower tunnel resistance change, which will reduce the read / write performance of the device. The angle is measured from the normal axis of the planar magnetic layer to the horizontal direction.

[0115] These etching processes allow SOT-MRAM devices to be fabricated at a very small scale (eg, high density) while avoiding shunting of the spacer layer 110, which is a problem with conventional methods of fabricating MRAM devices.

[0116] In some embodiments, the trenches formed by the process have a trench wall angle between 10-45 degrees (e.g., relative to the normal of the substrate) and more preferably between 10-30 degrees. It is worth noting that a trench wall angle greater than 45 degrees results in a larger device size, which results in a lower storage density / capacity. Conversely, a trench wall angle less than 10 degrees results in an increased risk of shunting (e.g., shorting) of the spacer layer 110, which results in a reduced yield.

[0117] In operation 712, a protective layer is deposited on the common group device layer and patterned. In some embodiments, the protective layer includes a photoresist and / or a metal layer. The photoresist and / or metal layer 715 are patterned to form a line in a direction perpendicular to the groove 711. In some embodiments, the line of the photoresist and / or metal layer 715 is parallel to and aligned with (e.g., overlapped with) the first wire 102 (e.g., SOT wire). In some embodiments, when the patterned photoresist or metal layer is in place, the conductivity of the exposed portion 713 of each line of the common group layer is destroyed. The photoresist and / or metal layer are subsequently removed.

[0118] In operation 714, multiple different instances of a second conductive material layer are deposited and patterned to form a plurality of second conductive lines 314 (eg, top electrodes) extending along a second direction that is different from the first direction of the first conductive lines 102 (eg, perpendicular to the first conductive lines 102).

[0119] In operation 716 , trench 711 is filled with a non-magnetic insulator.

[0120] In operation 718 ( Figure 7F ), the bit lines (e.g., Figure 3 The bit line 302 of the first conductive line 102 is formed on top of the second conductive line. The bit line is a conductive material electrically coupled to the second conductive line. In addition, the first transistor 116 (previously described) is formed. In some embodiments, each first transistor 116 is formed adjacent to a corresponding first conductive line 102, and a terminal (e.g., source or drain) of the first transistor 116 is electrically coupled to the corresponding first conductive line 102.

[0121] FIG. 8A to FIG. 8B A process (eg, method) 800 for fabricating an array of SOT-MRAM devices according to some embodiments is shown. In some embodiments, process 800 is used to fabricate any of the devices described herein (eg, Figure 1 A magnetic storage device 100, Figure 3 The magnetic memory device 300 and / or Figure 4 In some embodiments, the magnetic storage device 400 7A to 7F The diagram shows the FIG. 8A to FIG. 8B For the sake of brevity, the steps shown in 7A to 7F The operation described.

[0122] In some cases, process 800 generates an array of SOT-MRAM devices with a pitch of about 2-4F, a bit-to-bit spacing of 2-3F, and a bit-to-bit spacing of 4-12F. 2 Very high bit density.

[0123] The method includes depositing (802) a layer of a first conductive material. In some embodiments, the first conductive material exhibits a high spin Hall effect.

[0124] The method includes electrically isolating (803) a plurality of different instances of a first conductive material layer to form a plurality of first conductive lines (eg, SOT conductive lines) extending along a first direction. Figure 7B Operations 802 - 803 are graphically depicted in and described with reference to the same.

[0125] In some embodiments, each different instance of the first conductive material layer coincides with a corresponding line (eg, a word line) extending along the first direction (804) (eg, as shown in reference Fig. 7A described).

[0126] In some implementations, electrically isolating the plurality of different instances of the first conductive material layer includes (806) removing portions of the first conductive material layer (eg, etching the first conductive material).

[0127] In some embodiments, electrically isolating the different instances of the first conductive material layer includes (808) destroying conductivity of portions of the first conductive material layer without removing the portions of the first conductive material layer (eg, by oxidation or nitration).

[0128] The method includes depositing (810) a common set of device layers (e.g., as described in reference to Figure 7C In some embodiments, the common set of device layers includes a magnetic storage layer, a magnetic reference layer, and a spacer layer (eg, an insulating layer). In some embodiments, the magnetic storage layer is proximate to (eg, adjacent to) the first conductive material.

[0129] In some implementations, a common set of device layers is deposited (812) after electrically isolating the multiple different instances of the first conductive material layer (eg, such that SOT conductive lines are formed below the common set of device layers).

[0130] The method includes electrically isolating (814) different instances of a common set of device layers to form a plurality of spin-orbit torque magnetic random access memory (SOT-MRAM) devices. Each of the plurality of SOT-MRAM devices is located on a different instance of a first conductive material layer (e.g., as described in reference FIG. 7D to FIG. 7E described).

[0131] In some embodiments, electrically isolating different instances of the common set of device layers includes etching (816) the common set of device layers into lines extending in the second direction. For example, in some embodiments, the trenches (e.g., Fig.7DThe trench 711 is etched into the common group device layer. Various techniques and chemicals for etching the trench 711 are described above.

[0132] In some embodiments, the method further includes, before destroying the conductivity of the plurality of portions of each line without etching the plurality of portions of each line (e.g., operations 820, 826 below), depositing (818) a protective layer on the line and patterning the protective layer to expose the plurality of portions of the line (e.g., as described in reference to Fig. 7E 712 as described above).

[0133] In some embodiments, electrically isolating different instances of the common set of device layers further comprises destroying (820) conductivity of portions of each line without etching the portions of each line to form a conductive pillar from each line, wherein each SOT-MRAM device comprises a conductive pillar. For example, the pillar is made of a conductive material except for a thin insulating layer that forms a tunnel barrier.

[0134] In some embodiments, wherein etching comprises (822) reactive ion etching. In some embodiments, the reactive ion etching is based on carbonyl chemistry (824).

[0135] In some embodiments, electrically isolating different instances of the common set of device layers includes etching (826) the common set of device layers into lines extending in a first direction.

[0136] The method includes depositing (828) a second conductive material layer (eg, formed from a plurality of conductive layers) on different instances of the common set of device layers. Figure 3 The second conductor 314 layer, as referenced Fig. 7E 714 as described above).

[0137] In some embodiments, after electrically isolating the plurality of different instances of the first conductive material layer, a second conductive material layer (eg, as described in reference Fig. 7E 714 as described above).

[0138] The method includes electrically isolating (832) a plurality of different instances of the second conductive material layer to form a plurality of second conductive lines extending along a second direction. The second direction is different from the first direction (e.g., Figure 3 As shown, the first conductive line 102 and the second conductive line 314 are perpendicular).

[0139] In some embodiments, each distinct instance (834) of the second conductive material layer coincides with a corresponding line (eg, a source line) extending in the second direction.

[0140] Although some of the various figures illustrate multiple logical stages in a particular order, stages that are not dependent on order may be reordered and other stages may be combined or decomposed. Although some reordering or other groupings are specifically mentioned, others will be apparent to one of ordinary skill in the art, and thus the ordering and groupings presented here are not an exhaustive list of alternatives. Furthermore, it should be appreciated that the stages may be implemented in hardware, firmware, software, or any combination thereof.

[0141] It will also be understood that, although the terms first, second, etc. are used in some cases herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the various described implementations, a first device may be referred to as a second device, and similarly, a second device may be referred to as a first device. Both the first device and the second device are devices, but they are not the same device.

[0142] The terms used in the description of the various described embodiments in this article are only used for the purpose of describing specific embodiments and are not intended to be limited. As used in the description of the various described embodiments and the appended claims, the singular forms "one", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "and / or" used herein refer to and encompass any and all possible combinations of one or more associated listed items. It will be further understood that when used in this specification, the terms "include" and / or "comprising" specify the existence of stated features, integers, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0143] As used herein, the term "if" is optionally interpreted to mean "when" or "at" or "in response to determining" or "in response to detecting" or "according to a determination," depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected" is optionally interpreted to mean "upon the determination" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]" or "according to a determination that [stated condition or event] is detected," depending on the context.

[0144] For purposes of explanation, the foregoing description has been described with reference to specific embodiments. However, the above illustrative discussions are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen in order to best explain the principles behind the claims and their practical application, thereby enabling others skilled in the art to best use the embodiments with various modifications suitable for the particular use contemplated.

Claims

1. A method for manufacturing a magnetic storage device, comprising: Depositing a first conductive material layer, wherein the first conductive material layer is used to form a spin-orbit torque (SOT) line; electrically isolating the first conductive material layer to form a plurality of first conductive lines extending along a first direction; depositing a common group device layer on the first conductive material layer; Electrically isolating the common group device layer to form a plurality of spin-orbit torque magnetic random access memory (SOT-MRAM) devices, wherein each of the plurality of SOT-MRAM devices is located on the first conductive material layer; depositing a second conductive material layer on the common set of device layers; and electrically isolating the second conductive material layer to form a plurality of second conductive lines extending along a second direction, wherein the second direction is different from the first direction, Wherein, electrically isolating the common group device layer comprises etching the common group device layer into lines extending in the second direction.

2. The method according to claim 1, wherein: Electrically isolating the common set of device layers further includes destroying conductivity of portions of each line without etching the portions of each line to form a conductive pillar from each line, wherein each SOT-MRAM device includes a conductive pillar.

3. The method of claim 2, further comprising, before destroying the conductivity of the plurality of portions of each line without etching the plurality of portions of each line: depositing a protective layer over the wire; and The protective layer is patterned to expose the portions of the lines.

4. The method according to claim 1, wherein: The second conductive material layers coincide with corresponding lines extending in the second direction.

5. The method according to claim 1, wherein: The etching includes reactive ion etching.

6. The method according to claim 5, wherein: The reactive ion etching is based on carbonyl chemistry.

7. The method according to claim 1, wherein: The common set of device layers is deposited after electrically isolating the first conductive material layer.

8. The method according to claim 1, wherein: The second layer of conductive material is deposited after electrically isolating the first layer of conductive material.

9. The method according to claim 1, wherein: Electrically isolating the first layer of conductive material includes removing portions of the first layer of conductive material.

10. The method according to claim 1, wherein: Electrically isolating the first layer of conductive material includes disrupting conductivity of portions of the first layer of conductive material without removing the portions of the first layer of conductive material.

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