Soft-error-resistant SRAM

Abstract

The present invention discloses an SRAM storage unit of an SRAM with a soft error resistance having a double interlocking structure, including: first and second NMOS tubes connected with a common source and providing interlocking first and second storage nodes by the first and second NMOS tubes, first and second PMOS tubes connected with a common source and providing interlocking third and fourth storage nodes by the first and second PMOS tubes, the gate and source of the fifth MOS transistor connected with a common drain are connected between the first and third storage nodes of the same phase, the gate and source of the sixth MOS transistor connected with a common drain are connected between the second and fourth storage nodes of the same phase; the gate and drain of the seventh MOS transistor connected with a common source are connected between the first and fourth storage nodes of the opposite phase; the gate and drain of the eighth MOS transistor connected with a common source are connected between the second and third storage nodes of the opposite phase, and the fifth to eighth MOS transistors are all NMOS tubes. The present invention can tolerate the flipping of a node potential and can reduce the operating voltage.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, in particular to a soft error resistant SRAM. Background Art

[0002] The gradual reduction of integrated circuit technology nodes has brought many challenges to chip reliability, one of which is the soft error caused by single-particle effects.

[0003] Soft errors may occur in different electronic devices such as automotive electronics, medical devices, etc.

[0004] In recent years, as process nodes continue to advance, devices are getting closer and closer, and device sizes are getting smaller and smaller, which makes single-particle upsets caused by charge collection and charge sharing an important source of soft errors.

[0005] Traditional SRAM storage cells are usually composed of two CMOS with interconnected input and output, and do not have the function of tolerant to soft errors when node flip occurs.

[0006] like Figure 1 As shown, it is a circuit diagram of an SRAM storage unit of an existing soft error resistant SRAM, which is a quatro circuit, and the interlocking unit structure includes four PMOS tubes and four NMOS tubes; the PMOS tube P1 and the NMOS tube N1 are not directly connected to form a CMOS; similarly, the PMOS tube P2 and the NMOS tube N2 are not directly connected to form a CMOS. The gate of the PMOS tube P1 is connected to the node QN, and the gate of the NMOS tube N1 is connected to the node A; wherein the node QN is inverted with the node Q through the PMOS tube P2, and the node A is inverted with the node Q through the PMOS tube P3, so that the signals of the node A and the node QN are in-phase signals at last, so the connection structure of the PMOS tube P1 and the NMOS tube N1 is still similar to the CMOS at last. Similarly, the connection structure of the PMOS tube P2 and the NMOS tube N2 is also similar to the CMOS at last, so that the connection structure of the PMOS tube P1 and the NMOS tube N1 and the connection structure of the PMOS tube P2 and the NMOS tube N2 constitute a layer of interlocking structure with the node Q and the node QN as storage nodes.

[0007] Similarly, the connection structure of the PMOS tube P3 and the NMOS tube N3 is still similar to CMOS, and the connection structure of the PMOS tube P4 and the NMOS tube N4 is still similar to CMOS, so that the connection structure of the PMOS tube P3 and the NMOS tube N3 and the connection structure of the PMOS tube P4 and the NMOS tube N4 constitute another interlocking structure with the node A and the node B as the storage nodes, and finally realize a double interlocking unit structure, thereby realizing resistance to soft errors.

[0008] Figure 1 Two transmission transistors are used, namely NMOS transistor N5 and NMOS transistor N6. The gates of NMOS transistors N5 and N6 are connected to word line WL, the sources are connected to bit lines BL and BLB respectively, and the drains are connected to nodes Q and QN respectively. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a soft error resistant SRAM which can tolerate the flipping of a node potential, reduce the operating voltage and increase the reading and writing speed.

[0010] In order to solve the above technical problems, the SRAM storage unit of the soft error resistant SRAM provided by the present invention has a double interlocking structure, including:

[0011] A first NMOS tube and a second NMOS tube are connected with a common source, the drain of the first NMOS tube is a first storage node, the drain of the second NMOS tube is a second storage node, the source of the first NMOS tube and the source of the second NMOS tube are both grounded, the gate of the first NMOS tube is connected to the second storage node, the gate of the second NMOS tube is connected to the first storage node, and the first storage node and the second storage node are inverted to each other.

[0012] A first PMOS tube and a second PMOS tube are connected with a common source, the drain of the first PMOS tube is a third storage node, the drain of the second PMOS tube is a fourth storage node, the source of the first PMOS tube and the source of the second PMOS tube are both grounded, the gate of the first PMOS tube is connected to the fourth storage node, the gate of the second PMOS tube is connected to the third storage node, and the third storage node and the fourth storage node are inverted to each other.

[0013] The gate and source of the fifth MOS transistor connected with a common drain are connected between the first storage node and the third storage node of the same phase, so that the first storage node and the third storage node form a source follower relationship.

[0014] The gate and source of the sixth MOS transistor connected with a common drain are connected between the second storage node and the fourth storage node which are in phase, so that the second storage node and the fourth storage node form a source follower relationship.

[0015] The gate and drain of the common-source connected seventh MOS transistor are connected between the first storage node and the fourth storage node of the inverted phase.

[0016] The gate and drain of the common-source connected eighth MOS transistor are connected between the second storage node and the third storage node of inversion.

[0017] The fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are all NMOS transistors.

[0018] A further improvement is that the SRAM storage unit further includes a first transmission tube, a second transmission tube, a third transmission tube and a fourth transmission tube.

[0019] The first storage node is connected to an input end of the first transmission tube.

[0020] The second storage node is connected to an input end of the second transmission tube.

[0021] The third storage node is connected to an input end of the third transmission tube.

[0022] The fourth storage node is connected to the input end of the fourth transmission tube.

[0023] A further improvement is that the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube are of the same conductivity type.

[0024] A further improvement is that the gates of the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube are all connected to the word line.

[0025] A further improvement is that the output ends of the first transmission tube and the third transmission tube are both connected to the first bit line;

[0026] The output ends of the second transmission tube and the fourth transmission tube are both connected to a second bit line, and the first bit line and the second bit line are in opposite directions;

[0027] The drains of the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube serve as input ends and the sources serve as output ends.

[0028] A further improvement is that the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube are all PMOS tubes.

[0029] A further improvement is that the SRAM storage unit includes a write state, a hold state and a read state;

[0030] In the write state, a pair of mutually inverted write signals are pre-applied to the first bit line and the second bit line, and the word line is low-leveled to turn on the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube.

[0031] A further improvement is that when the SRAM storage unit is in a hold state, the word line increases the level to turn off the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube.

[0032] A further improvement is that when the SRAM storage unit is in a read state, the first bit line and the second bit line are pre-high potential, and the word line is high level to turn on the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube.

[0033] The present invention adds fifth and sixth MOS transistors connected with a common drain as source followers and seventh and eighth MOS transistors connected with a common source on the basis of first NMOS tubes and second NMOS tubes connected with a common source and first PMOS tubes and second PMOS tubes connected with a common source. The seventh and eighth MOS transistors can form an interlocking structure with the combination of the first PMOS tube and the second PMOS tube, and the fifth and sixth MOS transistors can form an interlocking structure between the combination of the first NMOS tube and the second NMOS tube and the combination of the first PMOS tube and the second PMOS tube. In this way, double interlocking can be achieved, so that the SRAM can tolerate the flipping of a node potential and resist soft errors.

[0034] The present invention can use four transmission tubes to connect four storage nodes. Compared with the circuit structure of two transmission tubes in the prior art, the number of transmission tubes in the present invention is increased, and the reading and writing speed is also increased.

[0035] Since the fifth to eighth MOS transistors are all NMOS transistors, the fifth MOS transistor forms a series structure with the first NMOS transistor and the sixth MOS transistor forms a series structure with the second NMOS transistor. This N-tube series structure can make the minimum operating voltage of the SRAM storage unit reach 0.68V, so the operating voltage can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0037] Figure 1 The invention is a circuit diagram of an SRAM storage unit of an existing soft error resistant SRAM;

[0038] Figure 2 1 is a circuit diagram of an SRAM storage unit of a soft error resistant SRAM according to a first embodiment of the present invention;

[0039] Figure 3A is a simulation waveform of an SRAM storage unit of the soft error-resistant SRAM of the first embodiment of the present invention at a normal working voltage;

[0040] Figure 3B1 is a simulation waveform of an SRAM storage unit of the soft error-resistant SRAM of the first embodiment of the present invention at a low operating voltage;

[0041] Figure 4 1 is a soft error simulation waveform of an SRAM memory cell of the soft error resistant SRAM according to the first embodiment of the present invention. DETAILED DESCRIPTION

[0042] like Figure 2 , which is a circuit diagram of an SRAM storage unit of an SRAM resistant to soft errors according to a first embodiment of the present invention; the SRAM storage unit of the SRAM resistant to soft errors according to the first embodiment of the present invention has a double interlocking structure, including:

[0043] A first NMOS tube N101 and a second NMOS tube N102 are connected with a common source, the drain of the first NMOS tube N101 is a first storage node Q101, the drain of the second NMOS tube N102 is a second storage node Q102, the source of the first NMOS tube N101 and the source of the second NMOS tube N102 are both grounded, the gate of the first NMOS tube N101 is connected to the second storage node Q102, the gate of the second NMOS tube N102 is connected to the first storage node Q101, and the first storage node Q101 and the second storage node Q102 are in anti-phase with each other.

[0044] A first PMOS tube P101 and a second PMOS tube P102 are connected with a common source, the drain of the first PMOS tube P101 is a third storage node Q103, the drain of the second PMOS tube P102 is a fourth storage node Q104, the source of the first PMOS tube P101 and the source of the second PMOS tube P102 are both grounded, the gate of the first PMOS tube P101 is connected to the fourth storage node Q104, the gate of the second PMOS tube P102 is connected to the third storage node Q103, and the third storage node Q103 and the fourth storage node Q104 are in antiphase with each other.

[0045] The gate and source of the fifth MOS transistor M101 connected in common drain are connected between the first storage node Q101 and the third storage node Q103 of the same phase, so that the first storage node Q101 and the third storage node Q103 form a source follower relationship.

[0046] The gate and source of the sixth MOS transistor M102 connected in common drain are connected between the second storage node Q102 and the fourth storage node Q104 which are in phase, so that the second storage node Q102 and the fourth storage node Q104 form a source follower relationship.

[0047] The gate and drain of the seventh MOS transistor M103 connected in common source connection are connected between the first storage node Q101 and the fourth storage node Q104 of the inverted phase.

[0048] The gate and drain of the common-source connected eighth MOS transistor M104 are connected between the second storage node Q102 and the third storage node Q103 of the inverted phase.

[0049] In the first embodiment of the present invention, the fifth MOS transistor M101, the sixth MOS transistor M102, the seventh MOS transistor M103 and the eighth MOS transistor M104 have the same conductivity type and are all NMOS transistors.

[0050] The SRAM storage unit further includes a first transmission transistor T101, a second transmission transistor T102, a third transmission transistor T103 and a fourth transmission transistor T104.

[0051] The first storage node Q101 is connected to the input end of the first transmission transistor T101.

[0052] The second storage node Q102 is connected to the input end of the second transmission transistor T102.

[0053] The third storage node Q103 is connected to the input end of the third transmission transistor T103.

[0054] The fourth storage node Q104 is connected to the input end of the fourth transmission transistor T104.

[0055] The conductivity types of the first transmission tube T101, the second transmission tube T102, the third transmission tube T103 and the fourth transmission tube T104 are the same and opposite to the conductivity type of the fifth MOS transistor M101, that is, the first transmission tube T101, the second transmission tube T102, the third transmission tube T103 and the fourth transmission tube T104 are all PMOS tubes.

[0056] The gates of the first transmission transistor T101 , the second transmission transistor T102 , the third transmission transistor T103 , and the fourth transmission transistor T104 are all connected to a word line WL.

[0057] The output ends of the first transmission tube T101 and the third transmission tube T103 are both connected to the first bit line BL.

[0058] The output ends of the second transmission tube T102 and the fourth transmission tube T104 are both connected to the second bit line BLB, and the first bit line BL and the second bit line BLB are in opposite directions;

[0059] The drains of the first transmission tube T101 , the second transmission tube T102 , the third transmission tube T103 and the fourth transmission tube T104 serve as input terminals and the sources serve as output terminals.

[0060] The SRAM storage unit includes a write state, a hold state and a read state.

[0061] In the write state, a pair of mutually inverted write signals are pre-applied to the first bit line BL and the second bit line BLB, and the word line WL is low-leveled to turn on the first transmission tube T101, the second transmission tube T102, the third transmission tube T103 and the fourth transmission tube T104.

[0062] When the SRAM storage unit is in the hold state, the word line WL increases the level to turn off the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103 and the fourth transmission transistor T104.

[0063] When the SRAM storage unit is in a read state, the first bit line BL and the second bit line BLB are pre-set to a high potential, and the word line WL is set to a low level to turn on the first transmission transistor T101, the second transmission transistor T102, the third transmission transistor T103 and the fourth transmission transistor T104.

[0064] The storage state of the SRAM storage unit of the first embodiment of the present invention is described as follows:

[0065] The storage state of the SRAM memory cell includes two, corresponding to the storage data "0" and the storage data "1" respectively.

[0066] When the cell storage data is "1", WL is "1", and the four PMOS transistors serving as transmission tubes are turned off. At this time, the potentials of the internal nodes are Q101=1, Q103=1, Q104=0, and Q102=0 respectively.

[0067] When the cell stores data "0", WL is "1", and the four PMOS transistors serving as transmission tubes are turned off. At this time, the potentials of the internal nodes are Q101=0, Q103=0, Q104=1, and Q102=1 respectively.

[0068] Flip description of the first embodiment of the present invention:

[0069] Nodes Q101, Q102, Q103, and Q104 form a double interlocking structure, thereby improving the soft error resistance of the SRAM storage unit. When any storage node is disturbed, the latch structure corresponding to the other pair of storage nodes can eliminate the interference of the disturbed storage node, such as node Q103 and node Q104 form a pair of interlocking storage nodes, and node Q101 and node Q102 form a pair of interlocking storage nodes;

[0070] If one of the nodes Q103 and Q104 is interfered with, the nodes Q101 and Q102 remain stable and the interference can be eliminated; if one of the nodes Q101 and Q102 is interfered with, the nodes Q103 and Q104 remain stable and the interference can be eliminated; therefore, the first embodiment of the present invention can improve the circuit's ability to resist soft errors.

[0071] The basic functional description of the circuit of the SRAM storage unit of the first embodiment of the present invention is as follows:

[0072] 1. Write "1": Figure 3A As shown, it is the simulation waveform of the SRAM storage unit of the soft error-resistant SRAM of the first embodiment of the present invention at the normal working voltage; it is assumed that the potentials of the four nodes Q101, Q103, Q104, and Q102 in the initial state are: 0, 0, 1, 1. The process of writing "1" first requires the bit line BL to be pulled up to 1, the bit line BLB to be pulled down to 0, and then the word line W to be pulled down to 0 so that the transmission tubes T101, T102, T103, and T104 are all turned on, the nodes Q101 and Q103 are pulled up to 1, and the nodes Q104 and Q102 are pulled down to 0. The 1 in the pull-up to 1 represents a logic high level, and the 0 in the pull-down to 0 represents a logic low level.

[0073] 2. Write "0": Assume that the potentials of the four nodes Q101, Q103, Q104, and Q102 in the initial state are 1, 1, 0, and 0 respectively. The process of writing "0" first requires the bit line BL to be pulled down to 0, the bit line BLB to be pulled up to 1, and then the word line W to be pulled down to 0 so that the transmission tubes T101, T102, T103, and T104 are all turned on, the nodes Q101 and Q103 are pulled down to 0, and the nodes Q104 and Q102 are pulled up to 1.

[0074] 3. Hold: When the word line signal WL is at a high level, the transmission tubes T101, T102, T103 and T104 are all in a closed state. The storage nodes Q101, Q103, Q104, Q102 in the storage unit are locked to each other to maintain the correct data.

[0075] 4. Read 1: The bit lines BL and BLB are pre-charged to 1, and then the word line WL is pulled down to 0 to turn on the transmission tubes T101, T102, T103 and T104. Since the nodes Q101 and Q103 store 1, the potential of the bit line BL remains unchanged. The 0 potential of the nodes Q102 and Q104 will cause the bit line BLB to be pulled down. When the potential difference between BL and BLB reaches a certain size, it will be read and amplified by the sensitive amplifier, and then the data 1 will be read out.

[0076] 5. Read 0: The bit lines BL and BLB are pre-charged to 1, and then the word line WL is pulled down to 0 to turn on the transmission tubes T101, T102, T103 and T104. Since the nodes Q102 and Q104 store 1, the potential of the bit line BLB remains unchanged. The 0 potential of the nodes Q101 and Q103 will cause the bit line BL to be pulled down. When the potential difference between BL and BLB reaches a certain size, it will be read and amplified by the sensitive amplifier, and then the data 0 will be read out.

[0077] The low voltage characteristics of the circuit of the SRAM storage unit of the first embodiment of the present invention are described as follows:

[0078] Depend on Figure 2 As shown in the figure, the SRAM storage unit of the first embodiment of the present invention adopts a structure of N tubes in series, that is, a structure of NMOS tubes N101 and M101 in series and a structure of NMOS tubes N102 and M102 in series. Therefore, under the same conditions, the minimum operating voltage of the SRAM storage unit of the first embodiment of the present invention can reach 0.68V, while the existing Figure 1 The Quatro memory cell is shown to operate at a minimum voltage of only 0.74V.

[0079] like Figure 3B 1 is a simulation waveform of the SRAM storage unit of the soft error-resistant SRAM of the first embodiment of the present invention at a low operating voltage; through simulation, it can be obtained that the lowest value of the low operating voltage can reach 0.68V.

[0080] like Figure 4 , which is a soft error simulation waveform of an SRAM storage unit of a soft error-resistant SRAM according to the first embodiment of the present invention; TF represents a transient error, and the waveform is described as follows:

[0081] At 15ns, a transient fault (TF) pulse is applied to the node Q101;

[0082] At 40ns, a TF pulse is applied to node Q104;

[0083] At 60ns, a TF pulse is applied to node Q102;

[0084] At 55ns, a TF pulse is applied to node Q103;

[0085] It can be proved that when a transient error flip occurs in one of the storage nodes Q101, Q103, Q104, and Q102, the circuit can restore each storage node to its original correct logic level through its own feedback.

[0086] The circuit function description of the first embodiment of the present invention is as follows:

[0087] When the word line signal WL is at a high level, all transmission tubes are turned off, and the circuit is in a holding mode, which can allow the potential of a certain node to flip.

[0088] Compared to Figure 1 As shown in the conventional Quatro circuit, the SRAM storage unit of the first embodiment of the present invention has a faster reading and writing speed due to the increase in the number of transmission tubes.

[0089] Compared to Figure 1 Compared with the conventional Quatro circuit shown in FIG. 1 , the SRAM memory cell of the first embodiment of the present invention can operate at a lower voltage.

[0090] In the first embodiment of the present invention, on the basis of the first NMOS transistor N101 and the second NMOS transistor N102 connected with a common source and the first PMOS transistor P101 and the second PMOS transistor P102 connected with a common source, a fifth MOS transistor M101 and a sixth MOS transistor M102 connected with a common drain as source followers and a seventh MOS transistor M103 and an eighth MOS transistor M104 connected with a common source are added. The seventh MOS transistor M103 and the eighth MOS transistor M104 can form an interlocking structure with the combination of the first PMOS transistor P101 and the second PMOS transistor P102, and the fifth MOS transistor M101 and the sixth MOS transistor M102 can form an interlocking structure between the combination of the first NMOS transistor N101 and the second NMOS transistor N102 and the combination of the first PMOS transistor P101 and the second PMOS transistor P102. In this way, double interlocking can be achieved, so that the SRAM can tolerate the flipping of a node potential and resist soft errors.

[0091] The first embodiment of the present invention can use four transmission pipes to connect four storage nodes. Figure 1 The circuit structure of two transmission tubes in the prior art shown in the figure is that the number of transmission tubes in the first embodiment of the present invention is increased, and the reading and writing speed is also increased.

[0092] The fifth to eighth MOS transistors M104 of the first embodiment of the present invention are all NMOS transistors. The fifth MOS transistor M101 forms a series structure with the first NMOS transistor N101, and the sixth MOS transistor M102 forms a series structure with the second NMOS transistor N102. This N-transistor series structure can make the minimum operating voltage of the SRAM storage unit reach 0.68V, so the operating voltage can be reduced.

[0093] The present invention has been described in detail above through specific embodiments, but these do not constitute a limitation of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A soft error resistant SRAM, characterized in that: The SRAM memory cell has a double interlock structure, including: A first NMOS tube and a second NMOS tube connected to a common source, the drain of the first NMOS tube being a first storage node, the drain of the second NMOS tube being a second storage node, the source of the first NMOS tube and the source of the second NMOS tube being grounded, the gate of the first NMOS tube being connected to the second storage node, the gate of the second NMOS tube being connected to the first storage node, and the first storage node and the second storage node being in anti-phase with each other; A first PMOS tube and a second PMOS tube connected to a common source, a drain of the first PMOS tube being a third storage node, a drain of the second PMOS tube being a fourth storage node, a source of the first PMOS tube and a source of the second PMOS tube being grounded, a gate of the first PMOS tube being connected to the fourth storage node, a gate of the second PMOS tube being connected to the third storage node, and the third storage node and the fourth storage node being in anti-phase with each other; The gate and source of the fifth MOS transistor connected with a common drain are connected between the first storage node and the third storage node of the same phase, so that the first storage node and the third storage node form a source follower relationship; The gate and source of the sixth MOS transistor connected with a common drain are connected between the second storage node and the fourth storage node of the same phase, so that the second storage node and the fourth storage node form a source follower relationship; The gate and drain of a seventh MOS transistor connected in common source are connected between the first storage node and the fourth storage node of the inverted phase; The gate and drain of the common-source connected eighth MOS transistor are connected between the second storage node and the third storage node of the inverted phase; The fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are all NMOS transistors.

2. The soft error resistant SRAM according to claim 1, characterized in that: The SRAM storage unit also includes a first transmission tube, a second transmission tube, a third transmission tube and a fourth transmission tube; The first storage node is connected to the input end of the first transmission tube; The second storage node is connected to the input end of the second transmission tube; The third storage node is connected to the input end of the third transmission tube; The fourth storage node is connected to the input end of the fourth transmission tube.

3. The soft error resistant SRAM according to claim 2, characterized in that: The first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube are all of the same conductivity type.

4. The soft error resistant SRAM according to claim 3, characterized in that: The gates of the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube are all connected to a word line.

5. The soft error resistant SRAM according to claim 4, characterized in that: The output ends of the first transmission tube and the third transmission tube are both connected to the first bit line; The output ends of the second transmission tube and the fourth transmission tube are both connected to a second bit line, and the first bit line and the second bit line are in opposite directions; The drains of the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube serve as input ends and the sources serve as output ends.

6. The soft error resistant SRAM according to claim 5, characterized in that: The first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube are all PMOS tubes.

7. The soft error resistant SRAM according to claim 6, characterized in that: The SRAM storage unit includes a write state, a hold state and a read state.

8. The soft error resistant SRAM according to claim 7, characterized in that: In the write state, a pair of mutually inverted write signals are pre-applied to the first bit line and the second bit line, and the word line is low-leveled to turn on the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube.

9. The soft error resistant SRAM according to claim 7, characterized in that: When the SRAM storage unit is in the hold state, the word line increases the level to turn off the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube.

10. The soft error resistant SRAM according to claim 7, characterized in that: When the SRAM storage unit is in a read state, the first bit line and the second bit line are pre-high potential, and the word line is high level to turn on the first transmission tube, the second transmission tube, the third transmission tube and the fourth transmission tube.

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