A method of forming a semiconductor device

Abstract

The application discloses a forming method of a semiconductor device, which comprises the following steps: providing a substrate, forming a pattern on the substrate, wherein the substrate comprises a pattern dense area and a pattern sparse area; forming a first barrier layer on the top of the pattern, and forming a first dielectric layer with a top higher than the top of the first barrier layer on the side of the pattern and the first barrier layer; the top of the first dielectric layer in the pattern sparse area is lower than the top of the first dielectric layer in the pattern dense area, thereby forming a sparse area recess; forming a second barrier layer on the first dielectric layer; forming a barrier extension layer on the second barrier layer, and performing a grinding treatment on the barrier extension layer until the top of the barrier extension layer is flush with the top of the second barrier layer; and etching at least the barrier extension layer, the second barrier layer and the first dielectric layer to a final target position. The application improves the uniformity of the chip, and further improves the performance of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a forming method of semiconductor device. BACKGROUND

[0002] Chemical Mechanical Polish (CMP) is a technology of realizing global planarization by using chemical corrosion and mechanical removal. In the manufacture of semiconductor devices, with the upgrading of process technology and the reduction of wire and gate size, the requirement of Lithography technology for the uniformity of wafer surface is higher and higher. The flatness of wafer and the uniformity within die are crucial to the whole semiconductor device. With the critical dimension becoming smaller and smaller, it is more and more challenging to control the flatness and uniformity of wafer surface caused by CMP.

[0003] CMP process is mainly divided into Poly-Si CMP, Silicon Oxide CMP, Silicon Carbide CMP, W CMP and Cu CMP according to the polishing object. In fact, for different materials, even if the same CMP process is carried out with the same parameters, the polishing rate, the remaining thickness after polishing, the uniformity and the flatness are not the same. In order to reduce the influence of pattern density and polishing material on the Within Die uniformity, a barrier layer needs to be constructed.

[0004] However, even if the barrier layer is constructed, and the abrasive with high selectivity and high polish efficiency (PE) is selected, the pad with higher hardness is selected, or the flatness of CMP is improved, the polishing selectivity of the material layer to be polished on the barrier layer is improved, or the material which is more difficult to polish is selected as the barrier layer, it is still unable to meet the requirement of advanced process for Within Die uniformity, which will result in poor performance of semiconductor device. SUMMARY

[0005] The present application aims to solve the problem that the pattern density has a great influence on the uniformity of chip, which further leads to poor performance of semiconductor device in the prior art. The present application provides a forming method of semiconductor device, wherein the semiconductor device formed by using the forming method of semiconductor device has better performance.

[0006] To solve the above technical problems, the embodiment of the present application discloses a forming method of a semiconductor device, comprising:

[0007] A substrate is provided, and a pattern is formed on the substrate; the substrate comprises a pattern dense area and a pattern sparse area;

[0008] A first barrier layer is formed on top of the pattern, and a first dielectric layer with a top higher than that of the first barrier layer is formed on the pattern and the periphery of the first barrier layer; the top of the first dielectric layer in the pattern sparse area is lower than that in the pattern dense area, forming a sparse area recess;

[0009] A second barrier layer is formed on the first dielectric layer;

[0010] A barrier extension layer is formed on the second barrier layer, and a grinding process is performed on the barrier extension layer until the top of the second barrier layer is flush;

[0011] At least the barrier extension layer, the second barrier layer and the first dielectric layer are etched to a final target position.

[0012] Preferably, the top of the first barrier layer in the pattern sparse area is lower than that in the pattern dense area.

[0013] Preferably, the barrier extension layer comprises:

[0014] A third barrier layer formed on the second barrier layer, and a consumption layer formed on the third barrier layer; or

[0015] A third barrier layer formed on the second barrier layer; or

[0016] A consumption layer formed on the second barrier layer.

[0017] Preferably, before the consumption layer is formed on the third barrier layer, the method further comprises:

[0018] An initial third barrier layer is formed on the second barrier layer;

[0019] A grinding process is performed on the initial third barrier layer to a first target position to form the third barrier layer.

[0020] Preferably, the first target position is the horizontal position of the top of the second barrier layer in the pattern dense area.

[0021] Preferably, the top of the second barrier layer in the pattern sparse area is lower than that in the pattern dense area.

[0022] Preferably, the initial third barrier layer is ground by a polysilicon layer abrasive to the first target position.

[0023] Preferably, the polysilicon layer abrasive is an alkaline polysilicon layer abrasive.

[0024] Preferably, the selectivity ratio of the polysilicon layer abrasive to the initial third barrier layer and the second barrier layer is greater than 100.

[0025] Preferably, after the consumption layer formed on the third barrier layer, the method further comprises: grinding the consumption layer by a cerium oxide-containing abrasive to the first target position.

[0026] Preferably, the selectivity ratio of the cerium oxide-containing abrasive to the consumption layer and the initial third barrier layer is greater than 100.

[0027] The selectivity ratio of the cerium oxide-containing abrasive to the consumption layer and the second barrier layer is greater than 30.

[0028] Preferably, the cerium oxide-containing abrasive is a cerium dioxide solution.

[0029] Preferably, the third barrier layer is a polysilicon layer.

[0030] Preferably, etching the consumption layer, the third barrier layer, the second barrier layer and the first dielectric layer to a final target position comprises:

[0031] Selecting a gas with the same etching rate for the consumption layer, the third barrier layer, the second barrier layer and the first dielectric layer to etch the consumption layer, the third barrier layer, the second barrier layer and the first dielectric layer to the final target position.

[0032] Preferably, the final target position is a horizontal position where the top of the first barrier layer of the pattern dense area is located.

[0033] Preferably, the material of the first barrier layer is silicon nitride.

[0034] Preferably, the first barrier layer is formed by chemical vapor deposition.

[0035] Preferably, the material of the second barrier layer is silicon nitride.

[0036] Preferably, the material of the consumption layer is silicon dioxide.

[0037] The beneficial effects of the present application are:

[0038] The second barrier layer is constructed on the surface of the first dielectric layer, which increases the area of the barrier layer, and can effectively avoid the problem of dishing sinking in some areas due to the small area of the first barrier layer, which cannot well block the first dielectric layer during the formation of the semiconductor device, thereby improving the flatness of the semiconductor device and further improving the performance of the semiconductor device.

[0039] Then, the initial third barrier layer is ground by using a polysilicon layer abrasive, which can make the area of the combined barrier layer structure composed of the second barrier layer and the third barrier layer after grinding larger than the area of the third barrier layer by using the high selectivity of the polysilicon layer abrasive, thereby greatly reducing the sinking of the first dielectric layer in the region corresponding to the pattern dense area.

[0040] Further, a consumption layer is formed on the third barrier layer, and the consumption layer is ground by using a cerium oxide-containing abrasive, which can effectively reduce the sinking of the first dielectric layer by using the high flatness of the cerium oxide-containing abrasive and the blocking effect of the combined barrier layer structure. The third barrier layer has the characteristic of wear resistance to the cerium oxide-containing abrasive, which further increases the area of the combined barrier layer structure.

[0041] Still further, the grinding process and etching are combined, different materials are selected for grinding or etching according to the different characteristics of the first dielectric layer, the consumption layer, the second barrier layer and the third barrier layer, which can further improve the uniformity of the chip and thereby improve the performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figures 1 to 2 is a process flow diagram for forming a semiconductor device provided by the prior art;

[0043] Figure 3 is a process flow diagram for forming a semiconductor device provided by the prior art;

[0044] Figures 4 to 8 is a process flow diagram for forming a semiconductor device provided by the prior art.

[0045] REFERENCE NUMERALS:

[0046] 1. pattern; 11. pattern dense area; 12. pattern sparse area; 2. first barrier layer; 3. first dielectric layer; 4. second barrier layer; 5. third barrier layer; 51. initial third barrier layer; 6. consumption layer; A target position; B1. first target position; B2. final target position. DETAILED DESCRIPTION

[0047] The following detailed description of the application will be made with reference to the accompanying drawings, in which: Although the description of the application will be in the general context of a method and system of embodying the application, those skilled in the art will realize that the application can be produced by other techniques. The description of the application is not intended to limit the application to the particular form set forth, but on the contrary, it is intended to cover any modifications or equivalents falling within the scope of the application. It should be noted that, as used in this specification, the singular form "a", "an" and "the" include plural references unless expressly and unequivocally limited by associated text to one singular reference. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same or similar result can be substituted for the specific embodiments shown. This disclosure is intended to cover all adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the application be contemplated to cover any and all such adaptations. Accordingly, the application is not intended to be limited to the specific form set forth herein, but on the contrary, is intended to cover such alternatives, modifications, and equivalents, as can be suggested by the disclosure and fall within the scope of the application.

[0048] It should be noted that in this specification, similar reference signs and letters in the following drawings represent similar items, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0049] In the description of the present embodiments, it should be noted that the terms "upper", "lower", "inner", "bottom", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed, and are only for the convenience of describing the application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the application.

[0050] The terms "first", "second", etc. are only used for differentiation in description and cannot be understood as indicating or implying relative importance.

[0051] In the description of the present embodiments, it should also be noted that, unless otherwise explicitly specified and limited, the terms "provided", "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present embodiments can be understood according to the specific circumstances.

[0052] As described in the background, due to the influence of pattern density, the uniformity of the existing chip is poor, which further leads to poor performance of the semiconductor device.

[0053] A method for forming a semiconductor device includes: Figure 1As shown, a substrate (not shown) is provided, and a pattern 1 is formed on the substrate. The pattern includes a pattern-dense area 11 and a pattern-sparse area 12; in addition, the pattern-dense area 11 and the pattern-sparse area 12 can be adjacent to each other or non-adjacent to each other.

[0054] The material of the substrate may be germanium (Ge), silicon (Si), silicon germanium (SiGe), silicon on insulator (SOI), germanium on insulator (GOI), etc. This embodiment does not specifically limit the substrate material.

[0055] Continue to refer Figure 1 A first barrier layer 2 is formed on the top of the pattern 1 , and a first dielectric layer 3 having a lowest point of the surface higher than the top of the first barrier layer 2 is formed on the peripheral sides of the pattern 1 and the first barrier layer 2 .

[0056] Then as Figure 2 As shown, during the grinding process, the first dielectric layer 3 is ground. Since the first barrier layer 2 occupies an insufficient area (a conventional barrier layer occupies less than 30% of the area), it cannot effectively prevent the grinding process from further consuming the first dielectric layer 3. As a result, the lowest point of the surface of the first dielectric layer 3 after grinding is significantly lower than the target position A where the grinding is expected to stop, i.e., the first dielectric layer 3 sinks (dishing). The target position A is the horizontal surface of the top of the first barrier layer 2.

[0057] In the above-mentioned formation method, the surface flatness of the first dielectric layer 3 is also poor, which is specifically manifested in that in the area where the pattern dense area 11 is located, at the corresponding position of the pattern dense area 11, the first dielectric layer 3 protrudes from the first dielectric layer 3 between the pattern dense areas 11. In the area where the pattern sparse area 12 is located, the surface of the first dielectric layer 3 is lower than the surface of the first dielectric layer 3 in the area where the pattern dense area 11 is located. Due to the unevenness of the first dielectric layer 3, after the grinding process, the thinner areas of the first dielectric layer 3 will be more likely to sink. Specifically, the surface of the first dielectric layer 3 in the pattern sparse area 12 is lower than the surface of the first dielectric layer 3 in the pattern dense area 11. Such sinking of the first dielectric layer 3 will make the chip uniformity poor, further leading to poor performance of the semiconductor device.

[0058] In order to solve the above problems, the present invention proposes a method for forming a semiconductor device, such as Figure 3 As shown, the following steps are included:

[0059] Step S1: providing a substrate and forming a pattern on the substrate; the pattern includes a pattern-dense area and a pattern-sparse area;

[0060] Step S2: forming a first barrier layer on top of the pattern, and forming a first dielectric layer on the pattern and the first barrier layer, the lowest point of the first dielectric layer being higher than the top of the first barrier layer; the top of the first dielectric layer in the sparse area of the pattern being lower than the top of the first dielectric layer in the dense area of the pattern, forming a sparse area recess;

[0061] Step S3: forming a second barrier layer on the first dielectric layer;

[0062] Step S4: forming a barrier extension layer on the second barrier layer, and performing a grinding process on the barrier extension layer until the top of the barrier extension layer is flush with the top of the second barrier layer;

[0063] Step S5: etching at least the barrier extension layer, the second barrier layer and the first dielectric layer to the final target position.

[0064] The above method improves the uniformity of the chip, thereby improving the performance of the semiconductor device.

[0065] In order to make the purpose, technical scheme and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0066] As shown in Figure 4 , a substrate (not shown in the figure) is provided, and a pattern 1 is formed on the substrate; the pattern includes a pattern dense area 11 and a pattern sparse area 12.

[0067] The material of the substrate can be germanium (Ge), silicon (Si), silicon germanium (SiGe), (SiGe), silicon on insulator (SOI), germanium on insulator (GOI) and the like, and the substrate material is not specifically limited in the present embodiment.

[0068] Continuing to refer to Figure 4 , a first barrier layer 2 is formed on top of the pattern 1, and a first dielectric layer 3 is formed on the pattern 1 and the first barrier layer 2, the lowest point of the first dielectric layer 3 being higher than the top of the first barrier layer 2.

[0069] It should be noted that the forming process of the pattern 1 is as follows: first, a material layer required for forming the pattern 1 is deposited on the substrate or other material layer, a mask layer and a material required for photolithography are then formed, and then photolithography, etching, ashing and cleaning and the like are sequentially performed to form the pattern 1; or the pattern 1 can be directly formed on the substrate or other material layer. The material of the pattern 1 is not specifically limited in the present embodiment, and can be silicon, a compound of silicon and the like.

[0070] In the present embodiment, the pattern 1 includes a pattern dense area 11 and a pattern sparse area 12 as shown in Figure 4 . The pattern dense area 11 refers to an area in which a larger number of pattern 1s are formed per unit area (i.e., the pattern is denser); and the pattern sparse area 12 refers to an area in which a smaller number of pattern 1s are formed per unit area (i.e., the pattern is sparser).

[0071] It is also necessary to explain that the first barrier layer 2 is formed on the top of the pattern 1, which can be directly formed on the top of the pattern 1, or the material layer required for forming the first barrier layer 2 is deposited on the top and the side of the pattern 1, and then the material layer is etched to form the pattern of the first barrier layer 2. The skilled in the art can choose as appropriate, and the embodiment is not limited. In other embodiments, the first barrier layer material can be one or a combination of silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), silicon carbon nitride (SiCN), and polycrystalline silicon (Poly-Si).

[0072] In this embodiment, the material of the first barrier layer 2 is silicon nitride.

[0073] In order to more obviously distinguish the pattern dense area 11 and the pattern sparse area 12, the thickness of the first barrier layer 2 formed on the pattern dense area 11 is slightly greater than the thickness of the first barrier layer 2 formed on the pattern sparse area 12. In actual process, the relative thickness of the first barrier layer 2 on the pattern sparse area 12 and the pattern dense area 11 can be the same or different.

[0074] When forming the first barrier layer 2, chemical vapor deposition (CVD) is preferred to form the first barrier layer 2; in other embodiments, physical vapor deposition process (PVD), atomic layer deposition process (ALD), heat treatment, etc. can also be used to form the first barrier layer 2.

[0075] Preferably, in this embodiment, when the first dielectric layer 3 is formed on the side of the pattern 1 and the first barrier layer 2, the material of the first dielectric layer 3 can be one or several of silicon oxide, silicon dioxide or other dielectric materials, which are not listed here.

[0076] Continuing to refer to Figure 4 The second barrier layer 4 is formed on the first dielectric layer 3, and the third barrier layer 5 is formed on the second barrier layer 4.

[0077] Preferably, the material of the second barrier layer 4 is silicon nitride, and in other embodiments, the first barrier layer material can be one or a combination of silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), silicon carbon nitride (SiCN), and polycrystalline silicon (Poly-Si). The material of the third barrier layer 5 is polycrystalline silicon, and the skilled in the art can also choose other material layers as the third barrier layer 5.

[0078] It should also be noted that, in this embodiment, the method for forming the third barrier layer 5 includes: forming an initial third barrier layer 51 on the second barrier layer 4 , and then grinding the initial third barrier layer 51 to a first target position B1 to form the third barrier layer 5 .

[0079] In this embodiment, the second barrier layer 4 and the third barrier layer 5 form a combined barrier layer structure.

[0080] The grinding process in this embodiment specifically refers to chemical mechanical grinding. Those skilled in the art can choose other grinding processes.

[0081] It should be noted that the first target position B1 refers to, for example Figure 5 The top of the second barrier layer 4 is shown on the side of the dense pattern area 11. At the first target location B1, in the area corresponding to the dense pattern area 11, the tops of the second barrier layer 4 and the third barrier layer 5 are flush. In the area corresponding to the sparse pattern area 12, the second barrier layer 4 is located between the first dielectric layer 3 and the third barrier layer 5. Furthermore, in the area corresponding to the sparse pattern area 12, the top of the third barrier layer 5 is slightly lower than the top of the third barrier layer 5 in the area corresponding to the dense pattern area 11. In the area corresponding to the sparse pattern area 12, the area between the third barrier layer 5 and the first target location B1 is the sparse area recess. In other words, the sparse area recess is formed in the area of ​​the third barrier layer 5 opposite the sparse pattern area 12.

[0082] When grinding the third barrier layer 5 to the first target position B1, a polysilicon abrasive is used. To significantly reduce the subsidence of the densely patterned area 11 and expand the area of ​​the combined barrier layer structure, a polysilicon abrasive with a high selectivity for the second barrier layer 4 is required. Specifically, the selectivity of the polysilicon abrasive for the third barrier layer 5 and the second barrier layer 4 is greater than 100. The polysilicon abrasive is alkaline.

[0083] In this embodiment, the structure of the combined barrier layer is as follows Figure 5 As shown, it includes a protrusion of the second barrier layer 4 at the position corresponding to the pattern-dense area 11, a depression of the second barrier layer 4 on both sides of the protrusion, and a third barrier layer 5. That is, at the position corresponding to the pattern-dense area 11, the second barrier layer 4 is the top of the second barrier layer 4 protruding from the top of the first dielectric layer 3 on the side of the pattern-dense area 11. In addition, a downward depression is formed in the second barrier layer 4 on the top of the first dielectric layer 3 on the side of the pattern-dense area 11. Moreover, in the area where the pattern-sparse area 12 is located, the surface of the combined barrier layer structure at the position corresponding to the pattern-sparse area 12 is not higher than the surface of the combined barrier layer structure at the position corresponding to the pattern-dense area 11.

[0084] It is precisely because the surface area of ​​the combined barrier layer structure is larger than the surface area of ​​the second barrier layer 4, especially in the pattern dense area 11, that the etching time of the first dielectric layer 3 in the pattern dense area 11 can be extended, so that the first dielectric layer 3 between the pattern dense areas 11 will not sink.

[0085] Next, if Figure 6 As shown, a sacrificial layer 6 is formed on the third barrier layer 5. This embodiment only schematically deposits one sacrificial layer 6. Of course, those skilled in the art can also deposit multiple sacrificial layers 6 as needed, and the material of the sacrificial layer 6 is preferably silicon dioxide.

[0086] After forming the sacrificial layer 6, as shown in FIG. Figure 7 As shown, the sacrificial layer 6 is ground until it is flush with the second barrier layer 4 to fill the sparse area depression formed on the third barrier layer 5. This process is to prevent sinking in the area corresponding to the sparse pattern area 12. After the sacrificial layer 6 is ground, the top of the second barrier layer 4 and the third barrier layer 5 in the area corresponding to the dense pattern area 11 are flush with the top of the sacrificial layer 6 in the area corresponding to the sparse pattern area 12.

[0087] Precisely because the defects in the sparse area are filled by the consumption layer 6, the thickness of the third barrier layer 5 and the second barrier layer 4, which play a blocking role, is larger in the pattern sparse area 12. This can shorten the etching time of the first dielectric layer 3 in the pattern sparse area 12, thereby preventing the first dielectric layer 3 between the sparse areas 11 from sinking.

[0088] It should be noted that during this grinding process of the sacrificial layer 6, the abrasive used is a cerium oxide-containing abrasive. To ensure that the top of the sacrificial layer 6 is flush with the tops of the second barrier layer 4 and the third barrier layer 5, a cerium oxide-containing abrasive with high planarization capability is preferably selected. Specifically, the selectivity of the cerium oxide-containing abrasive for the sacrificial layer 6 and the third barrier layer 5 should be greater than 100, and the selectivity for the sacrificial layer 6 and the second barrier layer 4 should be greater than 30. In this embodiment, a cerium dioxide solution is preferably used as the abrasive.

[0089] After the tops of the pattern dense area 11 and the pattern sparse area 12 are flush, Figure 8 As shown, the sacrificial layer 6 , the third barrier layer 5 , the second barrier layer 4 and the first dielectric layer 3 are etched to a final target position B2 .

[0090] Specifically, the final target position B2 is the position of the top 2 of the first barrier layer on the side of the pattern dense area 11. As mentioned above, in order to clearly distinguish the pattern sparse area 12 from the pattern dense area 11, the thickness of the first barrier layer 2 on the top of the pattern dense area 11 is slightly greater than the thickness of the first barrier layer 2 on the top of the pattern sparse area 11. Therefore, after etching, the following is formed:Figure 8 The top of the first barrier layer 2 on the top of the pattern sparse area 12 is also formed with the first dielectric layer 3. When the thickness of the first barrier layer 2 on the top of the pattern dense area 11 is equal to the thickness of the first barrier layer 2 on the top of the pattern sparse area 11, the top of the first barrier layer 2 of the pattern sparse area 12 will not have the first dielectric layer 3. When the thickness of the first barrier layer 2 on the top of the pattern dense area 11 is less than the thickness of the first barrier layer 2 on the top of the pattern sparse area 11, the first dielectric layer 3 will be formed on the top of the first barrier layer 2 on the top of the pattern dense area 11.

[0091] Figure 8 The etching of the consumption layer 6, the third barrier layer 5, the second barrier layer 4 and part of the first dielectric layer 3 is shown. Of course, on the basis of the above-mentioned etching, the first barrier layer 2 can also be etched, or the first dielectric layer 3 can be etched only to a position away from the top of the first barrier layer 2 on the top of the pattern dense area 11 by a certain distance.

[0092] In this embodiment, a gas with the same etching rate for the consumption layer 6, the third barrier layer 5, the second barrier layer 4 and the first dielectric layer 3 is used for etching, and a flat etching process is adopted during etching.

[0093] It should be noted that the way of preventing the first dielectric layer 3 between the pattern dense areas 11 from sinking in the embodiment of the present application is to supplement the barrier layer (dielectric layer) or consumption layer material in the sparse area recess, and to perform grinding treatment, so that the barrier layer (dielectric layer) or consumption layer material fills the sparse area recess.

[0094] Therefore, in another embodiment of the present application, the second barrier layer 4 can be formed on the first dielectric layer 3, and then the third barrier layer 5 is formed on the second barrier layer 4. Then the third barrier layer 5 is directly ground to be flush with the top of the second barrier layer 4.

[0095] In this embodiment, since the third barrier layer 5 can directly fill the sparse area recess, there is no need to further supplement the material forming the consumption layer.

[0096] In this embodiment, the method of forming the third barrier layer 5 is the same as the method of forming the third barrier layer 5 described above. This embodiment will not be described again.

[0097] Further, in another embodiment of the present application, the second barrier layer 4 can be formed on the first dielectric layer 3, and then the consumption layer 6 is formed on the second barrier layer 4. Then the consumption layer 6 is directly ground to be flush with the top of the second barrier layer 4.

[0098] The second barrier layer is constructed on the surface of the first dielectric layer, the area of the barrier layer is increased, and the problem of dishing sinking in some areas due to the small area of the first barrier layer and the poor blocking of the first dielectric layer during the formation of the semiconductor device is avoided, so that the flatness of the semiconductor device is improved, and the performance of the semiconductor device is further improved.

[0099] The initial third barrier layer is then ground by the polysilicon layer abrasive, the high selectivity of the polysilicon layer abrasive is utilized to make the area of the combined barrier layer structure composed of the second barrier layer and the third barrier layer after grinding larger than the area of the third barrier layer, so that the sinking of the first dielectric layer in the region corresponding to the pattern dense area is greatly reduced.

[0100] Further, the consumption layer is formed on the third barrier layer, and the consumption layer is ground by the cerium oxide-containing abrasive, the high flatness of the cerium oxide-containing abrasive and the blocking effect of the combined barrier layer structure are utilized to effectively reduce the sinking of the first dielectric layer. The third barrier layer has the characteristic of wear resistance to the cerium oxide-containing abrasive, which further increases the area of the combined barrier layer structure.

[0101] Further, the grinding process and etching are combined, different materials are selected for grinding or etching according to the different characteristics of the first dielectric layer, the consumption layer, the second barrier layer and the third barrier layer, the uniformity of the chip is further improved, and the performance of the semiconductor device is improved.

[0102] Although the application has been illustrated and described with reference to certain preferred embodiments thereof, it should be understood by those skilled in the art that the foregoing is a description of the application in terms of preferred embodiments only and is not intended to limit the application to the specific embodiments illustrated and described. Various modifications to the application can be made by those skilled in the art, including simple substitutions of elements or equivalents thereof, without departing from the spirit and scope of the application.

Claims

1. A method of forming a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, and forming a pattern on the substrate; the substrate comprises a pattern dense area and a pattern sparse area; forming a first barrier layer on top of the pattern, and forming a first dielectric layer with a top higher than that of the first barrier layer on the side of the pattern and the first barrier layer; the top of the first dielectric layer of the pattern sparse area is lower than that of the pattern dense area, forming a sparse area depression; forming a second barrier layer on the first dielectric layer; forming a barrier extension layer on the second barrier layer, and performing a grinding process on the barrier extension layer until the top of the second barrier layer is flush, the barrier extension layer comprises a third barrier layer formed on the second barrier layer and a consumption layer formed on the third barrier layer; the method for forming the third barrier layer comprises: forming an initial third barrier layer on the second barrier layer, and then performing a grinding process on the initial third barrier layer to a first target position to form the third barrier layer; etching at least the barrier extension layer, the second barrier layer and the first dielectric layer to a final target position.

2. The method of forming a semiconductor device of claim 1, wherein, The top of the first barrier layer of the pattern sparse area is lower than that of the pattern dense area.

3. The method for forming a semiconductor device according to Claim 1, wherein The first target position is the horizontal position of the top of the second barrier layer of the pattern dense area.

4. The method for forming a semiconductor device according to Claim 1, wherein The top of the second barrier layer of the pattern sparse area is lower than that of the pattern dense area.

5. The method for forming a semiconductor device according to Claim 1, wherein The grinding process on the initial third barrier layer to the first target position is performed by a polysilicon layer abrasive.

6. The method for forming a semiconductor device according to Claim 5, wherein The polysilicon layer abrasive is an alkaline polysilicon layer abrasive.

7. The method for forming a semiconductor device according to Claim 6, wherein The selectivity of the polysilicon layer abrasive to the initial third barrier layer and the second barrier layer is greater than 100.

8. The method for forming a semiconductor device according to Claim 1, wherein After the consumption layer formed on the third barrier layer, the method further comprises: performing a grinding process on the consumption layer to the first target position by a cerium oxide-containing abrasive.

9. The method for forming a semiconductor device according to claim 8, wherein: The selectivity of the cerium oxide-containing abrasive to the consumption layer and the initial third barrier layer is greater than 100; The selectivity of the cerium oxide-containing abrasive to the consumption layer and the second barrier layer is greater than 30.

10. The method of forming a semiconductor device according to Claim 8 or 9, wherein, The cerium oxide-containing abrasive is a cerium dioxide solution.

11. The method for forming a semiconductor device according to Claim 2, wherein The third barrier layer is a polysilicon layer.

12. The method for forming a semiconductor device according to Claim 1, wherein The etching of the consumption layer, the third barrier layer, the second barrier layer and the first dielectric layer to the final target position comprises: selecting a gas with the same etching rate to the consumption layer, the third barrier layer, the second barrier layer and the first dielectric layer to etch the consumption layer, the third barrier layer, the second barrier layer and the first dielectric layer to the final target position.

13. The method for forming a semiconductor device according to claim 1 or 12, wherein The final target position is the horizontal position of the top of the first barrier layer of the pattern dense area.

14. The method for forming a semiconductor device according to Claim 1, wherein The material of the first barrier layer is silicon nitride.

15. The method for forming a semiconductor device according to Claim 14, wherein The first barrier layer is formed by a chemical vapor deposition method.

16. The method for forming a semiconductor device according to Claim 1, wherein The material of the second barrier layer is silicon nitride.

17. The method for forming a semiconductor device according to Claim 1, wherein The material of the consumption layer is silicon dioxide.

Images