semiconductor devices

Abstract

The present application relates to a semiconductor device, comprising: a semiconductor substrate and an active region formed on the semiconductor substrate, the active region comprising a channel region, a gate structure formed on the channel region, and source and drain regions formed on both sides of the channel region; an interlayer dielectric layer formed on the active region; a top metal layer located on the interlayer dielectric layer and electrically connected to the active region through contact holes; and a passivation layer located on the top metal layer, the passivation layer comprising an oxygen-rich silicon layer and a silicon-rich silicon nitride layer stacked on the oxygen-rich silicon layer, wherein the thickness of the oxygen-rich silicon layer ranges from #imgabs0# and the refractive index of the oxygen-rich silicon layer ranges from 1.67 to 1.70. In the above-mentioned semiconductor device, by adjusting the thickness of the oxygen-rich silicon to within the range of #imgabs1# and adjusting its refractive index to within the range of 1.67 to 1.70, the HTRB stability of the semiconductor device can be improved without adding additional operations.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor device. Background Art

[0002] In semiconductor manufacturing, metal oxide semiconductor field effect transistors (MOSFETs) are generally not put into use immediately after production. Instead, they are tested for reliability and actual service life using relevant reliability tests. The high temperature reverse bias (HTRB) characteristic of MOSFETs is a very important reliability factor for MOSFETs, as it reflects the reverse breakdown characteristics of the PN junction at high temperatures.

[0003] Currently, the HTRB of the 500V lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) based on the CSMC high-voltage BCD G3S-SM platform has very poor stability and failure issues, which has an adverse impact on terminal applications and customer market promotion. Summary of the Invention

[0004] Based on this, it is necessary to propose a new semiconductor device to address the technical problem of poor HTRB stability of the current LDMOS.

[0005] A semiconductor device comprising:

[0006] A semiconductor substrate and an active region formed on the semiconductor substrate, the active region including a channel region, a gate structure formed on the channel region, and a source region and a drain region formed on both sides of the channel region, the channel region having a first conductivity type, and the source region and the drain region having a second conductivity type;

[0007] an interlayer dielectric layer formed on the active area;

[0008] a top metal layer, located on the interlayer dielectric layer and electrically connected to the active area through a contact hole;

[0009] A passivation layer is located on the top metal layer, and the passivation layer includes an oxygen-rich silicon layer and a silicon-rich silicon nitride layer stacked on the oxygen-rich silicon layer, wherein the thickness of the oxygen-rich silicon layer is in the range of The refractive index of the oxygen-rich silicon layer ranges from 67 to 70.

[0010] In one embodiment, the thickness of the oxygen-rich silicon layer is The refractive index of the oxygen-rich silicon layer is 67.

[0011] In one embodiment, the thickness of the silicon-rich silicon nitride layer is in the range of The refractive index of the silicon-rich silicon nitride layer ranges from 2.17 to 2.23.

[0012] In one embodiment, the semiconductor device is manufactured based on a CSMC high-voltage BCD platform.

[0013] In one embodiment, the breakdown voltage of the semiconductor device is greater than or equal to 500V.

[0014] In one embodiment, the semiconductor device is LDMOS.

[0015] In one embodiment, the semiconductor substrate has a first conductivity type, and the active region further includes:

[0016] a drift region having a second conductivity type and formed on the semiconductor substrate, wherein the drain region is formed in the drift region;

[0017] a body region, having a first conductivity type, and arranged side by side with the drift region on the semiconductor substrate;

[0018] A well region has a first conductivity type and is formed in the body region and has a doping concentration greater than that of the body region. The source region is formed in the well region. The channel region includes the well region and the body region located between the source region and the drift region.

[0019] In one embodiment, a field oxide is formed on the drift region between the drain region and the body region, and the gate structure extends onto the field oxide.

[0020] In one embodiment, the top metal layer includes a source metal strip and a gate metal strip, the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, an intermediate metal layer is sandwiched between the first dielectric layer and the second dielectric layer, the intermediate metal layer includes a first metal field plate covering the drain region and electrically connected to the drain region, a second metal field plate covering a portion of the field oxide and electrically connected to the gate structure, the first metal field plate is electrically connected to the drain metal strip, and the second metal field plate is electrically connected to the gate metal strip.

[0021] In one embodiment, a doped region is formed in the drift region below the field oxide, and the doped region has a first conductivity type.

[0022] The above-mentioned semiconductor device forms an interlayer dielectric layer on the active area and a top metal layer on the interlayer dielectric layer. The top metal layer is electrically connected to the active area. In order to protect the top metal layer, a passivation layer is also formed on the top metal layer. The passivation layer is usually stacked with oxygen-rich silicon and silicon-rich silicon nitride. Each electrode connection end passes through the passivation layer and is electrically connected to the corresponding top metal layer. In traditional technology, in order to improve the stability of the HTRB of semiconductor devices, improvements are generally made in terms of the internal structure design of the device, packaging materials, environmental impact, and interlayer dielectric layer. So far, no method has been found to improve the stability of the device HTRB by adjusting the parameters of the passivation layer. The thickness of the oxygen-rich silicon in the passivation layer used in traditional semiconductor devices is generally about 1000 nm. Its refractive index range is generally 1.60 to 1.63. In this application, by optimizing the parameters of the passivation layer, the thickness of the oxygen-rich silicon is adjusted to By reducing the thickness of the oxygen-rich silicon and increasing its refractive index to within the range of 2400-3000 and 1.67-1.70, the HTRB stability of semiconductor devices can be improved without any additional operations. Furthermore, reducing the thickness of the oxygen-rich silicon can save production costs and improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic structural diagram of a semiconductor device according to an embodiment;

[0024] Figure 2 is a schematic structural diagram of a semiconductor device according to another embodiment;

[0025] Figure 3 This is a graph showing the change trend of HTRB of semiconductor devices with the compressive stress of the passivation layer;

[0026] Figure 4 is the graph showing the change of compressive stress of the passivation layer with the thickness of the oxygen-rich silicon layer;

[0027] Figure 5 This is a diagram showing the HTRB test effect of semiconductor devices when oxygen-rich silicon has different refractive indices;

[0028] Figure 6 This is the test effect diagram of the traditional semiconductor device HTRB;

[0029] Figure 7 This is a test effect diagram of the semiconductor device HTRB of this application.

[0030] Component number description:

[0031] Semiconductor substrate: 100; channel region: 101; drift region: 110; drain region: 111; drain contact region: 112; doped region: 113; body region: 120; well region: 121; source region: 122; body contact region: 123; field oxygen: 200; gate structure: 300; interlayer dielectric layer: 400; first dielectric layer: 410; second dielectric layer: 420; intermediate metal layer: 500; first metal field plate: 510; second metal field plate: 520; first connection metal: 530; second connection metal: 540; top metal layer: 600; drain metal strip: 610; source metal strip: 620; substrate electrode strip: 630; passivation layer: 700; oxygen-rich silicon layer: 710; silicon-rich silicon nitride layer: 720. DETAILED DESCRIPTION

[0032] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] Combine Figure 1 As shown, the semiconductor device includes:

[0035] The semiconductor substrate 100 may be made of undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). As an example, in this embodiment, the semiconductor substrate 100 is made of single crystal silicon.

[0036] An active region is formed on the semiconductor substrate 100. The active region includes a channel region 101, a gate structure 300 formed on the channel region 101, and a source region 122 and a drain region 111 formed on both sides of the channel region 101. The channel region 101 has a first conductivity type, and the source region 122 and the drain region 111 both have a second conductivity type. The first conductivity type is opposite to the second conductivity type. When the first conductivity type is P-type, the second conductivity type is N-type, and when the first conductivity type is N-type, the second conductivity type is P-type. In this embodiment, the first conductivity type is P-type and the second conductivity type is N-type. The gate structure 300 is located on the channel region 101 and regulates the distribution of carriers in the channel region 101. When an inversion layer forms in the channel region 101, it becomes a conductive channel connecting the source region 122 and the drain region 111, thereby turning on the semiconductor device. When the inversion layer does not form in the channel region 101, the semiconductor device is turned off. The gate structure 300 includes a gate dielectric layer and a gate conductive layer. Specifically, the gate dielectric layer can be a silicon oxide layer, and the gate conductive layer can be a polysilicon layer.

[0037] Interlayer dielectric layer 400 is formed on the active area, specifically covering all structures in the active area to protect the active area. Specifically, interlayer dielectric layer 400 can be silicon oxide or silicon nitride, or a composite layer of silicon oxide and silicon nitride. In this embodiment, interlayer dielectric layer 400 includes a composite structure of silicon oxide, oxygen-rich silicon, and borophosphosilicate glass (BPSG).

[0038] The top metal layer 600 is located on the interlayer dielectric layer 400 and is electrically connected to the active region below the interlayer dielectric layer 400 through contact holes that penetrate the interlayer dielectric layer 400. Specifically, the top metal layer 600 includes a drain metal strip 610, a gate metal strip, and a source metal strip 620. The drain metal strip 610 is electrically connected to the drain region 111 through corresponding contact holes, the source metal strip 620 is electrically connected to the source region 122 through corresponding contact holes, and the gate metal strip is electrically connected to the gate structure 300 through corresponding contact holes. Specifically, a drain contact region 112 is formed on the surface of the drain region 111. The drain contact region 112 has a second conductivity type and a higher doping concentration than the drain region 111. The drain metal strip 610 contacts the drain contact region 112 through the contact holes, thereby reducing contact resistance. It can be understood that an intermediate metal layer can be provided in the interlayer dielectric layer 400 as needed, and the top metal layer 600 can be electrically connected to the active area below through the contact hole and the intermediate metal layer.

[0039] The passivation layer 700 is located on the top metal layer 600 and can conformally cover the top metal layer 600 and the interlayer dielectric layer 400 outside the top metal layer 600. The passivation layer 700 includes an oxygen-rich silicon (SRO) layer stacked on an oxygen-rich silicon layer 710 and a silicon-rich silicon nitride (SRN) layer. The thickness of the oxygen-rich silicon layer 710 is in the range of The refractive index of the oxygen-rich silicon layer 710 ranges from 1.67 to 1.70. Specifically, the refractive index of the oxygen-rich silicon layer 710 can be adjusted by adjusting the silicon content of the oxygen-rich silicon layer 710. In one embodiment, the oxygen-rich silicon layer 710 can be formed by a chemical vapor deposition process, and the reaction gases used to form the oxygen-rich silicon layer 710 include N2O and SiH4. The oxygen-rich silicon layer 710 can be formed with different refractive indices by adjusting the flow rates of N2O and SiH4.

[0040] In traditional technology, in order to improve the stability of HTRB of semiconductor devices, improvements are generally made in terms of device internal structure design, packaging materials, environmental impact, and interlayer dielectric layer 400. So far, no method has been found to improve the stability of device HTRB by adjusting the parameters of the passivation layer. The thickness of the oxygen-rich silicon layer used in the passivation layer of traditional semiconductor devices is usually Its refractive index range is usually 1.60 to 1.63.

[0041] Research has found that increasing the compressive stress of the passivation layer 700 can improve the stability of the HTRB of the semiconductor device. Figure 3 The figure shows the comparison of the HTRB test results of two groups of devices. The compressive stress |F| of the passivation layer 700 of the left group of devices is less than 4E+08, while the compressive stress |F| of the passivation layer 700 of the right group of devices is greater than 1E+09. The results show that the HTRB results of the group of devices with larger compressive stress of the passivation layer 700 are more stable. In this application, by optimizing the parameters of the passivation layer 700 and reducing the thickness D of the oxygen-rich silicon, the thickness of the oxygen-rich silicon layer 710 is reduced to In the range of , the compressive stress of the passivation layer 700 can be increased. Figure 4 Shown with regular thickness The oxygen-rich silicon layer and thickness are reduced to Comparison of the effect of the oxygen-rich silicon layer 710 on the compressive stress of the passivation layer 700, Figure 4 As shown in FIG, the thickness of the oxygen-rich silicon layer 710 is The corresponding compressive stress of the passivation layer 700 is much greater than the thickness of the oxygen-rich silicon layer 710. At the same time, the effect of changing the refractive index RI of the oxygen-rich silicon layer 710 on the compressive stress was also tested. Figure 4 As shown, the thickness of the tested multiple groups of oxygen-rich silicon layers 710 is The compressive stress of the passivation layer 700, which has a different refractive index from the oxygen-rich silicon layer 710, Figure 4 It is shown that when the refractive index of the oxygen-rich silicon layer 710 is different, the compressive stress of the passivation layer 700 is also different. Therefore, the refractive index of the oxygen-rich silicon layer 710 also has a certain influence on the compressive stress. In this application, the refractive index of the oxygen-rich silicon layer 710 is adjusted to the range of 1.67 to 1.70, which can further improve the stability of the device HTRB. Figure 5 As shown, the thickness of the oxygen-rich silicon layer 710 is When the refractive index of the oxygen-rich silicon layer is changed, multiple HTRB tests are performed on the semiconductor device. The results show that the HTRB results of the device corresponding to the refractive index of the oxygen-rich silicon layer 710 in the range of 1.67 to 1.70 are more stable. Figure 6 and Figure 7 The figure shows the comparison of HTRB results of a conventional semiconductor device and the semiconductor device of the present application, wherein: Figure 6 The thickness range of the oxygen-rich silicon layer 710 is HTRB test results of semiconductor devices with a refractive index range of 1.60 to 1.63, Figure 7 The thickness of the oxygen-rich silicon layer 710 is The test structure of the HTRB of the semiconductor device with a refractive index range of 1.67 to 1.70 can be seen from the comparison that the thickness of the oxygen-rich silicon layer 710 is reduced to Increasing its refractive index to 1.67-1.70 can improve the HTRB stability of semiconductor devices without adding additional operations. At the same time, reducing the thickness of oxygen-rich silicon can also save production costs and improve production efficiency.

[0042] In one embodiment, the thickness of the oxygen-rich silicon layer 710 is specifically selected from The refractive index of the oxygen-rich silicon layer 710 is specifically selected to be 1.67. In this case, the HTBR test result of the semiconductor device is optimal.

[0043] In one embodiment, the thickness of the silicon-rich silicon nitride layer 720 is in the range of The refractive index range of the silicon-rich silicon nitride layer 720 is 2.17 to 2.23, which is the parameter of the silicon-rich silicon nitride layer 720 in traditional technology. In this solution, only the parameters of the oxygen-rich silicon layer 710 are adjusted, and the silicon-rich silicon nitride layer 720 continues to use conventional parameters, which can make the HTRB test of the semiconductor device have better stability.

[0044] In one embodiment, the semiconductor device may be a lateral double diffused metal oxide semiconductor field effect transistor (LDMOS).

[0045] In a specific embodiment, if Figure 2As shown, the semiconductor substrate 100 has a first conductivity type, the above-mentioned active region also includes a drift region 110, the drift region 110 has a second conductivity type and is formed on the semiconductor substrate 100; the drain region 111 is formed in the drift region, and the doping concentration of the drain region 111 is greater than the doping concentration of the drift region 110; the active region also includes a body region 120, the body region 120 has the first conductivity type and the body region 120 and the drift region 110 are arranged side by side on the semiconductor substrate 100, a well region 121 is formed in the body region 120, the well region 121 has the first conductivity type, and the doping concentration of the well region 121 is higher than the doping concentration of the body region 120, the above-mentioned source region 122 is formed in the well region 121, the above-mentioned channel region 101 includes the well region 121 and the body region 120 located between the source region 122 and the drift region 110, and the gate structure 300 is formed on the channel region 101.

[0046] In one embodiment, a field oxide 200 is formed on the drift region 110 between the drain contact region 112 and the body region 120, and the gate structure 300 extends from the channel region 101 to a portion of the field oxide 200. Specifically, the gate conductive layer extends to the field oxide 200 to form a field plate structure to adjust the electric field distribution of the drift region 110, assist in depletion of the drift region 110, and thus enhance the device's withstand voltage.

[0047] Furthermore, the interlayer dielectric layer 400 includes a first dielectric layer 410 and a second dielectric layer 420. An intermediate metal layer 500 is sandwiched between the first dielectric layer 410 and the second dielectric layer 420. The intermediate metal layer 500 includes a first metal field plate 510 and a second metal field plate 520. The first metal field plate 510 covers the drain region 111 and is electrically connected to the drain region 111 through a contact hole. The second metal field plate 520 covers a portion of the field oxide 200 and is electrically connected to the gate structure 300 through a contact hole. Simultaneously, the drain metal strip 610 located on the second dielectric layer 420 is electrically connected to the first metal field plate 510 through a contact hole, and the gate metal strip located above the second dielectric layer 420 is electrically connected to the second metal field plate 520 through a contact hole. In this embodiment, the formation of the metal field plate within the interlayer dielectric layer 400 can further assist in the depletion of the drift region 110, thereby further enhancing the device's withstand voltage. In one embodiment, the intermediate metal layer 500 further includes a first connection metal 530 located above the source region 122. The first connection metal 530 is electrically connected to the source region 122 via a contact hole. The source metal strip 620 located on the second dielectric layer 420 is electrically connected to the first connection metal 530 via a contact hole. In one embodiment, a doped region 113 is further formed in the drift region 110 below the field oxide 200. The doped region 113 has a first conductivity type, i.e., the conductivity type of the doped region 113 is opposite to that of the drift region 110. This further assists in depletion of the drift region 110 and enhances the device's withstand voltage.

[0048] In one embodiment, a body contact region 123 is further formed within the well region 121. The body contact region 123 has a first conductivity type and a doping concentration greater than that of the well region 121. The top metal layer 600 on the interlayer dielectric layer 400 further includes a substrate electrode strip 630, which is electrically connected to the body contact region 123 via a contact hole. Furthermore, the intermediate metal layer 500 further includes a second connection metal 540, which is electrically connected to the body contact region 123 via a contact hole. The substrate electrode strip 630 is electrically connected to the second connection metal 540 via the contact hole.

[0049] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device is an LDMOS, comprising: A semiconductor substrate and an active region formed on the semiconductor substrate, the active region including a channel region, a gate structure formed on the channel region, and a source region and a drain region formed on both sides of the channel region, the channel region having a first conductivity type, and the source region and the drain region having a second conductivity type; an interlayer dielectric layer formed on the active area; a top metal layer, located on the interlayer dielectric layer and electrically connected to the active area through a contact hole; A passivation layer is located on the top metal layer and covers the top metal layer. The passivation layer includes an oxygen-rich silicon layer and a silicon-rich silicon nitride layer stacked on the oxygen-rich silicon layer. The thickness of the oxygen-rich silicon layer is in the range of The refractive index of the oxygen-rich silicon layer is in the range of 1.67 to 1.

70.

2. The semiconductor device according to claim 1, wherein The thickness of the oxygen-rich silicon layer is The refractive index of the oxygen-rich silicon layer is 1.

67.

3. The semiconductor device according to claim 1, wherein The thickness range of the silicon-rich silicon nitride is The refractive index of the silicon-rich silicon nitride is in the range of 2.17 to 2.

23.

4. The semiconductor device according to claim 1, wherein The semiconductor device is manufactured based on the CSMC high-voltage BCD platform.

5. The semiconductor device according to claim 4, wherein The breakdown voltage of the semiconductor device is greater than or equal to 500V.

6. The semiconductor device according to claim 1, wherein The semiconductor substrate has a first conductivity type, and the active region further includes: a drift region having a second conductivity type and formed on the semiconductor substrate, wherein the drain region is formed in the drift region; a body region, having a first conductivity type, and arranged side by side with the drift region on the semiconductor substrate; A well region has a first conductivity type and is formed in the body region and has a doping concentration greater than that of the body region. The source region is formed in the well region. The channel region includes the well region and the body region located between the source region and the drift region.

7. The semiconductor device according to claim 6, wherein A field oxide is formed on the drift region between the drain region and the body region, and the gate structure extends onto the field oxide.

8. The semiconductor device according to claim 7, wherein The top metal layer includes a drain metal strip and a gate metal strip, the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer, an intermediate metal layer is sandwiched between the first dielectric layer and the second dielectric layer, the intermediate metal layer includes a first metal field plate covering the drain region and electrically connected to the drain region, a second metal field plate covering a portion of the field oxide and electrically connected to the gate structure, the first metal field plate is electrically connected to the drain metal strip, and the second metal field plate is electrically connected to the gate metal strip.

9. The semiconductor device according to claim 7, wherein A doped region is formed in the drift region below the field oxide, and the doped region has a first conductivity type.

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