Fault-tolerant packaging substrate and semiconductor device

Abstract

This invention proposes a fault-tolerant packaging substrate and semiconductor device, belonging to the field of integrated circuit packaging technology. The fault-tolerant packaging substrate includes a substrate body, on which circuitry and power protection components are disposed. The circuitry is connected to pins through the power protection components. The power protection components can promptly melt and break the circuit when a short circuit occurs between the circuitry and the pins, thus protecting the circuitry on the substrate body.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit packaging technology, and relates to a substrate for chip packaging, specifically a fault-tolerant packaging substrate and semiconductor device. Background Technology

[0002] The substrate is the outer shell used to mount semiconductor integrated circuit chips. It plays a role in placing, fixing, sealing, protecting the chips, and enhancing their electrothermal performance. During chip packaging, the contacts on the chip need to be connected to the substrate with wires. The wires pass through the substrate and lead out pins at the packaging end of the substrate. Through the pins, they are connected to external circuits to transmit current, signals, and other information.

[0003] With the development of IC packaging technology, chips are evolving towards lower voltage and higher current, while simultaneously requiring smaller package sizes. This results in more and denser circuitry on the chip, and consequently, smaller pin spacing and higher current draw on the pins. Therefore, when there are numerous power supplies and pins on the substrate's package end, short circuits can easily occur during the soldering process after packaging, connecting adjacent power supplies to the pins. Furthermore, a short circuit in one power supply can cause other power supplies to burn out or short-circuit, ultimately damaging the entire packaged chip. Summary of the Invention

[0004] To address the problem that short circuits between adjacent power supplies and pins can easily occur during the soldering process of existing packaged chips, leading to the burning out of the entire packaged chip, this invention proposes a fault-tolerant packaging substrate and semiconductor device.

[0005] This invention discloses a fault-tolerant packaging substrate, in which a power protection component is embedded in the circuit embedding layer at the bottom of the packaging substrate. The circuits on the substrate body are connected to the pins through the power protection component. When a short circuit occurs in an individual pin, the power protection component melts in time, breaking the path between the pin and the circuit, ensuring the normal operation of other pins and avoiding affecting the overall performance of the chip. The specific technical solution is as follows:

[0006] A fault-tolerant packaging substrate is provided for packaging a chip. The packaging substrate includes a substrate body, on which circuits and power protection components are disposed. The circuits are used for electrical connection with the chip, and the circuits are connected to pins through the power protection components.

[0007] Furthermore, the substrate body is also provided with a connecting plate, and the power protection component is connected to the pins through the connecting plate.

[0008] Further specifying, the connecting disk is a copper disk.

[0009] Further defined, the circuit, power protection component, connection pad and pin constitute the power output branch of the chip, and there are multiple power output branches, which are connected in parallel on the substrate body.

[0010] Furthermore, the bottom of the substrate body is provided with a circuit embedding layer, and the power protection component and the connecting plate are both embedded in the circuit embedding layer.

[0011] Further specifying, the connecting plate is embedded in the circuit embedding layer, and the power protection component is partially embedded in the circuit embedding layer and located on the connecting plate, and is electrically connected to the connecting plate.

[0012] Further defined, the substrate body includes a multilayer substrate circuit layer and a multilayer substrate dielectric layer, wherein the substrate circuit layer and the substrate dielectric layer are stacked in a spaced manner from top to bottom.

[0013] One end of the circuit is connected to the topmost substrate circuit layer, and the other end passes through the substrate dielectric layer and the substrate circuit layer below the topmost substrate circuit layer from top to bottom and is electrically connected to the power protection component.

[0014] Furthermore, the connecting plate is welded to the pin.

[0015] Further specifying, the power protection component is a thin-film surface mount fuse or a square tube surface mount fuse.

[0016] A semiconductor device includes a chip and the aforementioned packaging substrate, wherein the packaging substrate is electrically connected to the chip via circuitry.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] 1. The present invention provides a fault-tolerant packaging substrate, which has a power protection component connected between the circuit and the pin. The power protection component can promptly melt the circuit and disconnect the path between the pin and the circuit when a short circuit occurs between the circuit and the pin, thereby protecting the circuit.

[0019] 2. A connecting plate is also provided on the substrate body. The power protection component is connected to the pin through the connecting plate. The connecting plate increases the connection area at the connection between the power protection component and the pin, so that the power protection component and the pin have stable contact.

[0020] 3. The circuit, power protection components, connection pads, and pins constitute a power output branch of the chip. There are multiple power output branches, which are connected in parallel on the substrate. The power protection components can promptly melt and disconnect the power output branch when one of the power output branches fails or when there is a connection error between the pins and the circuits in two adjacent power output branches, thus protecting the other power output branches that are working normally. This effectively prevents the entire packaged chip from being damaged due to the failure of a single power output branch, and protects the overall performance of the packaged chip.

[0021] 4. A circuit embedding layer is provided at the bottom of the substrate body. The power protection component and the connecting plate are embedded in the circuit embedding layer. The power protection component and the connecting plate can be positioned and protected without affecting the circuit distributed on the substrate body. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a substrate structure without power protection components.

[0023] Figure 2 This is a schematic diagram of the fault-tolerant packaging substrate of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of the semiconductor device of the present invention;

[0025] Among them, 1-substrate circuit layer; 2-substrate dielectric layer; 3-circuit embedding layer; 4-connecting pad; 5-power protection component; 6-pin; 7-line; 8-chip. Detailed Implementation

[0026] To make the technical solution of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of protection, but merely to illustrate selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] This invention discloses a fault-tolerant packaging substrate for packaging a chip 8. The packaging substrate includes a substrate body, on which circuitry 7 and a power protection component 5 are disposed. The circuitry 7 is electrically connected to the chip 8, and the circuitry 7 is connected to pins 6 via the power protection component 5. A connection pad 4 is also disposed on the substrate body, and the power protection component 5 is connected to the pins 6 via the connection pad 4. The connection pad 4 is a copper pad. The circuitry 7, power protection component 5, connection pad 4, and pins 6 constitute multiple power output branches of the chip, which are connected in parallel on the substrate body. A circuit embedding layer 3 is disposed at the bottom of the substrate body, and both the power protection component 5 and the connection pad 4 are embedded within the circuit embedding layer 3. The connection pad 4 is embedded within the circuit embedding layer 3, and the power protection component 5 is partially embedded within the circuit embedding layer 3 and located on the connection pad 4, and is electrically connected to the connection pad 4. The substrate body includes a multilayer substrate circuit layer 1 and a multilayer substrate dielectric layer 2, which are stacked alternately from top to bottom. One end of the circuit 7 is connected to the topmost substrate circuit layer 1, and the other end passes through the substrate dielectric layer 2 below the topmost substrate circuit layer 1 and the substrate circuit layer 1 from top to bottom, and is electrically connected to the power protection component 5. The connecting pad 4 is soldered to the pin 6. The power protection component 5 is a thin-film surface mount fuse or a square tube surface mount fuse.

[0028] The present invention provides a semiconductor device, including a chip 8 and the aforementioned packaging substrate, wherein the packaging substrate is electrically connected to the chip 8 via a line 7.

[0029] Example 1

[0030] The present invention provides a fault-tolerant packaging substrate, which includes a substrate body, on which a line 7 and a power protection component 5 are disposed. The line 7 is electrically connected to the upper end face of the power protection component 5, and the lower end face of the power protection component 5 is electrically connected to a pin 6.

[0031] Preferably, the power protection component 5 in this embodiment is a thin-film surface mount fuse or a square tube surface mount fuse.

[0032] Preferably, in this embodiment, pin 6 is a metal solder ball, which can serve both as a welding connection and as a conductor.

[0033] Example 2

[0034] This embodiment provides a fault-tolerant packaging substrate. Based on embodiment 1, it further includes a connecting disk 4 on the substrate body. The connecting disk 4 is disposed between the power protection component 5 and the pin 6. The upper end face of the connecting disk 4 contacts and is electrically connected to the lower end face of the power protection component 5, and the lower end face of the connecting disk 4 is electrically connected to the pin 6. The connecting disk 4 serves as a connecting disk between the power protection component 5 and the pin 6, increasing the contact area when the power protection component 5 and the pin 6 are connected.

[0035] Preferably, in this embodiment, the connecting disk 4 is a copper disk.

[0036] Example 3

[0037] See Figure 1 and Figure 2 In this embodiment, a fault-tolerant packaging substrate is provided. Based on embodiment 2, a line 7, a power protection component 5, a connecting disk 4, and a pin 6 constitute a power output branch of the chip 8. Four power output branches are provided on a substrate body and are connected in parallel on the substrate body.

[0038] It is particularly important to note that the power supply branch can carry either current or signal flow.

[0039] Example 4

[0040] This embodiment provides a fault-tolerant packaging substrate. Based on embodiment 3, it has a circuit embedding layer 3 at the bottom of the substrate body. The circuit embedding layer 3 has four embedding holes for embedding power protection components 5 and connecting pads 4. Each embedding hole corresponds to a power output branch. The embedding holes are through holes that penetrate the upper and lower surfaces of the circuit embedding layer 3. The power protection components 5 and connecting pads 4 are embedded in the embedding holes from top to bottom along the axial direction of the embedding holes. The upper surface of the power protection components 5 extends above the embedding holes, and the lower surface of the power protection components 5 is in contact with the upper surface of the connecting pads 4. The lower surface of the connecting pads 4 is on the same horizontal plane as the bottom of the embedding holes and the lower surface of the substrate body. The lower surface of the connecting pads 4 is electrically connected to the pins 6.

[0041] In this embodiment, both the power protection component 5 and the connecting plate 4 are connected to the wall of the buried hole by welding or adhesive bonding, with welding being the preferred connection method.

[0042] Preferably, the power protection component 5 and the embedded hole, as well as the connecting plate 4 and the embedded hole, can be soldered, soldered, or glued together.

[0043] Preferably, the lower end face of the connecting plate 4 contacts the pin 6 and is welded at the contact point.

[0044] Example 5

[0045] This embodiment provides a fault-tolerant packaging substrate. Based on embodiment 4, it has two substrate circuit layers 1 and two substrate dielectric layers 2 disposed on the substrate body. The two substrate circuit layers 1 are respectively an upper substrate circuit layer and a lower substrate circuit layer, and the two substrate dielectric layers 2 are respectively an upper substrate dielectric layer and a lower substrate dielectric layer. The upper substrate circuit layer, upper substrate dielectric layer, lower substrate circuit layer, and lower substrate dielectric layer are stacked sequentially from top to bottom. The axial direction of the substrate body refers to the direction shown in the accompanying drawings. Figure 1 and Figure 2 The height direction of the substrate body is shown; among the four power output branches, one end of the upper line 7 is connected to the uppermost substrate dielectric layer 2, and the other end of the line 7 is connected to the upper substrate dielectric layer, the lower substrate circuit layer and the lower substrate dielectric layer in sequence, and is electrically connected to the corresponding power protection component 5.

[0046] Preferably, in this embodiment, the upper end face of the circuit buried layer 3 is bonded to the lower end face of the bottom substrate dielectric layer 2 by adhesive.

[0047] It should be noted that in this invention, there are multiple substrate circuit layers 1 and substrate dielectric layers 2 on the substrate body. The number of these layers can be 2, 3, 4, 5, 6, 7, 8, 9, 10, or even more. The substrate circuit layers 1 and substrate dielectric layers 2 are stacked in a spaced manner from top to bottom, with each stacked layer corresponding to one substrate circuit layer 1 or substrate dielectric layer 2. One end of the upper line 7 in each power output branch is connected to the topmost substrate circuit layer 1, and the other end passes through the substrate dielectric layer 2 below the topmost substrate circuit layer 1 and the substrate circuit layer 1 from top to bottom and is connected to the power protection component 5.

[0048] This embodiment provides a method for assembling a fault-tolerant packaging substrate, which includes the following steps:

[0049] 1) Arrange the circuit 7 on the substrate body, and set the number of buried holes corresponding to the circuit 7 on the circuit buried layer 3. The power protection component 5 and the connecting plate 4 are buried in the buried hole from top to bottom along the axial direction of the buried hole, and the upper end face of the power protection component 5 extends to the top of the buried hole, so that the lower end face of the power protection component 5 is in close contact with the upper end face of the connecting plate 4, and the lower end face of the connecting plate 4 is on the same horizontal plane as the lower end face of the circuit buried layer 3 and the bottom end face of the buried hole.

[0050] 2) Solder the line 7 on the same power output branch to the upper end face of the power protection component 5, and at the same time bond the lower end face of the bottom substrate dielectric layer 2 to the upper end face of the circuit embedded layer 3 with adhesive.

[0051] 3) Weld pin 6 to the lower end face of connecting plate 4.

[0052] Example 6

[0053] See Figure 3 This embodiment is a semiconductor device, which includes a chip 8 and a packaging substrate of any one of embodiments 1-5. The chip 8 is electrically connected to the packaging substrate through a line 7 on the packaging substrate.

[0054] Preferably, in this embodiment, the lower surface of chip 8 is welded to the upper surface of the packaging substrate.

[0055] In addition to the aforementioned thin-film surface mount fuse or square tube surface mount fuse, the power protection component 5 of this invention can also be a resistor fuse or a self-resetting fuse, or other electrical components that are easily melted by high temperatures. Its function is to promptly melt the path between the pin 6 and the line 7 when the current on the pin 6 or the line 7 exceeds a preset current, thereby protecting the normally functioning line 7 on the substrate. In this invention, the position of the substrate circuit layer 1 corresponding to the line 7 on each power output branch is also specifically adjusted and set according to the specific chip function requirements. The number of buried holes corresponds to the number of power output branches. In addition to metal solder balls, the pin 6 can also be other connecting lines. In addition to copper plates, the connecting pad 4 can also be gold plates, silver plates, iron plates, or other conductive disc-shaped structures.

[0056] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fault-tolerant packaging substrate, characterized in that, The packaging substrate is used to package the chip (8). The packaging substrate includes a substrate body. The substrate body is provided with a line (7) and a power protection device (5). The line (7) is used to electrically connect with the chip (8). The line (7) is connected to the pin (6) through the power protection device (5). The power protection device (5) can melt the circuit in time when a short circuit occurs between the line (7) and the pin (6), disconnect the path between the pin (6) and the line (7), and protect the circuit. The substrate body is also provided with a connecting disk (4), and the power protection component (5) is connected to the pin (6) through the connecting disk (4). The connecting disk (4) increases the connection area at the connection between the power protection component (5) and the pin (6). The circuit (7), power protection component (5), connecting plate (4), and pin (6) constitute the power output branch of the chip. There are multiple power output branches, which are connected in parallel on the substrate. The power protection component can melt in time when one of the power output branches fails or when the pins and circuits in two adjacent power output branches are incorrectly connected or short-circuited, thus disconnecting the power output branch and protecting the other power output branches that can work normally.

2. The fault-tolerant packaging substrate as described in claim 1, characterized in that, The connecting plate (4) is a copper plate.

3. The fault-tolerant packaging substrate as described in claim 2, characterized in that, The bottom of the substrate body is provided with a circuit embedding layer (3), and the power protection component (5) and the connecting plate (4) are both embedded in the circuit embedding layer (3).

4. A fault-tolerant packaging substrate as described in claim 3, characterized in that, The connecting plate (4) is embedded in the circuit embedding layer (3), and the power protection component (5) is partially embedded in the circuit embedding layer (3) and located on the connecting plate (4), and is electrically connected to the connecting plate (4).

5. A fault-tolerant packaging substrate as described in claim 4, characterized in that, The substrate body includes a multilayer substrate circuit layer (1) and a multilayer substrate dielectric layer (2), wherein the substrate circuit layer (1) and the substrate dielectric layer (2) are stacked in a spaced manner from top to bottom. One end of the line (7) is connected to the topmost substrate circuit layer (1), and the other end passes through the substrate dielectric layer (2) and the substrate circuit layer (1) below the topmost substrate circuit layer (1) and is electrically connected to the power protection component (5).

6. A fault-tolerant packaging substrate as described in claim 5, characterized in that, The connecting plate (4) is electrically connected to the pin (6).

7. A fault-tolerant packaging substrate as described in any one of claims 1-6, characterized in that, The power protection component (5) is a thin-film surface mount fuse or a square tube surface mount fuse.

8. A semiconductor device, characterized in that, It includes a chip (8) and a packaging substrate as described in any one of claims 1-6, wherein the packaging substrate is electrically connected to the chip (8) via a line (7).

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