Display substrate, preparation method thereof, and display device

Abstract

The present disclosure provides a display substrate, a preparation method thereof, and a display device. The display substrate includes a display area and a border area. The border area includes a first circuit area, a routing area, and a second circuit area. The border area includes a border structure layer and a first planarization layer disposed on a substrate. The border structure layer of the first circuit area includes a first gate driving circuit. The border structure layer of the second circuit area includes a second gate driving circuit. The border structure layer of the routing area includes at least one output signal line, and the output signal line extends in a direction towards the display area. At least one exhaust groove is provided on the first planarization layer, and a positive projection of the exhaust groove on the substrate does not overlap a positive projection of the output signal line on the substrate. By setting that the positive projection of the exhaust groove on the substrate does not overlap the positive projection of the output signal line on the substrate, the present disclosure ensures the covering effect of the first planarization layer on the signal line, and effectively avoids defects such as short circuit or signal crosstalk.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technologies, and particularly to a display substrate, a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, lightness, flexibility, and low cost. With the continuous development of display technologies, display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFT) have become the mainstream products in the current display field.

[0003] It has been found by the inventors of the present application that there are problems such as short circuits or signal crosstalk in existing display devices. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of the claims.

[0005] The technical problem to be solved by the exemplary embodiments of the present disclosure is to provide a display substrate, a preparation method thereof, and a display device to solve the problems such as short circuits or signal crosstalk in existing display devices.

[0006] The present disclosure provides a display substrate, including a display area and a border area located on at least one side of the display area. The border area includes a first circuit area, a routing area, and a second circuit area arranged in sequence along the direction away from the display area. In a plane perpendicular to the display substrate, the border area includes a border structure layer disposed on a substrate and a first flat layer disposed on a side of the border structure layer away from the substrate. The border structure layer of the first circuit area includes a first gate driving circuit, the border structure layer of the second circuit area includes a second gate driving circuit, the border structure layer of the routing area includes at least one output signal line, and the output signal line extends in the direction of the display area. At least one exhaust groove is provided on the first flat layer, and a positive projection of the exhaust groove on the substrate does not overlap with a positive projection of the output signal line on the substrate.

[0007] In an exemplary embodiment, the exhaust groove is disposed in the routing area.

[0008] In an exemplary embodiment, the border structure layer of the routing area includes a plurality of output signal lines, the plurality of output signal lines are arranged at intervals along a direction parallel to the edge of the display area, and at least one exhaust groove is provided between adjacent output signal lines.

[0009] In an exemplary embodiment, a plurality of exhaust grooves are provided on the first flat layer, and the plurality of exhaust grooves are arranged at intervals along a direction parallel to the edge of the display area.

[0010] In an exemplary embodiment, along the direction away from the display area, the exhaust groove has a first width; the distance between the edge of the exhaust groove on the positive projection of the substrate near the output signal line and the edge of the output signal line on the positive projection of the substrate near the exhaust groove is greater than or equal to 20% of the first width.

[0011] In an exemplary embodiment, the distance between the edge of the exhaust groove on the positive projection of the substrate near the output signal line and the edge of the output signal line on the positive projection of the substrate near the exhaust groove is greater than or equal to 2.0 μm.

[0012] In an exemplary embodiment, along the direction away from the display area, the exhaust groove has a first width, and the first width is 8.0 μm to 10.0 μm.

[0013] In an exemplary embodiment, the thickness of the first flat layer is 1.35 μm to 2.0 μm.

[0014] In an exemplary embodiment, the border structure layer of the routing area at least includes: a first gate metal layer provided on the substrate, an insulating layer provided on the side of the first gate metal layer away from the substrate, and a first source-drain metal layer provided on the side of the insulating layer away from the substrate, and the first gate metal layer includes the output signal lines.

[0015] In an exemplary embodiment, the first source-drain metal layer includes a first signal line and a second signal line, the first signal line and the second signal line are located in the routing area and extend along a direction parallel to the edge of the display area, the first signal line is located on the side of the routing area close to the second circuit area, the second signal line is located on the side of the first signal line away from the second circuit area, and the exhaust groove is provided between the first signal line and the second signal line.

[0016] In an exemplary embodiment, the positive projection of the exhaust groove on the substrate does not overlap with the positive projection of the first signal line on the substrate, and the positive projection of the exhaust groove on the substrate does not overlap with the positive projection of the second signal line on the substrate.

[0017] In an exemplary embodiment, along a direction away from the display area, the exhaust groove has a first width; the distance between the edge of the exhaust groove close to the first signal line and the edge of the first signal line close to the exhaust groove is greater than or equal to 40% of the first width; the distance between the edge of the exhaust groove close to the second signal line and the edge of the second signal line close to the exhaust groove is greater than or equal to 40% of the first width.

[0018] In an exemplary embodiment, the distance between the edge of the exhaust groove close to the first signal line and the edge of the first signal line close to the exhaust groove is greater than or equal to 4.0 μm; the distance between the edge of the exhaust groove close to the second signal line and the edge of the second signal line close to the exhaust groove is greater than or equal to 4.0 μm.

[0019] The present disclosure also provides a display device, including the aforementioned display substrate.

[0020] The present disclosure also provides a method for manufacturing a display substrate, the display substrate including a display area and a border area located on at least one side of the display area; the border area includes a first circuit area, a routing area, and a second circuit area sequentially arranged along a direction away from the display area; the manufacturing method includes:

[0021] Forming a border structure layer on a substrate; the border structure layer of the first circuit area includes a first gate driving circuit, the border structure layer of the second circuit area includes a second gate driving circuit, the border structure layer of the routing area includes at least one output signal line, and the output signal line extends in a direction towards the display area;

[0022] Forming a first planarization layer on the border structure layer; at least one exhaust groove is provided on the first planarization layer, and the orthographic projection of the exhaust groove on the substrate does not overlap with the orthographic projection of the output signal line on the substrate.

[0023] The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. By setting that the orthographic projection of the exhaust groove on the substrate does not overlap with the orthographic projection of the output signal line on the substrate, the coating effect of the first planarization layer on the signal line is ensured, and short circuits or signal crosstalk and other defects are effectively avoided.

[0024] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0025] The accompanying drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure.

[0026] Figure 1 It is a schematic structural diagram of a display device;

[0027] Figure 2 It is a schematic structural diagram of a display substrate;

[0028] Figure 3 It is a schematic plan view of a display area;

[0029] Figure 4 It is a schematic cross-sectional view of a display area;

[0030] Figure 5 It is a schematic equivalent circuit diagram of a pixel driving circuit;

[0031] Figure 6 It is a timing diagram of the operation of a pixel driving circuit;

[0032] Figure 7 It is a schematic plan view of the border area of a display substrate;

[0033] Figure 8 It is a schematic plan view of the border area of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 9 It is a schematic diagram after forming the border structure layer pattern according to an exemplary embodiment of the present disclosure;

[0035] Figures 10 to 12 It is a schematic diagram after forming the first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0036] Figure 13 It is a schematic diagram after forming the connection electrode pattern according to an exemplary embodiment of the present disclosure;

[0037] Figure 14 It is a schematic cross-sectional view of an exhaust groove in a display substrate.

[0038] Explanation of reference numerals:

[0039] 10 - Substrate; 11 - First insulating layer; 12 - Second insulating layer;

[0040] 13 - Third insulating layer; 14 - Fourth insulating layer; 15 - First planarization layer;

[0041] 21 - First output signal line; 23 - Second output signal line; 31 - First signal line;

[0042] 32 - Second signal line; 33 - Third signal line; 34 - Fourth signal line;

[0043] 40 - Exhaust groove; 50 - Connecting electrode; 100 - Display area;

[0044] 102 - Driving circuit layer; 103 - Light-emitting structure layer; 104 - Encapsulation structure layer;

[0045] 200 - Border area; 210 - First circuit area; 211 - First shift register;

[0046] 220 - Lead area; 230 - Second circuit area; 231 - Second shift register;

[0047] 240 - Isolation dam area; 250 - Crack dam area; 260 - Cutting area;

[0048] 300 - Bonding area; 301 - Anode; 302 - Pixel definition layer;

[0049] 303 - Organic light-emitting layer; 304 - Cathode; 401 - First encapsulation layer;

[0050] 402 - Second encapsulation layer; 403 - Third encapsulation layer. Detailed implementation manners

[0051] To make the objectives, technical solutions, and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. Those of ordinary skill in the art can easily understand the fact that the manners and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0052] The drawing ratios in the present disclosure can be used as a reference in actual processes, but are not limited thereto. For example: the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are only schematic diagrams, and one manner of the present disclosure is not limited to the shapes or values shown in the drawings.

[0053] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity.

[0054] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of components is appropriately changed according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0055] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0056] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0057] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged with each other, and the "source terminal" and "drain terminal" can be interchanged with each other.

[0058] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0059] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes a state where the angle is more than 85° and less than 95°.

[0060] In this specification, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0061] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, and there can be chamfers, arc edges, and deformations, etc.

[0062] "About" in this disclosure means not strictly defining the boundary and allowing values within the process and measurement error ranges.

[0063] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data driver may sample the gray value using a clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in such a way that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where o may be a natural number.

[0064] Figure 2 is a schematic structural diagram of a display substrate. As Figure 2As shown, in an exemplary embodiment, the display substrate may include a display area 100 and a border area 200 located on at least one side of the display area 100. The display area 100 may include a plurality of regularly arranged sub-pixels. The sub-pixels may include a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The border area 200 may include a gate driving circuit (Gate Driver on Array, abbreviated as GOA) that transmits scan signals and light-emitting signals to the pixel driving circuits of the plurality of sub-pixels.

[0065] In an exemplary embodiment, the display substrate may further include a bonding area 300. The bonding area 300 may be located on one side of the display area 100. The bonding area 200 may include a bonding circuit for connecting signal lines to an external driving device.

[0066] Figure 3 It is a schematic plan view of a display area. In an exemplary embodiment, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits first-color light, a second sub-pixel P2 that emits second-color light, and a third sub-pixel P3 that emits third-color light. At least one sub-pixel may include a pixel driving circuit and a light-emitting device. The pixel driving circuit may be connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel where it is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where it is located.

[0067] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond-shaped, pentagonal, or hexagonal. The three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or pyramid shape, etc. In an exemplary embodiment, at least one pixel unit P may include four sub-pixels, which is not limited in the present disclosure.

[0068] Figure 4 It is a schematic cross-sectional view of a display area, showing the cross-sectional structures of three sub-pixels in the display area. As Figure 4As shown, in a plane perpendicular to the display substrate, the display area may include a driving circuit layer 102 disposed on a substrate 10, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate, and a packaging structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate. In some possible implementation manners, the display substrate may include other film layers, which are not limited in this disclosure.

[0069] In an exemplary embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of signal lines and a pixel driving circuit. The pixel driving circuit may include a plurality of transistors and a storage capacitor. Figure 4 Only one transistor 102A and one storage capacitor 102B are taken as examples for illustration. The light-emitting structure layer 103 of each sub-pixel may include a plurality of film layers constituting a light-emitting device. The plurality of film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 may be connected to the drain electrode of the transistor 102A through a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits corresponding color light under the drive of the anode 301 and the cathode 304. The packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403. The first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials, and the second packaging layer 402 may be made of organic materials. The second packaging layer 402 is disposed between the first packaging layer 401 and the third packaging layer 403 to form a stacked structure of inorganic material / organic material / inorganic material, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0070] In an exemplary embodiment, the organic light-emitting layer 303 may include a light-emitting layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0071] In an exemplary embodiment, the hole injection layer, the hole transport layer, and the electron blocking layer of all sub-pixels in the display area may be a common layer connected together, and the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0072] Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. AsFigure 5 As shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and one storage capacitor C. The pixel driving circuit is respectively connected to seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS).

[0073] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. Among them, the first node N1 is respectively connected to a first pole of a third transistor T3, a second pole of a fourth transistor T4, and a second pole of a fifth transistor T5. The second node N2 is respectively connected to a second pole of a first transistor, a first pole of a second transistor T2, a control pole of the third transistor T3, and a second end of the storage capacitor C. The third node N3 is respectively connected to a second pole of the second transistor T2, a second pole of the third transistor T3, and a first pole of a sixth transistor T6.

[0074] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power supply line VDD, and a second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control pole of the third transistor T3.

[0075] A control pole of the first transistor T1 is connected to the second scan signal line S2. A first pole of the first transistor T1 is connected to the initial signal line INIT. A second pole of the first transistor is connected to the second node N2. When a conductive level scan signal is applied to the second scan signal line S2, the first transistor T1 transfers an initial voltage to the control pole of the third transistor T3 to initialize the charge amount at the control pole of the third transistor T3.

[0076] A control pole of the second transistor T2 is connected to the first scan signal line S1. A first pole of the second transistor T2 is connected to the second node N2. A second pole of the second transistor T2 is connected to the third node N3. When a conductive level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control pole and the second pole of the third transistor T3.

[0077] A control pole of the third transistor T3 is connected to the second node N2, that is, the control pole of the third transistor T3 is connected to the second end of the storage capacitor C. A first pole of the third transistor T3 is connected to the first node N1. A second pole of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control pole and its first pole.

[0078] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1. The first electrode of the fourth transistor T4 is connected to the data signal line D. The second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D into the pixel driving circuit.

[0079] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E. The first electrode of the fifth transistor T5 is connected to the first power supply line VDD. The second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E. The first electrode of the sixth transistor T6 is connected to the third node N3. The second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0080] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1. The first electrode of the seventh transistor T7 is connected to the initial signal line INIT. The second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transfers an initial voltage to the first electrode of the light-emitting device to initialize the electric charge accumulated in the first electrode of the light-emitting device or to release the electric charge accumulated in the first electrode of the light-emitting device.

[0081] In an exemplary embodiment, the light-emitting device may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0082] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n - 1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and achieve a narrow border of the display panel.

[0083] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0084] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may employ low-temperature polysilicon thin-film transistors, or may employ oxide thin-film transistors, or may employ low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on a display substrate to form a low-temperature polycrystalline oxide (abbreviated as LTPO) display substrate can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve the display quality.

[0085] Figure 6 is a timing diagram of the operation of a pixel driving circuit. The following is through Figure 5 the operation process of the exemplary pixel driving circuit to illustrate the exemplary embodiments of the present disclosure. Figure 5 The pixel driving circuit in includes 7 transistors (the first transistor T1 to the sixth transistor T7) and 1 storage capacitor C, and all 7 transistors are P-type transistors.

[0086] In an exemplary embodiment, taking an OLED as an example, the operation process of the pixel driving circuit may include:

[0087] The first stage A1, called the reset stage, the signal of the second scan signal line S2 is a low-level signal, and the signals of the first scan signal line S1 and the emission signal line E are high-level signals. The signal of the second scan signal line S2 being a low-level signal causes the first transistor T1 to conduct, and the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scan signal line S1 and the emission signal line E being high-level signals cause the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 to be turned off, and the OLED does not emit light in this stage.

[0088] The second stage A2, known as the data writing stage or the threshold compensation stage, has the signal of the first scan signal line S1 being a low-level signal, the signals of the second scan signal line S2 and the light-emitting signal line E being high-level signals, and the data signal line D outputting a data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal of the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The conduction of the seventh transistor T7 provides the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializes (resets) the first electrode of the OLED, clears the pre-stored voltage inside it, completes the initialization, and ensures that the OLED does not emit light. The high-level signal of the second scan signal line S2 turns off the first transistor T1. The high-level signal of the light-emitting signal line E turns off the fifth transistor T5 and the sixth transistor T6.

[0089] The third stage A3, known as the light-emitting stage, has the signal of the light-emitting signal line E being a low-level signal, and the signals of the first scan signal line S1 and the second scan signal line S2 being high-level signals. The low-level signal of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to drive the OLED to emit light.

[0090] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0091] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * [(Vdd - Vd] 2

[0092] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0093] Figure 7 is a schematic plan view of a border area of a display substrate, and is Figure 2 an enlarged view of area C in Figure 7 As shown, in an exemplary embodiment, in a plane parallel to the display substrate, the border area 200 may include a first circuit area 210, a routing area 220, a second circuit area 230, an isolation area 240, a crack dam area 250, and a cutting area 260, which are sequentially arranged along a direction away from the display area 100.

[0094] In an exemplary embodiment, the first circuit area 210 may include a first gate driving circuit, and the first gate driving circuit is configured to output a first driving signal to the display area 100. The second circuit area 230 may include a second gate driving circuit, and the second gate driving circuit is configured to output a second driving signal to the display area 100. The routing area 230 may include a plurality of signal lines, and the plurality of signal lines are configured to output control signals to the first gate driving circuit and the second gate driving circuit.

[0095] In an exemplary embodiment, the first driving signal may be a scanning signal, and the second driving signal may be a light emitting signal. Alternatively, the first driving signal may be a light emitting signal, and the second driving signal may be a scanning signal.

[0096] In an exemplary embodiment, the isolation area 240 may include a power supply line, a first isolation dam, and a second isolation dam. The power supply line may extend along a direction parallel to the edge of the display area, and the power supply line is configured to output a low level signal (VSS) to a plurality of pixel driving circuits in the display area. The first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display area, and the first isolation dam and the second isolation dam are configured to block the organic layer in the encapsulation layer and prevent moisture from entering the display area. The crack dam area 250 may include a plurality of cracks, and the plurality of cracks are configured to reduce the stress on the display area during the cutting process, intercept the propagation of cracks in the direction of the display area, and avoid affecting the film layer structure of the display area. The cutting area 260 may include at least one cutting groove, and the cutting groove is configured to perform cutting along the cutting groove by a cutting device after all the film layers of the display substrate are prepared.

[0097] Figure 8 This is a schematic plan view of a border area of a display substrate according to an exemplary embodiment of the present disclosure. As Figure 8As shown, in an exemplary embodiment, the border area 200 may include a first circuit area 210, a routing area 220, and a second circuit area 230 sequentially arranged in a direction away from the display area. The first circuit area 210 may include a first gate driving circuit, the second circuit area 230 may include a second gate driving circuit, the routing area 230 may include a plurality of signal lines, the first gate driving circuit is configured to output a first driving signal to the display area, the second gate driving circuit is configured to output a second driving signal to the display area, and the plurality of signal lines are configured to output control signals to the first gate driving circuit and the second gate driving circuit.

[0098] In an exemplary embodiment, the first gate driving circuit in the first circuit area 210 may include a plurality of cascaded first shift registers 211. The plurality of first shift registers 211 may be sequentially arranged along the second direction D2. The first shift register 211 may include at least one first output signal line 21, and the first output signal line 21 may extend into the display area along the first direction D1.

[0099] In an exemplary embodiment, the second gate driving circuit in the second circuit area 230 may include a plurality of cascaded second shift registers 231. The plurality of second shift registers 231 may be sequentially arranged along the second direction D2. The second shift register 231 may include at least one second output signal line 23, and the second output signal line 23 may extend into the display area along the first direction D1.

[0100] In an exemplary embodiment, the first direction D1 and the second direction D2 intersect. The first direction D1 may be a direction approaching the display area, and the second direction D2 may be a direction parallel to the edge of the display area. The edge of the display area is the edge of the display area adjacent to the border area.

[0101] In an exemplary embodiment, after the first output signal line 21 extends into the display area, it may be connected to a scan signal line in the display area. The first gate driving circuit outputs a scan signal to the display area. After the second output signal line 23 extends into the display area, it may be connected to a light-emitting signal line in the display area. The second gate driving circuit outputs a light-emitting signal to the display area. Alternatively, after the first output signal line 21 extends into the display area, it may be connected to a light-emitting signal line in the display area. After the second output signal line 23 extends into the display area, it may be connected to a scan signal line in the display area.

[0102] In an exemplary embodiment, a cascaded shift register means that shift registers adjacent to each other in the second direction D2 are electrically connected. For example, the output terminal of one shift register is connected to the input terminal of another shift register adjacent to it in the second direction D2. Another example is that the input terminal of one shift register is connected to the output terminal of another shift register adjacent to it in the second direction D2.

[0103] In an exemplary embodiment, the wiring area 230 may include a first signal line 31, a second signal line 32, a third signal line 33, and a fourth signal line 34. Each signal line may extend along the second direction D2. The first signal line 31, the second signal line 32, the third signal line 33, and the fourth signal line 34 may be arranged in sequence along the first direction D1. That is, the first signal line 31 may be located on the side of the wiring area 230 close to the second circuit area 230, the fourth signal line 34 may be located on the side of the wiring area 230 close to the first circuit area 210, the second signal line 32 and the third signal line 33 may be located between the first signal line 31 and the fourth signal line 34, the second signal line 32 may be located on the side of the first signal line 31 far from the second circuit area 230, and the third signal line 33 may be located on the side of the second signal line 32 far from the second circuit area 230.

[0104] In an exemplary embodiment, the first shift register 211 may include a plurality of first transistors and a first capacitor, and the second shift register 231 may include a plurality of second transistors and a second capacitor. The present disclosure does not limit this here.

[0105] In an exemplary embodiment, in a plane perpendicular to the display substrate, the border area may include a substrate, a border structure layer provided on the substrate, and a first planar layer provided on the side of the border structure layer away from the substrate. In an exemplary embodiment, the border structure layer of the first circuit area 210 may include a first gate driving circuit, the border structure layer of the second circuit area 230 may include a second gate driving circuit, and the border structure layer of the wiring area 220 may include at least one second output signal line 23. The first end of the second output signal line 23 is connected to the second gate driving circuit, and the second end of the second output signal line 23 extends in the direction of the display area (the first direction D1).

[0106] In an exemplary embodiment, at least one exhaust groove 40 may be provided on the first planar layer, and the orthographic projection of the at least one exhaust groove 40 on the substrate does not overlap with the orthographic projection of the second output signal line 23 on the substrate.

[0107] In an exemplary embodiment, the exhaust groove 40 may be provided in the wiring area 220.

[0108] In an exemplary embodiment, the border structure layer of the routing area 220 may include a plurality of second output signal lines 23. The first ends of the plurality of second output signal lines 23 are all connected to the second gate driving circuit, and the second ends of the plurality of second output signal lines 23 all extend in the direction of the display area (the first direction D1). The exhaust groove 40 may be disposed between adjacent second output signal lines 23.

[0109] In an exemplary embodiment, a plurality of exhaust grooves 40 may be disposed on the first flat layer. The plurality of exhaust grooves 40 may be disposed in the routing area 220. The plurality of exhaust grooves 40 may be spaced apart along a direction parallel to the edge of the display area (the second direction D2). The plurality of exhaust grooves 40 are respectively disposed between adjacent second output signal lines 23, and the orthographic projection of the plurality of exhaust grooves 40 on the substrate does not overlap with the orthographic projection of the plurality of second output signal lines 23 on the substrate.

[0110] In an exemplary embodiment, along the direction away from the display area (the opposite direction of the first direction D1), the exhaust groove 40 has a first width, and the first width may be 8.0 μm to 10.0 μm.

[0111] In an exemplary embodiment, the border structure layer of the routing area 220 may at least include a first signal line 31 and a second signal line 32. The first signal line 31 and the second signal line 32 may extend along a direction parallel to the edge of the display area (the second direction D2) and be spaced apart in the direction of the display area (the first direction D1). The first signal line 31 is located on the side of the routing area 220 close to the second circuit area 230, and the second signal line 32 is located on the side of the first signal line 31 away from the second circuit area 230.

[0112] In an exemplary embodiment, the exhaust groove 40 may be disposed between the first signal line 31 and the second signal line 32.

[0113] In an exemplary embodiment, the orthographic projection of the exhaust groove 40 on the substrate does not overlap with the orthographic projection of the first signal line 31 on the substrate.

[0114] In an exemplary embodiment, the orthographic projection of the exhaust groove 40 on the substrate does not overlap with the orthographic projection of the second signal line 32 on the substrate.

[0115] In an exemplary embodiment, the border structure layer of the first circuit region 210 and the second circuit region 230 may include: a first insulating layer disposed on a substrate, a semiconductor layer disposed on a side of the first insulating layer away from the substrate, a second insulating layer disposed on a side of the semiconductor layer away from the substrate, a first conductive layer (first gate metal layer) disposed on a side of the second insulating layer away from the substrate, a third insulating layer disposed on a side of the first conductive layer away from the substrate, a second conductive layer (second gate metal layer) disposed on a side of the third insulating layer away from the substrate, a fourth insulating layer disposed on a side of the second conductive layer away from the substrate, and a third conductive layer (first source / drain metal layer) disposed on a side of the fourth insulating layer away from the substrate.

[0116] In an exemplary embodiment, the border structure layer of the routing region 220 may include: a first insulating layer and a second insulating layer disposed on a substrate, a first conductive layer (first gate metal layer) disposed on a side of the second insulating layer away from the substrate, a third insulating layer and a fourth insulating layer disposed on a side of the first conductive layer away from the substrate, and a third conductive layer (first source / drain metal layer) disposed on a side of the fourth insulating layer away from the substrate.

[0117] In an exemplary embodiment, the second output signal line 23 may be located in the first conductive layer (first gate metal layer), and the first signal line 31 and the second signal line 32 may be located in the third conductive layer (first source / drain metal layer).

[0118] An exemplary illustration is given below through the manufacturing process of a display substrate. The "patterning process" as mentioned in the present disclosure, for metal materials, inorganic materials or transparent conductive materials, includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out by any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out by any one of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by means of deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed in the same layer" as mentioned in the present disclosure means that A and B are simultaneously formed by the same patterning process. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0119] In an exemplary embodiment, the first circuit region 210 may include a plurality of cascaded first shift registers. The first shift register may include a plurality of first transistors and a first capacitor. The second gate driving circuit in the second circuit region 230 may include a plurality of cascaded second shift registers. The second shift register may include a plurality of second transistors and a second capacitor. Taking one first transistor and one first capacitor in the first circuit region 210 and one second transistor and one second capacitor in the second circuit region 230 as an example, the exemplary embodiment of the present disclosure shows that the preparation process of the substrate may include the following operations.

[0120] (1) Form a border structure layer pattern on the substrate, such as Figure 9 shown. In an exemplary embodiment, forming a border structure layer pattern on the substrate may include:

[0121] Deposit a first insulating film and a semiconductor film on the substrate in sequence, pattern the semiconductor film through a patterning process to form a first insulating layer 11 provided on the substrate and a semiconductor layer pattern provided on the first insulating layer 11. The semiconductor layer pattern may at least include a first active layer located in the first circuit region 210 and a second active layer located in the second circuit region 230.

[0122] Subsequently, deposit a second insulating film and a first conductive film in sequence, pattern the first conductive film through a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern and a first conductive layer pattern provided on the second insulating layer 12. The first conductive layer pattern may at least include a first gate electrode and a first electrode plate located in the first circuit region 210, a second gate electrode and a second electrode plate located in the second circuit region 230, and a second output signal line 23 located in the routing region. The second output signal line 23 may extend in the direction of the display region. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal layer (GATE1).

[0123] Subsequently, deposit a third insulating film and a second conductive film in sequence, pattern the second conductive film through a patterning process to form a third insulating layer 13 covering the first conductive layer and a second conductive layer pattern provided on the third insulating layer 13. The second conductive layer pattern may at least include a third electrode plate located in the first circuit region 210 and a fourth electrode plate located in the second circuit region 230. The orthographic projection of the third electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the orthographic projection of the fourth electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal layer (GATE2).

[0124] Subsequently, a fourth insulating film is deposited and patterned through a patterning process to form a fourth insulating layer 14 pattern covering the second conductive layer pattern. A plurality of active vias are formed on the fourth insulating layer 14. The plurality of active vias may include: at least two first active vias located in the first circuit region 210 and at least two second active vias located in the second circuit region 230. At least two of the first active vias may expose both ends of the first active layer, and at least two of the second active vias may expose both ends of the second active layer.

[0125] In an exemplary embodiment, in this patterning process, a plurality of spaced-apart cracks may be formed in the crack dam region, and a groove may be formed in the cutting region. The second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 in the cracks are removed to expose the surface of the first insulating layer 11, and the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 in the groove are removed to expose the surface of the substrate 10.

[0126] In an exemplary embodiment, two patterning processes may be used to form the cracks in the crack dam region and the groove in the cutting region. For example, first, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 are etched through a first mask (Etch Bending A MASK, abbreviated as EBA MASK) to form a first groove in the cutting region, a plurality of cracks in the crack dam region, and a plurality of active vias in the first circuit region and the second circuit region. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 in the first groove and the cracks are etched away to expose the surface of the first insulating layer 11. Then, the first insulating layer 11 in the first groove in the cutting region is etched through a second mask (Etch Bending B MASK, abbreviated as EBB MASK) to form a second groove on the first insulating layer 11. The first insulating layer in the second groove is etched away to expose the surface of the substrate. In the cutting region, the first groove exposes the second groove, forming a stepped groove structure. In the crack dam region, the plurality of spaced-apart cracks expose the surface of the first insulating layer, forming a concavo-convex crack dam structure. The EBA MASK and EBB MASK processes are patterning processes for grooving the bending region of the bonding region to reduce the thickness of the bending region. In an exemplary embodiment, forming a concavo-convex crack dam structure in the crack dam region can prevent the film layer structure in the display region and the circuit region from being affected during the cutting process. The plurality of spaced-apart cracks can not only reduce the stress on the display region and the circuit region but also intercept the propagation of cracks in the direction of the display region and the circuit region.

[0127] Subsequently, a third conductive thin film is deposited, and the third conductive thin film is patterned through a patterning process to form a third conductive layer pattern on the fourth insulating layer 14. The third conductive layer pattern may at least include: a first source electrode and a first drain electrode located in the first circuit region 210, a second source electrode and a second drain electrode located in the second circuit region 230, and a plurality of signal lines located in the routing region. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal layer (SD1).

[0128] In an exemplary embodiment, the first source electrode and the first drain electrode located in the first circuit region 210 are respectively connected to the first active layer through first active vias, and the second source electrode and the second drain electrode located in the second circuit region 230 are respectively connected to the second active layer through second active vias.

[0129] In an exemplary embodiment, the plurality of signal lines may include a first signal line 31, a second signal line 32, a third signal line 33, and a fourth signal line 34. Each signal line may extend along a direction parallel to the edge of the display region. The first signal line 31, the second signal line 32, the third signal line 33, and the fourth signal line 34 may be sequentially arranged along a direction close to the first circuit region 210. That is, the first signal line 31 may be located on one side of the routing region 230 close to the second circuit region 230, the fourth signal line 34 may be located on one side of the routing region 230 close to the first circuit region 210, the second signal line 32 and the third signal line 33 may be located between the first signal line 31 and the fourth signal line 34, the second signal line 32 may be located on one side of the first signal line 31 away from the second circuit region 230, and the third signal line 33 may be located on one side of the second signal line 32 away from the second circuit region 230.

[0130] So far, the border structure layer pattern is prepared. The border structure layer may include a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a first conductive layer, a third insulating layer 13, a second conductive layer, a fourth insulating layer 14, and a third conductive layer stacked on the substrate 10, as Figure 9 shown.

[0131] In an exemplary embodiment, the border structure layer of the first circuit region 210 may include a plurality of first transistors and a first capacitor that constitute a first shift register, Figure 9 Only one first transistor 210A and one first capacitor 210B are taken as examples herein. The first transistor 210A may include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, and the first capacitor 210B may include a first electrode plate and a third electrode plate.

[0132] In an exemplary embodiment, the border structure layer of the second circuit region 230 may include a plurality of second transistors and a second capacitor that constitute a second shift register, Figure 9Only a second transistor 230A and a second capacitor 230B are taken as examples herein. The second transistor 230A may include a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, and the second capacitor 230B may include a second electrode plate and a fourth electrode plate. In an exemplary embodiment, the first transistor 210A and the second transistor 230A may be switching transistors, and the switching transistors may be thin film transistors (TFTs).

[0133] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer and the third insulating layer may be referred to as a (GI) layer, and the fourth insulating layer may be referred to as an interlayer dielectric (ILD) layer. The first conductive layer, the second conductive layer, and the third conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc. The semiconductor layer may be made of various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0134] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. In an exemplary embodiment, the rigid substrate may be made of materials such as glass or quartz, and the flexible substrate may be made of materials such as polyimide (PI). The flexible substrate may be a single-layer structure, or a laminated structure composed of an inorganic material layer and a flexible material layer, which is not limited herein in the present disclosure.

[0135] (2) Form a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: coating a first planarization thin film on the substrate on which the foregoing pattern is formed, patterning the first planarization thin film through a patterning process to form a first planarization layer 15 pattern covering the third conductive layer pattern, and at least one exhaust groove 40 is formed on the first planarization layer 15, as Figure 10 、 Figure 11 and Figure 12 shown, Figure 10 is Figure 8 a schematic diagram of the A-A direction in Figure 11 and Figure 8Schematic diagram in the B-B direction in Figure 12 is Figure 8 Schematic diagram in the C-C direction in

[0136] In an exemplary embodiment, the first flat layer 15 may be formed on the first circuit region 210, the wiring region 220, and the second circuit region 230. The first flat layer 15 in the first circuit region 210 may cover the first source electrode and the first drain electrode, the first flat layer 15 in the second circuit region 230 may cover the second source electrode and the second drain electrode, and the first flat layer 15 in the wiring region 220 may cover the first signal line 31, the second signal line 32, the third signal line 33, and the fourth signal line 34.

[0137] In an exemplary embodiment, at least one exhaust groove 40 is provided on the first flat layer 15 in the wiring region 220. The first flat thin film in the exhaust groove 40 is removed to expose the surface of the fourth insulating layer 14. The exhaust groove 40 is configured to exhaust the water vapor generated in the first flat layer patterning process, so as to avoid adverse effects such as pixel failure, metal bulge, or film layer peeling caused by the water vapor entering the display area, and improve the process quality.

[0138] In an exemplary embodiment, the first flat layer may be made of an organic material such as resin. The thickness of the first flat layer may be about 1.35 μm to 2.0 μm, and the thickness is the dimension in the third direction D3.

[0139] Such as Figure 10 shown, in an exemplary embodiment, in the first direction D1 (the direction approaching the display area), the exhaust groove 40 may be provided between the first signal line 31 and the second signal line 32, and the orthographic projection of the exhaust groove 40 on the substrate does not overlap with the orthographic projection of the first signal line 31 on the substrate, and the orthographic projection of the exhaust groove 40 on the substrate does not overlap with the orthographic projection of the second signal line 32 on the substrate.

[0140] In an exemplary embodiment, the first width L1 of the exhaust groove 40 may be about 8.0 μm to 10.0 μm, and the first width L1 is the dimension of the exhaust groove 40 in the first direction D1.

[0141] In an exemplary embodiment, the first flat layer 15 may completely cover the edges on both sides of the first signal line 31 and the second signal line 32 in the first direction D1.

[0142] In an exemplary embodiment, in the first direction D1, the first distance M1 between the edge of the exhaust groove 40 closer to the first signal line 31 and the edge of the first signal line 31 closer to the exhaust groove 40 may be greater than or equal to 4.0 μm, that is, the first flat layer 15 covers the edge of the first signal line 31 closer to the exhaust groove 40, and the covering width may be greater than or equal to 4.0 μm. The covering width is the dimension in the first direction D1. In an exemplary embodiment, in the first direction D1, the second distance M2 between the edge of the exhaust groove 40 closer to the second signal line 32 and the edge of the second signal line 32 closer to the exhaust groove 40 may be greater than or equal to 4.0 μm, that is, the first flat layer 15 covers the edge of the second signal line 32 closer to the exhaust groove 40, and the covering width may be greater than or equal to 4.0 μm. By setting the covering widths of the first flat layer 15 covering the edges of the first signal line and the second signal line to be greater than or equal to 4.0 μm, the present disclosure ensures the covering of the edges of the first signal line and the second signal line by the first flat layer, effectively avoiding film peeling and improving the process quality.

[0143] As Figure 11 shown, in an exemplary embodiment, in the second direction D2 (the direction parallel to the edge of the display area), the exhaust groove 40 may be disposed between adjacent second output signal lines 23, and the orthographic projection of the exhaust groove 40 on the substrate does not overlap with the orthographic projection of the second output signal line 23 on the substrate.

[0144] In an exemplary embodiment, the first flat layer 15 may completely cover the edges on both sides of the second output signal line 23 in the second direction D2.

[0145] In an exemplary embodiment, for the exhaust groove 40 and the second output signal line 23 adjacent in the second direction D2, the third distance M3 between the edge of the orthographic projection of the exhaust groove 40 closer to the second output signal line 23 and the edge of the orthographic projection of the second output signal line 23 closer to the exhaust groove 40 on the substrate may be greater than or equal to 2.0 μm, that is, the covering width of the first flat layer 15 on the edge of the second output signal line 23 closer to the exhaust groove 40 may be greater than or equal to 2.0 μm. The covering width is the dimension in the second direction D2. By setting the covering width of the first flat layer 15 on the edge of the second output signal line 23 closer to the exhaust groove 40 to be greater than or equal to 2.0 μm, the present disclosure not only avoids the reduction of the slope angle of the side wall of the exhaust groove due to the reflection of the exposure light by the second output signal line 23, but also ensures the covering of the second output signal line 23 by the first flat layer 15, effectively avoiding film peeling and improving the process quality.

[0146] As Figure 12As shown, in an exemplary embodiment, an exhaust groove 40 is not provided in the area where the second output signal line 23 is located. That is, the first flat layer 15 can completely cover the area where the second output signal line 23 is located, and the orthographic projection of the exhaust groove 40 on the substrate does not overlap with the orthographic projection of the second output signal line 23 on the substrate.

[0147] In an exemplary embodiment, a plurality of exhaust grooves 40 may be formed on the first flat layer 15 in the routing area 220. The plurality of exhaust grooves 40 may be spaced apart along a direction parallel to the edge of the display area, and the orthographic projection of the plurality of exhaust grooves 40 on the substrate does not overlap with the orthographic projection of the plurality of second output signal lines 23 on the substrate.

[0148] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the exhaust groove 40 may be rectangular, polygonal or elliptical. In a plane perpendicular to the display substrate, the cross-sectional shape of the exhaust groove 40 may be rectangular or trapezoidal, and the present disclosure does not limit this here.

[0149] (3) Forming a connection electrode pattern. In an exemplary embodiment, forming the connection electrode pattern may include: on the substrate on which the foregoing patterns are formed, first forming a fourth conductive layer on the first flat layer in the display area, then forming a second flat layer covering the fourth conductive layer in the display area, and subsequently depositing a fifth conductive thin film. The fifth conductive thin film is patterned through a patterning process to form a fifth conductive layer pattern. The fifth conductive layer may at least include an anode located in the display area and a connection electrode 50 located in the border area, as Figure 13 shown, Figure 13 is Figure 8 a schematic diagram in the C-C direction in

[0150] In an exemplary embodiment, the anode in the display area may be provided on the second flat layer, and the connection electrode 50 in the border area may be provided on the first flat layer 15. The connection electrode 50 is configured to connect the subsequently formed cathode to the power supply line in the isolation area.

[0151] In subsequent processes, the preparation of the display substrate may include: forming a pixel definition layer in the display area; forming an organic light-emitting layer in the display area; forming a cathode in the display area and the border area, and the cathode in the border area is lapped with the connection electrode in the border area; forming a packaging structure layer in the display area and the border area, etc., and the present disclosure does not limit this here.

[0152] Figure 14 is a schematic cross-sectional structure diagram of an overlapping area between an exhaust groove and an output signal line in a display substrate. As Figure 14As shown, in the display substrate of the existing structure, an exhaust groove 40 is provided in the border area, and the exhaust grooves 40 are continuously arranged along a direction parallel to the edge of the display area. Through research by the inventors of the present application, it is found that since the exhaust groove 40 and the second output signal line 23 have an overlapping area, there is a situation where the first planar layer 15 fails to cover the first signal line 31 and the second signal line 32, resulting in problems such as short circuit or signal crosstalk. Through further research by the inventors of the present application, it is found that in the patterning process of the exhaust groove 40, due to the reflection characteristic of the metal material of the second output signal line 23 on the exposure light, the exposure degree of the first planar thin film in the area where the second output signal line 23 is located is more sufficient than that in other areas. After developing to form the pattern of the exhaust groove 40, the film thickness of the first planar layer 15 on the side wall of the exhaust groove 40 in the area where the second output signal line 23 is located is thinner, and the slope angle of the side wall of the exhaust groove 40 is smaller, so that the covering effect of the first planar layer 15 on the first signal line 31 and the second signal line 32 decreases. Since the covering effect of the first planar layer 15 on the first signal line 31 and the second signal line 32 decreases, after the connection electrode 50 is formed subsequently, the distance between the connection electrode 50 and the first signal line 31 and the distance between the connection electrode 50 and the second signal line 32 are relatively close, resulting in problems such as short circuit or signal crosstalk.

[0153] Regarding the problem of short circuit or signal crosstalk and other defects caused by covering failure in the existing structure, although it can be solved by increasing the thickness of the first planar layer, increasing the thickness of the first planar layer will not only cause production capacity loss, but also be unfavorable for the thinning of the product. In addition, this problem can be solved by increasing the slope angle of the side wall of the exhaust groove, but increasing the slope angle not only increases the process difficulty, but also easily causes defects such as film layer peeling. In addition, this problem can be solved by increasing the covering width of the first planar layer on the first signal line and the second signal line, but increasing the covering width of the first planar layer on the first signal line and the second signal line will reduce the width of the exhaust groove. Not only the accuracy of the exposure equipment cannot be satisfied, resulting in residues in the exhaust groove and easily causing film layer peeling defects, but also the exhaust area is reduced, which is not conducive to the discharge of water vapor in the first planar layer and affects the display effect of the display area. [[ID=?]] [[ID=?]]

[0154] As can be seen from the structure and preparation process of the substrate shown in the exemplary embodiments of the present disclosure, in the exemplary embodiments of the present disclosure, exhaust grooves are arranged at intervals in the wiring area. The exhaust grooves are only arranged between adjacent second output signal lines, and the orthographic projection of the exhaust grooves on the substrate does not overlap with the orthographic projection of the second output signal lines on the substrate, that is, no exhaust grooves are arranged on the first flat layer in the area where the second output signal lines are located, ensuring a relatively thick film thickness of the first flat layer in the area where the second output signal lines are located, ensuring the coating effect of the first flat layer on the first signal line and the second signal line, increasing the distance between the connection electrode and the signal line, and effectively avoiding defects such as short circuit or signal crosstalk. Compared with the solution of increasing the thickness of the first flat layer, the thickness of the first flat layer in the solution of the present disclosure can be less than or equal to 2.0 μm, which neither causes production capacity loss nor is conducive to the thinning of the product. Compared with the solution of increasing the slope angle of the side wall of the exhaust groove, the solution of the present disclosure neither increases the process difficulty nor causes defects such as film layer peeling. Compared with the solution of increasing the coating width, the solution of the present disclosure does not reduce the width of the exhaust groove, effectively ensuring the exhaust area and the display effect of the display area.

[0155] In the present disclosure, the coating width of the first flat layer on the edge of the second output signal line close to the exhaust groove is set to be greater than or equal to 2.0 μm, which not only avoids the reduction of the slope angle of the side wall of the exhaust groove caused by the reflection of the exposure light by the second output signal line, but also ensures the coating of the first flat layer on the second output signal line, effectively avoiding film layer peeling and improving the process quality.

[0156] In the present disclosure, the coating widths of the first flat layer covering the edge of the first signal line and covering the edge of the second signal line are set to be greater than or equal to 4.0 μm, ensuring the coating of the first flat layer on the edges of the first signal line and the second signal line, effectively avoiding film layer peeling and improving the process quality.

[0157] In the exemplary embodiments of the present disclosure, exhaust grooves are arranged on the first flat layer, and the width of the exhaust grooves can be about 8.0 μm to 10.0 μm, effectively ensuring the exhaust area. The exhaust grooves can effectively discharge the water vapor generated by the flat layer during the process, avoiding defects such as pixel failure, metal bulge or film layer peeling caused by the water vapor entering the display area, improving the process quality, and ensuring the display effect of the display area.

[0158] In the exemplary embodiments of the present disclosure, by arranging exhaust grooves at intervals, the thickness of the first flat layer can be about 1.35 μm to 2.0 μm. Compared with the thickness of the first flat layer in the existing structure being greater than 2.1 μm, it neither causes production capacity loss nor is conducive to the thinning of the product.

[0159] Exemplary embodiments of the present disclosure show that the preparation process of the display substrate has good process compatibility, simple process implementation, easy to implement, high production efficiency, low production cost, and high yield rate.

[0160] The structure of the display substrate and its preparation process disclosed in the present disclosure are only an exemplary illustration. In the exemplary embodiments, the corresponding structure can be changed according to actual needs, and the patterning process can be added or reduced. The present disclosure does not make any limitations here.

[0161] Exemplary embodiments of the present disclosure also provide a method for preparing a display substrate. In the exemplary embodiments, the display substrate may include a display area and a border area located on at least one side of the display area; the border area may include a first circuit area, a routing area, and a second circuit area arranged in sequence along the direction away from the display area; the preparation method may include:

[0162] Forming a border structure layer on the substrate; the border structure layer of the first circuit area includes a first gate driving circuit, the border structure layer of the second circuit area includes a second gate driving circuit, the border structure layer of the routing area includes at least one output signal line, and the output signal line extends in the direction of the display area;

[0163] Forming a first planarization layer on the border structure layer; at least one exhaust groove is provided on the first planarization layer, and the orthographic projection of the exhaust groove on the substrate does not overlap with the orthographic projection of the output signal line on the substrate.

[0164] The present disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device may be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0165] Although the disclosed embodiments are as above, the above content is only an embodiment adopted for the convenience of understanding the present disclosure, and is not used to limit the present disclosure. Any person skilled in the art within the scope of the present disclosure can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of this application shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, It includes a display area and a border area located on at least one side of the display area. The border area includes a first circuit area, a routing area, and a second circuit area arranged in sequence along the direction away from the display area. In the plane perpendicular to the display substrate, the border area includes a border structure layer provided on a substrate and a first flat layer provided on the side of the border structure layer away from the substrate. The border structure layer of the first circuit area includes a first gate driving circuit, the border structure layer of the second circuit area includes a second gate driving circuit, and the border structure layer of the routing area includes at least one output signal line that extends in the direction towards the display area. At least one exhaust groove is provided on the first flat layer, and the orthographic projection of the exhaust groove on the substrate does not overlap with the orthographic projection of the output signal line on the substrate. The border structure layer of the routing area at least includes: a first gate metal layer provided on the substrate, an insulating layer provided on the side of the first gate metal layer away from the substrate, and a first source-drain metal layer provided on the side of the insulating layer away from the substrate. The first gate metal layer includes the output signal line. The first source-drain metal layer includes a first signal line and a second signal line. The first signal line and the second signal line are located in the routing area and extend along the direction parallel to the edge of the display area. The first signal line is located on the side of the routing area close to the second circuit area, and the second signal line is located on the side of the first signal line away from the second circuit area. The exhaust groove is provided between the first signal line and the second signal line.

2. The display substrate according to claim 1, wherein The exhaust groove is provided in the routing area.

3. The display substrate according to claim 1, wherein The border structure layer of the routing area includes multiple output signal lines that are arranged at intervals along the direction parallel to the edge of the display area, and at least one exhaust groove is provided between adjacent output signal lines.

4. The display substrate according to claim 1, wherein Multiple exhaust grooves are provided on the first flat layer, and the multiple exhaust grooves are arranged at intervals along the direction parallel to the edge of the display area.

5. The display substrate according to claim 1, wherein Along the direction away from the display area, the exhaust groove has a first width. The distance between the edge of the orthographic projection of the exhaust groove on the substrate close to the output signal line and the edge of the orthographic projection of the output signal line on the substrate close to the exhaust groove is greater than or equal to 20% of the first width.

6. The display substrate according to claim 1, wherein The distance between the edge of the orthographic projection of the exhaust groove on the substrate close to the output signal line and the edge of the orthographic projection of the output signal line on the substrate close to the exhaust groove is greater than or equal to 2.0 μm.

7. The display substrate according to claim 1, characterized in that Along the direction away from the display area, the exhaust groove has a first width, and the first width is 8.0 μm to 10.0 μm.

8. The display substrate according to claim 1, wherein The thickness of the first flat layer is 1.35 μm to 2.0 μm.

9. The display substrate according to any one of claims 1 to 8, characterized in that, The orthographic projection of the exhaust groove on the substrate does not overlap with the orthographic projection of the first signal line on the substrate, and the orthographic projection of the exhaust groove on the substrate does not overlap with the orthographic projection of the second signal line on the substrate.

10. The display substrate according to any one of claims 1 to 8, characterized in that, Along the direction away from the display area, the exhaust groove has a first width; the distance between the edge of the exhaust groove closer to the first signal line and the edge of the first signal line closer to the exhaust groove is greater than or equal to 40% of the first width; the distance between the edge of the exhaust groove closer to the second signal line and the edge of the second signal line closer to the exhaust groove is greater than or equal to 40% of the first width.

11. The display substrate according to any one of claims 1 to 8, characterized in that, The distance between the edge of the exhaust groove closer to the first signal line and the edge of the first signal line closer to the exhaust groove is greater than or equal to 4.0 μm; the distance between the edge of the exhaust groove closer to the second signal line and the edge of the second signal line closer to the exhaust groove is greater than or equal to 4.0 μm.

12. A display device, comprising the display substrate according to any one of claims 1 to 11.

13. A method for manufacturing a display substrate, the display substrate comprising a display area and a border area located on at least one side of the display area; the border area includes a first circuit area, a routing area, and a second circuit area arranged in sequence along the direction away from the display area; the manufacturing method includes: Forming a border structure layer on a substrate; The border structure layer of the first circuit area includes a first gate driving circuit, the border structure layer of the second circuit area includes a second gate driving circuit, the border structure layer of the routing area includes at least one output signal line extending in the direction towards the display area; the border structure layer of the routing area at least includes: a first gate metal layer provided on the substrate, an insulating layer provided on the side of the first gate metal layer away from the substrate, and a first source-drain metal layer provided on the side of the insulating layer away from the substrate, the first gate metal layer includes the output signal line; the first source-drain metal layer includes a first signal line and a second signal line, the first signal line and the second signal line are located in the routing area and extend along a direction parallel to the edge of the display area, the first signal line is located on the side of the routing area closer to the second circuit area, and the second signal line is located on the side of the first signal line away from the second circuit area; Forming a first planarization layer on the border structure layer; at least one exhaust groove is provided on the first planarization layer, the orthographic projection of the exhaust groove on the substrate does not overlap with the orthographic projection of the output signal line on the substrate, and the exhaust groove is provided between the first signal line and the second signal line.

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