New programmable chopping architecture for reducing offset in analog front ends

Abstract

A novel programmable chopping architecture for reducing offset in an analog front end is provided. An integrated circuit device may include: an amplifier coupled to receive an analog input signal; an anti-aliasing filter coupled to an output of the amplifier; a buffer circuit coupled to an output of the anti-aliasing filter; a sigma-delta modulator configured to generate a digital data stream in response to the output of the buffer circuit; and a plurality of chopping circuits nested therebetween, including: a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset from the analog input signal; and a second pair of chopping circuits having at least the first pair of chopping circuits disposed therebetween. The amplifier, anti-aliasing filter, sigma-delta modulator, and chopping circuits may be formed using the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Description

Technical Field

[0001] The present disclosure relates generally to analog signal processing, and more particularly to analog "front end" circuits that can process analog signals for conversion to digital values. Background Art

[0002] Analog signal processing circuits can introduce undesirable offset voltages and / or currents into analog signals. For example, in the case of an analog-to-digital converter (ADC), offset voltages can cause inaccurate output values. One way to reduce offset voltage in analog circuits is to use a "chopper" circuit. A chopper circuit modulates the offset voltage to a higher frequency. A low-pass filter can then be used to remove the higher frequencies, eliminating or reducing the offset from the final value.

[0003] Figure 14 An example of a chopper circuit operation is shown as background art. The analog signal 1401 input to the chopper circuit can be periodically interrupted (e.g., to zero / reference value). The resulting chopper circuit output is shown as 1403.

[0004] Figure 15 A conventional ADC 1505 with "nested" chopper circuits is shown. The analog signal path can include a first chopper circuit pair, CHX, between the output of the sigma-delta modulator 1511 and the analog signal input. A second chopper circuit pair, CHY, can be nested within the first chopper circuit pair, CHX, between the input and output of a programmable gain amplifier (PGA) 1519 in the PGA section 1507. A third chopper circuit pair, CHZ, can be nested within the second chopper circuit pair, CHY, within the PGA 1519. The operating frequencies of the chopper pairs, CHX, CHY, and CHZ, can be set by a programmable frequency circuit 1517.

[0005] The analog signal conditioned by the chopping circuits CHX, CHY, and CHZ can be provided to a sigma-delta modulator 1511 (also referred to as a ΔΣ modulator) to generate a stream of digital values ​​corresponding to the amplitude of the analog signal. A decimator 1513 can downsample the digital stream to provide a digital output result 1515. Although the chopping circuit can reduce offset, it may not be suitable for integration with other circuit components, such as analog filters.

[0006] Due to noise or other effects, the analog signal received for processing may include undesirable frequency components. Furthermore, in the case of a sigma-delta ADC, it may be desirable to limit the input signal frequency range to ensure optimal results for the sampling frequency used. To address such issues, a conventional AFE (analog front end) may include an anti-aliasing filter configured to pass the desired frequencies of the analog input signal.

[0007] Figure 16 A conventional ADC 1605 is shown with an AAF (anti-aliasing filter) 1621 disposed between a PGA 1619 and a buffer 1609. The buffer 1609 can provide a buffered and filtered analog signal to a sigma-delta modulator 1611. The resulting stream of digital values ​​can be processed by a decimator 1613 to generate a digital output result 1615.

[0008] Conventional ADC 1605 may have offset voltages in various stages. However, incorporating a chopper circuit into such an arrangement can have drawbacks. When the AAF bandwidth is relatively small, previous chopper circuits may have mismatched settling for the positive and negative outputs (relative to analog ground). The sigma-delta modulator will then sample the mismatched signals, which introduces offset errors into the final digital result.

[0009] Figure 17 Another conventional ADC 1705 is shown that can include an AAF and a chopping circuit. ADC 1705 can include a pair of chopper circuits CHX, CHY, and CHZ, a PGA section 1707, and a buffer section 1723 with nested chopping. ADC 1705 also includes a sigma-delta modulator 1711, a decimator 1713, and a result section 1715. Such circuit elements can be formed using an integrated circuit substrate 1727. ADC 1705 also includes an AAF 1721′ formed from circuit elements external to the integrated circuit (i.e., an off-chip component). Although conventional ADC 1705 can provide AAF filtering with the chopping circuit, such an approach can be undesirably high in terms of component cost and size.

[0010] It would be desirable to achieve some way of providing an AFE that can provide both input signal filtering and low offset voltage. Summary of the Invention

[0011] According to one aspect of the present invention, an integrated circuit device (or integrated circuit) is provided, comprising: an amplifier coupled to receive an analog input signal; an anti-aliasing filter coupled to an output of the amplifier; a buffer circuit coupled to an output of the anti-aliasing filter; a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer circuit; and a plurality of chopping circuits nested therebetween, the plurality of chopping circuits comprising: a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset from the analog input signal, and a second pair of chopping circuits having at least the first pair of chopping circuits disposed therebetween; wherein the amplifier, the anti-aliasing filter, the sigma-delta modulator, and the chopping circuits are formed using a same integrated circuit substrate.

[0012] According to one aspect of the present invention, a method is provided, comprising: receiving an analog input signal at an input; amplifying the analog input signal through operation of an amplifier; filtering an output of the amplifier using an anti-aliasing filter; buffering the output of the anti-aliasing filter using a buffer circuit; modulating the output of the buffer circuit into a digital data stream using a sigma-delta modulator; and chopping the analog signal at a position between the input of the buffer circuit and the output of the buffer circuit using a plurality of chopping circuits, the plurality of chopping circuits including at least a first pair of chopping circuits and a second pair of chopping circuits disposed between the first pair of chopping circuits; wherein the amplifier, the anti-aliasing filter, the buffer circuit, the sigma-delta modulator, and the chopping circuits are formed using a same integrated circuit substrate.

[0013] According to one aspect of the present invention, a system is provided, comprising: an analog front end, the analog front end comprising: an amplifier coupled to receive at least one analog input signal; an anti-aliasing filter coupled to an output of the amplifier; a buffer circuit coupled to an output of the anti-aliasing filter; a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer circuit; and a plurality of chopping circuit pairs, the chopping circuit pairs having at least the amplifier disposed therebetween and configured to remove an offset from the at least one analog input signal; the amplifier, the anti-aliasing filter, the sigma-delta modulator, and the chopping circuit being formed using a same integrated circuit substrate; and at least one sensor configured to generate the at least one analog input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram of an analog-to-digital converter (ADC) according to an embodiment.

[0015] Figure 2 is a block diagram of an ADC according to another embodiment.

[0016] Figure 3 is a block diagram of an ADC according to another embodiment.

[0017] Figure 4 is a block diagram of an ADC according to another embodiment.

[0018] Figure 5 is a detailed block diagram of an ADC according to an embodiment.

[0019] 6A to 6D is a diagram illustrating various anti-aliasing filter (AAF) configurations according to an embodiment.

[0020] 7A to 7E is a diagram illustrating various masking circuits according to an embodiment.

[0021] Figure 8 is a timing diagram illustrating chopping control signals and AAF switching element control that may be included in an embodiment.

[0022] Figure 9 is a flow chart of a method according to an embodiment.

[0023] Figure 10 is a flow chart of a method according to another embodiment.

[0024] Figure 11 is a flow chart of a method according to another embodiment.

[0025] Figure 12 is a block diagram of a system according to an embodiment.

[0026] Figure 13 is a diagram of a system according to another embodiment.

[0027] Figure 14 is a diagram showing a chopping operation.

[0028] Figure 15 This is the block diagram of a conventional ADC.

[0029] Figure 16 is a block diagram of another conventional ADC.

[0030] Figure 17 is a block diagram of another conventional ADC. DETAILED DESCRIPTION

[0031] According to embodiments, the analog front end (AFE), which converts analog signals into digital data streams, can include both an analog anti-aliasing filter (AAF) and a chopping circuit to reduce any offset voltage in the system. In some embodiments, the AAF component can reconfigure the operation of the chopping circuit to improve the settling symmetry in the resulting chopped analog signal.

[0032] In some embodiments, the AFE may include nested chopper circuits. A first pair of chopper circuits may be located at the front and back ends of the analog signal path. One or more additional pairs of chopper circuits may be located within the first pair of chopper circuits, nested around circuit components (e.g., amplifiers) that may generate offsets.

[0033] In some embodiments, portions of the digital data stream that may be unsettled due to the chopping operation may be masked.Such masking may include replacing the potentially unsettled data stream value with a previously stored data stream value.

[0034] Figure 1 1 is a block diagram of an ADC 100 according to an embodiment. The ADC 100 may have an AFE formed of an amplifier section 102, an anti-aliasing filter (AAF) 104, and a sigma-delta modulator (hereinafter referred to as a "modulator") 106. The ADC 100 may also include a decimator 108 and a result section 110. According to an embodiment, the AFE may include one or more chopping circuit pairs formed therein. Figure 1 In the embodiment shown, the chopping circuit pair CH10 / 11 is formed between the input and output of the amplifier 118 in the amplifier section 102. However, in other embodiments, the chopping circuit pair may be located elsewhere in the AFE.

[0035] According to an embodiment, when the chopping circuit CH10 / 11 is active (e.g., interrupting the analog signal), the switching elements in the AAF 104 can reconfigure the AAF 104 to have a larger bandwidth. In the particular embodiment shown, when the chopping circuit is inactive, the switching elements sw1 and sw4 can be closed, while the switching elements sw2 and sw3 can be open. When the chopping circuit CH10 / 11 is active, the switching element sw1 can be open and the switching element sw2 can be closed, thereby bypassing the input resistance of the AAF 104.

[0036] The dynamic chopping control circuit 112 may generate signals for controlling the chopping circuits CH10 / 11 and reconfiguring the switching elements of the AAF 104 during a chopping operation.

[0037] The analog signal output from AFE 104 may be modulated by modulator 106 . The resulting stream of digital values ​​may be received by decimator 108 , which may generate ADC digital conversion results 110 , which may be provided as digital output values ​​116 .

[0038] In this manner, the AFE may include an AAF to filter the analog input signal and a chopping circuit to reduce or eliminate offset voltages that may appear in the AFE.

[0039] In some embodiments, ADC 100 may be part of the same integrated circuit. That is, all circuit components, including AAF 102, may be formed using the same integrated circuit substrate.

[0040] Figure 2 2 is a block diagram of an ADC 200 according to another embodiment. ADC 200 may include an AFE formed by an amplifier, which in the embodiment shown may be a programmable gain amplifier (PGA) 218, an AAF 204, and a modulator 206. The AFE may include a pair of chopping circuits CH20 / 21, which in the embodiment shown may be provided at the input of PGA 218 and the output of modulator 306. ADC 200 may also include a decimator 208 and a result section 220.

[0041] According to an embodiment, the modulator 206 can be reset when the chopping circuit CH20 / 22 is active. Such an action can help ensure that the modulator 206 remains stable. The modulator 206 can be reset in any suitable manner. As just one of many possible examples, the modulator 206 can include one or more integrator stages, and the integrating capacitors and feedback capacitors in such integrator stages can be reset.

[0042] The dynamic chopping control circuit 222 may generate a signal for controlling the chopping circuit CH20 / 22 and generate a signal for resetting the modulator 206 (modulator reset (mod reset)).

[0043] In this way, the modulator operation can be reset while the chopping circuit is active.

[0044] In some implementations, ADC 200 may be part of the same integrated circuit.

[0045] Figure 3FIG2 is a block diagram of an ADC 300 according to another embodiment. ADC 300 may include an AFE formed by a PGA section 302, a modulator 306, and a plurality of nested chopping circuit pairs CH30 / 31, CH32 / 33, and CH34 / 35. ADC 300 may also include a masking circuit 320, a decimator 308, and a result section 330.

[0046] The masking circuit (320 and / or 320') can mask portions of the data stream output from the modulator 306 during a chopping operation performed by one or more chopping circuits. If the chopping operation generates an unsettled data value, and such a data value is reflected in the data stream generated by the modulator 306, such a value in the data stream can be masked by replacing it with a data value. Masking the data value can include replacing or changing the digital stream generated by the modulator 306 that corresponds to the data that may be unsettled (i.e., the chopping operation). Figure 3 In the embodiment, the masking circuit 320 may be activated in response to the chopping operation performed by the chopping circuit pair CH34 / 35 (at the frequency Fchop1). However, in an alternative embodiment, the masking circuit 320 may be activated in response to any chopping operation that may result in unsettled data.

[0047] The masking circuits (320 and / or 320') can be located at various locations in the conversion path. As shown by the masking circuit 320, the masking circuit can mask the data values ​​as they are output from the modulator 306. However, as shown by the masking circuit 320', in other embodiments, masking can be performed at the "back end" of the conversion path, masking the data values ​​after digital processing steps, including but not limited to digital filtering and / or decimation.

[0048] Depending on the implementation, the AFE may have nested choppers. In a nested chopper arrangement, the circuit that introduces offset may include an inner chopper pair. This inner chopper pair may be nested within an outer chopper pair. Furthermore, the outer chopper pair may be nested within a channel chopper pair that may encompass the analog signal path. As one moves inward from the channel chopper circuits to the inner chopper circuits, the different levels of chopper circuits may operate at increasingly faster frequencies.

[0049] exist Figure 3, chopping circuits CH30 / 31 may be internal chopping circuits for amplifier 318 and may operate at a frequency Fchop3. Chopping circuits CH32 / 33 may be external chopping circuits for amplifier 318 and may operate at a frequency Fchop2. Chopping circuits CH34 / 35 may be channel chopping circuits and may operate at a frequency Fchop1. In some embodiments, Fchop3 > Fchop2 > Fchop1. Various chopping frequencies may be generated by dynamic chopping control circuit 312. Any or all of the chopping frequencies (Fchop1-3) may be programmable.

[0050] In this manner, embodiments may include masking circuitry that can mask data stream values ​​corresponding to one or more chopping operations in an analog signal processing path. Additionally, an analog signal path may include nested chopping circuits.

[0051] While embodiments may include an AFE that compensates for possible adverse effects of a chopping circuit, embodiments may also include an AFE that can compensate for adverse effects of switching between analog input signals.

[0052] Figure 4 4 is a block diagram of an ADC 400 according to another embodiment. ADC 400 may have an input multiplexer (MUX) 422, one or more chopping circuits (two shown as CH40 / 41), a PGA 418, an AAF 404, and a modulator 406. ADC 400 may also include a decimator 408 and a result section 410.

[0053] The input MUX 422 can selectively switch between two or more analog input signals (404-0 to 414-x). Because the analog input signals (404-0 to 414-x) can be at different levels, the analog filter (e.g., AAF) may take some time to stabilize when switching between analog input signals. In accordance with an embodiment, when switching to a new analog input signal, a switching element within the AAF 404 can bypass the filter element, thereby enabling the new signal level to be processed quickly. Figure 4 In the embodiment, when switching between the analog input signals (404-0 to 414-x), the switching element sw1 and the switching element sw4 may be opened, while the switching element sw3 is closed.

[0054] Signals for controlling the input MUX 422 and the switching elements in the AAF 404 may be generated by the input MUX control circuit 424 .

[0055] Figure 5is a more detailed block diagram of ADC 500 according to another embodiment. ADC 500 may be Figures 1 to 4 The ADC 500 may include a PGA section 502 , an AAF 504 , a buffer section 526 , a modulator 506 , a masking circuit 520 , a decimator 508 , and a result section 510 .

[0056] ADC 500 may also include nested chopping circuits. PGA section 502 may include internal chopping circuits CH54 / 55 nested within external chopping circuits CH52 / 53. Buffer section 526 may include internal chopping circuits CH58 / 59 nested within external chopping circuits CH56 / 57. These chopping circuits may be nested within channel chopping circuits CH50 / 51.

[0057] The chopping circuits (CH50-59) can be controlled by signals from the dynamic chopping control circuit 512. In the illustrated embodiment, the internal chopping circuits CH54 / 55 and the internal chopping circuits CH58 / 59 can be controlled by the signal Fchop3. The external chopping circuits CH52 / 53 and the external chopping circuits CH56 / 57 can be controlled by the signal Fchop2. The channel chopping circuits CH50 / 51 can be controlled by the signal Fchop1. In some embodiments, the signals Fchop1-3 can be periodic and have a frequency where Fchop3>Fchop2>Fchop1. However, in other embodiments, the chopping circuits can be controlled individually or in different groups.

[0058] The AAF 504 can be reconfigured in response to activation of the chopper circuit by changing the states of the switching elements sw1 to sw4. The switching element sw1 can be controlled in response to the signal Fchop3. The switching element sw2 can be controlled in response to the signal Fchop1 (and Fchop2). The switching element s3 can be controlled in response to the signal mux_in generated by the input MUX control circuit 524. 6A to 6D The specific configuration for AAF 504 is described in more detail.

[0059] Modulator 506 may be reset in response to signal Fchopl and equivalents as described herein.

[0060] The masking circuit 520 may be activated in response to the signal Fchop1. 7A to 7C Possible masking circuits are described in more detail.

[0061] 6A to 6D is a diagram illustrating a portion of an ADC 500 ′ with various configurations of switching elements for use in an AAF 504 .

[0062] Figure 6A The configuration of the AAF 504 is shown when the PGA internal chopping circuit CH54 / 55 is active. Switching element sw1 may be open, thereby preventing unwanted analog signal effects (eg, glitches) from propagating out of the AAF 504. Switching element sw2 and switching element sw3 may be open.

[0063] Figure 6B The AAF 504 configuration is shown when the PGA external chopping circuit CH52 / 53 is active. Switching element sw2 can be closed, while switching element sw1 can be open. This can improve stability symmetry and increase the bandwidth of the AAF 504. Switching element sw3 can be open.

[0064] Figure 6C The configuration of AAF 504 is shown when channel chopping circuit CH50 / 51 is active. Switching element sw2 can be briefly closed while switching element sw1 can be opened, thereby bypassing the input resistance of AAF 504. This can improve the settling speed of the analog signal.

[0065] Figure 6D The AAF 504 configuration is shown when switching from one analog input signal to another. Switching element sw3 can be closed, while switching elements sw1, sw2, and sw4 can be open. This essentially bypasses the filter elements of the AAF 504, allowing the new analog signal to be quickly output from the AAF 504.

[0066] 7A to 7E It is shown that according to the embodiment, it can be included in a similar Figure 5 Diagram of the masking circuit in the ADC of the ADC.

[0067] Figure 7AA portion of ADC 500A' is shown, wherein masking circuit 520A may include a ring buffer 520-0 and a data MUX 520-1. In operation, a stream of digital values ​​may be output from modulator 506. When the corresponding chopping circuit is inactive, data MUX 520-1 outputs the data stream received at input "0." Simultaneously, ring buffer 520-0 may store a running set of streaming data values ​​that may be applied at input "1." In this manner, data MUX input "1" will receive a delayed version of the data stream received at input "0." When the corresponding chopping circuit is active, data MUX 520-1 may output the data values ​​from ring buffer 520-0. Such stored data values ​​mask the data stream with older data values, thereby preventing data stream values ​​corresponding to unstable analog signal levels from propagating to decimator 508 for conversion into output digital values. In some embodiments, ring buffer 520-0 may be a first-in, first-out (FIFO) memory. In some implementations, the size (eg, depth) of the ring buffer can be programmable and / or can be changed dynamically (on-the-fly).

[0068] Figure 7B A portion of ADC 500B' is shown, wherein masking circuit 520B may include data MUX 520-1, delay stage 520-2, and interpolation circuit 520-3. When the corresponding chopping circuit is in an inactive state, data MUX 520-1 outputs a data stream received at input "0." Simultaneously, interpolation circuit 520-3 may generate a stream of interpolated data values ​​generated based on the current data stream and stored by delay stage 520-2. When the corresponding chopping circuit is in an active state, data MUX 520-1 may output the interpolated data stream values. In some embodiments, the delay value for delay stage 520-2 is programmable and / or can be dynamically changed.

[0069] Figure 7CA portion of an ADC 500C' is shown, wherein a masking circuit 520C may include a data MUX 520-1, a first delay element 520-4, and a second delay element 520-5. Delay element 520-5 may have the same delay as 520-4. However, in alternative embodiments, such delays may be different. When the corresponding chopping circuit is inactive, data MUX 520-1 outputs a data stream received at input "0" that is delayed by the first delay element 520-4. When the corresponding chopping circuit is active, data MUX 520-1 may output a data stream received at input "1" that is delayed by the second delay element 520-5. In some embodiments, the delay values ​​for second delay elements 520-5 and / or 520-4 may be programmable and / or dynamically changeable.

[0070] Figure 7D A portion of ADC 500D' is shown, where masking circuit 520D may include synthesis circuit 520-6. Synthesis circuit 520-6 may synthesize data stream values ​​in response to activation of one or more chopper circuits. Synthesis circuit 520-6 may output the data stream from modulator 506 when the corresponding chopper circuit is not activated. In some embodiments, synthesis circuit 520-6 may include a lookup table or the like to generate the synthesized data stream values ​​in response to the data stream values ​​output from modulator 506.

[0071] Figure 7E A portion of an ADC 700E is shown, wherein a masking circuit 520E may include a machine learning (ML) engine 520-7 and a MUX 520-1. The ML engine 520-7 may include a machine learning inference engine that is trained to generate masked (e.g., corrected) data stream values ​​based on data stream values ​​that include undesirable effects, such as those caused by chopper operation. When the designated chopper circuit is not activated, the data MUX 520-1 outputs the data stream received at input "0" (i.e., the output of the modulator 506). If the designated chopper circuit is activated, the data MUX 520-1 may output the data stream values ​​from the ML engine 520-7.

[0072] The ML engine 520 - 7 may take any suitable form. Figure 7EAn example of an ML engine 520-7' that may be included in an embodiment is shown. ML engine 520-7' is shown in a training configuration. When being trained, ML engine 520-7' may include an encoder 520-7a, a latent space 520-7b, a decoder 520-7c, and a training agent 520-7d. Data stream values ​​output during the chopping operation (data stream (training)) may be applied to encoder 520-7a, which may encode such values ​​into latent space 520-7b. Latent space values ​​520-b may be decoded by decoder 520-7c to generate inferred data stream values. Training agent 520-7d may compare the inferred data stream values ​​with expected data stream values ​​(e.g., responses without undesirable errors / artifacts). Based on such comparison, training agent 520-7d may modify encoder 520-7a and / or decoder 520-7c. In some embodiments, the encoder 520 - 7a and / or the decoder 520 - 7c may include an artificial neural network, where the neural weights are adjusted by a training agent 520 - 7d .

[0073] In some embodiments, the Figures 5 to 7C For example, all circuit elements in the ADC, including analog filters (e.g., AAFs), can be formed using the same semiconductor substrate. This contrasts with conventional methods that use off-chip components to form analog filters.

[0074] Figure 8 is shown to include a Figure 5 A timing diagram of signals in an embodiment of an embodiment of an embodiment. Figure 8 The following waveforms are included: "Modulator Clock", which can be a sampling clock that can indicate the frequency of the sigma-delta conversion produced by the modulator; "Chopping Clock", which can be a signal for an internal chopping circuit; "Nested Chopping Clock", which can be a signal for an external chopping circuit; "Channel Chopping Clock", which can be a signal for a channel chopping circuit; "AAF sw1" shows the operation of switching element sw1 within the AAF (the switching element feeding into the filter resistor), where a high logic level indicates that the switch is closed; and "AAF sw2" shows the operation of switching element sw2 within the AAF (the switching element that bypasses the filter resistor), where a high logic level indicates that the switch is closed.

[0075] In the illustrated operation, switching element sw1 may be controlled synchronously with the chopping clock, while switching element sw2 may be controlled synchronously with the channel chopping clock. Furthermore, the frequency of the chopping clock may be greater than the nested chopping clock, which may be greater than the channel chopping clock.

[0076] It is understood that the examples provided are by way of example Figure 8 . Depending on the embodiment, any of the illustrated signals - including both frequency and phase relative to any of the other signals - can be programmable. Additionally or alternatively, control of the switching elements within the AAF can also be programmable. As just two of many possible variations, the switching element activation (closing or opening) can be programmed to be synchronized with any of the illustrated signals (including some type of transition or both types of transitions), and the duration of the switching element activation can be programmable (i.e., how long the switching element is closed and / or open). In some embodiments, the duration of the switching element can be programmed to multiple modulator clock half cycles or multiple modulator clock cycles.

[0077] although Figures 1 to 8 Having shown various AFEs, ADCs, and corresponding methods, additional methods will now be described.

[0078] Figure 9 is a flow chart of method 930 according to an embodiment. Method 930 may include performing a chopping operation 930-0 on an analog signal. Such an action may include using any suitable chopping method. In some embodiments, chopping can be used to reduce or substantially eliminate offset in the analog signal processing path.

[0079] The resulting chopped analog signal can be filtered using an analog filter. However, some or all filter elements 930-2 can be bypassed during chopping. The output of the analog filter can be sigma-delta converted to a digital stream 930-4. Such an action can include any suitable conversion operation and can produce an output data stream at the sampling rate. The data stream can be multi-bit or as small as a single-bit data stream. Digital values ​​corresponding to the analog signal can be generated 930-6 based on the data stream generated by the sigma-delta conversion operation.

[0080] Figure 10 1030 is a flow chart of a method 1030 according to another embodiment. Method 1030 may include performing a chopping operation 1030-0 on an analog signal. Such an action may include using any suitable chopping method and may reduce / eliminate offset. The resulting chopped analog signal may be sigma-delta converted to a digital stream 1030-2. Such an action may include any suitable conversion as described herein or an equivalent.

[0081] During the chopping period, the digital stream may be masked 1030-4. Such an action may include replacing or altering the digital stream generated by the sigma-delta modulator during the chopping period. This may include portions of the data stream before and / or after the gain change. Replacing the data stream may include replacing those data stream values ​​generated during the gain change with data stream values, including previously stored values. The previously stored values ​​may be the data stream values ​​immediately preceding the data stream values ​​corresponding to the gain change. Altering the data stream may include performing an arithmetic operation or a logical operation on the data stream values. As just two of many possible examples, the data stream values ​​corresponding to the gain change may be averaged with previous data stream values ​​and / or interpolated relative to other data stream values, such as previously stored data stream values.

[0082] A digital value 1030 - 6 corresponding to the analog signal may be generated based on the digital stream including the masked portion of the digital stream.

[0083] Figure 11 11 is a flow chart of a method 1130 according to another embodiment. Method 1130 may include amplifying an analog signal using a PGA 1103-0. Such an action may include adjusting the gain value of the PGA if the analog signal is determined to be outside of one or more range value limits. The output of the PGA may be filtered using an AAF 1130-2. The output of the AAF may be buffered using a buffer circuit 1130-4.

[0084] The analog signal from the buffer circuit may be sigma-delta converted to a digital stream 1130-6. Such actions may include any conversion described herein and equivalents.

[0085] If one or more types of chopping occur in the analog signal path (Y in 1130-8), the input resistor 1130-10 of the AAF can be bypassed. Additionally, the data stream generated by the ΣΔ conversion can be masked 1130-12.

[0086] If one or more types of chopping have not occurred (N in 1130 - 8 ), then processing of the analog signal may continue (returning to 1130 - 0 ).

[0087] While embodiments may include an ADC system, embodiments may also include other systems.

[0088] Figure 121 is a block diagram of a battery monitoring system 1270 according to an embodiment. System 1270 may include a battery 1272, a control unit 1274, a current sampler 1280, and an ADC system 1200. Power 1276 may be supplied from (i.e., the battery is discharging) and / or supplied to (i.e., the battery is charging) the battery 1272. Battery 1272 may include one or more temperature sensors 1278.

[0089] ADC system 1200 can take any of the forms described herein or equivalents and can provide accurate conversion by removing offset using a chopping circuit while providing analog filtering using an AAF. Such capabilities can be provided on a single integrated circuit and do not require off-chip circuit components.

[0090] In the illustrated embodiment, the ADC system 1200 can generate digital values ​​corresponding to the analog signals provided by the current sampler 1280. Additionally or alternatively, the ADC 1200 can generate digital values ​​corresponding to analog temperature readings from the temperature sensor 1278 and voltage readings for the battery 1272. In some embodiments, the ADC 1200 can include an input MUX 1222 for selectively connecting different analog input signals to the inputs of the PGA in the ADC.

[0091] The digital values ​​generated by the ADC system 1200 may be sent to the control unit 1274 over the bus system 1278 .

[0092] Figure 13 13 is a diagram of an automotive system 1380 according to an embodiment. System 1380 may include a battery 1372 and a smart battery sensor 1382. Smart battery sensor 1382 may include an ADC system 1300. ADC system 1300 may take any form or an equivalent of those described herein and may generate digital signals corresponding to the operation of battery 1372, including, but not limited to, terminal voltage, charge current, and / or discharge current.

[0093] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of the present invention. Therefore, it should be emphasized and understood that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various parts of this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be appropriately combined in one or more embodiments of the present invention.

[0094] Similarly, it should be understood that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes combined in a single embodiment, figure, or description thereof for the purpose of simplifying the disclosure, thereby aiding understanding of one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as reflecting an intention that the claims require more features than are expressly recited in each claim. Rather, inventive aspects lie in less than all the features of a single, foregoing disclosed embodiment. Therefore, the claims appended following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

Claims

1. An integrated circuit device comprising: an amplifier coupled to receive an analog input signal; an anti-aliasing filter coupled to an output of the amplifier; a buffer circuit coupled to an output of the anti-aliasing filter; a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer circuit; as well as A plurality of chopping circuits nested within each other, the plurality of chopping circuits comprising: a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove an offset from the analog input signal, and a second pair of chopping circuits, the second pair of chopping circuits having at least the first pair of chopping circuits disposed therebetween; in The amplifier, the anti-aliasing filter, the sigma-delta modulator, and the chopper circuit are formed using a same integrated circuit substrate.

2. The integrated circuit device according to claim 1, wherein: The second pair of chopping circuits includes the amplifier, the anti-aliasing filter, and the buffer circuit disposed therebetween.

3. The integrated circuit device according to claim 2, wherein: The plurality of chopping circuits further include a third pair of chopping circuits having the buffer circuit disposed therebetween.

4. The integrated circuit device according to claim 1 , wherein: The anti-aliasing filter is configured to change an analog filter element configuration during chopping operation of the first pair of chopping circuits.

5. The integrated circuit device according to claim 1 , further comprising: A masking circuit is configured to mask a portion of a digital data stream output from the sigma-delta modulator during a chopping operation of the first pair of chopping circuits.

6. The integrated circuit device according to claim 5, wherein: The masking circuit comprises: a memory circuit configured to store a portion of the digital data stream, and A multiplexer is coupled to selectively output the digital data stream or the data value stored in the memory circuit.

7. The integrated circuit device according to claim 1, wherein: The plurality of chopping circuits further include: a third pair of chopping circuits disposed between the first pair of chopping circuits, the third pair of chopping circuits having the amplifier disposed therebetween, wherein the first pair of chopping circuits operating at a first frequency, the second pair of chopping circuits operating at a second frequency slower than the first frequency, and The third pair of chopping circuits operates at a third frequency that is faster than the first frequency.

8. The integrated circuit device according to claim 1, further comprising: an input multiplexer configured to selectively connect one of a plurality of input signals to the amplifier as the analog input signal; as well as The anti-aliasing filter is configured to change an analog filter element configuration when the input multiplexer switches between input signals.

9. A method for analog signal processing, comprising: receiving an analog input signal at an input; amplifying the analog input signal through the operation of the amplifier; filtering the output of the amplifier using an anti-aliasing filter; buffering the output of the anti-aliasing filter using a buffer circuit; modulating the output of the buffer circuit into a digital data stream using a sigma-delta modulator; as well as chopping the analog signal at a location between an input of the buffer circuit and an output of the buffer circuit using a plurality of chopping circuits, the plurality of chopping circuits including at least a first pair of chopping circuits and a second pair of chopping circuits disposed between the first pair of chopping circuits; in The amplifier, the anti-aliasing filter, the buffer circuit, the sigma-delta modulator, and the chopper circuit are formed using a same integrated circuit substrate.

10. The method according to claim 9, further comprising: An analog filter element configuration of an anti-aliasing filter is changed during chopping operation of at least two of the chopping circuits.

11. The method according to claim 9, wherein: Chopping an analog signal involves: chopping the analog input signal at the input of the amplifier and the output of the buffer circuit using the first pair of chopping circuits, and The analog input signal is chopped at an input of the amplifier and an output of the amplifier using the second pair of chopping circuits.

12. The method according to claim 11, further comprising: chopping the analog input signal at an input of the amplifier and an output of the amplifier using a third pair of chopping circuits nested within the second pair of chopping circuits; in the first pair of chopping circuits operating at a first frequency, The second pair of chopping circuits operates at a second frequency faster than the first frequency, and The third pair of chopping circuits operates at a third frequency that is faster than the second frequency.

13. The method according to claim 9, further comprising: Portions of a digital data stream output from the sigma-delta modulator are masked during chopping operations of at least two of the chopping circuits.

14. The method according to claim 9, further comprising: selectively connecting different signals to the input as the analog input signals through operation of an input multiplexer; as well as When the input multiplexer switches between different signals, the analog filter element configuration of the anti-aliasing filter is changed.

15. A system for analog signal processing, comprising: An analog front end, the analog front end comprising: an amplifier coupled to receive at least one analog input signal; an anti-aliasing filter coupled to an output of the amplifier; a buffer circuit coupled to an output of the anti-aliasing filter; a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer circuit; and a plurality of chopping circuit pairs having at least the amplifier disposed therebetween and configured to remove an offset from the at least one analog input signal; The amplifier, the anti-aliasing filter, the sigma-delta modulator, and the chopper circuit are formed using a same integrated circuit substrate; and At least one sensor is configured to generate the at least one analog input signal.

16. The system of claim 15, wherein: The at least one sensor includes a plurality of sensors; The analog front end further includes: an input multiplexer configured to selectively connect one of the sensors to the amplifier, and The anti-aliasing filter is configured to change an analog filter element configuration when the input multiplexer switches from one sensor to another.

17. The system of claim 15, wherein: The at least one sensor is a battery current sensor.

18. The system of claim 15, wherein: The plurality of chopping circuit pairs include: a first pair of chopping circuits operating at a first frequency, and A second pair of chopping circuits is disposed within the first pair of chopping circuits and operates at a second frequency faster than the first frequency.

19. The system of claim 18, wherein: The anti-aliasing filter is configured to bypass an input resistance of the anti-aliasing filter during a chopping transition of at least the first pair of chopping circuits.

20. The system of claim 18, wherein: The analog front end also includes a masking circuit configured to mask a portion of the digital data stream from the sigma-delta modulator during chopping operation of at least the first pair of chopping circuits.

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