Flip-chip structure of a transmon qubit for quantum computing devices

Abstract

A quantum computing device (300) is formed using a first chip (302) and a second chip (306), the first chip having a first substrate (303), a first set of pads (312A, B), and a set of Josephson junctions (304) disposed on the first substrate. The second chip has a second substrate (307), a second set of pads (308) disposed on the second substrate opposite the first set of pads, and a second layer (310A, B) formed on a subset of the second set of pads. The second layer is configured for bonding the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions, the subset selected to avoid frequency conflicts between qubits in a set of qubits. A qubit is formed using one Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset, the other Josephson junction rendered unusable for forming a qubit.

Description

Technical Field

[0001] This invention generally relates to methods and systems for manufacturing superconducting devices and superconducting quantum devices. More specifically, this invention relates to devices, methods, and systems for manufacturing transmon qubit flip-chip structures for quantum computing devices. Background Technology

[0002] In the following text, the “Q” prefix in a word or phrase indicates a reference to that word or phrase in the context of quantum computing, unless explicitly distinguished in use.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, a branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave in strange ways, simultaneously existing in more than one state and interacting with other particles very far away. Quantum computing utilizes these quantum phenomena to process information.

[0004] The computers we use today are called classic computers (also referred to here as "conventional" computers or conventional nodes, or "CN"). In the so-called von Neumann architecture, conventional computers use conventional processors, semiconductor memory, and magnetic or solid-state storage devices manufactured using semiconductor materials and technologies. Specifically, the processors in conventional computers are binary processors, that is, they operate on binary data represented in 1s and 0s.

[0005] A quantum processor (q-processor) uses the odd-numbered property of entangled qubit devices (commonly referred to here as "qubits," or multiple "qubits") to perform computational tasks. In the specific realm of quantum mechanics, matter particles can exist in multiple states, such as "on," "off," and simultaneously "on" and "off." Where binary computation using semiconductor processors is restricted to using only on and off states (equivalent to 1 and 0 in binary code), a quantum processor utilizes these quantum states of matter to output signals usable in data computation.

[0006] Conventional computers encode information using bits. Each bit can take the value 1 or 0. These 1s and 0s serve as on / off switches that ultimately drive the computer's functionality. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both 1 and 0 simultaneously. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, a state (whether 1 or 0 or both) can depend on the state of the other, and more information about the two qubits can be ascertained when they are entangled compared to when they are processed individually.

[0007] Using these two principles, qubits operate as more sophisticated information processors, enabling quantum computers to function in ways that allow them to solve problems that are difficult to handle with conventional computers. The feasibility of using a quantum processor with superconducting qubits has been successfully built and demonstrated. (IBM is a registered trademark of International Business Machines Corporation in the United States and other countries.)

[0008] A superconducting qubit includes a Josephson junction. A Josephson junction is a superconducting tunnel junction formed by separating two thin-film superconducting metal layers using a non-superconducting material. When the metal in the superconducting layer becomes superconducting—for example, by lowering the temperature of the metal to a specific cryogenic temperature—electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other. Other methods exist for forming Josephson junctions, and this description is not intended to be limiting. In a qubit, the Josephson junction (which functions as a distributed nonlinear inductor) is electrically connected in parallel with one or more capacitive devices forming a nonlinear microwave oscillator. The oscillator has a resonant / transition frequency determined by the inductance and capacitance values ​​in the qubit circuit. Any reference to the term "qubit" is a reference to a superconducting qubit circuit employing a Josephson junction unless explicitly distinguished in use.

[0009] In its superconducting state, the material firstly provides no resistance to the passage of electric current. When the resistance drops to zero, the current can circulate within the material without dissipating any energy. Secondly, the material exhibits the Meissner effect, meaning that external magnetic fields, provided they are weak enough, will not penetrate the superconductor but will remain on its surface. When one or both of these properties are no longer exhibited by the material, it is said to be in a normal state and no longer superconducting.

[0010] The critical temperature of a superconducting material is the temperature at which the material begins to exhibit superconducting properties. Superconducting materials exhibit very low or zero resistivity in response to the flow of electric current. A critical field is the highest magnetic field at a given temperature at which a material remains superconducting.

[0011] Superconductors are generally classified into one of two types. Type I superconductors exhibit a single transition at the critical field. When the critical field is reached, a Type I superconductor transitions from a non-superconducting state to a superconducting state. Type II superconductors involve two critical fields and two transition regions. At or below the lower critical field, a Type II superconductor exhibits a superconducting state. Above the upper critical field, a Type II superconductor does not exhibit superconducting properties. Between the upper and lower critical fields, a Type II superconductor exhibits a mixed state. In the mixed state, a Type II superconductor exhibits an incomplete Meissner effect, meaning that an external magnetic field in a specific quantization packet penetrates the superconducting material.

[0012] Information processed by qubits is carried or transmitted as microwave signals / photons in the microwave frequency range. These microwave signals are captured, processed, and analyzed to decipher the encoded quantum information. A readout circuit is a circuit coupled to the qubit to capture, read, and measure its quantum state. The output of the readout circuit is information that can be used by a q processor to perform calculations.

[0013] A superconducting qubit has two quantum states – |0> and |1>. These two states can be the two energy states of an atom, such as the grounded (|g>) and first stimulated (|e>) states of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of the nucleus or electron spin, the two locations of crystal defects, and the two states of a quantum dot. Because the system possesses quantum properties, any combination of these two states is allowed and valid.

[0014] Superconducting devices, such as qubits, are fabricated using superconducting and semiconductor materials using known semiconductor manufacturing techniques. Superconducting devices typically use one or more layers of different materials to achieve their device characteristics and functions. Material layers can be superconducting, conductive, semiconducting, insulating, resistive, inductive, capacitive, or possess any number of other properties. Different methods may be necessary to form different material layers, taking into account the properties of the materials, their shape, size, or placement, other materials adjacent to them, and many other considerations.

[0015] Software tools used to design semiconductor and superconducting devices can be manufactured, manipulated, or otherwise integrated with electrical layouts and device components on a very small scale. When formed in a suitable substrate, some components that such tools can manipulate can be measured in just a few nanometers.

[0016] A layout, including its shape and position, is a shape selected in the tooling according to the device's objectives. Once a design layout (also simply called a layout) is completed for a device or set of devices, the design is converted into a set of masks or intermediate masks. A set of masks or mask masters consists of one or more masks or mask templates. During manufacturing, a semiconductor wafer is exposed to light or radiation through a mask to form micro-assemblies including the structures described. This process is called photolithography. Masks can be used to fabricate or print the contents of the mask onto the wafer. During the photolithography process, radiation is focused through the mask and at certain desired intensities. This intensity of radiation, combined with any material used for radiation deposition, is often referred to as the "dose." The focus and dose of radiation are controlled to achieve the desired shape and electrical properties of the structures on the wafer.

[0017] The fabrication process for semiconductor or superconducting devices includes not only metering but also other methods for depositing and / or removing materials with various electrical and / or mechanical properties. For example, an ion beam of the material can be used to deposit conductive materials; hard insulators can be dissolved using chemicals or etched using mechanical methods. These examples of operations in the fabrication process are not intended to be limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other operations in the fabrication process that can be used to manufacture devices according to the illustrative embodiments, and these operations are contemplated within the scope of the illustrative embodiments.

[0018] Superconducting devices are typically planar, meaning that the superconducting structure is fabricated on a plane. Non-planar devices are three-dimensional (3D) devices, some of which have structures formed above or below a given fabrication plane.

[0019] Some qubits are fabricated using a flip-chip geometry. In a flip-chip geometry, a qubit chip (also called a "Q chip") with multiple individual qubits is fabricated on a substrate, and an interposer chip with one or more connections is fabricated on a separate substrate. Solder bumps are deposited onto chip pads on a first surface of the qubit chip and / or the interposer chip, and the qubit chip or interposer chip is flipped so that its first side faces down. The qubit chip and the interposer chip are aligned and bump-bonded, such that the solder on the solder bumps completes the electrical connection between the qubit chip and the interposer chip.

[0020] According to the illustrative embodiments described herein, flip-chip geometries can combine an interposer chip with other chips containing qubit components rather than complete qubits. For example, a junction chip (also referred to as a “J-chip”) is one type of chip according to the illustrative embodiments, having multiple individual Josephson junctions fabricated thereon. When an interposer layer is combined with the J-chip in a flip-chip configuration as illustrated herein, the multiple Josephson junctions can be used to form a qubit. According to exemplary embodiments, an interposer chip with one or more connections is fabricated on a separate substrate. Bumps of suitable material, such as solder materials having desired electrical, thermal, ductility, and malleability under low temperature and other operating conditions, are deposited on chip pads on the first surface of the J-chip and / or interposer chip, as described herein. Generally, any reference to solder bumps should be interpreted to include bumps made of materials that meet these requirements. The J-chip or interposer chip is flipped such that the first side of the flipped chip faces the first surface of the unflipped chip of the two chips. The J-chip and interposer chip are aligned and bump-engaged such that the material of the bumps completes the electrical connection between the J-chip and the interposer chip.

[0021] The readout circuit typically uses a resonator coupled to a qubit via electromagnetic resonance (usually microwave or radio frequency resonance). The resonator in the readout circuit system includes inductive and capacitive elements. Some qubits are fixed-frequency qubits, meaning their resonant frequency is immutable. Other qubits are frequency-tunable qubits. A q processor can employ fixed-frequency qubits, frequency-tunable qubits, or a combination thereof.

[0022] These illustrative embodiments recognize that a fixed-frequency qubit is designed to be frequency-fixed to improve noise immunity. These illustrative embodiments also recognize that negative effects can occur when the resonant frequencies of two coupled qubits on a chip are the same or within a frequency threshold band, or when their higher transition frequencies are at or near resonance, such as crosstalk, quantum decoherence, energy decay, generation of mixed states, unintended information transfer, quantum state leakage, etc. These illustrative embodiments further recognize that such qubits can also negatively affect the performance or utility of certain quantum gates, such as cross-resonance gates, which have stringent requirements on the spectrum of the resonant frequencies of the qubits operating on them. These illustrative embodiments further recognize that a challenge in fixed-frequency qubit-based quantum processors is frequency congestion or frequency conflict between adjacent qubits.

[0023] These illustrative embodiments recognize that another challenge in fixed-frequency qubit-based quantum processors is the low on / off ratio between the microwave signal enabling an interaction (interaction strength) and the interaction between coupled qubits (interaction strength). These illustrative embodiments further recognize that yet another challenge in fixed-frequency qubit-based quantum processors is enabling a gate of interest without generating unwanted interactions at other sites. These illustrative embodiments further recognize that defects in fabrication and materials used in currently available manufacturing methods for fixed-frequency qubits lead to deviations from a desired resonant frequency.

[0024] These illustrative embodiments further recognize that, in certain circumstances, a Josephson junction of a qubit can be tuned to adjust a resonant frequency of that qubit. However, these illustrative embodiments recognize that once a flip-chip assembly has been formed, a Josephson junction on the qubit chip or J-chip becomes physically inaccessible to operations such as laser annealing, by which the impedance of the Josephson junction can be modified or adjusted. In this case, the flip-chip assembly becomes fixed with a qubit configuration in which one Josephson junction has an undesirable impedance. Therefore, the illustrative embodiments recognize the need for a flip-chip configuration in which qubits can be formed with a desired resonant frequency even after the internal plug-in has been flipped over the J-chip.

[0025] Therefore, there is a need in this field to address the aforementioned problems. Summary of the Invention

[0026] From a first aspect, the present invention provides a method for manufacturing a quantum computing device, the method comprising: forming a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate; and forming a second chip having a second substrate, a second set of pads disposed on the second substrate opposite to the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer being configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions, the subset being selected to avoid frequency conflicts between qubits in a set of qubits generated by the Josephson junctions in the subset of the Josephson junctions.

[0027] In another aspect, the present invention provides a superconductor manufacturing system including photolithography components, which, when operated on at least one die, is used to manufacture a quantum computing device for performing multiple operations, including: forming a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate; and forming a second chip having a second substrate, a second set of pads disposed on the second substrate opposite to the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer being configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions, the subset being selected to avoid frequency conflicts between qubits in a set of qubits generated by the Josephson junctions in the subset of the Josephson junctions.

[0028] In another aspect, the present invention provides a superconductor manufacturing system including photolithography components, which, when operated on at least one die, is used to manufacture a quantum computing device for performing the operations of the present invention.

[0029] In a further aspect, the present invention provides a computer implementation method for manufacturing a quantum processor, the method comprising: forming a set of qubits, at least one of which is formed in a flip-chip configuration comprising a pair of chips, the formation of the chip pair comprising: forming a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate; and forming a second chip having a second substrate, a second set of pads disposed on the second substrate opposite to the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer being configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions, the subset being selected to avoid frequency conflicts between qubits in the set of qubits, the qubits in the set of qubits being generated by the Josephson junctions in the subset of the Josephson junctions.

[0030] These illustrative embodiments provide a method and system for manufacturing a quantum computing device. The embodiment forms a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The embodiment further forms a second chip having a second substrate, a second set of pads disposed on the second substrate opposite to the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions, which is selected to avoid frequency conflicts between qubits in a set of qubits generated by the Josephson junctions in the subset of the Josephson junctions. Thus, this embodiment provides a quantum computing device in a flip-chip configuration, wherein several Josephson junctions on the J-chip are fabricated with manufacturing variations in characteristics, and only some Josephson junctions are selected to form qubits with desired frequency conflict avoidance characteristics.

[0031] Another embodiment further forms an unusable Josephson junction within the set of Josephson junctions, wherein, in response to the first Josephson junction being excluded from a subset of the set of Josephson junctions, the first Josephson junction in the set is modified to become the unusable Josephson junction. Thus, this embodiment provides a flip-chip configuration quantum computing device in which other Josephson junctions on the J-chip are rendered unusable in the quantum computing device.

[0032] Another embodiment further forms a disconnected pad in the first set of pads, wherein the first set of pads includes a first pad electrically connected to the first Josephson junction, and wherein the first pad is electrically disconnected from the first Josephson junction to form the disconnected pad, which renders the first Josephson junction unusable. Thus, this embodiment provides a hardware modification to render the Josephson junction on the J-chip unusable in the quantum computing device.

[0033] In another embodiment, an electrical characteristic of the first Josephson junction is modified so that it no longer functions as a Josephson junction. Thus, this embodiment provides another hardware change to make the Josephson junction on the J-chip unusable in the quantum computing device.

[0034] In another embodiment, the subset is selected based on measurements of parameters associated with each Josephson junction in the set. Thus, this embodiment provides a characteristic of the Josephson junctions on the J-chip, based on which the junction can be selected for use in the quantum computing device.

[0035] In another embodiment, the resonance frequency associated with a particular qubit is selected from one of the following: (i) a predicted resonance frequency calculated based on the measured parameters, and (ii) the actual measured resonance frequency of the particular qubit. Thus, this embodiment provides a predicted characteristic of qubits formed using a Josephson junction on a J-chip, based on which the junction can be selected for use in the quantum computing device.

[0036] In another embodiment, the parameter includes the resistance associated with the Josephson junction in the group of Josephson junctions. Thus, this embodiment provides specific characteristics of the Josephson junction on the J-chip, based on which the junction can be selected for use in the quantum computing device.

[0037] In another embodiment, the resistor is the normal-state resistance of the Josephson junction. Thus, this embodiment provides a unique characteristic of the Josephson junction on the J-chip, based on which the junction can be selected for use in the quantum computing device.

[0038] Another embodiment further forms a first set of bumps on the first chip. The embodiment also includes a group of bumps formed on a first layer of the second chip, the group of bumps being formed of a material having above-threshold ductility in a room temperature range, wherein the group of bumps is configured to be cold-soldered to the first set of protrusions. Thus, this embodiment provides an apparatus for removably configuring two chips in a flip-chip configuration.

[0039] In another embodiment, the first set of protrusions is selected from at least one of the group consisting of gold and platinum. Thus, this embodiment provides a material for a device for removably configuring two chips in a flip-chip configuration.

[0040] In another embodiment, the bump set is selected from at least one of the group consisting of indium, tin, lead, and bismuth. Thus, the embodiment provides an apparatus for bonding two configured chips in a flip-chip configuration.

[0041] Another embodiment further forms a flip-chip assembly including a first chip detachably attached to the second chip using a cold solder joint, wherein the parameters of the Josephson junction within the flip-chip assembly are adjustable by removing the flip-chip assembly at the cold solder joint. Thus, this embodiment provides a detachable configuration of the two chips or an adjustable Josephson junction feature in a flip-chip configuration.

[0042] One embodiment includes a manufacturing system for manufacturing the quantum computing device. Attached Figure Description

[0043] The invention will now be described by way of example only, with reference to preferred embodiments as shown in the following figures:

[0044] Figure 1 A block diagram of a network that can implement the illustrative embodiments of the data processing system is depicted;

[0045] Figure 2 The qubits used in quantum processors are described;

[0046] Figure 3 An example cross-sectional view of a flip-chip quantum computing device is depicted, illustrating a problem that can be solved using illustrative embodiments;

[0047] Figure 4 A block diagram depicts an example J-chip structure according to an illustrative embodiment;

[0048] Figure 5 A block diagram depicts an example structure in the fabrication of a flip-chip device according to an illustrative embodiment;

[0049] Figure 6 A block diagram depicts an example structure in the fabrication of a flip-chip device according to an illustrative embodiment;

[0050] Figure 7 An example graph depicts a method for calculating the predicted frequency of a qubit based on a measured junction resistance, according to an illustrative embodiment.

[0051] Figure 8A block diagram depicts an example structure in the fabrication of a flip-chip device according to an illustrative embodiment;

[0052] Figure 9 A block diagram depicts an example structure in the fabrication of a flip-chip device according to an illustrative embodiment;

[0053] Figure 10 A block diagram depicts an example flip-chip structure in the fabrication of a flip-chip device according to an illustrative embodiment;

[0054] Figure 11 A top view schematic diagram of an example J-chip structure according to an illustrative embodiment is depicted;

[0055] Figure 12 A block diagram depicts an alternative example structure according to an illustrative embodiment;

[0056] Figure 13 A block diagram of an example J-chip assembly according to an illustrative embodiment is depicted;

[0057] Figure 14 A block diagram depicts an example J-chip structure according to an illustrative embodiment;

[0058] Figure 15 A block diagram depicts an example detachable structure according to an illustrative embodiment;

[0059] Figure 16 A block diagram depicts an example separable conductive coupling structure according to an illustrative embodiment;

[0060] Figure 17 A block diagram depicts another example structure of a detachable conductive coupling according to an illustrative embodiment;

[0061] Figure 18 A flowchart depicts an example process for fabricating a flip-chip quantum computing device according to an illustrative embodiment;

[0062] Figure 19 A flowchart illustrating an example process for fabricating a flip-chip quantum computing device is depicted according to an illustrative embodiment; and

[0063] Figure 20 A flowchart illustrating an example process for fabricating a flip-chip quantum computing device is depicted according to an illustrative embodiment. Detailed Implementation

[0064] The illustrative embodiments used to describe the present invention generally address the aforementioned problems or needs, as well as other related problems or needs, by providing a method for manufacturing a transmon qubit flip-chip structure usable in a flip-chip quantum computing device. The illustrative embodiments also provide a system for manufacturing the transmon qubit flip-chip structure for a flip-chip quantum computing device.

[0065] Refer to the accompanying drawings and see details. Figure 1 These figures are example diagrams of a data processing environment in which illustrative embodiments can be implemented. Figure 1 This is merely an example and is not intended to assert or imply any limitation regarding the environment in which different embodiments may be implemented. Specific embodiments may be modified in many ways based on the environment depicted in the following description.

[0066] Figure 1 A block diagram depicts a network in which an illustrative embodiment of a data processing system can be implemented. Data processing environment 100 is a computer network in which the illustrative embodiment can be implemented. Data processing environment 100 includes network 102. Network 102 is a medium for providing communication links between different devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0067] The client or server are merely example roles of certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles of these data processing systems. Servers 104 and 106 are coupled to network 102 along with storage unit 108. Software applications can execute on any computer in data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. Data processing systems such as server 104 or 106 or clients 110, 112, or 114 can contain data and may have software applications or software tools executing on them.

[0068] Device 132 is an example of a mobile computing device. For example, device 132 may take the form of a smartphone, tablet computer, laptop computer, client 110 in fixed or portable form, wearable computing device, or any other suitable device. Described as being in Figure 1 Any software application running in another data processing system within the device can be configured to run in a similar manner in device 132. Figure 1 Any data or information stored or generated in another data processing system may be configured to be stored or generated in device 132 in a similar manner.

[0069] Application 105 implements the embodiments described herein. Manufacturing system 107 is a software component of any suitable system for manufacturing a quantum device, such as a Josephson junction, a qubit, and other superconducting structures used in quantum computing devices. Generally, manufacturing systems for manufacturing superconducting devices (including devices for quantum computing purposes) and their corresponding software components are known. Application 105 provides instructions to such a known manufacturing system via manufacturing application 107 to induce the assembly of a novel flip-chip quantum device considered in these illustrative embodiments in the manner described herein.

[0070] See Figure 2 The figure depicts a qubit used in a quantum processor. The qubit 200 includes a capacitor structure 202 and a Josephson junction 204. The Josephson junction 204 is formed by separating two thin-film superconducting metal layers using a non-superconducting material. When the metal in the superconducting layer becomes superconducting—for example, by lowering the temperature of the metal to a specific cryogenic temperature—electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other. In the superconducting qubit 200, the Josephson junction 204, with its small inductance, is electrically coupled in parallel with the capacitor structure 202, thus forming a nonlinear resonator.

[0071] See Figure 3 This figure depicts an example cross-sectional view of a flip-chip quantum computing device, illustrating a problem that can be solved using an illustrative embodiment. The flip-chip quantum computing device 300 includes a J-chip 302 having a substrate 303. The substrate 303 is selected as a suitable material on which a Josephson junction can be formed, and ultimately, this material is suitable for forming qubits using the Josephson junction. The substrate 303 includes a Josephson junction 304 formed on a first surface of the substrate 303. In this embodiment, as illustrated herein, the Josephson junction 304 has an associated impedance that contributes to setting the resonant frequency of a qubit in which the qubits of the Josephson junction 304 can be used.

[0072] Substrate 303 comprises a material that, when operated in a low-temperature range, exhibits a residual resistivity (RRR) of at least 100 and a thermal conductivity greater than 1 W / (cm*K) at 4 Kelvin. RRR is the ratio of the resistivity of the material at room temperature to that at 0 K. Since 0 K is not practically achievable, an approximation at 4 K is used. For example, sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, or diamond can be used to form substrate 303 for operation in a temperature range from 77 K to 0.01 K. These examples of substrate materials are not intended to be limiting. Many other materials suitable for forming substrate 303 will be conceived by those skilled in the art based on this disclosure, and these materials are contemplated within the scope of the exemplary embodiments.

[0073] The flip-chip quantum computing device 300 further includes an interposer chip 306, which includes an interposer substrate 307. The interposer substrate 307 comprises a material exhibiting an RRR of at least 100 and a thermal conductivity greater than 1 W / (cm*K) at 4 Kelvin. For example, the interposer substrate 307 can be formed using sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, or diamond for operation in a temperature range from 77 K to 0.01 K. These examples of substrate materials are not intended to be limiting. Many other materials suitable for forming the substrate 307 will be apparent to those skilled in the art based on this disclosure, and these materials are considered within the scope of the illustrative embodiments. In certain embodiments, one or more of the substrate 303 and the interposer substrate 307 are formed of silicon or another suitable substrate material.

[0074] Intermediate chip 306 includes a conventional ground plane 308 formed on a first surface of interpolation substrate 307. In a particular embodiment, the ground plane 308 is formed of a superconducting material, a variety of superconducting materials, a metallic material, or a combination thereof.

[0075] J-chip 302 includes a first pad 312A and a second pad 312B formed on a first surface of substrate 303. The first landing pad 312A and the second landing pad 312B are part of a ground plane (not shown) on J-chip 302. In a particular embodiment, the landing pads 312A-B are formed of a superconducting material, a variety of superconducting materials, a metallic material, or a combination thereof.

[0076] The ground layer 308 of the interposer chip 306 is bonded to the J-chip 302 via a first bump joint 310A and a second bump joint 310B. In some embodiments, a single bump joint or more than two bump joints may also be used to bond the ground layer 308 of the interposer 306 to the J-chip 302. In such embodiments, the J-chip 302 may be formed with an appropriate number of pads to achieve a desired number of ground plane connections.

[0077] Electrical connections are formed between the interposer chip 306 and the J-chip 302 via a first bump bond 310A and a first pad 312A, and a second bump bond 310B and a second pad 312B. In embodiments, at least one of aluminum, niobium, titanium, titanium nitride, palladium, gold, silver, copper, or platinum is used to form the ground plane 308, the first landing pad 312A, and the second landing pad 312B for operation in a temperature range of 77K to 0.01K. In embodiments, an indium, tin, and bismuth alloy operating in a temperature range of 77K to 0.01K is used to form the bump bonds 310A and 310B. These examples of ground plane, bump bond materials, and pad materials are not intended to be limiting. Many other materials suitable for forming the first layer will be conceived by those skilled in the art based on this disclosure, and these materials are considered within the scope of the illustrative embodiments.

[0078] The quantum resonant frequency is difficult to control due to variations in the Josephson junction inductance during manufacturing. Josephson junctions fabricated via shadow evaporation (e.g., via a Dolan bridge technique) naturally exhibit variations in their Josephson inductance. For identically designed, fabricated / processed single-junction transmon qubits, each qubit can naturally have a different resonant frequency (e.g., a variation of 100 MHz–200 MHz). Such conditions can lead to frequency conflicts for fixed-frequency qubits using cross-resonant entanglement gates, such as a frequency conflict between a qubit using Josephson junction 304 and a second-coupled qubit using another Josephson junction on J-chip 302.

[0079] These illustrative embodiments recognize that preventing frequency conflicts is a challenging problem for fixed-frequency superconducting qubits, and that the qubit frequency is difficult to change or modify using conventional methods after chip fabrication. The frequency of a qubit is inversely proportional to the square root of the product of the Josephson inductance and the total capacitance across the Josephson junction. Therefore, methods for resolving frequency conflicts include changing the frequency of a single-junction transmon qubit by modifying the junction inductance or the total capacitance across the junction (e.g., in parallel with the junction).

[0080] Several methods have been proposed to adjust the junction inductance to tune the resonant frequency, but each method has limitations and drawbacks. For example, changing the inductance is difficult to perform precisely. Alternatively, frequency tuning can be performed by changing the capacitance (e.g., by etching the substrate (e.g., a silicon (Si) substrate) in the gaps of a planar capacitor to change the effective dielectric constant). However, such etching exposes the Josephson junction to significantly more fabrication processes. Furthermore, etching and related processes introduce additional loss mechanisms. Moreover, etching and related processes are typically used only to reduce capacitance and increase qubit frequency, rather than to increase capacitance and correspondingly decrease qubit frequency.

[0081] One embodiment provides a flip-chip geometry including a J-chip and an insertion chip, the insertion chip being used to form a qubit in a quantum processor. The J-chip includes a plurality of Josephson junctions defined on a substrate.

[0082] This embodiment provides a novel design and fabrication method for a quantum computing device in a flip-chip geometry. In this embodiment, a design / fabrication system designs and fabricates a J-chip having multiple Josephson junctions using known processes for fabricating a single Josephson junction. The design / fabrication system further designs and fabricates an interpolator chip.

[0083] Each fabricated Josephson junction has a normal-state resistance, which can be measured, for example, by electrically probing the Josephson junction resistance above the superconducting transition temperature. The resonant frequency of a qubit using a particular Josephson junction can be predicted based on the measured Josephson junction resistance of that particular Josephson junction. One specific embodiment uses a fitted curve that correlates the Josephson junction resistance with frequency to calculate the predicted frequency of such a qubit. Although different embodiments illustrate the measurement of the Josephson junction resistance, in other embodiments, the measurement of the Josephson junction's impedance or inductance can be used to predict the resonant frequency of a qubit using that Josephson junction.

[0084] In one embodiment, the design / manufacturing system determines possible frequency collisions based on predicted resonant frequencies generated by a set of more than one Josephson junction fabricated on J-chip 302. Specifically, this embodiment determines the predicted resonant frequencies of possible qubits, which can use one Josephson junction from the set of Josephson junctions. From the set of possible qubits, this embodiment determines a first subgroup of possible qubits that satisfies the frequency collision separation threshold (which uses a Josephson junction from a corresponding first subgroup of the set of Josephson junctions). Correspondingly and optionally, from the set of possible qubits, this embodiment determines a second subgroup of possible qubits (which uses a Josephson junction from a corresponding second subgroup of the set of Josephson junctions), which does not satisfy the frequency collision separation threshold.

[0085] In one embodiment, the qubit resonant frequency is a function of the spacing distance between the interposer chip and the J-chip. The design / manufacturing system also determines a suitable separation gap distance, frequency tuning range, and sensitivity between the interposer chip and the J-chip based on the desired frequency adjustment, which will result in an acceptable number of qubits in the first subset. In another embodiment, the design / manufacturing system joins the interposer chip and the J-chip at the spacing distance to achieve the desired qubit frequency and number of qubits in the flip-chip arrangement.

[0086] In a particular embodiment, the design / manufacturing system bonds the interposer chip and the J-chip. In one embodiment, a bump bonding process is used to perform the bonding. In other particular embodiments, other suitable methods for bonding the interposer chip and the J-chip may be used.

[0087] Another embodiment provides a method for manufacturing a flip-chip quantum computing device, such that the method can be implemented as a software application. Applications implementing this manufacturing method embodiment can be configured to operate in conjunction with existing superconducting manufacturing systems, such as lithography systems.

[0088] For clarity of description and without implying any limitation thereof, these illustrative embodiments are described using a number of instances of Josephson junctions in a set arranged on a substrate, or multiple qubits using a subset of that set of Josephson junctions. Embodiments may be implemented with different numbers of Josephson junctions in that set, different numbers of Josephson junctions forming qubits in that subset, different arrangements, superconducting devices, rather than using a single qubit formed from a single Josephson junction in that subset, types of quantum computing devices not based on low-temperature superconductors within the scope of the illustrative embodiments, or some combination thereof.

[0089] Furthermore, simplified diagrams of the example flip chip geometry are used in the accompanying drawings and illustrative embodiments. In actual flip chip manufacturing, additional structures not shown or described herein, or structures different from those shown and described herein, may exist without departing from the scope of the illustrative embodiments. Similarly, within the scope of the illustrative embodiments, the structures shown or described in the example flip chip may be manufactured differently to produce similar operations or results as described herein.

[0090] The different shaded areas in the two-dimensional diagrams of exemplary structures, layers, and constructions are intended to represent different structures, layers, materials, and constructions in exemplary fabrication, as described herein. The different structures, layers, materials, and constructions can be manufactured using suitable materials known to those skilled in the art.

[0091] The specific shapes, positions, locations, or dimensions of the shapes depicted herein are not intended to limit the illustrative embodiments unless such characteristics are explicitly described as features of the embodiments. Shapes, positions, locations, dimensions, quantities, or certain combinations thereof have been chosen only for clarity of the drawings and illustrations and may have been enlarged, minimized, or otherwise altered from actual lithography that may be used to achieve the actual shape, position, location, or size of the objective lens according to the exemplary embodiments.

[0092] Furthermore, these illustrative embodiments are described merely as examples with respect to a specific practical or hypothetical superconducting device (e.g., a currently feasible qubit). The steps described by the different illustrative embodiments can be adapted to fabricate different quantum computing devices in a similar manner, and such adaptations are contemplated within the scope of the illustrative embodiments.

[0093] When implemented in an application, the embodiments cause the manufacturing process to perform certain steps as described herein. The steps of the manufacturing process are illustrated in several figures. In a specific manufacturing process, not all steps are necessary. Without departing from the scope of the illustrative embodiments, some manufacturing processes may perform the steps in a different order, combine certain steps, remove or replace certain steps, or perform some combination of these and other manipulations of the steps.

[0094] These illustrative embodiments are described by way of example only, relating to certain types of materials, electrical properties, thermal properties, structures, constructions, shapes, layer orientations, directions, steps, operations, planes, dimensions, quantities, data processing systems, environments, components, and applications. Any particular manifestation of these and other similar products is not intended to limit the invention. Any suitable manifestation of these and other similar products may be chosen within the scope of the illustrative embodiments.

[0095] The illustrative embodiments are described using specific designs, architectures, layouts, diagrams, and tools only as examples and are not limited to the illustrative embodiments. The illustrative embodiments may be used in conjunction with other comparable or similar designs, architectures, layouts, diagrams, and tools.

[0096] One advantage that can be provided by one embodiment is that no additional processes are required on the J-chip after manufacturing, which does not provide the risk of junction damage or failure.

[0097] The examples in this disclosure are for clarity of description only and are not intended to limit the illustrative embodiments. Any advantages listed herein are merely examples and are not intended to limit these illustrative embodiments. Additional or different advantages may be achieved through the particular illustrative embodiments. Furthermore, the particular illustrative embodiments may have some, all, or none of the advantages listed above.

[0098] See Figure 4 The figure depicts a block diagram of an example J-chip structure according to an illustrative embodiment. Figure 1 The application 105 interacts with the manufacturing system 107 to produce or manipulate the structure 400 as described herein. The substrate 402 is... Figure 3 An example of substrate 302 in the example.

[0099] The embodiments allow a manufacturing system to deposit material 404 to form a set of pads 408. For example, a mask may be designed to include a layout of one or more pads 408. The manufacturing system operating in conjunction with the embodiments uses a mask to pattern the material 404 into the shape of the pads 408 on (or in) a substrate 402 via the aforementioned photolithography process. The pattern of the pads 408 corresponding to the etched pattern in the hard mask layer may also allow the photolithography process to deposit material 404 in the shape of the pads 408. These and other possible ways of forming pads 408 via photolithography processes are considered within the scope of the illustrative embodiments.

[0100] The pad set 408 includes a material 404 having high electrical and thermal conductivity (above the threshold RRR and above the threshold thermal conductivity) over a low temperature range. In embodiments, at least one of aluminum, niobium, titanium, titanium nitride, palladium, gold, silver, copper, or platinum, operating in a temperature range of 77K to 0.01K, is used to form the set of pads 408. These examples of layer materials are not intended to be limiting. Many other materials suitable for forming this set of pads will be apparent to those skilled in the art based on this disclosure, and these materials are considered within the scope of these illustrative embodiments.

[0101] In an embodiment, a set of pads 408 is deposited on one side (e.g., the side of substrate 402 facing the interposer in a flip-chip structure). For example, the set of pads 408 may be a thin film deposition of particles 406 on substrate 402. Particles 406 may be deposited using thin film deposition techniques in photolithography. This example of a deposition method is not intended to be limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other methods and processes suitable for forming this set of pads, and these methods and processes are contemplated within the scope of the illustrative embodiments. In an embodiment, particles 406 have the capability to be used to deposit an under-bump metal (UBM) layer (at least on...) Figure 5 The material (described in the text) is electrically isolated from the substrate 402. In one embodiment, the pad 408 is optional, for example, when the substrate or underlying structure (e.g., a ground plane formed in some other way) has the electrical characteristics required for fabricating the UBM layer on top of such structure, the UBM layer can be formed directly on the substrate or underlying structure to the desired height.

[0102] See Figure 5 The figure depicts a block diagram of an example structure achieved in the fabrication of a flip-chip device according to an illustrative embodiment. Figure 1 The application 105 interacts with the manufacturing system 107 to produce or manipulate the fabrication 500 as described herein. The substrate 502 is... Figure 4 Substrate 402 or Figure 3 Example of substrate 302. Pad 504 is from Figure 4 An example of pad 408, and it can be optional for the reasons described above.

[0103] A UBM is a conductive structure electrically coupled to a Josephson junction on a J-chip. The material of the UBM allows for the reliable formation and adhesion of bumps of a suitable conductive material (e.g., low-temperature superconducting solder bumps). Therefore, functionally, the UBM operates as part of a superconducting path from a bump to the Josephson junction under low-temperature operating conditions.

[0104] Structure 500 is an optional mask structure used in the photolithography process. Figure 4 The configuration reached by structure 400 in the middle. Alternatively, when not utilized Figure 4 When the pad is 408, it can be obtained from Figure 3 Structure 300 in the figure reaches structure 500, and the UBM structure described in this figure can be directly formed on a substrate or another structure to the desired height using a mask with an appropriate configuration in a photolithography process, in a manner previously described herein.

[0105] The descriptions of the masks and photolithography techniques should not be construed as limiting the manner in which the structures described herein are formed. The masks and methods of material deposition depicted are merely simplified and generalized examples. Photolithography of the described structures is possible in many respects. For example, the described structures are currently achieved by patterning the resist using photolithography (light) or electron beam lithography (electron beam), developing the resist, then subtracting the deposited material from openings in the resist or depositing material in openings in the resist. Finally, the resist is removed. Pads, resonators, and ground planes are typically fabricated subtractively, while junctions and UBMs are typically fabricated additively using currently available manufacturing facilities (and subsequent stripping processes). Manufacturing processes and techniques are constantly evolving, and other methods of forming the described structures are contemplated within the scope of the illustrative embodiments, provided that the resulting structures possess the electrical, mechanical, thermal, and operational characteristics as described herein.

[0106] In one embodiment, the first layer 510 is patterned using a mask on pad 504 via a photolithography process (e.g., using a deposition method) to form a UBM. In another embodiment, as depicted in structure 550, the first layer 552 is patterned on substrate 502 to a desired height via a photolithography process to form a UBM in the manner described herein. As a non-limiting example, thin-film deposition techniques can be used in photolithography to pattern the first layer 510 to deposit particles 508. As another example, the first layer 510 can be patterned using sputtering techniques known in photolithography. These examples of methods for forming a UBM are not intended to be limiting. Many other methods and processes suitable for forming UBMs will be conceived by those skilled in the art based on this disclosure, and these methods and processes are contemplated within the scope of the illustrative embodiments. Further description of the UBM 510 using structure 500 is for clarity of description only and does not imply any limitation on any embodiment. The configuration shown using UBM 510 or its equivalents can be implemented using UBM 552 or its equivalents without departing from the scope of the illustrative embodiments.

[0107] See Figure 6 The figure depicts a block diagram of an example structure achieved in the fabrication of a flip-chip device according to an illustrative embodiment. Figure 1 The application 105 interacts with the manufacturing system 107 to produce or manipulate the configuration structure 600 as described herein. The substrate 602 is... Figure 5 Examples of substrate 502 in structure 500 or 550. Pad 604 is a UBM, in a combination of structure 504 and first layer 510 or in... Figure 5 The configuration is in the manner of layer 552. One embodiment provides a manufacturing system configured to manufacture quantum computing devices or components thereof, as seen in [reference needed]. Figure 1The method described is to pattern material 606 into a Josephson junction 610 on a J-chip substrate 602. As a non-limiting example, the Josephson junction 610 can be patterned using photolithography with a suitably designed mask.

[0108] See Figure 7 The figure depicts an example of calculating a predicted frequency of a qubit based on a measured junction resistance, according to an illustrative embodiment. Figure 7 A graph is shown showing a predicted qubit frequency f01 relative to a Josephson junction resistance R. Graph 700 includes curves 702 and 704. According to one embodiment, a resistance R is obtained by measuring (e.g., by electrical probing) a resistance of the Josephson junction. Based on the measured resistance R, a predicted resonant frequency of the qubit using that Josephson junction can be determined by reading the corresponding values ​​on the Y-axis of curves 702 and 704 in graph 700.

[0109] See Figure 8 The figure depicts a block diagram of an example structure achieved in the fabrication of a flip-chip device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate configuration 800 as described herein. Configuration 800 includes an insertion substrate 802, a set of pads 804 formed on the front side of the insertion substrate 802, and a set of resonator signal lines 806. In one embodiment, the pads 804 and the resonator signal lines 806 are formed by exhibiting characteristics similar to... Figure 3 The ground layer 308 is formed of a material with similar electrothermal properties. In another embodiment, the pads 804 and the resonator signal lines 806 are made of a material with similar electrothermal properties to the ground layer 308. Figure 3 The ground plane 308 is formed of the same material. In one embodiment, the pad 804 and the resonator signal line 806 are in... Figure 3 The ground plane 308 is patterned at the same photolithography step as the patterned ground plane 308. In another embodiment, the pad 804 and the resonator signal line 806 are patterned separately, and after the photolithography step, the ground plane 308 is patterned at the same photolithography step as the patterned ground plane 308. Figure 3 The middle part is patterned.

[0110] The embodiment allows the manufacturing system to deposit material 810 (e.g., patterning using deposition process 808 in photolithography) to form a first layer 812 on the set of pads 804. In the embodiment, a functionally similar Figure 5 The first layer 812 is patterned using a material and photolithography process similar to that used for patterning the first layer 510 on the patterned pad 504. The first layer 812 forms a UBM layer on the corresponding pad 804.

[0111] See Figure 9The figure depicts a block diagram of an example structure achieved in the fabrication of a flip-chip device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to generate or manipulate configuration structure 900 as described herein. Structure 900 is... Figure 8 Further development of the structure 800, and reference numerals 802, 804, 806 and 812 as indicated in relation to Figure 8 The same or similar structures are depicted and described.

[0112] The embodiment causes the manufacturing system to perform appropriate photolithography operation 910 to deposit material 912, thereby forming a second layer 914 on the first layer 812. In the embodiment, the second layer 914 is deposited only on the first layer 812 on a subset of the set of pad-UBM structures 804-812. In one embodiment, the subset of the set of pad-UBM structures 804-812 corresponds to a selected subset of the set of Josephson junctions. As explained herein, not all Josephson junctions in a set of Josephson junctions can meet the requirements for forming qubits, and only a subset of Josephson junctions can be selected. The subset of the selected subset of the set of pad-UBM structures 804-812 corresponding to the Josephson junctions are those pad-UBM structures that receive the second layer 914. In practice, the embodiment causes a photolithography mask to be created such that only the selected subset of the pad-UBM structures 804-812 receives the deposition of material 912 to form the second layer 914. Other methods, such as, but not limited to, hard mask creation instead of photolithographic masks, are also possible for similar purposes, and they are considered within the scope of the illustrative embodiments.

[0113] In an embodiment, the second layer 914 is a set of solder bumps. Examples of the second layer 914 in an embodiment are bumps formed using indium, tin, and bismuth, or some combination thereof, for operation in a temperature range of 77K to 0.01K. These examples of the second layer material are not intended to be limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming the second layer, and these materials are considered within the scope of the illustrative embodiments.

[0114] In one embodiment, a second layer 914 is deposited on top of a first layer 906. For example, the second layer 914 is an injection-molded solder joint (IMS) deposition of particles 912 on top of the first layer 812. In some embodiments, layer 812 may be absent, and particles 912 may be deposited onto pad 804 to form bumps 914. In some other embodiments, pad 804 may be absent, and bumps 914 may be formed on the UBM layer 812. In some other embodiments, the pad-UBM layer combination 804-812 may be formed using alternative materials in an alternative manner, but for a similar purpose—to enable electrical connections from points in the interpolator chip to the Josephson junction. In this case, bumps 914 may be formed at or on the alternative structure without departing from the scope of the illustrative embodiments.

[0115] See Figure 10 The figure depicts a block diagram of an example flip-chip structure achieved in the fabrication of a flip-chip device according to an illustrative embodiment. Figure 1 The application 105 interacts with the manufacturing system 107 to generate or manipulate the configuration structure 1000 as described herein.

[0116] The embodiment oriented the manufacturing system such that the intermediate board chip 802 with corresponding structures is oriented relative to the J-chip 602, and the intermediate board chips 802 with corresponding structures are oriented relative to each other such that their respective structures face each other to form a flip-chip configuration. For example, the intermediate board chip is shown flipped over the J-chip so that... Figure 9 The bump 914 described in the text and Figure 6 The structure 604 on the J-chip 602 makes physical and electrical contact.

[0117] See Figure 11 The figure depicts a top view of an example J-chip structure according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to generate or manipulate structure 1100 to form structure 1101 as described herein. In structure 1100, it is assumed... Figure 6 The J-chip substrate 602 is configured with three non-limiting examples of Josephson junctions 610. Each Josephson junction 610 is electrically connected to a corresponding pair of pads 504, and these pairs of pads 504 have a... Figure 5 The UBM layer 510 is manufactured in the manner described herein.

[0118] For clarity, only three Josephson junctions and their corresponding connection pairs are shown, and this does not imply any limitation on the illustrative embodiments to a configuration of only three or fewer Josephson junctions on a contemplated J-chip. An embodiment can be implemented and practiced with a single J-chip comprising any number of Josephson junctions and their corresponding connection structures, without any limitations imposed by the illustrative embodiments, and is limited only by the prior art in any given time.

[0119] In one embodiment, application 105 determines that a subset of the group of Josephson junctions 610 will be removed to avoid frequency conflicts. One embodiment causes the manufacturing system to disable the subset of the group of Josephson junctions 610, thus forming structure 1101. A disabled Josephson junction is represented in structure 1101 as Josephson junction 1112. A Josephson junction can be disabled in a variety of ways, including but not limited to physically damaging or altering the Josephson junction, electrically damaging or altering an electrical characteristic of the Josephson junction, disconnecting the Josephson junction from one or two corresponding pads of the Josephson junction, physically damaging or altering one or two pads of the Josephson junction, electrically damaging or altering the electrical characteristics of one or two pads of the Josephson junction, physically damaging or altering a UBM layer on one or two pads of the Josephson junction, electrically damaging or altering the electrical characteristics of a UBM layer on one or two pads of the Josephson junction, covering one or two pads or one or two UBMs of the Josephson junction with an insulating layer, or some combination of these and many other possible ways that render a Josephson junction unusable.

[0120] For example, in one embodiment, the fabrication system ablates a subset of the set of Josephson junctions 1112 from the surface of the J-chip substrate 602. For example, the fabrication system can use laser ablation to remove the subset of the set of Josephson junctions 1112. As another example, the fabrication system can use focused ion beam (FIB) to remove the subset of the set of Josephson junctions 1112. In another embodiment, the fabrication system destroys the subset of the set of Josephson junctions 1112 by disconnecting electrical connectors 1108 and 1110 that connect the Josephson junctions 1112 to their corresponding pair of pads 504. Disconnection of connectors 1108 and 1110 can also be performed via ablation, FIB, or another suitable method.

[0121] See Figure 12 The figure depicts a block diagram of an alternative example structure according to an illustrative embodiment. Figure 1 The application 105 interacts with the manufacturing system 107 to produce or manipulate the structure 1200 as described herein. Structure 1200 is... Figure 8Example of structure 800. Structure 1200 begins with an insertion substrate 802, a set of pads 804, a set of resonators 806, and a first layer 812 formed on the set of pads 804.

[0122] A Josephson junction can be disabled or rendered unusable in a quantum computing device simply by not connecting to it. For example, an unwanted Josephson junction (along with the bonding pads and UBM layer) can be kept unconnected by simply not forming a bump on the interposer chip at a location corresponding to the UBM layer of the Josephson junction. Without the bump, the bonding pads on the interposer at that location will not make electrical contact with the UBM layer of the Josephson junction, thus rendering the Josephson junction unusable.

[0123] The embodiments enable the construction of a mask to prevent certain interpolated pads from receiving material 1212 deposited using process 1210 in the manufacturing system. Thus, as can be seen in the example results of such selective deposition, the second layer 904 is formed only on certain pad-UBM combinations 804-812 and not on other pads. For example, a single pad-UBM combination 804-812 in the area marked 1202 has no second layer—bumps. As another example, a pair of pad-UBM combinations 804-812 in the area marked 1204 have no bumps.

[0124] See Figure 13 This figure depicts a block diagram of an example J-chip assembly according to an illustrative embodiment. As a non-limiting example, assembly 1300 shows an insert chip flipped onto a J-chip, wherein some Josephson junctions from the J-chip are connected to a plurality of circuits and components on the insert chip, and other Josephson junctions remain at least disconnected and preferably rendered unusable.

[0125] See Figure 14 The figure depicts a block diagram of an example detachable J-chip structure according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 1400 as described herein. Structure 1400 is Figure 5 Example of structure 500 in the example.

[0126] Structure 1400 includes a J-chip substrate 1402, similar to Figure 5 Substrate 502. Pad 1404 is similar to... Figure 5 Pad 504 in the first layer. The first layer 1406 is similar. Figure 5 The first layer, 510.

[0127] Implementation examples enable manufacturing systems (such as...) Figure 1 The manufacturing system 107 creates a set of protrusions 1412 on a first layer 1406 of a set of pads 1404 on a substrate 1402. For example, an embodiment may allow a mask 1408 in the manufacturing system to deposit material 1410 to form the protrusion set 1412. In an embodiment, the manufacturing system 107 includes a wire connector to deposit material 1410 and form the protrusions 1412. For example, the wire connector may form a first half of a ball joint before being pulled upwards to deposit the remainder of the protrusion. In an embodiment, the protrusion 1412 is a pillar. For example, the protrusion 1412 may have a conical, triangular, cylindrical, or rectangular cross-section.

[0128] In one embodiment, the protrusion 1412 comprises a material 1410 having a predetermined ductility (above a threshold) at room temperature. In one embodiment, the protrusion 1412 is formed using a material exhibiting at least 20% elongation at break in the room temperature range. For example, the protrusion 1412 can be formed using gold, platinum, or a gold-coated superconducting material. These examples of protrusion materials, qubit substrate materials, protrusion shapes, and deposition methods are not intended to be limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials and methods suitable for forming substrates, J-chips, and protrusions, and these materials and methods are considered within the scope of the illustrative embodiments.

[0129] See Figure 15 The figure depicts a block diagram of an example detachable structure according to an illustrative embodiment. Figure 1 The application 105 interacts with the manufacturing system 107 to generate or manipulate the configuration structure 1500 as described herein.

[0130] Structure 1500 includes Figure 9 The interpolator chip configuration is constructed on substrate 802 in a manner that allows for interpolation. Structure 1550 further includes... Figure 6 Constructed on substrate 602 in a manner and in Figure 14 The J-chip configuration can be further modified in this way.

[0131] The embodiment enables the manufacturing system to couple the J-chip configuration to the interposer chip configuration such that a protrusion 1412 on the J-chip is detachably but electrically coupled to a corresponding bump 914 on the interposer chip. It should be noted that the protrusion 1412 can be formed and interfaced with the bump on the interposer chip even when the corresponding Josephson junction has been disabled in the manner described herein.

[0132] In one embodiment, a separable conductive coupling between protrusion 1412 and bump 914 is achieved by having manufacturing system 107 cold-weld protrusion 1412 with solder bump 914. For example, protrusion 1412 pierces the corresponding solder bump 914. Cold welding is a welding process in which coupling occurs at the interface of the two parts to be welded, where the interface is in the room temperature range. In cold welding, the interface is solid. In this way, a set of protrusions is detachably but electrically coupled to a corresponding set of bumps.

[0133] See Figure 16 The figure depicts a block diagram of an example detachable conductive coupling structure according to an illustrative embodiment. Structure 1600 is... Figure 15 An example of a cold-welded connection between the group of protrusions and the group of solder bumps. Structure 1600 includes, as shown in the example... Figure 8 Pad 804 and UBM layer 812 on the interpolator chip, such as Figure 9 The bump 914 in the middle, such as Figure 5 The pads 504 and UBM layer 510 on the J-chip, and as shown in the image. Figure 14 The protrusion 1412 in the middle.

[0134] In one embodiment, bump 914 comprises a material having predetermined ductility (above a threshold) at room temperature. In another embodiment, bump 914 is formed using a material exhibiting at least 20% elongation at break in a room temperature range. For example, at least one of indium, tin, lead, bismuth, and any combination thereof is used to form bump 914. In one embodiment, bump 914 comprises a material exhibiting superconductivity in a low temperature range. In one embodiment, bump 914 contacts the UBM layer on the interpolator chip and on the J-chip. In other words, as shown, bump 914 extends fully—and provides a complete conductive path between UBM layers 812 and 510.

[0135] See Figure 17 The figure depicts a block diagram of another example structure of a detachable conductive coupling according to an illustrative embodiment. Structure 1700 is... Figure 15 An example of a cold-welded connection between the group of protrusions and the group of solder bumps. For example... Figure 8 The interpolator chip in the middle has a structure of pad 804 (1700) and UBM layer 812, such as... Figure 9 The bump 914 in the middle, such as Figure 5 The pads 504 and UBM layer 510 on the J-chip, and as shown in the image. Figure 14 The protrusion 1412 in the middle.

[0136] In one embodiment, the bump 914 comprises a material having a predetermined ductility (above a threshold) at room temperature. In another embodiment, using... Figure 16The described material is used to form bump 914. In one embodiment, bump 914 contacts only the UBM layer on one chip and not the UBM layer on the other chip. For example, as shown, bump 914 contacts UBM layer 812 on the interposer chip but not UBM layer 510 on the J-chip. In other words, bump 914 extends partially—and only provides a complete conductive path between UBM layers 812 and 510 when pierced by protrusion 1412, as illustrated. In an embodiment, the capacitance of the electrical connection is determined by the distance between the first pad 804 and the second pad 504. For example, the capacitance is inversely proportional to the distance or gap height between the first pad 804 and the second pad 504. In an embodiment, protrusion 1412 has a height corresponding to the desired capacitance of the electrical connection. In an embodiment, the gap height is a function of the height of protrusion 1412 and the compressive force during cold soldering. For example, the gap height may be inversely proportional to the amount of compressive force during cold soldering. As another example, the gap height may be directly related to the height of protrusion 1412.

[0137] These examples of substrate materials, bump materials, deposition methods, and pad materials are not intended to be limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials and deposition methods suitable for forming components of the device, and these materials are considered within the scope of these illustrative embodiments. In one embodiment, the height of the corresponding protrusions varies among a set of protrusions formed on the surface. For example, the height of the protrusions may vary to accommodate substrate warping.

[0138] See Figure 18 The figure depicts a flowchart of an example process for fabricating a flip-chip quantum computing device according to an illustrative embodiment. In one or more embodiments, process 1800 is implemented in application 105, which enables the fabrication system (such as...) Figure 1 The manufacturing system 107 in the document performs the operations described herein.

[0139] In block 1802, the application causes the fabrication system to form a first set of pads on the J-chip. In block 1804, the application causes the fabrication system to deposit a first layer on the first set of pads. In block 1806, the application causes the fabrication system to form a set of Josephson junctions on the J-chip, each of the Josephson junctions having a junction resistance (a slightly inductive impedance).

[0140] In block 1808, this application enables the manufacturing system to measure the Josephson junction resistance of each Josephson junction in a set of Josephson junctions formed in block 1806, for example, by electrically probing the Josephson junction resistance of each Josephson junction. This application causes the manufacturing system to calculate a predicted frequency for each qubit, which can be based on a specific Josephson junction having a measured Josephson junction resistance. In one specific embodiment, the design / manufacturing system uses a fitted curve that correlates the Josephson junction resistance with the frequency to calculate the predicted frequency for each qubit, such as... Figure 7 The curve is 700.

[0141] In block 1810, the application causes the fabrication system to select a first subset of the set of Josephson junctions in response to the calculation, to avoid or mitigate potential frequency conflicts between qubits that might be caused by these Josephson junctions in the first subset. In one embodiment, in block 1812, the fabrication system selects a second subset of the second set of pads on the interpolator chip to deposit a second layer. In one embodiment, the second subset of the second set of pads corresponds to the selected first subset of the set of Josephson junctions. In practice, the application causes a mask to be constructed that allows only the pads in the second subset to receive the deposited material of the second layer. The application then causes the photolithography components of the fabrication system to use the mask when depositing the material of the second layer onto the second set of pads.

[0142] In one embodiment, the application causes the manufacturing system to determine a separation gap distance between the interposer chip and the J-chip based on a selected subset of the Josephson junctions, the frequency tuning range, and the sensitivity. In block 1814, the application causes the manufacturing system to join the interposer chip and the J-chip at the determined gap distance to achieve a desired qubit frequency in a flip-chip arrangement. In a particular embodiment, the manufacturing system uses a bump bonding process to join the interposer chip and the J-chip. In other particular embodiments, other suitable methods for permanently or temporarily (removably) joining the interposer chip and the J-chip may be used. Process 1800 then ends.

[0143] See Figure 19 The figure depicts a flowchart of an example process for fabricating a flip-chip quantum computing device according to an illustrative embodiment. In one or more embodiments, process 1800 is implemented in application 105, which enables the fabrication system (such as...) Figure 1 The manufacturing system 107 in the document performs the operations described herein.

[0144] In block 1902, the application enables the manufacturing system to form a first set of pads on the J-chip. In block 1904, the application enables the manufacturing system to deposit a first layer on the first set of pads. In block 1906, the application enables the manufacturing system to form a set of Josephson junctions on the J-chip, each of the Josephson junctions having a junction resistance.

[0145] In block 1908, the application enables the manufacturing system to measure the Josephson junction resistance of each Josephson junction, for example, by electrically probing the Josephson junction resistance of a single Josephson junction. This application causes the manufacturing system to calculate a predicted frequency for each qubit based on the measured Josephson junction resistance. In one specific embodiment, the design / manufacturing system uses a fitted curve that correlates the Josephson junction resistance of a particular Josephson junction with a frequency to calculate the predicted frequency of a qubit to be formed using that Josephson junction, such as... Figure 7 The curve is 700.

[0146] In block 1910, the application causes the fabrication system to select a first subset of the set of Josephson junctions in response to the calculation to avoid potential frequency conflicts in the resulting qubits. In block 1912, in response to the selection, the application causes the fabrication system to remove, disable, or otherwise render unreachable or unusable a second subset of the set of Josephson junctions. In one embodiment, the intersection of the first and second subsets is an empty set. In block 1914, the application causes the fabrication system to deposit a second layer on a second set of pads on an interposer chip. In practice, the application causes a mask to be constructed that allows the pads in the second set to receive the deposited material of the second layer. The application then causes the photolithography components of the fabrication system to use the mask when depositing the material of the second layer onto the second set of pads.

[0147] In one embodiment, the application causes the manufacturing system to determine a separation gap distance between the interposer chip and the J-chip based on a selected subset of the Josephson junctions, the frequency tuning range, and the sensitivity. In block 1916, the manufacturing system joins the interposer chip and the J-chip at the determined gap distance to achieve the desired qubit frequency in a flip-chip arrangement. In a particular embodiment, the application causes the manufacturing system to join the interposer chip and the J-chip using a bump bonding process. In other particular embodiments, other suitable methods for joining the interposer chip and the J-chip may be used. Process 1900 then ends.

[0148] See Figure 20 The figure depicts a flowchart of an example process for fabricating a flip-chip quantum computing device according to an illustrative embodiment. In one or more embodiments, process 1800 is implemented in application 105, which enables the fabrication system (such as...) Figure 1The manufacturing system 107 in the document performs the operations described herein.

[0149] In block 2002, the application enables the manufacturing system to form a first set of pads on the J-chip. In block 2004, the application enables the manufacturing system to deposit a first layer on the first set of pads. In block 2006, the application enables the manufacturing system to deposit a first set of pillar-shaped bumps (protrusions) on the first layer of the J-chip. In block 2008, the application enables the manufacturing system to reach a set of Josephson junctions on the J-chip, each of which has a junction resistance.

[0150] In block 2010, the application causes the manufacturing system to measure the Josephson junction resistance of each Josephson junction, for example, by electrically probing the Josephson junction resistance. The application causes the manufacturing system to calculate a predicted frequency for each qubit generated by one of the Josephson junctions in the group based on the measured Josephson junction resistance. In one specific embodiment, the design / manufacturing system uses a fitted curve that correlates the Josephson junction resistance with the frequency to calculate the predicted frequency for each qubit, such as... Figure 7 The curve is 700.

[0151] In block 2012, the application causes the manufacturing system to select a first subset of the set of Josephson junctions in response to the computation to avoid or mitigate potential frequency conflicts in the qubits caused by these Josephson junctions in the first subset. In block 2014, in response to the selection, the application causes the manufacturing system to remove, disable, or otherwise render a second subset of the set of Josephson junctions inaccessible or unavailable. In one embodiment, the intersection of the first and second subsets is an empty set. In block 2016, the application causes the manufacturing system to deposit a second layer on a second set of pads on the interpolator chip in response to the selection. In one embodiment, the second subset of the second set of pads corresponds to the selected first subset of the qubits. In another embodiment, the manufacturing system deposits a second layer on a second set of pads on an interposer chip.

[0152] In box 2018, the application enables the manufacturing system to form a temporary bond between the interposer chip and the J-chip. In box 2020, the application measures the actual frequency of the set of qubits generated by a first subset of the Josephson junction during cryogenic operation. In box 2022, the application determines whether the actually measured frequency meets a threshold used to avoid frequency collisions.

[0153] In block 2026 (the "No" path of block 2022), the fabrication system alters the frequency of one or more qubits in the group of qubits. In one embodiment, the fabrication system heats the flip-chip assembly, separates the insert chip from the J-chip, and performs a laser annealing process to change the resistance of one or more Josephson junctions in the first subgroup of Josephson junctions. The process then temporarily bonds the interposer chip to the J-chip in the manner of block 2018 and returns to block 2020.

[0154] In block 2024 (the "Yes" path of block 2022), the application enables the manufacturing system to durablely bond the interposer chip and the J-chip at a defined gap distance to achieve the desired qubit frequency in a flip-chip arrangement. In a particular embodiment, the application enables the manufacturing system to persistently or permanently bond the interposer chip and the J-chip using a bump bonding process. In other particular embodiments, other suitable methods for bonding the interposer chip and the J-chip may be used. In one embodiment, the application enables the manufacturing system to determine a separation gap distance between the interposer chip and the J-chip based on a selected subset of the Josephson junctions, the frequency tuning range, and the sensitivity. Process 2000 then ends.

[0155] Different embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of the invention. Although different connections and positional relationships (e.g., top, bottom, above, below, adjacent, etc.) are illustrated between elements in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, while maintaining the function even if the orientation changes. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the invention is not schematically limited in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, reference in this specification to forming layer "A" on layer "B" includes the case where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," provided that the relevant features and functions of layer "A" and layer "B" are substantially not altered by this or these intermediate layers.

[0156] The following definitions and abbreviations are used to interpret the claims and description. As used herein, the terms “comprising (present tense),” “comprising (continuous tense),” “including (present tense),” “comprising (continuous tense),” “having (present tense),” “containing (present tense),” or “containing (continuous tense),” or any other variation thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus comprising a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such compositions, mixtures, processes, methods, articles, or apparatus.

[0157] Additionally, the term "illustrative" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to 2, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0158] References to "an embodiment," "an embodiment," "an exemplary embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that incorporating other embodiments, whether explicitly described or not, to affect such a feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0159] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include the degree of error associated with a measurement based on a specific quantity of equipment available at the time of filing of this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0160] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to the technology found in the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. A method of fabricating a quantum computing device, the method comprising: forming a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate; forming a second chip having a second substrate, a second set of pads arranged on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions, the subset of the set of Josephson junctions selected to avoid frequency collisions between qubits in a group of qubits, the qubits in the group of qubits resulting from Josephson junctions in the subset of Josephson junctions; and forming an unusable Josephson junction in the set of Josephson junctions, wherein responsive to a first Josephson junction being excluded from the subset of the set of Josephson junctions, the first Josephson junction in the set of Josephson junctions is modified to become the unusable Josephson junction.

2. The method of claim 1, further comprising: forming a disconnected pad in the first set of pads, wherein the first set of pads includes a first pad electrically connected to the first Josephson junction, and wherein the first pad is electrically disconnected from the first Josephson junction to form the disconnected pad, the disconnected pad rendering the first Josephson junction unusable.

3. The method of claim 1, wherein an electrical property of the first Josephson junction is modified such that the first Josephson junction no longer functions as a Josephson junction.

4. The method of any of the preceding claims 1-3, wherein the subset of the set of Josephson junctions is selected based on a measurement of a parameter associated with each Josephson junction in the set of Josephson junctions.

5. The method of claim 4, wherein a resonant frequency associated with a qubit is a member selected from the group consisting of: (i) a predicted resonant frequency calculated based on the measured parameter, and (ii) an actual measured resonant frequency of the qubit.

6. The method of claim 4, wherein the parameter comprises a resistance associated with a Josephson junction in the set of Josephson junctions.

7. The method of claim 6, wherein the resistance is a normal state resistance of the Josephson junction.

8. The method of any of the preceding claims 1-3, further comprising: forming a first set of bumps formed on the first chip; and forming a set of bumps formed on the second layer of the second chip, the set of bumps formed from a material having a higher ductility than a threshold value in a room temperature range, wherein the set of bumps is configured to cold weld to the first set of bumps.

9. The method of claim 8, wherein the first set of bumps has at least one selected from the group consisting of gold and platinum. the set of bumps is at least one selected from the group consisting of indium, tin, lead, and bismuth.

10. The method of claim 8, wherein, 11. The method of claim 8, further comprising: ​ forming a flip chip assembly including the first chip removably attached to the second chip using the cold weld, wherein parameters of Josephson junctions within the flip chip assembly are adjustable by disassembling the flip chip assembly with the cold weld.

12. The method of any one of claims 1 to 3, wherein, The method is a computer-implemented method.

13. A superconductor fabrication system comprising a photolithography assembly, the superconductor fabrication system fabricating, when operating on at least one die, a quantum computing device for performing the method of any one of claims 1-12.

14. A method of fabricating a quantum processor, the method comprising: forming a group of qubits, at least one qubit in the group of qubits formed in a flip chip configuration, the flip chip configuration including a pair of chips, forming the pair of chips including: forming a first chip, the first chip having a first substrate, a first set of pads, and a group of Josephson junctions disposed on the first substrate; and forming a second chip, the second chip having a second substrate, a second set of pads arranged on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer configured to join the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the group of Josephson junctions, the subset of the group of Josephson junctions selected to avoid frequency collisions between qubits in the group of qubits, the qubits in the group of qubits resulting from Josephson junctions in the subset of Josephson junctions, wherein an unusable Josephson junction is formed in the group of Josephson junctions, wherein in response to a first Josephson junction being excluded from the subset of the group of Josephson junctions, the first Josephson junction in the group of Josephson junctions is modified to become the unusable Josephson junction.

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