LED chip package and method of manufacturing the same

Abstract

A light emitting package includes a first LED sub-unit having a first surface and a second surface facing away, a second LED sub-unit disposed on the second surface of the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a plurality of connection electrodes having side surfaces and electrically connected to at least one of the LED sub-units, the connection electrodes covering the side surfaces of the at least one of the LED sub-units, a first passivation layer surrounding at least the side surfaces of the connection electrodes, the first passivation layer exposing at least a portion of the first surface of the first LED sub-unit, a base having a first surface and a second surface facing away, the first surface of the base facing the LED sub-units, and a first electrode disposed on the first surface of the base and connected to at least one of the at least one connection electrode.

Description

TECHNICAL FIELD

[0001] Exemplary embodiments of the present invention relate to a light emitting chip for a display and a manufacturing method thereof, and more particularly, to a micro light emitting chip having a stacked structure and a manufacturing method thereof. BACKGROUND

[0002] As an inorganic light source, a light emitting diode (LED) has been used in various technical fields such as displays, vehicle lamps, general lighting, etc. With the advantages of long lifespan, low power consumption, and high response speed, light emitting diodes have rapidly replaced existing light sources.

[0003] Light emitting diodes have been mainly used as a backlight light source in display devices. However, recently, a micro LED display capable of directly implementing an image using light emitting diodes has been developed.

[0004] Generally, a display device implements various colors by using light of mixed colors of blue, green, and red light. The display device includes a pixel each having sub-pixels corresponding to blue, green, and red colors, and the color of a certain pixel can be determined based on the colors of the sub-pixels in the certain pixel, and an image can be displayed by selective activation of a combination of pixels.

[0005] Since an LED can emit various colors according to its constituent material, a display device can generally have independent LED chips emitting blue, green, and red light arranged on a two-dimensional plane. However, when one LED chip is provided for each sub-pixel, the number of LED chips to be mounted to form a display device becomes very large (e.g., more than several hundreds of thousands or millions), which can require a large amount of time and complexity for a mounting process. In addition, since the sub-pixels are arranged on a two-dimensional plane in the display device, a relatively large area is required for one pixel including sub-pixels for blue, green, and red light, and reducing the light emitting area of each sub-pixel will deteriorate the brightness of the sub-pixel.

[0006] In addition, a micro LED generally has a very small size with a surface area of about 10,000 square μm or less, and thus various technical problems arise due to the small size. For example, an array of micro LEDs is formed on a substrate, and the micro LEDs can be monolithically singulated into each micro LED chip by cutting the substrate. The individual micro LED chips can then be mounted on another substrate (e.g., a printed circuit board), during which various transfer techniques can be employed. However, the handling of each micro LED chip during these transfer steps is generally difficult due to its small size and its fragile structure. In addition, electrodes formed on a target substrate, such as a target substrate of a display device, are generally spaced apart from each other at a pitch corresponding to the pitch of electrodes of a conventional pixel having a plurality of sub-pixels arranged on a two-dimensional plane.

[0007] The above information disclosed in this Background section is only for understanding of the background of the inventive concept and thus it may contain information that does not constitute prior art. SUMMARY

[0008] TECHNICAL PROBLEM

[0009] A light emitting chip constructed according to the principles of the present invention and some exemplary embodiments is capable of protecting a light emitting stack structure during various transfer processes.

[0010] A light emitting chip (e.g., micro-LED) and a display using the same constructed according to the principles of the present invention and some exemplary embodiments have a simplified structure that reduces the time for a mounting process during manufacturing.

[0011] A light emitting chip (e.g., micro-LED) constructed according to the principles of the present invention and some exemplary embodiments is capable of being mounted on a conventional display device with an enhanced internal structure that facilitates handling and transfer.

[0012] A light emitting chip (e.g., micro-LED) constructed according to the principles of the present invention and some exemplary embodiments is capable of being mounted on a conventional display device with an enhanced internal structure that facilitates handling and transfer.

[0013] A light emitting package (e.g., micro-LED) constructed according to the principles of the present invention and some exemplary embodiments has increased light efficiency and color purity achieved by removing a substrate of a light emitting stack structure, such as a growth substrate of one of the LED stacks.

[0014] Additional features of the invention will be set forth in the description that follows, and in part will become apparent from the description, or can be learned by practice of the invention concepts.

[0015] TECHNICAL SOLUTION

[0016] A light emitting package according to an exemplary embodiment includes a first LED sub-unit having a first surface facing away and a second surface, a second LED sub-unit disposed on the second surface of the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a plurality of connection electrodes having side surfaces and electrically connected to at least one of the first, second, and third LED sub-units, the plurality of connection electrodes covering the side surfaces of at least one of the first, second, and third LED sub-units, a first passivation layer surrounding at least the side surfaces of the plurality of connection electrodes, the first passivation layer exposing at least a portion of the first surface of the first LED sub-unit, a substrate having a first surface facing away and a second surface, the first surface of the substrate facing the LED sub-units, and a first electrode disposed on the first surface of the substrate and connected to at least one of the plurality of connection electrodes.

[0017] The plurality of connection electrodes can be superposed with at least one of the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit.

[0018] The light emitting package can further include a second passivation layer contacting side surfaces of at least some of the plurality of connection electrodes.

[0019] The second passivation layer can be disposed between the plurality of connection electrodes.

[0020] The first passivation layer can include at least one of a black epoxy molding compound and a polyimide film.

[0021] The first electrode can include a plurality of contact electrodes each spaced apart from each other by a first distance and corresponding to one of the plurality of connection electrodes, and the light emitting package can further include a second electrode disposed on the second surface of the substrate, each of the second electrode being spaced apart from each other by a second distance and connected to a corresponding one of the plurality of contact electrodes, the second distance can be greater than the first distance.

[0022] The first passivation layer and the second passivation layer can include different materials.

[0023] The first LED sub-unit can include a first LED light emitting stack, the second LED sub-unit can include a second LED light emitting stack, and the third LED sub-unit can include a third LED light emitting stack, the first, second, and third LED light emitting stacks can have areas superposed with the substrate sequentially decreasing in size, and at least one of the LED light emitting stacks can include a micro LED having a surface area less than about 10,000 square µm.

[0024] The light emitting package can further include a second passivation layer disposed between the plurality of connection electrodes and the third LED sub-unit, wherein an angle defined between a side surface of the second passivation layer and the first surface of the first LED sub-unit can be less than about 80°.

[0025] At least one of the plurality of connection electrodes can cover at least the side surface and the top surface of the second passivation layer.

[0026] A light emitting package according to another exemplary embodiment includes a first LED sub-unit having a first surface facing away and a second surface, a second LED sub-unit disposed on the second surface of the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a plurality of connection electrodes having side surfaces and electrically connected to at least one of the first, second, and third LED sub-units, the plurality of connection electrodes covering the side surfaces of at least one of the first, second, and third LED sub-units, a first passivation layer at least surrounding the side surfaces of the plurality of connection electrodes and having a portion covering at least part of the first surface of the first LED sub-unit, a substrate having a first surface facing away and a second surface, the first surface of the substrate facing the LED sub-units, and a first electrode disposed on the first surface of the substrate and connected to at least one of the plurality of connection electrodes.

[0027] The portion of the first passivation layer covering the first surface of the first LED sub-unit can have a thickness less than about 100 µm.

[0028] The first passivation layer can contact the first surface of the first LED sub-unit.

[0029] The light emitting package can further include a second electrode disposed on the second surface of the substrate and connected to the first electrode, wherein the second electrode can include a first portion overlapping at least one of the LED sub-units and having a first area, and a second portion not overlapping at least one of the LED sub-units and having a second area greater than the first area.

[0030] The light emitting package can further include a second passivation layer contacting at least the side surfaces of the connection electrodes.

[0031] The first passivation layer and the second passivation layer can include different materials.

[0032] At least one of the plurality of connection electrodes can contact a side surface and a top surface of the second passivation layer.

[0033] At least one of the plurality of connection electrodes can have an angled shape.

[0034] The first passivation layer can be disposed between the plurality of connection electrodes.

[0035] At least one connection electrode of the plurality of connection electrodes can have a first surface facing away and a second surface, the first surface of the at least one connection electrode facing the LED sub-units, the first surface of the at least one connection electrode can have an area greater than an area of the second surface of the at least one connection electrode.

[0036] It will be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description serve to explain the principles of the application.

[0038] Figure 1 is a schematic cross-sectional view of a light emitting package constructed in accordance with an exemplary embodiment of the application.

[0039] Figure 2 is a schematic cross-sectional view of a light emitting package constructed in accordance with another exemplary embodiment of the application.

[0040] Figure 3 is a schematic cross-sectional view of a light emitting stack structure constructed in accordance with an exemplary embodiment.

[0041] Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A are plan views showing a process of manufacturing a light emitting chip according to exemplary embodiments.

[0042] Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B are cross-sectional views taken along line A-A' of their corresponding plan views shown in Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A are schematic cross-sectional views taken along line A-A' and line B-B' of

[0043] Figure 3 is a schematic plan view showing a process of manufacturing a light emitting chip according to exemplary embodiments, Figure 4A and Figure 4B are schematic cross-sectional views taken along line A-A' and line B-B' of Figure 5A

[0044] Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A and Figure 8B ​is a schematic cross-sectional view illustrating a process of manufacturing a light emitting package according to an exemplary embodiment. Figure 9A

[0045] Figure 9B is a schematic cross-sectional view illustrating a process of manufacturing a light emitting package according to another exemplary embodiment. Figure 10A

[0046] Figure 10B is a schematic cross-sectional view of a light emitting package constructed according to an exemplary embodiment of the present invention.

[0047] Figure 10C is a schematic cross-sectional view of a light emitting package constructed according to another exemplary embodiment of the present invention.

[0048] Figure 10A and Figure 11 is a plan view illustrating a process of manufacturing a light emitting chip according to another exemplary embodiment.

[0049] Figure 12 and Figure 13 is a cross-sectional view taken along line A-A' of the corresponding plan view illustrated in Figure 14 and Figure 15

[0050] Figure 16 and Figure 17 is a schematic cross-sectional view illustrating a process of manufacturing a light emitting package according to an exemplary embodiment.

[0051] Figure 1 , Figure 18 , Figure 2 , Figure 19 and Figure 20 is a schematic cross-sectional view illustrating a process of manufacturing a light emitting package according to an exemplary embodiment. Figure 21A

[0052] Figure 22A is a schematic cross-sectional view illustrating a process of manufacturing a light emitting package according to another exemplary embodiment. Figure 21B DETAILED DESCRIPTION

[0053] ​​​​​In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable terms that refer to a non-limiting example of an apparatus or method that employs one or more of the inventive concepts disclosed herein. It will be apparent, however, that various exemplary embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, various exemplary embodiments can be different, but need not be mutually exclusive. For example, specific shapes, configurations, and characteristics of an exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concepts.

[0054] Unless otherwise indicated, the exemplary embodiments shown are to be understood as providing illustrative features that vary details of some ways in which the inventive concepts can be implemented in practice. Thus, unless otherwise indicated, features, components, modules, layers, films, panels, regions, and / or aspects of various embodiments (hereinafter, individually or collectively referred to as "elements") can be combined, separated, interchanged, and / or rearranged, among others, without departing from the inventive concepts.

[0055] The use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries and / or regions of the particular elements being portrayed more clearly understood. As such, the presence of

[0056] When an element (such as a layer) is referred to as being “on” another element, or “connected to” or “coupled to” another element, it can be directly on the other element or directly connected or coupled to the other element, or one or more intervening elements can be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. In this regard, the term “connected” can mean physical, electrical, and / or fluidic connection, with or without intervening elements. Also, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a straight rectangular coordinate system (e.g., the x-axis, the y-axis, and the z-axis), and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any one of X, Y, and Z only, or any combination of any two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ, for example. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0057] Although the terms “first,” “second,” etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

[0058] Spatially relative terms such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” “on,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like can be used herein for descriptive purposes, and by this description, can encompass different orientations of the device in use, operation, and / or manufacture in the description of the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms "including," "containing," "comprising," "having," and the like are used herein to mean that there are no restrictions on the presence of other steps, elements, components, members, and / or limitations, but that other steps, elements, components, members, and / or limitations are optional. It also is noted that the terms "substantial," "approximately," and other similar terms are used herein to mean that a deviation of ±20% is acceptable, unless otherwise indicated.

[0060] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of idealized embodiments and / or intermediate structures of the exemplary embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments disclosed herein are not to be construed as being limited to the particular shapes of regions illustrated in the drawings as a strict matter of construction. Indeed, the regions illustrated in the drawings are schematic and are not to be interpreted as being limiting in any way as to the actual shapes of the regions that would be expected to result from, for example, manufacturing techniques and / or tolerances. In this manner, a region that is schematically illustrated as a rectangle can have the shape of a rectangle or other shape, such as an oval, based on manufacturing techniques and / or tolerances.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs as a result of his / her general knowledge. The terms, such as those defined in a generally used dictionary, should be interpreted as having a meaning that is consistent with its meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0062] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As used herein, a light emitting stack structure, a light emitting chip, a light emitting package, or a light emitting module according to exemplary embodiments can include a micro LED having a surface area of less than about 10,000 square μm known in the art. In other exemplary embodiments, the micro LED can have a surface area of less than about 4,000 square μm or less than about 2,500 square μm according to a specific application.

[0063] Figure 22B is a schematic cross-sectional view of a light emitting package constructed according to exemplary embodiments of the present invention.

[0064] Referring to Figure 21AThe light emitting package 110 according to the illustrated exemplary embodiment includes the light emitting chip 100, the passivation layer 90 surrounding at least sides of the light emitting chip 100, the molding layer 91 surrounding at least sides of the passivation layer 90, and the circuit board 11p. An array of light emitting chips can be formed on a substrate, including in Figure 22A The light emitting chip 100 in the light emitting package 110 of FIG. 1A is illustratively shown as a light emitting chip that has been singulated from an array, and then the singulated light emitting chip is further processed to form the light emitting package 110.

[0065] The light emitting chip 100 according to the exemplary embodiment can include at least two or more light emitting sub-units or light emitting stacks, such as one disposed on another in a vertical direction. In this way, the light emitting chip 100 can display various colors of light according to an operating state of each light emitting stack, whereas a conventional light emitting device can display various colors by a combination of a plurality of light emitting units that emit monochromatic light. More specifically, a conventional light emitting device typically includes light emitting units that respectively emit different colors of light (e.g., red, green, and blue light) spaced apart from one another along a two-dimensional plane to achieve full color display. As such, a conventional light emitting unit occupies a relatively large area. However, the light emitting chip 100 constructed according to the exemplary embodiment can emit light having various colors by stacking a plurality of light emitting stacks, thereby providing high integration by a significantly smaller area than in a conventional light emitting device and achieving a full color spectrum.

[0066] Further, when the light emitting chip 100 including the light emitting stack structure is mounted to another substrate to manufacture a display device, the number of chips to be mounted can be significantly reduced compared to a conventional light emitting device, for example, due to its stacked structure. As such, especially when tens or hundreds of thousands of pixels are formed in one display device, the manufacturing of a display device employing the light emitting stack structure can be significantly simplified. The light emitting chip 100 can include a light emitting stack structure as shown in Figure 23 which includes three light emitting stacks and a plurality of connection electrodes connected to the light emitting stacks, which will be described in greater detail below.

[0067] According to the exemplary embodiment, the passivation layer 90 can be formed around the light emitting stack structure. More specifically, as Figure 24As illustrated in the middle, a passivation layer 90 can be formed between the connection electrodes of the light emitting stack structure. According to the illustrated exemplary embodiment, the passivation layer 90 can be formed to be substantially flush with the top surfaces of the connection electrodes, and can include an epoxy molding compound (EMC) that can be formed to have various colors such as black or transparent, without being limited thereto. However, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the passivation layer 90 can include polyimide (PID), and in this case, the PID can be provided as a dry film rather than a liquid type to increase the level of flatness when applied to the light emitting stack structure. In some exemplary embodiments, the passivation layer 90 can include a material having photosensitivity. In this way, the passivation layer 90 can protect the light emitting structure from external impacts that can be applied during subsequent processes, as well as provide sufficient contact area to the light emitting chip 100 to facilitate its handling during subsequent transfer steps. In addition, the passivation layer 90 can prevent leakage of light toward the side surfaces of the light emitting chip 100 to prevent or at least inhibit interference of light emitted from the adjacent light emitting chip 100.

[0068] The molding layer 91 can surround at least the side surfaces of the light emitting chip 100 to protect the light emitting chip 100 from external impacts. According to the illustrated exemplary embodiment, the molding layer 91 can expose at least one surface of the light emitting chip 100 to increase light efficiency and color purity. In this case, since the substrate on which the light emitting stack structure is grown has been removed in the illustrated exemplary embodiment, the light emitted from the light emitting package 110 can have increased brightness and purity. According to the exemplary embodiment, the molding layer 91 can include an organic polymer or an inorganic polymer. In some exemplary embodiments, the molding layer 91 can include substantially the same material as that of the passivation layer 90. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the molding layer 91 and the passivation layer 90 can include different materials from each other.

[0069] The circuit board 11p can include lower circuit electrodes 11pa, middle circuit electrodes 11pb, and upper circuit electrodes 11pc connected to each other. The upper circuit electrodes 11pc can be spaced apart from each other at a predetermined pitch P. For example, the pitch (or distance) between the upper circuit electrodes 11pc can correspond to the pitch (or distance) of the electrodes of a target substrate such as a display device. In this way, the light emitting package 110 according to the exemplary embodiment can be mounted on a conventional display device without changing the configuration of the target substrate of the display device.

[0070] Figure 25 is a schematic cross-sectional view of a light emitting package according to another exemplary embodiment.

[0071] Referring to Figure 26 , the light emitting package 120 according to the illustrated exemplary embodiment is the same as the light emitting package 110 except for the shape of the molding layer 91.Figure 27 The light-emitting package 110 is substantially the same. More specifically, according to the exemplary embodiment shown, a molding layer 91 covers the top surface of the light-emitting chip 100. In this way, the molding layer 91 can protect the light-emitting chip 100 from external particles (such as dust and moisture) or external impacts that penetrate into the light-emitting stack structure, and can also prevent external light from being reflected from the substrate 11 toward the user. Furthermore, when as Figure 28 When the molding layer 91 shown covers the top surface of the light-emitting chip 100, the light transmittance can be controlled by adjusting the thickness of the molding layer 91 or by forming the molding layer 91 with a material that provides the desired light transmittance. Since, apart from the shape of the molding layer 91, the light-emitting package 120 and... Figure 29 The light-emitting package 110 is substantially the same as that of the light-emitting package 120, so repeated descriptions of the constituent elements of the light-emitting package 120 will be omitted to avoid redundancy.

[0072] Figure 19 This is a schematic cross-sectional view of a light-emitting stacked structure constructed according to an exemplary embodiment.

[0073] Reference Figure 30 The light-emitting stack structure according to the illustrated exemplary embodiment includes a first LED sub-unit, a second LED sub-unit, and a third LED sub-unit disposed on a substrate 11. The first LED sub-unit may include a first light-emitting stack 20, the second LED sub-unit may include a second light-emitting stack 30, and the third LED sub-unit may include a third light-emitting stack 40. Although the figures show a light-emitting stack structure including three light-emitting stacks 20, 30, and 40, the inventive concept is not limited to the specific number of light-emitting stacks formed in the light-emitting stack structure. For example, in some exemplary embodiments, the light-emitting stack structure may include two or more light-emitting stacks. Hereinafter, the light-emitting stack structure will be described with reference to the light-emitting stack structure including three light-emitting stacks 20, 30, and 40 according to an exemplary embodiment.

[0074] The substrate 11 can include a light-transmissive insulating material to transmit light therethrough. However, in some exemplary embodiments, the substrate 11 can be formed to be semi-transparent to transmit only light having a specific wavelength, or to be partially transparent to transmit only a portion of light having a specific wavelength. The substrate 11 can be a growth substrate capable of epitaxially growing the third light emitting stack 40 thereon, for example, a sapphire substrate. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the substrate 11 can include various other transparent insulating materials. For example, the substrate 11 can include glass, quartz, silicon, an organic polymer, or an organic-inorganic composite material, for example, silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium oxide (Ga2O3), or a silicon substrate. As another example, the substrate 11 in some exemplary embodiments can be a printed circuit board or a composite substrate including electrical lines therein, the electrical lines for providing a light emitting signal and a common voltage to each of the light emitting stacks formed on the printed circuit board or the composite substrate.

[0075] Each of the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 is configured to emit light toward the substrate 11. As such, light emitted from the first light emitting stack 20 can pass through the second light emitting stack 30 and the third light emitting stack 40, for example. According to exemplary embodiments, light emitted from each of the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 can have different wavelength bands from each other, and the further away from the substrate 11 a light emitting stack is disposed, the longer wavelength light the light emitting stack can emit. For example, the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 can emit red light, green light, and blue light, respectively. However, the inventive concept is not limited thereto. As another example, the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 can emit red light, blue light, and green light, respectively. On the other hand, when the substrate 11 is removed from the light emitting chip 100 as shown in FIG. 1B, the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 of the light emitting stack structure can be considered to be sequentially disposed in the order of the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40. Figure 20 Figure 1 ​The first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 can emit green light, blue light, and red light, respectively. As another example, one or more of the light emitting stacks can emit light having substantially the same wavelength band. As yet another example, when the light emitting stack structure includes micro-LEDs (micro-LEDs having a surface area less than about 10,000 square µm as known in the art or having a surface area less than about 4,000 or 2,500 square µm in other exemplary embodiments), due to the small form factor of the micro-LEDs, the light emitting stacks disposed farther from the substrate 11 can emit light having a shorter wavelength band than the light emitted from the light emitting stacks disposed closer to the substrate 11 without adversely affecting operation. In this case, the micro-LEDs can be operated at a low operating voltage, and thus, a separate color filter can not be needed between the light emitting stacks. Hereinafter, the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 will be exemplarily described as emitting red light, green light, and blue light, respectively, according to exemplary embodiments.

[0076] The first light emitting stack 20 includes a first-type semiconductor layer 21, an active layer 23, and a second-type semiconductor layer 25. According to exemplary embodiments, the first light emitting stack 20 can include a semiconductor material emitting red light such as aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), and gallium phosphide (GaP), but is not limited thereto. A first lower contact electrode 25p can be disposed under the second-type semiconductor layer 25 of the first light emitting stack 20.

[0077] The second light emitting stack 30 includes a first-type semiconductor layer 31, an active layer 33, and a second-type semiconductor layer 35. According to exemplary embodiments, the second light emitting stack 30 can include a semiconductor material emitting green light such as indium gallium nitride (InGaN), gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indium phosphide (AlGaInP), and aluminum gallium phosphide (AlGaP), but is not limited thereto. A second lower contact electrode 35p is disposed under the second-type semiconductor layer 35 of the second light emitting stack 30.

[0078] The third light emitting stack 40 includes a first-type semiconductor layer 41, an active layer 43, and a second-type semiconductor layer 45. According to exemplary embodiments, the third light emitting stack 40 can include a semiconductor material emitting blue light such as gallium nitride (GaN), indium gallium nitride (InGaN), and zinc selenide (ZnSe), but is not limited thereto. A third lower contact electrode 45p is disposed on the second-type semiconductor layer 45 of the third light emitting stack 40.

[0079] According to exemplary embodiments, each of the first type semiconductor layers 21, 31, 41 and each of the second type semiconductor layers 25, 35, 45 of the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 can have a single layer structure or a multi-layer structure, and in some exemplary embodiments can include superlattice layers. Further, the active layers 23, 33, and 43 of the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 can have a single quantum well structure or a multi-quantum well structure.

[0080] Each of the first lower contact electrode 25p, the second lower contact electrode 35p, and the third lower contact electrode 45p can include a transparent conductive material to transmit light. For example, the lower contact electrodes 25p, 35p, and 45p can include a transparent conductive oxide (TCO) such as tin oxide (SnO), indium oxide (InO2), zinc oxide (ZnO), indium tin oxide (ITO), and indium tin zinc oxide (ITZO), but are not limited thereto.

[0081] The first adhesive layer 61 is disposed between the first light emitting stack 20 and the second light emitting stack 30, and the second adhesive layer 63 is disposed between the second light emitting stack 30 and the third light emitting stack 40. The first adhesive layer 61 and the second adhesive layer 63 can include a non-conductive material that transmits light. For example, the first adhesive layer 61 and the second adhesive layer 63 can each include an optical clear adhesive (OCA) that can include an epoxy, a polyimide, SU8, a spin-on glass (SOG), a benzocyclobutene (BCB), or others, but are not limited thereto.

[0082] According to exemplary embodiments, each of the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 can be independently driven. More specifically, one of the first type semiconductor layers and the second type semiconductor layers of each light emitting stack can be applied with a common voltage Sc, and the other of the first type semiconductor layers and the second type semiconductor layers of each light emitting stack can be applied with a respective light emitting signal S R , S G , and S B . For example, according to the illustrated exemplary embodiments, the first type semiconductor layers 21, 31, and 41 of each light emitting stack can be n-type, and the second type semiconductor layers 25, 35, and 45 of each light emitting stack can be p-type. In this case, the third light emitting stack 40 can have an opposite stacking order compared to the first light emitting stack 20 and the second light emitting stack 30, such that the p-type semiconductor layer 45 is disposed on top of the active layer 43 to simplify the manufacturing process. Hereinafter, according to the illustrated exemplary embodiments, the first type semiconductor layers and the second type semiconductor layers can be interchangeably referred to as p-type semiconductor layers and n-type semiconductor layers, respectively.

[0083] Although the light emitting stack structure according to the illustrated exemplary embodiments has a common p-type structure, however, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the first type semiconductor layers 21, 31, and 41 of each light emitting stack can be p-type, and the second type semiconductor layers 25, 35, and 45 of each light emitting stack can be n-type, to form a common n-type light emitting stack structure. Also, in some exemplary embodiments, the stacking order of each light emitting stack can be variously modified, without being limited to the stacking order illustrated in the drawings. Hereinafter, the light emitting stack structure according to the illustrated exemplary embodiments will be described with reference to a common p-type light emitting stack structure.

[0084] According to exemplary embodiments, the light emitting stack structure can further include various additional components to improve the purity and efficiency of light emitted therefrom. For example, in some exemplary embodiments, a wave pass filter can be formed between adjacent light emitting stacks to prevent or at least inhibit light having a shorter wavelength from traveling toward a light emitting stack that emits a longer wavelength. Also, in some exemplary embodiments, a concavo-convex portion can be formed on a light emitting surface of at least one of the light emitting stacks to balance the brightness of light between the light emitting stacks. For example, since green light generally has higher visibility than red and blue light, in some exemplary embodiments, a concavo-convex portion can be formed on a light emitting stack that emits red or blue light to improve its light efficiency, thereby balancing the visibility between light emitted from the light emitting stacks.

[0085] Hereinafter, a method of forming a light emitting chip according to exemplary embodiments will be described with reference to the accompanying drawings.

[0086] Figure 1 , Figure 1 , Figure 3 , Figure 1 , Figure 2 and Figure 2 are plan views illustrating a process of manufacturing a light emitting chip according to exemplary embodiments. Figure 1 , Figure 2 , Figure 1 , Figure 3 , Figure 3 and Figure 1 are cross-sectional views taken along line A-A' of their corresponding plan views illustrated in Figure 1 , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A are cross-sectional views taken along line A-A' of their corresponding plan views illustrated in

[0087] Referring back to Figure 9AThe first-type semiconductor layer 41, the active layer 43, and the second-type semiconductor layer 45 of the third light emitting stack 40 can be sequentially grown on the substrate 11 by, for example, a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. The third lower contact electrode 45p can be formed on the second-type semiconductor layer 45 by, for example, a physical vapor deposition method or a chemical vapor deposition method, and can include a transparent conductive oxide (TCO). When the third light emitting stack 40 emits blue light according to an exemplary embodiment, the substrate 11 can include Al2O3 (e.g., a sapphire substrate), and the third lower contact electrode 45p can include a transparent conductive oxide (TCO) such as tin oxide (SnO), indium oxide (InO2), zinc oxide (ZnO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), etc., without being limited thereto. The first light emitting stack 20 and the second light emitting stack 30 can be similarly formed by sequentially growing a first-type semiconductor layer, an active layer, and a second-type semiconductor layer on a temporary substrate, respectively, and a lower contact electrode including a transparent conductive oxide can be formed on a second-type semiconductor layer by, for example, a physical vapor deposition method or a chemical vapor deposition method, etc., respectively.

[0088] According to an exemplary embodiment, at least one of the temporary substrates of the first light emitting stack 20 and the second light emitting stack 30 can be removed by, for example, a laser lift-off process, a chemical process, a mechanical process, etc., when the first light emitting stack 20 and the second light emitting stack 30 are made to be adjacent to each other and the first adhesive layer 61 is disposed between the first light emitting stack 20 and the second light emitting stack 30. In this case, in some exemplary embodiments, a concavo-convex portion can be formed on the exposed light emitting stack to improve light efficiency. Then, the first light emitting stack 20 and the second light emitting stack 30 can be made to be adjacent to the third light emitting stack 40 and the second adhesive layer 63 is disposed between the first light emitting stack 20 and the second light emitting stack 30 and the third light emitting stack 40, and the remaining one of the temporary substrates of the first light emitting stack 20 and the second light emitting stack 30 can be removed by, for example, a laser lift-off process, a chemical process, a mechanical process, etc. In this case, in some exemplary embodiments, a concavo-convex portion can be formed on the remaining exposed light emitting stack to improve light efficiency.

[0089] In another exemplary embodiment, a second adhesive layer 63 can be formed on the third light emitting stack 40. Then, the second light emitting stack 30 can be brought into abutment with the third light emitting stack 40 with the second adhesive layer 63 interposed therebetween, and the temporary substrate of the second light emitting stack 30 can be removed through a laser lift-off process, a chemical process, a mechanical process, etc. Then, a first adhesive layer 61 can be formed on the second light emitting stack 30. Then, the first light emitting stack 20 can be brought into abutment with the second light emitting stack 30 with the first adhesive layer 61 interposed therebetween. Once the first light emitting stack 20 is bonded to the second light emitting stack 30 bonded to the third light emitting stack 40, the temporary substrate of the first light emitting stack 20 can be removed through a laser lift-off process, a chemical process, a mechanical process, etc.

[0090] Referring to Figure 4B and Figure 5B Each of the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40 can be patterned via an etching process, etc. to expose portions of the first-type semiconductor layer 21, the first lower contact electrode 25p, the first-type semiconductor layer 31, the second lower contact electrode 35p, the third lower contact electrode 45p, and the first-type semiconductor layer 41. According to the illustrated exemplary embodiment, the first light emitting stack 20 has the smallest area among the light emitting stacks 20, 30, and 40. However, the inventive concept is not limited to the relative sizes of the light emitting stacks 20, 30, and 40.

[0091] Referring to Figure 6B and Figure 7B A portion of a top surface of the first-type semiconductor layer 21 of the first light emitting stack 20 can be patterned, such as via a wet etching, at which a first upper contact electrode 21n can be formed. In this way, the level of ohmic contact between the first-type semiconductor layer 21 and the first upper contact electrode 21n can be increased. The first upper contact electrode 21n can have a single-layer structure or a multi-layer structure, and can include Al, Ti, Cr, Ni, Au, Ag, Sn, W, Cu, or alloys thereof, such as an Au-Te alloy or an Au-Ge alloy, without being limited thereto. In an exemplary embodiment, the first upper contact electrode 21n can have a thickness of about 100 nm, and include a metal having a high reflectivity to increase light emitting efficiency in a downward direction toward the substrate 11.

[0092] Referring to Figure 8B and Figure 9BA first insulating layer 81 can be disposed on at least a portion of the side surfaces of the first, second, and third light emitting stacks 20, 30, and 40. The first insulating layer 81 can include various organic or inorganic insulating materials, such as polyimide, SiO2, SiN x , Al2O3, etc. For example, the first insulating layer 81 can include a distributed Bragg reflector (DBR). As another example, the first insulating layer 81 can include a black organic polymer. In some example embodiments, a metal reflective layer that is electrically floating can be further disposed on the first insulating layer 81 to reflect light emitted from the light emitting stacks 20, 30, and 40 toward the substrate 11. In some example embodiments, the first insulating layer 81 can have a single layer structure or a multi-layer structure formed of two or more insulating layers having different refractive indexes from each other.

[0093] According to example embodiments, portions of the first insulating layer 81 can be removed to form first, second, third, and fourth contact holes 20CH, 30CH, 40CH, and 50CH. The first contact hole 20CH is defined on the first upper contact electrode 21n to expose a portion of the first upper contact electrode 21n. The second contact hole 30CH can expose a portion of the first-type semiconductor layer 31 of the second light emitting stack 30. The third contact hole 40CH can expose a portion of the first-type semiconductor layer 41 of the third light emitting stack 40. The fourth contact hole 50CH can expose portions of the first, second, and third lower contact electrodes 25p, 35p, and 45p. The fourth contact hole 50CH can include a second sub-contact hole 50CHb that exposes the first lower contact electrode 25p and a first sub-contact hole 50CHA that exposes a portion of the second and third lower contact electrodes 35p and 45p. However, in some example embodiments, a single first sub-contact hole 50CH can expose each of the first, second, and third lower contact electrodes 25p, 35p, and 45p.

[0094] Referring to Figure 4A and Figure 5A , first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are formed on the first insulating layer 81 in which the first, second, third, and fourth contact holes 20CH, 30CH, 40CH, and 50CH are formed. The first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd can be formed by, for example, forming a conductive layer on substantially the entire surface of the substrate 11 and patterning the conductive layer using a photolithography process or the like.

[0095] The first pad 20pd is formed to be superposed with a region where the first contact hole 20CH is formed, so that the first pad 20pd can be connected to the first upper contact electrode 21n of the first light emitting stack 20 through the first contact hole 20CH. The second pad 30pd is formed to be superposed with a region where the second contact hole 30CH is formed, so that the second pad 30pd can be connected to the first type semiconductor layer 31 of the second light emitting stack 30 through the second contact hole 30CH. The third pad 40pd is formed to be superposed with a region where the third contact hole 40CH is formed, so that the third pad 40pd can be connected to the first type semiconductor layer 41 of the third light emitting stack 40 through the third contact hole 40CH. The fourth pad 50pd is formed to be superposed with a region where the fourth contact hole 50CH is formed, more particularly, a region where the first sub-contact hole 50CHa and the second sub-contact hole 50CHb are formed, so that the fourth pad 50pd can be connected to the first lower contact electrode 25p of the first light emitting stack 20, the second lower contact electrode 35p of the second light emitting stack 30, and the third lower contact electrode 45p of the third light emitting stack 40 through the first sub-contact hole 50CHa and the second sub-contact hole 50CHb.

[0096] Referring to Figure 6A and Figure 7A A second insulating layer 83 can be formed on the first insulating layer 81. The second insulating layer 83 can include various organic insulating materials or inorganic insulating materials, such as polyimide, SiO2, SiN x , Al2O3, etc. For example, the second insulating layer 83 can include a distributed Bragg reflector (DBR). As another example, the second insulating layer 83 can include a black organic polymer. In some example embodiments, a metal reflective layer electrically floating can be further provided on the second insulating layer 83 to reflect light emitted from the light emitting stacks 20, 30, and 40 toward the substrate 11. In some example embodiments, the second insulating layer 83 can have a single layer structure or a multi-layer structure formed of two or more insulating layers having different refractive indexes from each other. The second insulating layer 83 is then patterned and first, second, third, and fourth through-holes 20ct, 30ct, 40ct, and 50ct are formed therein.

[0097] The first via hole 20ct formed on the first pad 20pd exposes a portion of the first pad 20pd. The second via hole 30ct formed on the second pad 30pd exposes a portion of the second pad 30pd. The third via hole 40ct formed on the third pad 40pd exposes a portion of the third pad 40pd. The fourth via hole 50ct formed on the fourth pad 50pd exposes a portion of the fourth pad 50pd. In the illustrated exemplary embodiment, the first via hole 20ct, the second via hole 30ct, the third via hole 40ct, and the fourth via hole 50ct can be defined in regions where the first pad 20pd, the second pad 30pd, the third pad 40pd, and the fourth pad 50pd are formed, respectively.

[0098] Referring to Figure 8A and Figure 9A The first bump electrode 20bp, the second bump electrode 30bp, the third bump electrode 40bp, and the fourth bump electrode 50bp are formed on the second insulating layer 83 where the first via hole 20ct, the second via hole 30ct, the third via hole 40ct, and the fourth via hole 50ct are formed. The first bump electrode 20bp is formed to be superposed on a region where the first via hole 20ct is formed, so that the first bump electrode 20bp can be connected to the first pad 20pd through the first via hole 20ct. The second bump electrode 30bp is formed to be superposed on a region where the second via hole 30ct is formed, so that the second bump electrode 30bp can be connected to the second pad 30pd through the second via hole 30ct. The third bump electrode 40bp is formed to be superposed on a region where the third via hole 40ct is formed, so that the third bump electrode 40bp can be connected to the third pad 40pd through the third via hole 40ct.

[0099] The fourth bump electrode 50bp is formed to overlap with a region in which the fourth via hole 50ct is formed, such that the fourth bump electrode 50bp is connected to the fourth pad 50pd through the fourth via hole 50ct. More specifically, the fourth pad 50pd is connected to the second-type semiconductor layers 25, 35, and 45 of the first, second, and third light emitting stacks 20, 30, and 40 through the first and second sub-contact holes 50CHa and 50CHb defined on the first, second, and third lower contact electrodes 25p, 35p, and 45p. Specifically, the fourth pad 50pd is connected to the first lower contact electrode 25p through the second sub-contact hole 50CHb, and is connected to the second and third lower contact electrodes 35p and 45p through the first sub-contact hole 50CHa. In this way, since the fourth pad 50pd can be connected to the second and third lower contact electrodes 35p and 45p through a single first sub-contact hole 50CHa, the manufacturing process of the light emitting chip 100 can be simplified, and the area occupied by the contact hole in the light emitting chip 100 can be reduced. At least a portion of the fourth bump electrode 50bp can overlap with the fourth pad 50pd. The fourth bump electrode 50bp is connected to the fourth pad 50pd through the fourth via hole 50ct in an overlapping region between the fourth bump electrode 50bp and the fourth pad 50pd, with the second insulating layer 83 interposed therebetween.

[0100] The first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp can be formed by depositing a conductive layer on the substrate 11 and patterning the conductive layer, for example, the conductive layer can include at least one of Ni, Ag, Au, Pt, Ti, Al, Cr, Wi, TiW, Mo, Cu, TiCu, etc. Hereinafter, the first pad 20pd and the first bump electrode 20bp can be collectively referred to as a first contact portion 20C, the second pad 30pd and the second bump electrode 30bp can be collectively referred to as a second contact portion 30C, the third pad 40pd and the third bump electrode 40bp can be collectively referred to as a third contact portion 40C, and the fourth pad 50pd and the fourth bump electrode 50bp can be collectively referred to as a fourth contact portion 50C.

[0101] According to exemplary embodiments, the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C can be formed at various locations. For example, when the light emitting chip 100 has a substantially quadrangular shape as shown in the drawings, the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C can be provided around each corner of the substantially quadrangular shape. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the light emitting chip 100 can be formed to have various shapes, and the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C can be formed at other locations according to the shape of the light emitting device.

[0102] The first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are spaced apart from and insulated from each other. Also, the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp are spaced apart from and insulated from each other. According to exemplary embodiments, each of the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp can cover at least a portion of the side surface of the first, second, and third light emitting stacks 20, 30, and 40, which can facilitate dissipation of heat generated from the first, second, and third light emitting stacks 20, 30, and 40 there through.

[0103] The inventive concept is not limited to the specific structure of the contact portions 20C, 30C, 40C, and 50C. For example, in some exemplary embodiments, the bump electrode 20bp, 30bp, 40bp, or 50bp can be omitted from at least one of the contact portions 20C, 30C, 40C, and 50C. In this case, the pad 20pd, 30pd, 40pd, or 50pd of the contact portion 20C, 30C, 40C, or 50C can be connected to the corresponding connection electrode 20ce, 30ce, 40ce, or 50ce.

[0104] Figure 3 is a schematic plan view showing a process of manufacturing a light emitting chip according to exemplary embodiments, Figure 4A and Figure 4B are schematic cross-sectional views taken along lines A-A' and B-B' of Figure 5A , respectively.

[0105] Referring to Figure 5B , Figure 6A and Figure 6BThe first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce can be formed on the light emitting stack structure spaced apart from each other. The first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce can be electrically connected to the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp, respectively, to transmit an external signal to each of the light emitting stacks 20, 30, and 40. More specifically, according to the illustrated exemplary embodiment, the first connection electrode 20ce can be connected to the first bump electrode 20bp connected to the first upper contact electrode 21n through the first pad 20pd to be electrically connected to the first type semiconductor layer 21 of the first light emitting stack 20. The second connection electrode 30ce can be connected to the second bump electrode 30bp connected with the second pad 30pd to be electrically connected to the first type semiconductor layer 31 of the second light emitting stack 30. The third connection electrode 40ce can be connected to the third bump electrode 40bp connected with the third pad 40pd to be electrically connected to the first type semiconductor layer 41 of the third light emitting stack 40. The fourth connection electrode 50ce can be connected to the fourth bump electrode 50bp connected with the fourth pad 50pd to be electrically connected to the second type semiconductor layers 25, 35, and 45 of the light emitting stacks 20, 30, and 40, respectively, via the first, second, and third lower contact electrodes 25p, 35p, and 45p.

[0106] According to the illustrated exemplary embodiment, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce can have a substantially elongated shape vertically protruding away from the substrate 11. The connection electrodes 20ce, 30ce, 40ce, and 50ce can include a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof, but are not limited thereto. For example, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce can include two or more metals or a plurality of different metal layers to reduce stress acting on the elongated connection electrodes 20ce, 30ce, 40ce, and 50ce from them. In another exemplary embodiment, when the connection electrodes 20ce, 30ce, 40ce, and 50ce include Cu, an additional metal can be deposited or plated thereon to suppress oxidation of the Cu. In some exemplary embodiments, when the connection electrodes 20ce, 30ce, 40ce, and 50ce include Cu / Ni / Sn, the Cu can prevent the Sn from penetrating into the light emitting stack structure. In some exemplary embodiments, the connection electrodes 20ce, 30ce, 40ce, and 50ce can include a seed layer for forming a metal layer during a plating process, which will be described in more detail below.

[0107] As shown in the drawings, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce can have a substantially flat upper surface to facilitate electrical connection between the light emitting stack structure and an external wire or electrode to be described later. According to exemplary embodiments, when the light emitting chip 100 includes a micro-LED having a surface area less than about 10,000 square µm as known in the art or a surface area less than about 4,000 square µm or 2,500 square µm in other exemplary embodiments, the connection electrodes 20ce, 30ce, 40ce, and 50ce can be overlapped with a portion of at least one of the first, second, and third light emitting stacks 20, 30, and 40 as shown in the drawings. More specifically, the connection electrodes 20ce, 30ce, 40ce, and 50ce can be overlapped with at least one step formed in a side surface of the light emitting stack structure. In this way, since the bottom surface of the connection electrode has a larger area than the top surface thereof, a larger contact area can be formed between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light emitting stack structure. Accordingly, the connection electrodes 20ce, 30ce, 40ce, and 50ce can be more stably formed on the light emitting stack structure. For example, one side surface L of the connection electrodes 20ce, 30ce, 40ce, and 50ce facing the outside and the other side surface L' thereof facing the center of the light emitting chip 100 can have different lengths (or heights). More specifically, the length of one side surface L of the connection electrode facing the outside can be greater than the length of the other side surface L' thereof facing the center of the light emitting chip 100. For example, the difference in length between the two back-to-back side surfaces L and L' of the connection electrode can be greater than the thickness (or height) of at least one of the light emitting stacks 20, 30, and 40. In this way, the structure of the light emitting chip 100 can be strengthened with the larger contact area between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light emitting stack structure. Furthermore, since the connection electrodes 20ce, 30ce, 40ce, and 50ce can be overlapped with at least one step formed in a side surface of the light emitting stack structure, heat generated from the light emitting stack structure can be more effectively dissipated to the outside.

[0108] According to an exemplary embodiment, a length difference between one side surface L of the connection electrode facing the outside and the other side surface L' of the connection electrode facing the center of the light emitting chip 100 can be about 3㎛. In this case, the light emitting stack structure can be formed thin, specifically, the first LED stack 20 can have a thickness of about 1㎛, the second LED stack 30 can have a thickness of about 0.7㎛, the third LED stack 40 can have a thickness of about 0.7㎛, the first adhesive layer 61 and the second adhesive layer 63 can each have a thickness of about 0.2㎛ to about 0.3㎛, but are not limited thereto. According to another exemplary embodiment, a length difference between one side surface L of the connection electrode facing the outside and the other side surface L' of the connection electrode facing the center of the light emitting chip 100 can be about 10㎛ to 16㎛. In this case, the light emitting stack structure can be formed relatively thick and have a more stable structure, specifically, the first LED stack 20 can have a thickness of about 4㎛ to about 5㎛, the second LED stack 30 can have a thickness of about 3㎛, the third LED stack 40 can have a thickness of about 3㎛, the first adhesive layer 61 and the second adhesive layer 63 can each have a thickness of about 3㎛, without being limited thereto. However, the inventive concept is not limited to a specific length difference between the back side surfaces of the connection electrode, but the length difference between the back side surfaces of the connection electrode can vary.

[0109] In some exemplary embodiments, at least one of the connection electrodes 20ce, 30ce, 40ce, and 50ce can be overlapped with the side surface of each of the light emitting stacks 20, 30, and 40, thereby balancing the temperature between the light emitting stacks 20, 30, and 40 from each other and effectively dissipating the internally generated heat to the outside. Furthermore, when the connection electrodes 20ce, 30ce, 40ce, and 50ce include a reflective material such as metal, the connection electrodes 20ce, 30ce, 40ce, and 50ce can reflect light emitted from at least one or more light emitting stacks 20, 30, and 40, thereby improving light efficiency.

[0110] The method of forming the first connection electrode 20ce, the second connection electrode 30ce, the third connection electrode 40ce, and the fourth connection electrode 50ce is not specifically limited. For example, according to an exemplary embodiment, a seed layer can be deposited on the light emitting stack as a conductive surface, and the seed layer can be patterned by using photolithography or the like such that the seed layer is disposed at a desired location where the connection electrode is to be formed. Then, the seed layer can be plated with a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or an alloy thereof, and the seed layer can be removed. In some exemplary embodiments, an additional metal can be deposited or plated on the plated metal (e.g., the connection electrode) by electroless nickel immersion gold (ENIG) or the like to prevent or at least inhibit oxidation of the plated metal. In some exemplary embodiments, the seed layer can remain in each connection electrode.

[0111] According to an exemplary embodiment, when the bump electrodes 20bp, 30bp, 40bp, and 50bp are omitted from the contact portions 20C, 30C, 40C, and 50C, the pads 20pd, 30pd, 40pd, and 50pd can be connected to the respective connection electrodes 20ce, 30ce, 40ce, and 50ce. For example, after forming the through-holes 20ct, 30ct, 40ct, and 50ct to partially expose the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C, a seed layer can be deposited on the light emitting stack as a conductive surface, and the seed layer can be patterned by using photolithography or the like such that the seed layer is disposed at a desired location where the connection electrode is to be formed. In this case, the seed layer can overlap at least a portion of each pad 20pd, 30pd, 40pd, and 50pd. According to an exemplary embodiment, the seed layer can be deposited to a thickness of about 1000A, but is not limited thereto. Then, the seed layer can be plated with a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or an alloy thereof, and the seed layer can be removed. In some exemplary embodiments, an additional metal can be deposited or plated on the plated metal (e.g., the connection electrode) by electroless nickel immersion gold (ENIG) or the like to prevent or at least inhibit oxidation of the plated metal. In some exemplary embodiments, the seed layer can remain in each connection electrode.

[0112] Figure 7A Figure 7B Figure 8A Figure 8B Figure 9A Figure 9B Figure 10A are schematic cross-sectional views illustrating a process of manufacturing a light emitting package according to an exemplary embodiment. Figure 10B

[0113] ​​​​​​​​Typically, during fabrication, an array of light emitting dies is formed on a substrate. The substrate can then be cut along the scribe lines to singulate (to separate) each light emitting die, which can be transferred to another substrate or tape for further processing (such as packaging) of the light emitting dies using various transfer techniques. In this case, when the light emitting dies include connecting electrodes (such as metal bumps or pillars protruding outward from the light emitting structure), various issues can occur during subsequent processes (such as in the step of transferring) due to the exposed structure of the connecting electrodes of the bare light emitting dies. Furthermore, when the light emitting dies include micro-LEDs having a surface area less than about 10000 square pm, less than about 4000 square pm, or less than about 2500 square pm depending on the application, the processing of the light emitting dies can become more difficult due to their small form factor.

[0114] For example, when the connecting electrodes have a substantially elongated shape (such as a strip), it becomes difficult to transfer the light emitting dies using conventional vacuum methods because the light emitting dies cannot have sufficient suction area due to the protruding structure of the connecting electrodes. Furthermore, the exposed connecting electrodes can directly be subjected to various stresses during subsequent processes (such as when the connecting electrodes contact manufacturing equipment), which can cause damage to the structure of the light emitting dies. As another example, when the light emitting dies are transferred by adhering an adhesive tape on the top surface (e.g., the surface opposite to the substrate) of the light emitting dies, the contact area between the light emitting dies and the adhesive tape can be limited to the top surface of the connecting electrodes. In this case, the adhesion of the light emitting dies to the adhesive tape can be weaker and the light emitting dies can undesirably detach from the adhesive tape upon transfer, as opposed to when the adhesive tape is adhered to the bottom surface (e.g., the substrate) of the dies. As another example, when the light emitting dies are transferred using conventional pick-and-place methods, the ejection pins can directly contact the portion of the light emitting dies disposed between the connecting electrodes, thereby damaging the top structure of the light emitting structure.

[0115] Figure 10C An array of light emitting stack structures formed on a substrate 11 is shown. Referring to FIG. 1, the array of light emitting stack structures includes a plurality of light emitting dies 100 arranged in a matrix. Each light emitting die 100 includes a light emitting structure 10, a first connecting electrode 20ce, a second connecting electrode 30ce, a third connecting electrode 40ce, and a fourth connecting electrode 50ce. The light emitting structure 10 includes a first semiconductor layer 12, a second semiconductor layer 14, and a light emitting layer 16 disposed between the first semiconductor layer 12 and the second semiconductor layer 14. The first connecting electrode 20ce is disposed on the first semiconductor layer 12, the second connecting electrode 30ce is disposed on the second semiconductor layer 14, and the third and fourth connecting electrodes 40ce and 50ce are disposed on the light emitting layer 16. The first, second, third, and fourth connecting electrodes 20ce, 30ce, 40ce, and 50ce are arranged in a substantially cross shape. Figure 10A A passivation layer 90 is disposed between the connecting electrodes 20ce, 30ce, 40ce, and 50ce. The passivation layer 90 can be formed to be substantially flush with the top surfaces of the connecting electrodes 20ce, 30ce, 40ce, and 50ce by a polishing process or the like. In this way, the passivation layer 90 can protect the light emitting structure from external impacts that can be applied during subsequent processes, as well as provide sufficient contact area for the light emitting die 100 to facilitate its processing during subsequent transfer steps. Furthermore, the passivation layer 90 can prevent light from leaking towards the side surfaces of the light emitting die 100 to prevent or at least inhibit interference of light emitted from adjacent light emitting dies 100.

[0116] Referring to FIG. 2, the array of light emitting stack structures is singulated to form a plurality of light emitting dies 100. The singulation can be performed by a scribing process, a dicing process, or the like.Figure 10A The substrate 11 (e.g., a growth substrate) having the light emitting chip 100 formed thereon can be mounted on the temporary substrate 95. The temporary substrate 95 is not particularly limited as long as it can support the array of light emitting chips 100 during subsequent processes. For example, in some exemplary embodiments, the temporary substrate 95 can be a tape.

[0117] Referring to Figure 10B The substrate 11 can be removed from the light emitting chip 100 using various known methods in the art. For example, in some exemplary embodiments, a laser beam can be irradiated to the substrate 11 such as using a known laser lift-off (LLO) method to lift off the substrate 11 from the light emitting chip 100. In this way, since the substrate 11 is removed from the light emitting chip 100, light emitted from the light emitting chip 100 does not pass through the substrate 11, thereby increasing light efficiency and color purity of the light emitting chip 100. In this case, even though the substrate 11 is removed from the light emitting chip 100, since the light emitting chip 100 configured according to exemplary embodiments has a reinforcing structure at least partially formed by the connection electrodes 20ce, 30ce, 40ce, and 50ce having a substantially elongated shape and the passivation layer 90 at least surrounding the side surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce, the light emitting chip 100 can withstand various external stresses that can occur during manufacturing or in use that act on it.

[0118] In some exemplary embodiments, a concavo-convex portion can be formed on the surface of the third LED stack 40 exposed due to the removal of the substrate 11 to balance the visibility of light emitted from each light emitting stack.

[0119] Referring to Figure 10C and Figure 11 According to exemplary embodiments, a laser L can be irradiated between the light emitting chips 100 to monolithicize (separate) the light emitting chips 100 from each other. However, the inventive concept is not limited to a specific method for separating the light emitting chips 100. For example, in some exemplary embodiments, the light emitting chips 100 can be monolithicized by mechanically cutting using a blade or the like along the scribe line.

[0120] Referring to Figure 12 The light emitting chips 100 can be transferred and mounted on the circuit board 11p. The temporary substrate 95 can be removed once or before the light emitting chips 100 are mounted on the circuit board 11p.

[0121] In exemplary embodiments, the circuit board 11p can include a lower circuit electrode 11pa, an upper circuit electrode 11pc, and an intermediate circuit electrode 11pb disposed between the lower circuit electrode 11pa and the upper circuit electrode 11pc, which are electrically connected to each other. The lower circuit electrode 11pa can be connected to each of the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce, respectively. In some exemplary embodiments, the lower circuit electrode 11pa can be surface-treated by ENIG to facilitate electrical connection with the connection electrodes of the light emitting chip 100 by partially fusing the lower circuit electrode 11pa at a high temperature.

[0122] According to exemplary embodiments, the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce of the light emitting chip 100 can be bonded to the lower circuit electrode 11pa of the circuit board 11p, respectively, for example, by anisotropic conductive film (ACF) bonding. When the light emitting chip 100 is bonded to the circuit board 11p by ACF bonding, which can be performed at a lower temperature than in other bonding methods, the light emitting chip 100 can be protected from exposure to a high temperature during bonding. However, the inventive concept is not limited to a specific bonding method. For example, in some exemplary embodiments, the light emitting chip 100 can be bonded to the circuit board 11p using anisotropic conductive paste (ACP) including at least one of Cu and Sn, solder, ball grid array (BGA), or micro bumps. In this case, since the upper surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce and the passivation layer 90 are substantially flush with each other due to a polishing process or the like, the adhesion of the light emitting chip 100 to the anisotropic conductive film can be increased, thereby forming a more stable structure when bonded to the circuit board 11p.

[0123] According to exemplary embodiments, the upper circuit electrode 11pc can be spaced apart from each other at a predetermined pitch. For example, the pitch between the upper circuit electrodes 11pc can correspond to the pitch of the electrodes of a target substrate, such as a display device. In this way, the light emitting package 110 according to exemplary embodiments can be mounted on a conventional display device without changing the configuration of the target substrate of the display device.

[0124] Referring to Figure 13After the passivation layer 90 is formed, a molding layer 91 can be formed on the light emitting chip 100 mounted on the circuit board 11p. The molding layer 91 can surround at least a side surface of the light emitting chip 100 to protect the light emitting chip 100 from external impact. According to the illustrated exemplary embodiment, the molding layer 91 can expose at least one surface of the light emitting chip 100 to increase light efficiency. In this case, since the light emitting chip 100 according to the illustrated exemplary embodiment does not include the growth substrate 11, light emitted from the light emitting package 110 can have increased brightness and purity. According to exemplary embodiments, the molding layer 91 can include an organic polymer or an inorganic polymer. In some exemplary embodiments, the molding layer 91 can include substantially the same material as that of the passivation layer 90. However, since the molding layer 91 is formed later, the two layers are different even though they are formed of the same material. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the molding layer 91 and the passivation layer 90 can include different materials from each other.

[0125] The light emitting chip 100 surrounded by the molding layer 91 can then be cut to provide a light emitting package 110 of Figure 14 Although Figure 15 the light emitting package 110 is illustrated as including one light emitting chip 100 therein, the inventive concept is not limited to the specific number of light emitting chips 100 in the light emitting package. For example, in some exemplary embodiments, the light emitting chip 100 surrounded by the molding layer 91 can be cut in a desired configuration so that the light emitting package can include at least one or more light emitting chips 100 therein by various methods known in the art in consideration of a final device (such as a display device) to which the light emitting package can be mounted. For example, the light emitting package 110 can include one or more light emitting chips 100 arranged in an n x m arrangement, where n and m are natural numbers.

[0126] Figure 16 is a schematic cross-sectional view illustrating a process of manufacturing a light emitting package according to another exemplary embodiment. Figure 17

[0127] Referring to Figure 1 , according to another exemplary embodiment, the molding layer 91 can be formed to cover a top surface of the light emitting chip 100 (e.g., the third LED stack 40). As described above, in this case, the molding layer 91 can include an organic polymer or an inorganic polymer having photosensitivity to transmit light emitted from the light emitting chip 100. In this way, the light emitting chip 100 of the light emitting package 120 can be protected from external stress, etc. The light emitting chip 100 surrounded by the molding layer 91 can then be cut to provide a light emitting package 120 of Figure 11 Although Figure 11 ​The light emitting package 120 is shown to include one light emitting chip 100 therein, but the inventive concept is not limited to the specific number of light emitting chips 100 in the light emitting package. For example, in some exemplary embodiments, the light emitting chip 100 surrounded by the molding layer 91 can be diced in a desired configuration, so that the light emitting package can include at least one or more light emitting chips 100 therein by various methods known in the art.

[0128] As described above, Figure 12 The process of forming the passivation layer 90 before the light emitting chips 100 are isolated from each other (or singulated) is exemplarily shown. However, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the light emitting chips 100 formed on the substrate 11 can be isolated from each other before the process of forming the passivation layer 90 thereon. More specifically, referring back to Figure 13 The isolation process can be performed before the passivation layer 90 is formed on the light emitting chips 100, so that the third light emitting stacks 40 formed substantially throughout the substrate 11 across the light emitting chips 100 can be separated from each other, thereby exposing at least portions of the substrate 11 between the light emitting chips 100. In this case, the side surfaces of the third light emitting stacks 40 between the light emitting chips 100 can also be exposed by the isolation process. As such, when the passivation layer 90 is formed on each of the light emitting chips 100 during a subsequent process, the passivation layer 90 can cover not only the surfaces of the light emitting chips 100 as shown in Figure 14 In this way, the passivation layer 90 can further improve the reliability of the light emitting chips 100 with respect to the external environment. In addition, the passivation layer 90 can substantially block light emitted from each light emitting stack toward a longitudinal direction thereof, thereby improving light efficiency toward a vertical direction of the light emitting chips 100.

[0129] Figure 15 is a schematic cross-sectional view of a light emitting package constructed according to an exemplary embodiment of the invention, Figure 16 is a schematic cross-sectional view of a light emitting package constructed according to another exemplary embodiment of the invention.

[0130] Referring to Figure 17 The light emitting package 210 according to the exemplary embodiment includes a light emitting chip 200, a circuit board 11p' including a lower circuit electrode 11pa', a middle circuit electrode 11pb', and an upper circuit electrode 11pc', and a molding layer 91' surrounding at least side surfaces of the light emitting chip 200.

[0131] The molding layer 91' can surround at least sides of the light emitting chip 200 to protect the light emitting chip 200 from external impact. According to the illustrated exemplary embodiment, the molding layer 91' can expose at least one surface in the light emitting chip 200 to increase light efficiency and color purity. In this case, since the light emitting chip 200 according to the illustrated exemplary embodiment does not include a substrate on which a light emitting stack structure is grown, light emitted from the light emitting package 210 can have increased brightness and purity. According to an exemplary embodiment, the molding layer 91' can include an organic polymer or an inorganic polymer. In some exemplary embodiments, the molding layer 91' can include substantially the same material as the passivation layer 290. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the molding layer 91' and the passivation layer 290 can include different materials from each other.

[0132] The light emitting package 210 according to an exemplary embodiment is substantially the same as the light emitting package 110 of Figure 1 , which will be described in more detail below. The circuit board 11p' and constituent elements thereof are substantially the same as the circuit board 11p described above, and thus repetitive descriptions thereof will be omitted to avoid redundancy.

[0133] According to an exemplary embodiment, the upper circuit electrodes 11pc' of the light emitting package 210 can be spaced apart from each other at a predetermined pitch corresponding to a pitch of electrodes of a final device. In this way, even if a layout of electrodes of a final device such as a display device is designed for a conventional light emitting device, the light emitting package 210 can be easily mounted on a substrate of the final device.

[0134] Referring to Figure 17 , the light emitting package 220 according to an exemplary embodiment is substantially the same as the light emitting package 210 of Figure 18 except for a shape of the molding layer 91'. More specifically, the molding layer 91' according to the illustrated exemplary embodiment covers a top surface of the light emitting chip 200. In this way, the molding layer 91' can protect the light emitting chip 200 from external impact or from penetration of external particles such as dust and moisture into the light emitting stack structure. Further, when the molding layer 91' covers the top surface of the light emitting chip 200 as illustrated in Figure 2 , a transmittance of light can be controlled by adjusting a thickness of the molding layer 91' or by forming the molding layer 91' with a material that provides a desired light transmittance. Since the light emitting package 220 is substantially the same as the light emitting package 210 of Figure 18 except for the shape of the molding layer 91', repetitive descriptions of constituent elements thereof will be omitted to avoid redundancy.

[0135] Figure 2 and Figure 18 is a plan view illustrating a process of manufacturing a light emitting chip according to another exemplary embodiment. Figures 11 to 17 and Figure 11 is a cross-sectional view taken along line A-A' of its corresponding plan view illustrated in Figure 11 and Figure 19 .

[0136] Referring to Figure 20 and Figure 19 , the light emitting chip 200 according to an exemplary embodiment includes a light emitting stack structure, connection electrodes 20ce', 30ce', 40ce', and 50ce', and a passivation layer 290 formed between the light emitting stack structure and the connection electrodes 20ce', 30ce', 40ce', and 50ce'. The light emitting stack structure has a substantially similar configuration to that illustrated in Figure 1 and 9B . However, according to the illustrated exemplary embodiment, the passivation layer 290 can be formed to cover at least a portion of the upper surface of the light emitting stack structure illustrated in Figure 20 and Figure 19 . More specifically, the passivation layer 290 can cover at least a portion of the upper surface of the first light emitting stack 20 disposed on the top of the light emitting stack structure to protect the light emitting stack structure from external stress during manufacturing.

[0137] According to the illustrated exemplary embodiment, the passivation layer 290 can form an inclined angle with respect to the substrate 11. For example, the angles G and G' (see Figure 20 ) formed between the passivation layer 290 and the substrate 11 can be less than about 80°. When the inclined angle is greater than about 80°, the passivation layer 290 cannot sufficiently cover the steps formed on the side surface of the light emitting stack structure. In some exemplary embodiments, the inclined angle between the passivation layer 290 and the substrate 11 can be greater than about 60° and less than about 70°. In this way, the connection electrodes 20ce', 30ce', 40ce', and 50ce' (see Figure 19 and 22B ) to be formed on the passivation layer 290 can also be stably formed on the light emitting stack structure. In some exemplary embodiments, the edge formed between the top surface and the side surface of the passivation layer 290 can form a smooth angle such that the connection electrodes 20ce', 30ce', 40ce', and 50ce' to be formed thereon can have a substantially uniform thickness. However, the inventive concept is not limited thereto, and in some exemplary embodiments, a substantially sharp edge can be formed between the top surface and the side surface of the passivation layer 290.

[0138] Referring to Figure 21A and Figure 22AAccording to the illustrated exemplary embodiment, first, second, third, and fourth connection electrodes 20ce', 30ce', 40ce', and 50ce' are formed on the passivation layer 290, spaced apart from each other. As described above, the first, second, third, and fourth connection electrodes 20ce', 30ce', 40ce', and 50ce' can be electrically connected to the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp, respectively, as in the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce of the light emitting chip 100, to transmit an external signal to each of the light emitting stacks 20, 30, and 40. More specifically, the first connection electrode 20ce' can be connected to the first bump electrode 20bp connected to the first upper contact electrode 21n through the first pad 20pd, to be electrically connected to the first type semiconductor layer 21 of the first light emitting stack 20. The second connection electrode 30ce' can be connected to the second bump electrode 30bp connected with the second pad 30pd, to be electrically connected to the first type semiconductor layer 31 of the second light emitting stack 30. The third connection electrode 40ce' can be connected to the third bump electrode 40bp connected with the third pad 40pd, to be electrically connected to the first type semiconductor layer 41 of the third light emitting stack 40. The fourth connection electrode 50ce' can be connected to the fourth bump electrode 50bp connected with the fourth pad 50bp, to be electrically connected to the second type semiconductor layers 25, 35, and 45 of the light emitting stacks 20, 30, and 40, respectively, via the first, second, and third lower contact electrodes 25p, 35p, and 45p.

[0139] The method of forming the first, second, third, and fourth connection electrodes 20ce', 30ce', 40ce', and 50ce' is not particularly limited. For example, according to exemplary embodiments, a conductive layer can be deposited on the passivation layer 290, which can be patterned by using photolithography or the like, such that each of the conductive layer is superposed with the portions of the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp exposed by the passivation layer 290, respectively. The conductive layer (e.g., connection electrode) according to exemplary embodiments can include a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof. In this case, a separate plating process can be omitted. In some exemplary embodiments, an additional metal can be deposited on the conductive layer by electroless nickel immersion gold (ENIG) or the like, to prevent or at least inhibit oxidation of the connection electrodes 20ce', 30ce', 40ce', and 50ce'.

[0140] According to the illustrated exemplary embodiment, each of the connection electrodes 20ce', 30ce', 40ce', and 50ce' can have a curved shape or an angled shape that protrudes away from the substrate 11 to substantially cover the light emitting stack and the passivation layer 290. As shown in the figures, each of the connection electrodes 20ce', 30ce', 40ce', and 50ce' can have a substantially flat upper surface to facilitate electrical connection between the light emitting stack and external lines or electrodes, and to increase adhesion of the light emitting chip 200 to other elements such as a PCB during subsequent bonding and transfer steps. The connection electrodes 20ce', 30ce', 40ce', and 50ce' according to the illustrated exemplary embodiment can surround the at least a portion of each light emitting stack 20, 30, and 40 to protect the light emitting stack such that the light emitting chip 200 has a more stable structure that can be subjected to various subsequent processes along with the passivation layer 290. For example, the connection electrodes 20ce', 30ce', 40ce', and 50ce' that surround at least the sides of the light emitting stack can absorb at least a portion of stress that would otherwise act directly on the light emitting stack, thereby protecting the light emitting chip during fabrication.

[0141] According to the illustrated exemplary embodiment, the third connection electrode 40ce' is shown to be asymmetric with the first connection electrode 20ce'. More specifically, each of the connection electrodes 20ce', 30ce', 40ce', and 50ce' can have a portion that does not overlap the passivation layer 290, for example, Figure 21B The area of the portion of the third connection electrode 40ce' that does not overlap the passivation layer 290 is shown to be greater than the area of the portion of the first connection electrode 20ce' that does not overlap the passivation layer 290 near the two opposite ends of the substrate 11. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the connection electrodes 20ce', 30ce', 40ce', and 50ce' can all be symmetric with each other. For example, the portion of each of the connection electrodes 20ce', 30ce', 40ce', and 50ce' that does not overlap the passivation layer 290 can have the same area as each other.

[0142] Although the drawings show that the passivation layer 290 is not formed between the portions of the connection electrodes 20ce', 30ce', 40ce', and 50ce' disposed on the top surface of the passivation layer 290, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the passivation layer 290 can be formed between the connection electrodes 20ce', 30ce', 40ce', and 50ce' such that the upper surface of the passivation layer 290 can be substantially flush with the upper surfaces of the connection electrodes 20ce', 30ce', 40ce', and 50ce'. In this way, the adhesion of the light emitting chip 200 to a PCB or the like during a subsequent process can be further enhanced. The portions of the passivation layer 290 disposed between the connection electrodes 20ce', 30ce', 40ce', and 50ce' can be formed before or after the connection electrodes 20ce', 30ce', 40ce', and 50ce' are formed. Since the constituent elements of the light emitting chip 200 according to the illustrated exemplary embodiments are substantially the same as those of the light emitting chip 100 described above, a repetitive description of substantially the same elements will be omitted to avoid redundancy.

[0143] Figure 22B and Figure 21A are schematic sectional views illustrating a process of manufacturing a light emitting package according to exemplary embodiments.

[0144] Referring to Figure 22A , the array of the light emitting chips 200 formed on the growth substrate 11 can be separated from each other and transferred to be mounted on a circuit board 11p'. The circuit board 11p' according to exemplary embodiments is substantially the same as the circuit board 11p described above, and thus a repetitive description thereof will be omitted to avoid redundancy. As described above, the upper circuit electrodes 11pc' of the circuit board 11p' can be spaced apart from each other at a desired pitch such that the pitch of the electrodes of a final device, such as a display device, is met.

[0145] Referring to Figure 21A , once the light emitting chips 200 separated from each other are mounted on the circuit board 11p', the substrate 11 of the light emitting chips 200 can be removed by various known methods in the art, such as by an LLO method. In this way, since the substrate 11 is removed from the light emitting chips 200, light emitted from the light emitting chips 200 does not pass through the substrate 11, thereby increasing the light efficiency and color purity of the light emitting chips 200. In this case, even though the substrate 11 is removed from the light emitting chips 200, the light emitting chips 200 configured according to exemplary embodiments can withstand various external stresses that can occur during manufacturing or in use due to at least in part to the reinforced structure thereof having the passivation layer 290 and the connection electrodes 20ce', 30ce', 40ce', and 50ce' having a curved shape.

[0146] AlthoughFigure 21B and Figure 9A It is shown that the growth substrate 11 is removed from the light emitting chip 200 after the substrate 11 is cut (e.g., the light emitting chip 200 is singulated), however, the inventive concept is not limited thereto.

[0147] Figure 9A , Figure 9B , Figure 22B , Figure 22A and Figure 22A are schematic cross-sectional views illustrating a process of manufacturing a light emitting package according to an exemplary embodiment. Figure 22B

[0148] Referring to Figure 22B , according to another exemplary embodiment, the growth substrate 11 is removed from the selected light emitting chip 200, rather than removing the substrate 11 from the light emitting chip 200 after cutting the substrate 11 as shown in Figure 23 and Figure 24 .

[0149] More specifically, the array of light emitting chips 200 formed on the substrate 11 can be separated from each other by an isolation process, so that the third light emitting stack 40 formed substantially throughout the substrate 11 across the light emitting chips 200 can be separated from each other. In this case, the isolation process can be performed before or after forming the passivation layer 290 on the light emitting stack structure.

[0150] Once the light emitting chips 200 are isolated from each other such that at least a portion of the substrate 11 disposed between the light emitting chips 200 is exposed, the light emitting chips 200 are mounted on the circuit board 11p'. In this case, the lower circuit electrode 11pa' can be formed to correspond to only the portion of the light emitting chip 200 formed on the substrate 11. Once the light emitting chips 200 are placed on the circuit board 11p', a laser L can be selectively irradiated to the light emitting chip 200 to be transferred as shown in Figure 23 In this case, according to an exemplary embodiment, the connection electrodes of the light emitting chips 200 can be bonded to the lower circuit electrodes 11pa' of the circuit board 11p', respectively, for example, by anisotropic conductive film (ACF) bonding. When the light emitting chips 200 are bonded to the circuit board 11p' by ACF bonding which can be performed at a lower temperature than other bonding methods, the light emitting chips 200 can be protected from exposure to high temperatures during bonding. However, the inventive concept is not limited to a specific bonding method. For example, in some exemplary embodiments, the light emitting chips 200 can be bonded to the circuit board 11p' using anisotropic conductive paste (ACP) including at least one of Cu and Sn, solder, ball grid array (BGA), or micro bumps. In this case, since the light emitting chips 200 are not exposed to high temperatures during bonding, the light emitting chips 200 can be protected from damage due to heat. Figure 24 ​The portion of the connection electrode shown superimposed with the passivation layer 290 of the light emitting chip 200 is substantially planar, so the adhesion of the light emitting chip 200 to the anisotropic conductive film can be increased, thereby forming a more stable structure when bonded to the circuit board 11p'.

[0151] Referring to Figure 23 The base 11 can then be lifted, and the light emitting chips 200 selectively irradiated with the laser L can be mounted on the circuit board 11p'. The remaining light emitting chips 200 not irradiated with the laser L can be lifted together with the base 11, and later transferred to a different or the same circuit board 11p' as needed.

[0152] In some exemplary embodiments, a concavo-convex portion can be formed on the surface of the top LED stack exposed due to the removal of the base 11, to balance the visibility of light emitted from each light emitting stack.

[0153] Referring to Figure 24 Once the light emitting chips 200 are mounted on the circuit board 11p', a molding layer 91' can be formed to surround at least the side surfaces of the light emitting chips 200. According to exemplary embodiments, the molding layer 91' can transmit a portion of light emitted from the light emitting chips 200, and can also reflect, diffract, and / or absorb a portion of external light to prevent the external light from being reflected by the light emitting chips 200 toward a direction that can be visible to a user. The molding layer 91' can surround at least the side surfaces of the light emitting chips 200 to protect the light emitting chips 200 from external moisture and stress, and to strengthen the structural configuration of the light emitting package to facilitate a subsequent transfer and / or mounting process.

[0154] According to the exemplary embodiments shown, the molding layer 91' can be formed between the connection electrodes 20ce', 30ce', 40ce', and 50ce' of the light emitting chips 200, and cover at least a portion of the passivation layer 290. The molding layer 91' according to exemplary embodiments can include an epoxy molding compound (EMC) that can be formed to have various colors such as black or transparent, without being limited thereto. For example, in some exemplary embodiments, the molding layer 91' can include a polyimide (PID) dry film having photosensitivity. The molding layer 91' can be formed by various methods known in the art such as lamination, transfer molding, and / or printing methods. For example, the molding layer 91' can be formed by a vacuum lamination process in which an organic polymer sheet is disposed on the light emitting chips 200, and high temperature and pressure are applied in a vacuum to improve light uniformity by providing a substantially planar top surface of the light emitting package. In some exemplary embodiments, the molding layer 91' and the passivation layer 290 can include substantially the same material or different materials from each other.

[0155] Referring to Figure 25, taking into account the final device to which the light emitting package can be mounted, such as a display device, the circuit board 11p' can be cut in a desired configuration to provide the light emitting package. For example, the light emitting package 210 can include one or more light emitting chips 200 arranged in an n x m arrangement, where n and m are natural numbers. Although Figure 26 An exemplary light emitting package including two light emitting chips 200 is illustrated, but the inventive concept is not limited to the specific number of light emitting chips 200 formed in one package.

[0156] According to the illustrated exemplary embodiment, the molding layer 91' can expose at least a portion of the light emitting chip 200. For example, a portion of the light emitting chip 200 contacting the substrate 11 can be exposed by the molding layer 91', such as the third light emitting stack 40, to further increase the light efficiency and color purity of light emitted from the light emitting chip 200. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the molding layer 91' can cover a portion of the light emitting chip 200 contacting the substrate 11.

[0157] Figure 27 is a schematic cross-sectional view illustrating a process of manufacturing a light emitting package according to another exemplary embodiment. Figure 28

[0158] Referring to Figure 29 , according to an exemplary embodiment, the molding layer 91' can be formed to cover the light emitting chip 200 mounted on the circuit board 11p' illustrated in Figure 19 . In this way, the molding layer 91' can protect the light emitting chip 200 from external stress, etc., and can also prevent external light from being reflected toward a user. Further, the transmittance of light can be controlled by adjusting the thickness of the molding layer 91' or by forming the molding layer 91' with a material providing a desired light transmittance. Then taking into account the final device to which the light emitting package can be mounted, such as a display device, the circuit board 11p' can be cut in a desired configuration to provide the light emitting package, such as the light emitting package 220 illustrated in Figures 25 to 27 Figure 23 Figure 24 Figure 26 Figure 22B Figure 27 Figure 28 Figure 29 Figure 29 Figure 30 Figure 20 Figure 30 Figure 27 Figure 20 . For example, the light emitting package 220 can include one or more light emitting chips 200 arranged in an n x m arrangement, where n and m are natural numbers.

[0159] While certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent to those of ordinary skill in the art. Therefore, the inventive concept is not limited to the specific embodiments described herein but only by the scope of the appended claims and various obvious modifications and equivalent arrangements as would be readily perceived by one of ordinary skill in the art having the benefit of this disclosure.​

Claims

1. A light emitting package comprising: a first LED sub-unit having a first surface facing away and a second surface; a second LED sub-unit disposed on the second surface of the first LED sub-unit; a third LED sub-unit disposed on the second LED sub-unit; a plurality of connection electrodes having side surfaces and covering side surfaces of at least one of the first, second, and third LED sub-units, the plurality of connection electrodes including: a first connection electrode electrically connected to the first LED sub-unit; a second connection electrode electrically connected to the second LED sub-unit; a third connection electrode electrically connected to the third LED sub-unit; and a fourth connection electrode electrically connected to all of the first, second, and third LED sub-units; a first passivation layer at least surrounding the side surfaces of the plurality of connection electrodes, the first passivation layer completely exposing the first surface of the first LED sub-unit; a base having a third surface facing away and a fourth surface, the third surface of the base facing the first, second, and third LED sub-units; and a first electrode disposed on the third surface of the base and including a plurality of contact electrodes spaced apart from each other by a first distance on the third surface of the base, the plurality of contact electrodes being respectively electrically connected to the first, second, and third LED sub-units by being connected to the first, second, third, and fourth connection electrodes, wherein each of the plurality of connection electrodes is superposed with side surfaces of two or more of the first, second, and third LED sub-units.

2. The light emitting package of claim 1, wherein, The light emitting package further comprises a second passivation layer contacting side surfaces of at least some of the plurality of connection electrodes.

3. The light emitting package of claim 2, wherein, The second passivation layer is disposed between the plurality of connection electrodes.

4. The light emitting package of claim 1, wherein, The first passivation layer includes at least one of a black epoxy molding compound and a polyimide film. 5.The light emitting package of claim 1, wherein: the light emitting package further comprises second electrodes disposed on the fourth surface of the base, the respective second electrodes being spaced apart from each other by a second distance and connected to respective ones of the plurality of contact electrodes; and the second distance is greater than the first distance.

6. The light emitting package of claim 3, wherein, The first passivation layer and the second passivation layer include different materials. 7.The light emitting package of claim 1, wherein: the first LED sub-unit includes a first LED light emitting stack; the second LED sub-unit includes a second LED light emitting stack; the third LED sub-unit includes a third LED light emitting stack; the first, second, and third LED light emitting stacks have areas superposed with the base that decrease in order; and at least one of the LED light emitting stacks includes a micro LED having a surface area less than 10,000 square µm.

8. The light emitting package of claim 7, wherein, The light emitting package further comprises a second passivation layer disposed between the plurality of connection electrodes and the third LED sub-unit, wherein an angle defined between a side surface of the second passivation layer and the first surface of the first LED sub-unit is less than 80°.

9. The light emitting package of claim 8, wherein, At least one of the plurality of connection electrodes covers at least a side surface and a top surface of the second passivation layer.

10. A light emitting package comprising: a first LED sub-unit having a first surface facing away and a second surface; a second LED sub-unit disposed on the second surface of the first LED sub-unit; a third LED sub-unit disposed on the second LED sub-unit; a plurality of connection electrodes having side surfaces and covering side surfaces of at least one of the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit, the plurality of connection electrodes including a first connection electrode electrically connected to the first LED sub-unit, a second connection electrode electrically connected to the second LED sub-unit, a third connection electrode electrically connected to the third LED sub-unit, and a fourth connection electrode electrically connected to all of the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit; a first passivation layer at least surrounding the side surfaces of the plurality of connection electrodes and having a portion covering at least a portion of the first surface of the first LED sub-unit; a substrate having a third surface facing away and a fourth surface, the third surface of the substrate facing the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit; and a first electrode disposed on the third surface of the substrate and including a plurality of contact electrodes spaced apart from each other by a first distance on the third surface of the substrate, the plurality of contact electrodes being respectively electrically connected to the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit by being connected to the first connection electrode, the second connection electrode, the third connection electrode, and the fourth connection electrode, wherein each of the plurality of connection electrodes is superposed with side surfaces of two or more of the first LED sub-unit through the third LED sub-unit.

11. The light emitting package of claim 10, wherein, The portion of the first passivation layer covering the first surface of the first LED sub-unit has a thickness less than 100 µm.

12. The light emitting package of claim 10, wherein, The first passivation layer contacts the first surface of the first LED sub-unit.

13. The light emitting package of claim 10, wherein, The light emitting package further includes a second electrode disposed on the fourth surface of the substrate and connected to the first electrode, wherein the second electrode includes a first portion superposed with at least one of the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit and having a first area, and a second portion not superposed with at least one of the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit and having a second area greater than the first area.

14. The light emitting package of claim 10, wherein, The light emitting package further includes a second passivation layer at least contacting the side surfaces of the plurality of connection electrodes.

15. The light emitting package of claim 14, wherein, The first passivation layer and the second passivation layer include different materials.

16. The light emitting package of claim 14, wherein, At least one of the plurality of connection electrodes contacts a side surface and a top surface of the second passivation layer.

17. The light emitting package of claim 10, wherein, At least one of the plurality of connection electrodes has an angular shape.

18. The light emitting package of claim 10, wherein, The first passivation layer is disposed between the plurality of connection electrodes.

19. The light emitting package of claim 10, wherein: At least one of the plurality of connection electrodes has a fifth surface and a sixth surface facing away, the fifth surface of the at least one connection electrode facing the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit; and An area of the fifth surface of the connection electrode is greater than an area of the sixth surface of the connection electrode.

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