Operation method, device and related product

Abstract

The present disclosure relates to an operation method and device and related products. A board card includes a storage device, an interface device, a control device, and a machine learning chip. The machine learning chip is connected to the storage device, the control device, and the interface device. The storage device is configured to store data. The interface device is configured to implement data transmission between the machine learning chip and an external device. The control device is configured to monitor the state of the machine learning chip.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a multiply-accumulate instruction processing apparatus, method, and related products. Background Technology

[0002] With the continuous development of technology, machine learning, especially neural network algorithms, is being used more and more widely. It has found excellent applications in fields such as image recognition, speech recognition, and natural language processing. However, due to the increasing complexity of neural network algorithms and the ever-growing types and amounts of data operations involved, related technologies suffer from low efficiency and slow speed in performing multiplication and addition operations on data. Summary of the Invention

[0003] In view of this, the present disclosure provides a multiply-accumulate instruction processing apparatus, method and related products.

[0004] According to a first aspect of this disclosure, a multiply-accumulate instruction processing apparatus is provided, the apparatus comprising:

[0005] The control module is used to parse the received multiply-accumulate instruction, obtain the opcode and operation field of the multiply-accumulate instruction, determine the multiply-accumulate operation processing corresponding to the multiply-accumulate instruction based on the opcode, obtain the first data, second data, third data and fourth storage area required to execute the multiply-accumulate instruction based on the operation field, and determine the multiply-accumulate operation strategy.

[0006] The processing module is configured to perform multiplication and addition operations on the first data, the second data, and the third data according to the multiplication and addition operation strategy, obtain the operation result, and store the operation result in the fourth storage area.

[0007] The opcode is used to indicate that the multiply-accumulate instruction performs a multiply-accumulate operation on the data. The operation field includes a first storage area for storing the first data, a second storage area for storing the second data, a third storage area for storing the third data, and a fourth storage area.

[0008] According to a second aspect of this disclosure, a machine learning computing apparatus is provided, the apparatus comprising:

[0009] One or more of the multiply-accumulate instruction processing devices described in the first aspect above are used to obtain tensors to be processed and control information from other processing devices, execute specified machine learning operations, and transmit the execution results to other processing devices through an I / O interface;

[0010] When the machine learning computing device includes multiple multiply-accumulate instruction processing devices, the multiple multiply-accumulate instruction processing devices can be connected and transmit data through a specific structure;

[0011] The multiple multiply-accumulate instruction processing devices are interconnected and transmit data through a PCIe bus to support larger-scale machine learning operations; the multiple multiply-accumulate instruction processing devices share the same control system or have their own control systems; the multiple multiply-accumulate instruction processing devices share memory or have their own memory; the interconnection method of the multiple multiply-accumulate instruction processing devices is any interconnection topology.

[0012] According to a third aspect of this disclosure, a combined processing apparatus is provided, the apparatus comprising:

[0013] The machine learning computing device, general interconnect interface and other processing device described in the second aspect above;

[0014] The machine learning computing device interacts with the other processing devices to jointly complete the computational operations specified by the user.

[0015] According to a fourth aspect of this disclosure, a machine learning chip is provided, the machine learning chip including the machine learning network computing device described in the second aspect above or the combined processing device described in the third aspect above.

[0016] According to a fifth aspect of this disclosure, a machine learning chip packaging structure is provided, the machine learning chip packaging structure including the machine learning chip described in the fourth aspect above.

[0017] According to a sixth aspect of this disclosure, a board is provided that includes the machine learning chip packaging structure described in the fifth aspect above.

[0018] According to a seventh aspect of this disclosure, an electronic device is provided, the electronic device comprising the machine learning chip described in the fourth aspect above or the board described in the sixth aspect above.

[0019] According to the eighth aspect of this disclosure, a method for processing multiply-accumulate instructions is provided, the method comprising:

[0020] The received multiply-accumulate instruction is parsed to obtain the opcode and operation field of the multiply-accumulate instruction. The multiply-accumulate operation processing corresponding to the multiply-accumulate instruction is determined according to the opcode. The first data, second data, third data and fourth storage area required to execute the multiply-accumulate instruction are obtained according to the operation field. The multiply-accumulate operation strategy is also determined.

[0021] According to the multiplication-addition operation strategy, the first data, the second data, and the third data are multiplied and added to obtain the operation result, and the operation result is stored in the fourth storage area.

[0022] The opcode is used to indicate that the multiply-accumulate instruction performs a multiply-accumulate operation on the data. The operation field includes a first storage area for storing the first data, a second storage area for storing the second data, a third storage area for storing the third data, and a fourth storage area.

[0023] In some embodiments, the electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a dashcam, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, headphones, mobile storage, a wearable device, a vehicle, a home appliance, and / or a medical device.

[0024] In some embodiments, the means of transportation includes airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; and the medical devices include MRI scanners, ultrasound scanners and / or electrocardiographs.

[0025] The multiply-accumulate instruction processing apparatus, method, and related products provided in this disclosure include: a control module, configured to parse received multiply-accumulate instructions to obtain the opcode and operation field of the multiply-accumulate instructions, determine the multiply-accumulate operation corresponding to the multiply-accumulate instructions based on the opcode, obtain first data, second data, third data, and a fourth storage area required to execute the multiply-accumulate instructions based on the operation field, and determine a multiply-accumulate operation strategy. A processing module is configured to perform multiply-accumulate operations on the first data, second data, and third data according to the multiply-accumulate operation strategy, obtain the operation result, and store the operation result in the fourth storage area. The opcode indicates that the processing performed on the data by the multiply-accumulate instructions is a multiply-accumulate operation, and the operation field includes a first storage area storing the first data, a second storage area storing the second data, a third storage area storing the third data, and a fourth storage area. The multiply-accumulate instruction processing apparatus, method, and related products provided in this disclosure can perform multiply-accumulate operations on multiple data items with a single multiply-accumulate instruction. Compared with related technologies that require at least two instructions to perform multiply-accumulate operations, this method offers higher processing efficiency, faster processing speed, and wider applicability.

[0026] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0028] Figure 1a , Figure 1b A block diagram of a combined processing apparatus according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A schematic diagram of the structure of a board according to an embodiment of the present disclosure is shown.

[0030] Figure 3 A block diagram of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is shown.

[0031] Figure 4 A block diagram of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is shown.

[0032] Figure 5 A schematic diagram illustrating an application scenario of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is shown.

[0033] Figure 6a and Figure 6b A schematic diagram illustrating an application scenario of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is shown.

[0034] Figure 7a and Figure 7b A schematic diagram illustrating an application scenario of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is shown.

[0035] Figure 8a and Figure 8b A schematic diagram illustrating an application scenario of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is shown.

[0036] Figure 9 A schematic diagram showing the circular buffer storage area of ​​a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is provided.

[0037] Figure 10 A flowchart illustrating a multiply-accumulate instruction processing method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0038] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0039] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0040] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0041] As neural network algorithms are increasingly used in image recognition, speech recognition, and natural language processing, their complexity is rising, involving a growing variety and quantity of data operations. Multiplication-addition (M&A) involves performing both multiplication and addition on data. For example, in Example 1, two data points are multiplied to obtain the result, which is then added to the other data to arrive at the final result. In related technologies, implementing the M&A operation in Example 1 requires two instructions: a multiplication instruction and an addition instruction. During the operation, the result of the multiplication instruction needs to be written back to memory, and then the result of the multiplication instruction is read from memory for addition. Throughout the M&A process, the result of the multiplication instruction is temporary data; therefore, reading and writing this temporary data not only reduces the overall execution time but also incurs additional power consumption. Furthermore, due to data dependencies, the addition instruction can be blocked by the multiplication instruction, affecting overall instruction execution efficiency and reducing the execution speed of the M&A operation.

[0042] This disclosure provides a machine learning computing device capable of performing neural network algorithm-related operations. The machine learning computing device may include one or more multiply-accumulate instruction processing devices for processing data through multiply-accumulate operations based on received multiply-accumulate instructions. These devices are used to obtain data to be processed and control information from other processing devices and execute specified machine learning operations. The machine learning computing device can obtain multiply-accumulate instructions from other machine learning computing devices or non-machine learning computing devices and transmit the execution results to peripheral devices (also referred to as other processing devices) via I / O interfaces. Peripheral devices include, for example, cameras, monitors, mice, keyboards, network cards, Wi-Fi interfaces, and servers. When more than one multiply-accumulate instruction processing device is included, these devices can be linked and transmit data through a specific structure, such as interconnecting and transmitting data via a PCIe bus, to support larger-scale neural network operations. In this case, they can share the same control system or have independent control systems; they can share memory or each accelerator can have its own memory. Furthermore, the interconnection method can be any interconnection topology.

[0043] This machine learning computing device has high compatibility and can be connected to various types of servers via a PCIe interface.

[0044] Figure 1a A block diagram of a combined processing apparatus according to an embodiment of the present disclosure is shown. Figure 1a As shown, the combined processing unit includes the aforementioned machine learning computing unit, general interconnect interface, and other processing units. The machine learning computing unit interacts with the other processing units to jointly complete the user-specified operations.

[0045] Other processing devices include one or more processor types such as central processing unit (CPU), graphics processing unit (GPU), and neural network processor. There is no limit to the number of processors included in other processing devices. These other processing devices serve as interfaces between the machine learning computing device and external data and control, including data transfer and basic control such as starting and stopping the machine learning computing device. Other processing devices can also collaborate with the machine learning computing device to complete computational tasks.

[0046] A general interconnect interface is used to transfer data and control commands between the machine learning computing device and other processing devices. The machine learning computing device obtains the required input data from other processing devices and writes it to on-chip storage; it can obtain control commands from other processing devices and write them to on-chip control cache; it can also read data from the machine learning computing device's storage module and transmit it to other processing devices.

[0047] Figure 1b A block diagram of a combined processing apparatus according to an embodiment of the present disclosure is shown. In one possible implementation, such as Figure 1b As shown, the combined processing apparatus may further include a storage device, which is connected to the machine learning computing device and other processing devices respectively. The storage device is used to store data stored in the machine learning computing device and other processing devices, and is particularly suitable for data that cannot be fully stored in the internal storage of the machine learning computing device or other processing devices.

[0048] This combined processing device can serve as a System-on-a-Chip (SoC) for devices such as mobile phones, robots, drones, and video surveillance equipment, effectively reducing the core area of ​​the control unit, increasing processing speed, and lowering overall power consumption. In this case, the universal interconnect interface of the combined processing device connects to certain components of the device, such as cameras, monitors, mice, keyboards, network cards, and Wi-Fi interfaces.

[0049] This disclosure provides a machine learning chip, which includes the aforementioned machine learning computing device or combined processing device.

[0050] This disclosure provides a machine learning chip packaging structure, which includes the aforementioned machine learning chip.

[0051] This disclosure provides a circuit board, Figure 2 A schematic diagram of a board according to an embodiment of the present disclosure is shown. Figure 2 As shown, the board includes the aforementioned machine learning chip package structure or the aforementioned machine learning chip. In addition to the machine learning chip 389, the board may also include other supporting components, including but not limited to: a storage device 390, an interface device 391, and a controller 392.

[0052] The storage device 390 is connected to the machine learning chip 389 (or the machine learning chip within a machine learning chip package) via a bus for storing data. The storage device 390 may include multiple sets of storage cells 393. Each set of storage cells 393 is connected to the machine learning chip 389 via a bus. Each set of storage cells 393 can be understood as DDR SDRAM (Double Data Rate SDRAM).

[0053] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

[0054] In one embodiment, the storage device 390 may include four groups of storage cells 393. Each group of storage cells 393 may include multiple DDR4 chips. In one embodiment, the machine learning chip 389 may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification. It is understood that when each group of storage cells 393 uses DDR4-3200 chips, the theoretical bandwidth for data transmission can reach 25600MB / s.

[0055] In one embodiment, each group of memory cells 393 includes multiple parallel-connected Double Data Rate (DDR) synchronous dynamic random access memories (DRAMs). DDR can transfer data twice within one clock cycle. A controller for controlling the DDR is provided in the machine learning chip 389 for controlling the data transfer and data storage of each memory cell 393.

[0056] Interface device 391 is electrically connected to machine learning chip 389 (or a machine learning chip within a machine learning chip package). Interface device 391 is used to realize data transmission between machine learning chip 389 and external devices (e.g., servers or computers). For example, in one embodiment, interface device 391 can be a standard PCIe interface. For instance, data to be processed is transferred from the server to machine learning chip 389 via a standard PCIe interface, realizing data transfer. Preferably, when using a PCIe 3.0 x 16 interface, the theoretical bandwidth can reach 16000 MB / s. In another embodiment, interface device 391 can also be other interfaces; this disclosure does not limit the specific form of the other interfaces mentioned above, as long as the interface device can realize the switching function. Furthermore, the calculation results of the machine learning chip are still transmitted back to the external device (e.g., the server) by the interface device.

[0057] The controller 392 is electrically connected to the machine learning chip 389. The controller 392 is used to monitor the status of the machine learning chip 389. Specifically, the machine learning chip 389 and the controller 392 can be electrically connected via an SPI interface. The controller 392 may include a microcontroller (MCU). The machine learning chip 389 may include multiple processing chips, multiple processing cores, or multiple processing circuits, capable of driving multiple loads. Therefore, the machine learning chip 389 can operate in different states, such as high load and low load. The controller can be used to regulate the operating status of multiple processing chips, multiple processing cores, and / or multiple processing circuits within the machine learning chip.

[0058] This disclosure provides an electronic device that includes the aforementioned machine learning chip or board.

[0059] Electronic devices may include data processing devices, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, dashcams, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, home appliances, and / or medical devices.

[0060] Transportation equipment may include airplanes, ships, and / or vehicles. Household appliances may include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, light bulbs, gas stoves, and range hoods. Medical equipment may include MRI scanners, ultrasound scanners, and / or electrocardiographs.

[0061] Figure 3 A block diagram of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is shown. Figure 3 As shown, the device includes a control module 11 and a processing module 12.

[0062] The control module 11 is used to parse the received multiply-accumulate instructions, obtain the opcode and operation field of the multiply-accumulate instructions, determine the multiply-accumulate operation processing corresponding to the multiply-accumulate instructions based on the opcode, obtain the first data, second data, third data and fourth storage area required to execute the multiply-accumulate instructions based on the operation field, and determine the multiply-accumulate operation strategy.

[0063] The processing module 12 is used to perform multiplication and addition operations on the first data, the second data, and the third data according to the multiplication and addition operation strategy, obtain the operation result, and store the operation result in the fourth storage area.

[0064] The opcode is used to indicate that the multiply-accumulate instruction performs a multiply-accumulate operation on the data. The operation field includes a first storage area for storing the first data, a second storage area for storing the second data, a third storage area for storing the third data, and a fourth storage area.

[0065] In this embodiment, the first data, the second data, and the third data can be data of types such as scalars, vectors, matrices, and tensors, and this disclosure does not impose any restrictions on them. The multiplication-addition operation processing includes two data processes: multiplication processing and addition processing. The addition operation processing can be performed first and then the multiplication operation processing, or the multiplication operation processing can be performed first and then the addition operation processing, and this disclosure does not impose any restrictions on them.

[0066] In this embodiment, the multiplication-addition operation strategy is used to indicate the order of addition and multiplication operations in the multiplication-addition process, as well as the data corresponding to the addition and multiplication operations. The first data, second data, and third data each include at least one data item. When at least one of the first, second, and third data items includes multiple data items, the multiplication-addition operation strategy can also indicate the operational correspondence between the data, describing the order of the data obtained when the first, second, and third data items are operated on. For example, operations correspond to forward order number selection, operations correspond to reverse order number selection, etc., to ensure that corresponding addition and multiplication operations can be performed between the data items.

[0067] In this embodiment, the control module can obtain the first data, second data, and third data corresponding to the first storage area, the second storage area, and the third storage area, respectively. The first storage area, the second storage area, the third storage area, and the destination storage area can be physical addresses such as the starting address for data storage, or logical addresses or linear addresses; this disclosure does not impose any limitations on this. The control module can obtain multiply-accumulate instructions, the first data, the second data, and the third data through a data input / output unit, which can be one or more data I / O interfaces or I / O pins. Those skilled in the art can set the representation of the storage areas according to actual needs; this disclosure does not impose any limitations on this.

[0068] In this embodiment, a multiply-accumulate instruction may include an opcode and an operation field. The opcode may be a pre-configured instruction sequence number, used to inform the device executing the instruction which specific instruction needs to be executed. The operation field may include the source of all data (including first data, second data, and third data) and parameters (corresponding multiply-accumulate operation strategy, fourth storage area) required to execute the corresponding instruction, such as the storage area of ​​the data, the storage area of ​​the multiply-accumulate operation strategy, the fourth storage area, etc. For example, the operation field may include a first storage area, a second storage area, a third storage area, and a fourth storage area.

[0069] It should be understood that those skilled in the art can set the instruction format of the multiply-accumulate instruction as well as the opcodes and operation fields it contains as needed, and this disclosure does not impose any restrictions on this.

[0070] In this embodiment, the device may include one or more control modules and one or more processing modules. The number of control modules and processing modules can be set according to actual needs, and this disclosure does not limit this. When the device includes one control module, the control module can receive multiply-accumulate instructions and control one or more processing modules to perform multiply-accumulate operations. When the device includes multiple control modules, each control module can receive multiply-accumulate instructions and control the corresponding one or more processing modules to perform multiply-accumulate operations.

[0071] The multiply-accumulate instruction processing apparatus provided in this disclosure includes: a control module, configured to parse received multiply-accumulate instructions to obtain the opcode and operation field of the multiply-accumulate instructions, determine the multiply-accumulate operation corresponding to the multiply-accumulate instructions based on the opcode, obtain first data, second data, third data, and a fourth storage area required to execute the multiply-accumulate instructions based on the operation field, and determine a multiply-accumulate operation strategy. A processing module is configured to perform multiply-accumulate operations on the first data, second data, and third data according to the multiply-accumulate operation strategy, obtain the operation result, and store the operation result in the fourth storage area. The opcode indicates that the processing performed on the data by the multiply-accumulate instructions is a multiply-accumulate operation, and the operation field includes a first storage area storing the first data, a second storage area storing the second data, a third storage area storing the third data, and a fourth storage area. The multiply-accumulate instruction processing apparatus provided in this disclosure can perform multiply-accumulate operations between multiple data using a single multiply-accumulate instruction. Compared with related technologies that require at least two instructions to perform multiply-accumulate operations, this apparatus offers higher processing efficiency, faster processing speed, and wider applicability.

[0072] In one possible implementation, the first data, the second data, and the third data are multiplied and added according to a multiplication-addition strategy to obtain the result, including:

[0073] Based on the multiplication-addition operation strategy, determine the order of operations, the processing order, and the corresponding relationships between the first, second, and third data.

[0074] Based on the operational correspondence and the order of operation processing, the data to be operated on first is processed by the first operation to obtain the intermediate result;

[0075] Based on the operational correspondence and processing order, a second operation is performed on the intermediate results and the subsequent operation data to obtain the final result.

[0076] The first operation processing is either multiplication or addition, and the second operation processing is either multiplication or addition. The first operation processing is different from the second operation processing.

[0077] In this implementation, the order of operations determines whether the first and second operations correspond to multiplication or addition. For example, if the order is "multiplication first," then the first operation is multiplication and the second operation is addition. If the order is "addition first," then the first operation is addition and the second operation is multiplication. The data to be processed first can be the data among the first, second, and third data that undergoes the first operation, such as the first and second data. The data to be processed later can be the data among the first, second, and third data that undergoes the second operation along with the intermediate result (i.e., data other than the data processed first), such as the third data. As shown in the example in Table 1, based on the "all ascending order" operation correspondence, it can be determined that multiplying a1 in the first data by b1 in the second data, and then adding the intermediate result to c1 in the third data, yields the final result. In other words, based on the "all-ascending order" operation correspondence, the multiplication and addition operations are performed sequentially from front to back on the data in the first, second, ..., nth order of the first, second, ..., third data, to obtain the corresponding operation result. Different multiplication and addition operation strategies can be pre-set with corresponding codes to facilitate their addition to the multiplication and addition instructions. To illustrate the process of executing multiplication and addition instructions and their corresponding codes, Table 1 below provides an example.

[0078] Table 1 Examples of Multiply-Accumulate Instructions

[0079]

[0080] In one possible implementation, the operation domain may include a multiply-accumulate operation strategy.

[0081] In one possible implementation, the opcode is also used to indicate the multiplication-addition strategy.

[0082] In one possible implementation, a default multiplication-addition operation strategy can be pre-set. When the multiplication-addition operation strategy cannot be determined based on the multiplication-addition instruction, the default multiplication-addition operation strategy can be set as the multiplication-addition operation strategy of the current multiplication-addition instruction. The default multiplication-addition operation strategy can be set as follows: the first and second data are the data to be operated on first, and the third data is the data to be operated on last; the first operation is a multiplication operation, and the second operation is an addition operation (operation processing order), and the operation correspondence is all in ascending order. Those skilled in the art can set the default multiplication-addition operation strategy according to actual needs, and this disclosure does not impose any restrictions on it.

[0083] In one possible implementation, the processing module 12 may include at least one adder and at least one multiplier. Each multiplier performs the multiplication operation in the multiplication-addition operation. Each adder performs the addition operation in the multiplication-addition operation.

[0084] In this implementation, the number of multipliers and adders in the processing module can be set according to processing needs. The more adders and multipliers there are, the faster the processing module can perform multiplication and addition operations and the higher the processing efficiency.

[0085] In one possible implementation, the opcode may contain a preprocessing identifier, or the opcode field may include a preprocessing identifier.

[0086] The control module 11 is further configured to determine the processing operation corresponding to the prior processing identifier and the corresponding data to be processed, wherein the data to be processed includes at least one of the first data, the second data and the third data.

[0087] The processing module 12 is also used to preprocess the corresponding data to be processed according to the processing operation corresponding to the preprocessing identifier before performing multiplication and addition operations on the first data, the second data and the third data.

[0088] In this implementation, the processing operations include arithmetic operations, logical operations, and data format conversion of the data to be processed, and this disclosure does not impose any limitations on these operations.

[0089] In one possible implementation, the processing operations may include at least one of the following: data format conversion processing and data operation processing. Data format conversion processing may include at least one of the following: floating-point number conversion processing, fixed-point number conversion processing, and floating-point / fixed-point number conversion processing. Data operation processing may include at least one of the following: trigonometric function operation processing, inverse trigonometric function operation processing, logarithm operation processing, exponential operation processing, maximum value operation processing, minimum value operation processing, convolution operation processing, pooling operation processing, fully connected operation processing, and activation operation processing.

[0090] In this implementation, data format conversion can involve converting the format of the data to be processed. The data format includes data type and data length. Data types include floating-point data types, fixed-point data types, and so on.

[0091] In this implementation, data of the fixed-point data type can be represented using a fixed-point representation method. Fixed-point numbers can be 8-bit, 16-bit, 32-bit, etc. Data of the floating-point data type can be represented using a floating-point representation method. Floating-point numbers can be 8-bit, 16-bit, 32-bit, etc.

[0092] In one possible implementation, the floating-point number data type is a binary representation of data. Floating-point numbers can be 8-bit, 16-bit, 32-bit, etc. They include a sign bit, an exponent bit, and significant bits. Floating-point numbers can be unsigned or have a sign bit.

[0093] Taking an 8-bit floating-point number as an example. When the floating-point number has no sign bit, the digits are counted from right to left (from low to high), starting from 0. The exponent bit can be the leftmost digit (the 7th bit) or any other digit in the 8 bits. When the floating-point number has a sign bit, there is 1 sign bit, 1 exponent bit, and 6 significant digits. The sign bit and exponent bit can be located in any non-overlapping position within the 8 bits of the floating-point number. This disclosure does not impose any restrictions on this.

[0094] For example, floating-point numbers count digits from right to left, starting from 0. An 8-bit floating-point number X in binary form is: X7X6X5X4X3X2X1X0, where X7 is the sign bit, X6 is the exponent, and X5X4X3X2X1X0 are the significant digits.

[0095] In one possible implementation, the value of the floating-point number can be represented by the following formula (1):

[0096] ±m·base p+e+1 =±1.d·base 2p+e+1 Formula (1)

[0097] Where m is the sign of the floating-point number, base is the base, usually 2. e is the exponent of the floating-point number, p is the highest non-zero digit in the significant digits of the floating-point number, and d is the fractional part of the significant digits of the floating-point number.

[0098] For example, assuming the floating-point number is "01010101", then the value of the floating-point number is 010101 * 2. 4+1+1 =1.0101*2 2 * 4+1+1 By using floating-point numbers, the data representation range can be increased and the accuracy of data calculation can be improved with the same bit width.

[0099] In this implementation, floating-point conversion processing refers to converting the data to be processed into a floating-point number of a specified length. Fixed-point conversion processing refers to converting the data to be processed into a fixed-point number of a specified length. Floating-to-fixed-point conversion processing refers to converting the data to be processed into a floating-to-fixed-point number of a specified length. The specified length can include 8 bits, 16 bits, 32 bits, etc.

[0100] In this implementation, data processing can include performing arithmetic operations, logical operations, and other operations on the data to be processed.

[0101] In one possible implementation, trigonometric function operations can refer to performing operations such as sine, cosine, tangent, and cotangent on the data to be processed. Inverse trigonometric function operations can refer to performing operations such as arcsine, arccosine, arctangent, and arccotangent on the data to be processed. Logarithmic operations can refer to performing logarithmic operations on the data to be processed. Exponential operations can refer to performing exponential operations on the data to be processed. Maximum value operations can refer to performing a maximum value operation on the data to be processed when there are multiple data points, and using the maximum value as the corresponding first, second, or third data point. For example, if the data to be processed includes the first data points 1, 2, and 4, then after performing the maximum value operation, the data point 4 is used as the first data point for subsequent multiplication and addition operations.

[0102] Minimum value processing refers to performing a minimum value operation on multiple data points, using the minimum value as the first, second, or third data point. For example, if the data to be processed includes 1, 2, and 4 as the first data point, then after the minimum value operation, the data point 1 is used as the first data point for subsequent multiplication and addition operations. Convolution operations and pooling operations can include max pooling, average pooling, and other pooling operations. Activation operations use activation functions including rectified linear units (ReLU), exponential functions such as the exp function (an exponential function with base e), and linear functions such as the sigmoid function.

[0103] In this implementation, different identifiers corresponding to preprocessing and postprocessing can be pre-set to ensure that the device can determine the corresponding processing operation based on the preprocessing identifier and / or postprocessing identifier in the multiply-accumulate instruction. For example, assuming that the preprocessing operation is "float-to-fixed point conversion" of the data to be processed, and the data to be processed are the first data, the second data, and the third data, the corresponding preprocessing identifier can be set to "ffABC", where "ff" indicates that the processing operation is float-to-fixed point conversion, and A, B, and C in ABC represent the first data, the second data, and the third data to be processed, respectively. Assuming that the postprocessing operation is to perform a ReLU operation on the calculation result, the postprocessing identifier can be set to "relu".

[0104] It should be noted that the above data processing is only an example provided by this disclosure. In fact, those skilled in the art can set the data processing and its corresponding identifiers according to actual needs, and this disclosure does not impose any restrictions on this.

[0105] In one possible implementation, the opcode may contain a post-processing identifier, or the operation field may include a post-processing identifier.

[0106] The control module is also used to determine the processing operation corresponding to the post-processing identifier.

[0107] The processing module is also used to perform post-processing on the calculation results according to the processing operation corresponding to the post-processing identifier, and to store the post-processed calculation results in the fourth storage area.

[0108] The post-processing of the calculation results can be found in the description of the pre-processing of the data to be calculated above, and will not be repeated here.

[0109] Figure 4 A block diagram of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is shown. In one possible implementation, such as Figure 4 As shown, the device may further include a storage module 13. The storage module 13 is used to store the first data, the second data, and the third data.

[0110] In this implementation, the storage module may include memory, such as one or more of a cache and registers, and the cache may include a fast temporary cache. The first data, second data, and third data can be stored in the cache and / or registers of the storage module as needed; this disclosure does not limit this.

[0111] In one possible implementation, the device may also include a direct memory access module for reading or storing data from the storage module.

[0112] In one possible implementation, such as Figure 4 As shown, the control module 11 may include an instruction storage submodule 111, an instruction processing submodule 112, and a queue storage submodule 113.

[0113] The instruction storage submodule 111 is used to store multiply-accumulate instructions.

[0114] The instruction processing submodule 112 is used to parse the multiply-accumulate instruction to obtain the opcode and operation field of the multiply-accumulate instruction.

[0115] The queue storage submodule 113 is used to store an instruction queue, which includes multiple instructions to be executed arranged in the order of execution. These instructions may include multiplication-accumulation instructions. They may also include other calculation instructions related to the multiplication-accumulation instructions.

[0116] In this implementation, the execution order of multiple instructions to be executed can be arranged according to the receipt time, priority level, etc., to obtain an instruction queue, so as to execute multiple instructions to be executed sequentially according to the instruction queue.

[0117] In one possible implementation, such as Figure 4 As shown, the control module 11 may also include a dependency processing submodule 114.

[0118] When it is determined that the first instruction to be executed among a plurality of instructions to be executed has a dependency relationship with the zeroth instruction to be executed preceding the first instruction to be executed, the dependency processing submodule 114 can cache the first instruction to be executed in the instruction storage submodule 112. After the zeroth instruction to be executed is completed, the first instruction to be executed is retrieved from the instruction storage submodule 112 and sent to the processing module 12. Here, the first instruction to be executed and the zeroth instruction to be executed are instructions among a plurality of instructions to be executed.

[0119] The dependency relationship between the first instruction to be executed and the zeroth instruction to be executed preceding it includes: the storage area storing the data required by the first instruction to be executed and the storage area storing the data required by the zeroth instruction to be executed have overlapping areas. Conversely, the absence of a dependency relationship between the first instruction to be executed and the zeroth instruction to be executed can be defined as the absence of overlapping areas between their corresponding storage areas.

[0120] In this way, the dependencies between instructions to be executed can be used to ensure that the next instruction to be executed is executed only after the previous one has been completed, thus guaranteeing the accuracy of the calculation results.

[0121] In one possible implementation, the instruction format for the multiply-accumulate instruction can be:

[0122] MLUTADD addr1 addrA addrB addrC type sign0 sign1

[0123] Where MLUTADD is the opcode, and addr1, addrA, addrB, addrC, type, sign0, and sign1 are the operation fields. MLUTADD indicates that the instruction is a multiply-accumulate instruction. addr1 is the fourth storage area. addrA is the first storage area. addrB is the second storage area. addrC is the third storage area. Type is the multiply-accumulate operation strategy. sign0 is the first-processing flag. sign1 is the last-processing flag.

[0124] In one possible implementation, the instruction format of the multiply-accumulate instruction can also be:

[0125] MLUTADD.type.sign0.sign1addr1 addrAaddrB addrC

[0126] In this context, MLUTADD.type.sign0.sign1 is the opcode, MLUTADD indicates that the instruction is a multiply-accumulate instruction, Type is the multiply-accumulate operation strategy, sign0 is the first-processing flag, and sign1 is the last-processing flag.

[0127] Alternatively, the instruction format for the multiply-add instruction can also be:

[0128] MLUTADD.type addr1 addrA addrB addrC sign0 sign1,

[0129] MLUTADD.type.sign0 addr1 addrA addrB addrC sign1,

[0130] MLUTADD.type.sign1 addr1 addrA addrB addrC sign0 etc.

[0131] Taking Example 1 in the table as an example, the corresponding instruction can be MLUTADD 500 101 102 103 01ffABCrelu. After the device receives this instruction, it obtains the first data (a1, a2), the second data (b1), and the third data (c1, c2) from positions 101, 102, and 103, respectively. Preprocessing is performed to convert the data formats of the first data (a1, a2), the second data (b1), and the third data (c1, c2) into floating-point data formats. After conversion, multiplication and addition operations are performed to obtain the results a1·b1+c1 and a2·b1+c2. Then, postprocessing is performed to perform ReLU operations on the results to obtain the final ReLU result.

[0132] It should be understood that those skilled in the art can set the opcode of the multiply-add instruction, the position of the opcode in the instruction format, and the position of the operation field as needed, and this disclosure does not impose any restrictions on this.

[0133] In one possible implementation, the device may be located in one or more of a graphics processing unit (GPU), a central processing unit (CPU), and an embedded neural network processing unit (NPU).

[0134] Please see Figure 5 , Figure 5This diagram illustrates an application scenario of the multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure. The control module 11 and processing module 12 can be processors 100. These processors can be general-purpose processors (e.g., central processing unit CPU, graphics processing unit GPU) or dedicated processors (e.g., artificial intelligence processors, scientific computing processors, or digital signal processors). The present disclosure does not limit the type of processor. The storage device 200 includes at least one target storage area 210, which can be a data storage area, such as a first storage area, a second storage area, a third storage area, a fourth storage area, etc. It is understood that the control module and / or processing module can access a target storage area 210 by performing read operations or write operations. Performing a read operation on a target storage area 210 by the control module and / or processing module can refer to the control module and / or processing module acquiring first data, second data, third data, fourth data, intermediate results, etc., from the target storage area 210. The control module and / or processing module performing a write operation on a target storage area 210 can mean that the control module and / or processing module writes fourth data, intermediate results, or other data into the target storage area 210. In related technologies, since the control module can execute multiple operations in parallel, to avoid conflicts, when the operation judgment submodule determines that the multiple operations executed in parallel by the control module and / or processing module are all operations on a target storage area 210, the operation judgment submodule controls the control module and / or processing module to execute only one of the multiple operations, while blocking other operations, which will lead to a decrease in the efficiency of the control module and / or processing module. The method provided in this disclosure further divides the target storage area 210 into multiple fine-grained areas 211. When the operation judgment submodule determines that multiple operations executed in parallel by the control module and / or processing module are all operations targeting a certain target storage area 210, the operation judgment submodule can determine whether the fine-grained areas 211 targeted by the multiple operations overlap. If the fine-grained areas 211 targeted by the operations do not overlap, the operation judgment submodule can control the control module and / or processing module to execute the multiple operations in parallel, thus greatly improving the efficiency of the control module and / or processing module. It should be noted that the storage device 200 can be located inside the control module and / or processing module (e.g., on-chip cache or registers), or it can be located outside the control module and / or processing module and can communicate with the control module and / or processing module (e.g., under-chip memory). This disclosure does not limit the type of storage device. The operations involved in this disclosure can be basic operations supported by the hardware of the control module and / or processing module, or micro-instructions (e.g., request signals) parsed from the basic operations. This disclosure does not limit the specific type of operation.The control module and / or processing module of this disclosure can execute two operations in parallel, or more than two operations in parallel. This disclosure does not limit the number of operations to be executed in parallel.

[0135] In one possible implementation, the control module 11 may also include an operation judgment submodule.

[0136] An operation judgment submodule is used to determine whether there is a second operation targeting the target storage area corresponding to the first operation before the control module or the processing module executes the first operation.

[0137] When the second operation exists, it is determined whether there is an overlap between the first fine-grained region in the target storage area currently targeted by the first operation and the second fine-grained region in the target storage area targeted by the second operation;

[0138] When there is no overlap between the first fine-grained region and the second fine-grained region, the control module or the processing module is controlled to perform the first operation.

[0139] The first operation includes at least one of the following: reading first data from the first storage area, reading second data from the second storage area, reading third data from the third storage area, and storing the operation result in the fourth storage area.

[0140] The first and second operations can be read or write operations on data such as first data, second data, third data, fourth data, and intermediate results. The target storage area can be any area of ​​data involved in the storage method, such as the first storage area, second storage area, third storage area, and fourth storage area; this disclosure does not impose any restrictions on this.

[0141] In one possible implementation, the target storage region may include at least one fine-grained region. The determination of the size and / or number of fine-grained regions may include one or any combination of methods determined by hardware design, methods based on multiply-accumulate operation strategies, and methods defined based on relevant parameters in the operation. For example, the method determined by hardware design means that the size of the fine-grained region is determined during hardware design, such as determining one or more rows of the target storage region as a fine-grained region. Based on the multiply-accumulate operation strategy, for example, if the fourth data is a two-dimensional matrix of size M*Q (M and Q are both positive integers), representing the number of bytes occupied by storage (i.e., M bytes per row, Q rows in total), it can be determined that M bytes constitute a fine-grained region, and the target storage region, i.e., the fourth storage region, includes Q fine-grained regions. The method defined based on relevant parameters in the operation includes dividing the target storage region into multiple fine-grained regions according to the size and / or number of fine-grained regions carried in the operation. It should be noted that the sizes of the multiple fine-grained regions can be the same or different. For example, the number of bits for each fine-grained region can be 64 bits, 256 bits, 512 bits, etc. The size and / or number of each fine-grained region can be determined according to requirements. This disclosure does not limit this.

[0142] In one possible implementation, the existence of an ongoing second operation targeting the target storage area can be determined based on its occupancy status. For example, the occupancy status list can be queried to determine if the target storage area is occupied; if it is, the result indicates that an ongoing second operation is occurring on the target storage area. This occupancy status list can be pre-set and stored on the storage device, or it can be generated before the processing and control modules begin executing a task and deregistered after the task is completed. When the occupancy status of any storage area changes, the processing and control modules update the contents of the occupancy status list to record the occupancy status of each storage area.

[0143] In one possible implementation, the existence of an ongoing second operation targeting the target storage area can be determined by querying the execution status of each operation. For example, the storage areas corresponding to the operation fields of each operation can be recorded, along with the execution status of each operation. If the execution status of the operation targeting the target storage area is incomplete, the result is that an ongoing second operation targeting the target operation area exists. Alternatively, the occupancy status of the operation field can be checked to determine whether the target storage area corresponding to the operation field is occupied, thereby determining whether an ongoing second operation targeting the target storage area exists. This disclosure does not limit the criteria for determining whether an ongoing second operation targeting the target storage area exists.

[0144] In one possible implementation, the second operation can be an operation on data, and the data targeted by the second operation can be the same as the data targeted by the first operation. In this case, the storage area of ​​the data targeted by the second operation is the same as the target storage area. When the second operation is not completed, there is a second operation targeting the target storage area; or the storage area of ​​the data targeted by the second operation overlaps with the target storage area. When the second operation operates on the overlapping area, there is a second operation targeting the target storage area.

[0145] In one possible implementation, before the first operation is performed on the target storage area, it can be determined whether there is an ongoing second operation on the target storage area.

[0146] In one possible implementation, during the execution of the first operation targeting the target storage area, it can also be determined whether a second operation targeting the target storage area is in progress.

[0147] The first and second fine-grained regions can be any of the multiple fine-grained regions within the target storage region. Alternatively, the entire storage region containing the target storage region can be divided into fine-grained regions, in which case the size of the fine-grained region targeted by each operation on the entire storage region is consistent.

[0148] Alternatively, each operation can divide the target storage area into fine-grained regions according to the fine-grained partitioning information carried in each operation. In this case, different operations can perform fine-grained partitioning of the same storage area with different degrees of granularity. The first fine-grained region can be any fine-grained region among multiple fine-grained regions divided by the first operation into, and the second fine-grained region can be any fine-grained region obtained by the second operation after fine-grained partitioning the storage area containing its operands. The sizes of the first and second fine-grained regions can be different.

[0149] For example, the first operation can carry the size of a first fine-grained region (the number of bits of data in each fine-grained region), and this first fine-grained region size can be set to 64 bits. The second operation can carry the size of a second fine-grained region (e.g., the number of bits of data in each fine-grained region), and this second fine-grained region size can be set to 256 bits. That is, when performing the first operation, each 64 bits is considered a fine-grained region, while when performing the second operation, each 256 bits is considered a fine-grained region. Alternatively, both the first and second operations can carry a fine-grained region size (e.g., the number of bits of data in each fine-grained region) of 512 bits. Similarly, the first operation can carry the number of first fine-grained regions (e.g., set to 4), while the second operation carries the number of second fine-grained regions (e.g., set to 8). That is, when performing the first operation, the target storage area is divided into 4 fine-grained regions, while when performing the second operation, the target storage area is divided into 8 fine-grained regions. It can be understood that the operation can also carry both the size and number of fine-grained regions simultaneously. The size and / or number of each fine-grained region can be determined according to requirements, and this disclosure does not limit this.

[0150] It is understandable that operations on the target storage area are operations on each fine-grained region within the target storage area. For example, target storage area A consists of rows 1 to 10, with each row representing a fine-grained region, and target storage area A comprises 10 fine-grained regions. A write operation on target storage area A can be viewed as a write operation on these 10 fine-grained regions. The execution process can be as follows: write the first fine-grained region (row 1), then write the second fine-grained region (row 2), then the third fine-grained region (row 3), and so on, until the tenth fine-grained region (row 10) is written, thus completing the write operation on target storage area A.

[0151] When an operation is performed on a target storage region, the state of a fine-grained region within that region can include a completed operation, an ongoing operation, or an unoperated operation. The current fine-grained region being operated on is in the "ongoing operation" state. Therefore, when an operation is performed on a target storage region, it can be considered that an operation is performed on a fine-grained region within that region, and the fine-grained region being operated on is the current fine-grained region being operated on.

[0152] In one possible implementation, the first fine-grained region in the target storage region currently targeted by the first operation may include a fine-grained region in the target storage region targeted by the first operation to be executed, typically the first fine-grained region. It may also include a fine-grained region in the target storage region currently targeted by the first operation being executed, and can be any fine-grained region. The second fine-grained region in the target storage region currently targeted by the second operation may be a fine-grained region in the target storage region currently targeted by the second operation being executed, and can be any fine-grained region.

[0153] In one possible implementation, the overlap between a first fine-grained region in the target storage area targeted by the first operation and a second fine-grained region in the target storage area targeted by the second operation can be determined based on physical addresses, pointer positions, and fine-grained region identifiers. For example, the current physical addresses of each operation can be recorded. Based on the current physical addresses of the first and second operations, and the correspondence between physical addresses and fine-grained regions, the first and second fine-grained regions in the target storage area targeted by the first and second operations can be determined, thereby determining whether the first and second fine-grained regions overlap. The physical address can include one or any combination of the start address, end address, set position address, or real-time operation address of the fine-grained region. Another example is setting pointers for each operation, pointing to the fine-grained region currently targeted by the operation. Based on the pointer positions of the first and second operations, the first and second fine-grained regions in the target storage area targeted by the first and second operations can be determined, thereby determining whether the first and second fine-grained regions overlap. For example, identifiers can be set for each fine-grained region, and the overlap between the first and second fine-grained regions can be determined by recording the identifier of the fine-grained region currently being operated on. The identifier can include any combination of letters, numbers, or symbols. The overlap between the first and second fine-grained regions can also be determined in other ways; this disclosure does not limit the criteria for determining whether the first and second fine-grained regions overlap.

[0154] In one possible implementation, if the first fine-grained region in the target storage area currently targeted by the first operation does not overlap with the second fine-grained region in the target storage area currently targeted by the second operation, the first fine-grained region may be a fine-grained region that the second operation has already completed, or it may be a fine-grained region that the second operation does not need to perform. In this case, executing the first operation will not affect the operation process and result of the second operation, and the first operation can be executed.

[0155] According to this embodiment, when a second operation exists targeting the target storage region corresponding to the first operation, it can be determined whether there is an overlap between the first fine-grained region currently targeted by the first operation and the second fine-grained region currently targeted by the second operation. If there is no overlap, the first operation is executed. In this way, the first operation and the second operation can be executed as long as their fine-grained regions do not overlap, allowing the first operation and the second operation to operate on the target storage region simultaneously, thereby improving the processor's processing efficiency.

[0156] In one possible implementation, the method may further include blocking the first operation when the first fine-grained region overlaps with the second fine-grained region.

[0157] In one possible implementation, the first fine-grained region and the second fine-grained region overlap, including complete or partial overlap. When the first and second fine-grained regions overlap, if the first operation is executed, the operation on the overlapping region may affect the execution of the second operation, leading to inaccurate results, or vice versa. In this case, the first operation can be blocked, i.e., its execution can be paused. The first operation can be executed after the second operation has completed its operation on the second fine-grained region within the target memory area. Alternatively, the first operation can be executed when the first and second fine-grained regions do not overlap.

[0158] In this embodiment, when the first fine-grained region and the second fine-grained region overlap, the first operation is blocked, which can avoid operation errors and inaccurate operation results caused by the overlap of the fine-grained regions of each operation, and ensure the correctness of each operation.

[0159] Figure 6a and Figure 6b A schematic diagram illustrating an application scenario of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is provided. Figure 6a and Figure 6b As shown, the overall storage area 20 includes a target storage area 21, which is divided into four fine-grained areas: fine-grained area 22, fine-grained area 23, fine-grained area 24, and fine-grained area 25.

[0160] like Figure 6aAs shown, currently it only includes write operations, and the write pointer wp represents the fine-grained area in the target storage area 21 that the write operation is currently targeting. At the beginning of the write operation, the write pointer wp points to the fine-grained area 22. First, it can be judged whether there is a second operation on the target storage area 21 that is in progress. If the judgment result is that there is no second operation, then the write operation on the fine-grained area 22 is started; when the write operation on the fine-grained area 22 is completed, the write pointer wp is incremented, that is, wp++, and it points to the next fine-grained area 23. After the same judgment, the write operation on the fine-grained area 23 is started; when the write operation on the fine-grained area 23 is completed, the write pointer wp is incremented and points to the next fine-grained area 24. After the same judgment, the write operation on the fine-grained area 24 is started.

[0161] For another example Figure 6b As shown, currently it includes two operations, a read operation and a write operation, where the read operation is the first operation and the write operation is the second operation. And the write pointer wp of the write operation and the read pointer rp of the read operation are used to represent the fine-grained areas that the write operation and the read operation are currently targeting respectively.

[0162] When performing the read operation (the first operation), it is judged whether there is a second operation on the target storage area 21 that is in progress. After judgment, currently there is a second operation, the write operation, on the target storage area 21. Further, it is judged whether the first fine-grained area in the target storage area 21 that the read operation (the first operation) is currently targeting ( Figure 6b the fine-grained area 22 therein) overlaps with the second fine-grained area in the target storage area 21 that the write operation (the second operation) is currently targeting ( Figure 6b the fine-grained area 24 therein). For example, it can be determined that the first fine-grained area and the second fine-grained area do not overlap according to the numbers of the fine-grained areas (22 and 24), or according to the relationship between rp and wp (rp = 0, wp = 2, rp < wp). Then, the read operation (the first operation) can be executed.

[0163] When the read operation on the fine-grained region 22 is completed, rp is incremented, i.e., rp++, and it points to the next fine-grained region 23. After the same judgment, the first operation starts to operate on the fine-grained region 23. When the read operation on the fine-grained region 23 is completed, rp is incremented and points to the next fine-grained region 24. In this case, it continues to judge whether there is an overlap between the first fine-grained region and the second fine-grained region. If the fine-grained region numbers are the same or the pointer rp = wp, it can be judged that the first fine-grained region in the target storage region 21 targeted by the first operation overlaps with the second fine-grained region in the target storage region 21 targeted by the second operation, then the first operation cannot be executed and the first operation is blocked. When the second operation completes the operation on the fine-grained region 24 and wp is incremented and points to the next fine-grained region 25, since the numbers of the fine-grained regions are different (24 and 25) or the pointer rp < wp, the first operation can be executed.

[0164] In a possible implementation manner, at least one of the first operation and the second operation can be a write operation. That is, when the operation on the operand is write-after-read (the second operation is a write operation and the first operation is a read operation), read-after-write (the second operation is a read operation and the first operation is a write operation), or write-after-write (both the second operation and the first operation are write operations), the method in the embodiments of the present disclosure can be adopted.

[0165] For example, if the first operation is a read operation and the second operation is a write operation, the data that the first operation needs to read needs to be the data after the write operation of the second operation. If the number of the second fine-grained region in the target storage region targeted by the second operation is 8, then the first operation can only read the data of the fine-grained regions numbered before 8. That is to say, if the first fine-grained region in the target storage region currently targeted by the first operation is any one of the fine-grained regions numbered 1 to 7, the first operation can be executed.

[0166] In a possible implementation manner, if both the first operation and the second operation are read operations, the relationship between the fine-grained regions of the first operation and the second operation will not affect the operation result. The method in the embodiments of the present disclosure can be adopted, or the first operation can be directly executed without judging the fine-grained regions.

[0167] In this embodiment, when at least one of the first operation and the second operation is a write operation, by using the method in the embodiments of the present disclosure, by dividing the target storage region into one or more fine-grained regions and performing operations in units of the fine-grained regions, operations such as read-after-write, write-after-read, and write-after-write can be correctly executed to obtain accurate execution results, and the waiting time between operations can be reduced, thereby improving the execution efficiency of the processor.

[0168] In one possible implementation, the size and / or number of the fine-grained regions can be determined based on at least one of the regions containing data of a set length and the regions containing data of a set dimension.

[0169] It is understood that determining the size and / or quantity of the fine-grained region can be pre-set before the operation is generated, or it can be determined in real time when each operation is generated. Pre-setting the size and / or quantity of the fine-grained region before the operation can include determining the size and / or quantity based on at least one of a pre-set data region of a preset length or a pre-set data region of a preset dimension. The pre-set data of the preset length and the pre-set data of the preset dimension can be independent of the operands of each operation, or they can be determined in advance based on a combination of the operands of each operation, depending on requirements. Determining the size and / or quantity of the fine-grained region in real time when each operation is generated can include determining the data of the preset length or the data of the preset dimension based on the operands of each operation; that is, the size and / or quantity of the fine-grained region can be determined in real time based on the different operands of each operation.

[0170] For example, the size and / or number of fine-grained regions can be determined based on the size of the region containing data of a set length. For instance, the size of the fine-grained region can be set based on the size of the target storage region containing the data of a set length, and this region can have a fixed bit width. For example, if data B is 20*10*5 three-dimensional data, and its storage method in the target storage region is 40*25 (i.e., 40 bits of data per line, 25 lines in total), then the set length can be set to 40 bits, and each line of the target storage region can be set as a fine-grained region; the target storage region of data B can be divided into 25 fine-grained regions. Alternatively, each 5 lines of the target storage region can be set as a fine-grained region, and the target storage region of data B can be divided into 5 fine-grained regions. This disclosure does not impose any limitations on this.

[0171] It is understood that, based on at least one of the regions containing data of a set length and the regions containing data of a set dimension, the size and / or number of fine-grained regions can be determined in the target storage region, or in the overall storage region containing the target storage region, or in other regions within the overall storage region. The above examples only illustrate one scenario, and this disclosure does not limit the applicable scope of determining the size and / or number of fine-grained regions based on at least one of the regions containing data of a set length and the regions containing data of a set dimension.

[0172] In one possible implementation, the size and / or number of fine-grained regions can be determined based on the size of the region containing the data of a set dimension. For example, if data C is a 20*10 two-dimensional data, the target storage area of ​​data C can be divided into 10 fine-grained regions based on the set dimension of 1 and the length of 20.

[0173] Furthermore, the size and / or number of fine-grained regions can be determined simultaneously based on the size of the region containing data of a specified length and the size of the region containing data of a specified dimension within the target storage area. For example, for data C, fine-grained regions can be divided based on data with a specified dimension of 2 and a size of 4*2, thereby dividing the target storage area of ​​data C into 25 fine-grained regions.

[0174] It should be understood that those skilled in the art can set the size and / or number of fine-grained regions according to actual circumstances, and this disclosure does not impose any restrictions on this.

[0175] In this embodiment, the size and / or quantity of the fine-grained region are determined based on the size of the region containing data of a set length and / or the size of the region containing data of a set dimension. This allows for the division of the fine-grained region according to the data characteristics, improving the flexibility of the fine-grained region division and thus increasing the efficiency of multi-operation execution. It also makes the division results of the fine-grained region more consistent with the characteristics of different operands, thereby adapting to the processing needs of different types of operands and further improving the overall execution efficiency of multi-operation.

[0176] In one possible implementation, the size and / or number of the fine-grained regions may be determined based on at least one of hardware computing power and hardware bandwidth.

[0177] Among them, hardware computing power can be the amount of data that the hardware can process in parallel within a computing cycle, and hardware bandwidth can be the data transmission capacity, such as the amount of data transmitted per unit time.

[0178] For example, a processor using this processor operation method has a hardware computing capability of processing 100 bits of data in parallel within one computing cycle and a hardware bandwidth of transmitting 200 bits of data per unit time. For a target storage area of ​​1000 bits in size, the target storage area can be divided into 10 fine-grained areas based on the hardware computing capability, with each fine-grained area including 100 bits of data; or the target storage area can be divided into 5 fine-grained areas based on the hardware bandwidth, with each fine-grained area including 200 bits of data.

[0179] It should be understood that hardware computing power and hardware bandwidth may vary depending on the processor hardware, and this disclosure does not limit hardware computing power or hardware bandwidth.

[0180] It is understood that, based on at least one of hardware computing power and hardware bandwidth, the size and / or number of fine-grained regions can be determined within the target storage region, or within the overall storage region containing the target storage region, or within other regions of the overall storage region. The above examples only illustrate one scenario, and this disclosure does not limit the applicable scope of determining the size and / or number of fine-grained regions based on at least one of hardware computing power and hardware bandwidth.

[0181] In this way, the size and / or number of fine-grained regions can be determined based on the processor's processing power (hardware computing power and / or hardware bandwidth), making the division of fine-grained regions more in line with the needs of different hardware usage environments. This allows the operations performed based on the fine-grained regions to be synchronized with the processor's processing power, maximizing the hardware's execution efficiency and thus improving the processor's processing efficiency.

[0182] In one possible implementation, the first operation can be an operation in a first instruction to be executed, and the second operation can be an operation in a second instruction to be executed, wherein the second instruction to be executed is an instruction to be executed in the instruction queue that precedes the first instruction to be executed.

[0183] In this embodiment, the first operation and the second operation can be operations in different instructions. By using the method in this embodiment, the efficiency of instruction execution can be improved.

[0184] In one possible implementation, the first operation and the second operation can also be two operations in the same instruction to be executed (such as a multiply-accumulate instruction). The second operation can be independent of the first operation, or the second operation can be based on the result of the first operation.

[0185] In one possible implementation, the target storage area may include one or more non-operable areas, or may include contiguous or non-contiguous non-operable areas.

[0186] In one possible implementation, the target storage region may include one or more operable regions, and may include contiguous or non-contiguous operable regions. This disclosure does not limit this.

[0187] In one possible implementation, the target storage region corresponding to the first operation is identified, and then it is determined whether a second operation is currently in progress targeting the target storage region. If a second operation exists, it is determined whether a first fine-grained region in the target storage region targeted by the first operation is located within an operable region. If a second operation exists and the first fine-grained region in the target storage region targeted by the first operation is located within an operable region, it is then determined whether there is any overlap between the first fine-grained region in the target storage region targeted by the first operation and the second fine-grained region in the target storage region targeted by the second operation. If there is no overlap between the first fine-grained region and the second fine-grained region, the first operation is executed.

[0188] In one possible implementation, the inoperable area may include a prohibited operation area and non-prohibited operation areas. If the first operation is a write operation, and some data in the data corresponding to the first operation is immutable, the storage area containing that portion of data can be set as a prohibited operation area to avoid accidental modification of that data. If the ongoing second operation is a read operation (read-after-write) that reads data prior to the first operation, one or more fine-grained areas containing the second operation can be set as non-prohibited operation areas. After the second operation completes reading from the non-prohibited operation area, the non-prohibited operation area can be changed to an operable area. This disclosure does not limit the classification and division methods of inoperable areas.

[0189] In this embodiment, it can first determine whether the fine-grained region of the first operation is operable, and then determine the relationship between the fine-grained regions of different operations. On the one hand, it improves the efficiency of the judgment, and on the other hand, it can protect the specified data to prevent erroneous operations, and can also prohibit reading and writing of the specified space, thereby reserving the space for performing other operations, further improving the flexibility of the processor when performing fine-grained synchronization.

[0190] In one possible implementation, the non-operable region may be a plurality of fine-grained regions, including the second fine-grained region, and the position of the second fine-grained region within the non-operable region is updated with the operation position of the second operation. The method may further include: updating the position of the non-operable region after the second fine-grained region in the target storage region targeted by the second operation is moved out of the non-operable region.

[0191] In other words, the inoperable regions of multiple fine-grained regions, including the second fine-grained region, do not necessarily update with the update of the second fine-grained region in the target storage region targeted by the second operation. The position of the inoperable regions is updated only after the second fine-grained region in the target storage region is moved out of the inoperable region. For example, the inoperable region can be R fine-grained regions (R is an integer greater than 1), including the second fine-grained region. The current inoperable region includes the 2nd to the 2+R-1th fine-grained regions. After the second operation completes execution within the R fine-grained regions and then moves out of the inoperable region, the position of the inoperable region is updated along with the position of the fine-grained region targeted by the second operation. The updated inoperable region includes the 2+Rth to the 2+R+R-1th fine-grained regions. The size of R can be arbitrarily determined according to requirements.

[0192] Figure 7a and Figure 7b A schematic diagram illustrating an application scenario of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is provided. Figure 7a As shown, the target storage area 30 includes eight fine-grained areas, of which the operable area includes five fine-grained areas (fine-grained area 31, fine-grained area 35, fine-grained area 36, ​​fine-grained area 37, and fine-grained area 38), and the non-operable area M0 includes three fine-grained areas (fine-grained area 32, fine-grained area 33, and fine-grained area 34). The second fine-grained area in the target storage area 30 currently targeted by the second operation is fine-grained area 32.

[0193] After the second operation completes its operation on fine-grained region 32, the second fine-grained region in the target storage region 30 currently targeted by the second operation becomes fine-grained region 33. At this time, the second fine-grained region (fine-grained region 33) in the target storage region 30 currently targeted by the second operation has not been moved out of the non-operable region, and the position of the non-operable region is not updated. After the second operation completes its operation on fine-grained region 33, the second fine-grained region in the target storage region 30 currently targeted by the second operation becomes fine-grained region 34. At this time, the position of the non-operable region is not updated. The second fine-grained region (fine-grained region 34) in the target storage region 30 has not yet been moved out of the non-operable region, and the position of the non-operable region is not updated. After the second operation completes the operation on fine-grained region 34, the second fine-grained region in the target storage region 30 currently targeted by the second operation is fine-grained region 35. At this time, the second fine-grained region (fine-grained region 35) in the target storage region 30 currently targeted by the second operation has been moved out of the non-operable region, and the position of the non-operable region is updated to fine-grained regions 35, 36, and 37. It should be noted that this disclosure does not limit the size of the non-operable region.

[0194] like Figure 7b As shown, after updating the location of the non-operable area, in the target storage area 30, the operable area includes 5 fine-grained areas (fine-grained area 31, fine-grained area 32, fine-grained area 33, fine-grained area 34 and fine-grained area 38), and the non-operable area M0 includes 3 fine-grained areas (fine-grained area 35, fine-grained area 36 and fine-grained area 37).

[0195] In this way, it is not necessary to update the location of non-operable areas in real time, which reduces the overhead of updating non-operable areas.

[0196] In one possible implementation, the inoperable region may be a plurality of fine-grained regions, including the second fine-grained region, and the second fine-grained region is located at a set position within the inoperable region, the position of the inoperable region being updated with the operation position of the second operation.

[0197] In other words, when the inoperable region comprises multiple fine-grained regions, including the second fine-grained region, the position of the second fine-grained region within the inoperable region can be set (e.g., middle position, last position, etc.). The position of the inoperable region is updated according to the operation position of the second operation. For example, the inoperable region can be R fine-grained regions, including the second fine-grained region. The current inoperable region includes the 2nd to the 2+R-1th fine-grained regions, and the set position of the second fine-grained region within the inoperable region is the Sth (where S≤R). After the second operation completes its operation on the currently targeted fine-grained region, the second operation begins its operation on the next fine-grained region. At this time, the position of the inoperable region is updated according to the operation position of the second operation, and the updated inoperable region includes the 2+1 to the 2+Rth fine-grained regions. The size of R and the value of S can be determined according to requirements. This disclosure does not limit the number of fine-grained regions included in the inoperable region or the position of the second fine-grained region within the inoperable region.

[0198] Figure 8a and Figure 8b A schematic diagram illustrating an application scenario of a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is provided. Figure 8aAs shown, the target storage area 40 includes eight fine-grained areas. The operable area includes five fine-grained areas (fine-grained area 41, fine-grained area 45, fine-grained area 46, fine-grained area 47, and fine-grained area 48), and the non-operable area M1 includes three fine-grained areas (fine-grained area 42, fine-grained area 43, and fine-grained area 44). The second fine-grained area in the target storage area 40 targeted by the second operation is set to the second fine-grained area located in the non-operable area M1, namely fine-grained area 43.

[0199] After the second operation completes its operation on the fine-grained region 43, the second fine-grained region in the target storage region 40 currently targeted by the second operation is the fine-grained region 44. At this time, the position of the non-operable region is updated according to the operation position of the second operation, so that the second fine-grained region in the target storage region 40 currently targeted by the second operation is located in the second fine-grained region of the non-operable region M1.

[0200] like Figure 8b As shown, after updating the location of the inoperable area, in the target storage area 40, the operable area includes 5 fine-grained areas (fine-grained area 41, fine-grained area 42, fine-grained area 46, fine-grained area 47 and fine-grained area 48), and the inoperable area M1 includes 3 fine-grained areas (fine-grained area 43, fine-grained area 44 and fine-grained area 45).

[0201] In this way, the location of non-operable areas can be updated in real time, improving the synchronization of fine-grained processing and thus further improving the efficiency of data synchronization processing.

[0202] In one possible implementation, the target storage area may include a circular buffer storage area. The circular buffer storage area can be used to cyclically store data.

[0203] Figure 9 A schematic diagram showing the circular buffer storage area of ​​a multiply-accumulate instruction processing apparatus according to an embodiment of the present disclosure is provided. Figure 9 As shown, the target storage area 50 includes a circular buffer storage area 51 with addresses from start_addr to end_addr.

[0204] For example, the second operation is a write operation, which writes the operand to the circular buffer storage area 51. Its address pointer point starts from start_addr and stores data sequentially downwards until end_addr, that is, the storage space of the circular buffer storage area 51 is filled. At this time, the address pointer point jumps back to start_addr and checks whether the address has been used by the first operation that needs to be synchronized. If it has been used, the data is stored at this address, overwriting the original data. Then the address pointer point moves downwards sequentially until end_addr. At this time, the data can be overwritten again, and the above process is repeated.

[0205] In this embodiment, a circular buffer storage area is used to store data, which can save data storage space and improve storage space utilization.

[0206] In one possible implementation, the circular buffer storage area can be divided into multiple fine-grained regions. For each fine-grained region, the overwriteability of data in the fine-grained region can be managed through a list, flags, or other means. For example, an overwrite flag can be set to indicate whether data in the fine-grained region is overwriteable.

[0207] For example, if the first operation is a read operation and the second operation is a write operation (i.e., write first and then read), the write pointer wp and the read pointer rp can be used to represent the fine-grained regions currently targeted by the second and first operations, respectively. When the coverage flag of the second fine-grained region currently targeted by the second operation is overwhelmable, the second operation can be executed to write data. After the data is written, the coverage flag of the second fine-grained region is set to non-overwhelmable, wp++, and the second fine-grained region currently targeted by the second operation becomes the next fine-grained region. If wp > end_addr, then wp = start_addr. When the first and second fine-grained regions currently targeted by the first operation do not overlap, and the coverage flag of the first fine-grained region is non-overwhelmable, the first operation can be executed to read data. After the data is read, the coverage flag of the first fine-grained region is set to overwhelmable, rp++, and the first fine-grained region currently targeted by the first operation becomes the next fine-grained region. If rp > end_addr, then rp = start_addr. When the first and second fine-grained regions overlap, i.e., rp = wp, the first operation cannot be executed. The first operation must wait for the second operation to complete its operation on the currently targeted second fine-grained region before it can be executed.

[0208] In this embodiment, the circular buffer access area is divided into multiple fine-grained areas, so that multiple operations can operate on the circular buffer storage area simultaneously, thereby improving processing efficiency.

[0209] In one possible implementation, the fine-grained region may include a status identifier, which may include a completed or incomplete state for the operation on the fine-grained region. Specifically, when the first and second fine-grained regions do not overlap, it is determined whether the status identifier of the first fine-grained region is in the completed state; if so, the first operation is executed.

[0210] In one possible implementation, the fine-grained region may include a status flag, which may indicate whether the operation on the fine-grained region is completed or incomplete. For example, the status flag can be represented using 0 and 1, where 0 indicates that the operation on the fine-grained region is incomplete and 1 indicates that the operation on the fine-grained region is completed, or 0 indicates that the operation on the fine-grained region is completed and 1 indicates that the operation on the fine-grained region is incomplete. This disclosure does not limit the representation of the status flag.

[0211] In one possible implementation, the second operation can set the status flags of the fine-grained regions in the target storage region that have been operated on to the "operation completed" state, and set the status flags of the fine-grained regions that have not been operated on or are currently being operated on to the "operation incomplete" state. Alternatively, it can set the status flags of some fine-grained regions in the fine-grained regions that have been operated on to the "operation completed" state, and set the status flags of the other fine-grained regions to the "operation incomplete" state. For example, if the second operation has completed operations on 5 fine-grained regions, the status flags of the first 3 fine-grained regions can be set to the "operation completed" state, and the status flags of the other fine-grained regions can be set to the "operation incomplete" state.

[0212] In one possible implementation, when a second operation is in progress targeting a target storage region, for the first fine-grained region currently targeted by the first operation and the second fine-grained region currently targeted by the second operation, after determining that the first fine-grained region and the second fine-grained region do not overlap, it can be determined whether the status flag of the first fine-grained region is in the operation completed state; if the status flag of the first fine-grained region is in the operation completed state, the first operation can be executed.

[0213] In this embodiment, the fine-grained region includes a status identifier. When the first fine-grained region and the second fine-grained region do not overlap, the first operation is determined to be executable based on the status identifier of the first fine-grained region, which can improve processing efficiency while improving the accuracy of data processing.

[0214] In one possible implementation, the fine-grained region may include a status identifier, which may include a completed or incomplete state for operating the fine-grained region. Specifically, it is determined whether the status identifier of the first fine-grained region is in the completed state; if so, the first operation is performed when the first and second fine-grained regions do not overlap.

[0215] In other words, when a second operation is in progress targeting a target storage region, for the first fine-grained region currently targeted by the first operation and the second fine-grained region currently targeted by the second operation, after determining that the status of the first fine-grained region is marked as completed, the first operation can be executed based on the overlap between the first and second fine-grained regions. If the first and second fine-grained regions do not overlap, the first operation can be executed.

[0216] In this embodiment, the fine-grained region includes a status identifier. After determining that the status identifier of the first fine-grained region is in the state of operation completion, the first operation can be determined as to be executable based on the overlap relationship between the first and second fine-grained regions. This can improve the accuracy of data processing while improving the processing efficiency of the processor.

[0217] In one possible implementation, the second operation and the first operation are operations on the same data. That is, the storage areas of the second operation and the first operation are both target storage areas and completely overlap. After dividing the target storage area of ​​the data into multiple fine-grained areas, according to the method in the embodiments of this disclosure, two operations operating on the same data can be executed in parallel without affecting the execution results of each operation.

[0218] In one possible implementation, the method may further include: dividing the overall storage area containing the target storage area into multiple fine-grained regions.

[0219] In one possible implementation, the target storage area can be a portion or all of the overall storage area of ​​the storage device, wherein the overall storage area includes a plurality of pre-defined fine-grained areas.

[0220] For example, the overall storage area containing the target storage region is RAM1. RAM1 can include m pre-defined fine-grained regions (m is a positive integer). The target storage region can occupy n fine-grained regions in RAM1 (n is a positive integer, and n <= m). It should be noted that the target storage region can also include a portion of a fine-grained region. In RAM1 as shown in the example above, assume that each fine-grained region is a row in the overall storage area RAM1, and each row is 100 bits. The target storage region can include the first (n-1) complete fine-grained regions, and also include a portion of the last fine-grained region, for example, the first 80 bits in the nth row (nth fine-grained region) of RAM1.

[0221] In one possible implementation, when the overall storage area of ​​the storage device is divided into multiple fine-grained regions, for any operation on any target storage area within the overall storage area—whether it's the target storage area of ​​the data targeted by the first operation or the overlapping area between the storage area of ​​the second operation and the target storage area—the fine-grained region within the target storage area or the overlapping area can be determined based on the fine-grained division result of the overall storage area. Any operand of any operation resides in a fine-grained region of the same size within the overall storage area.

[0222] In one possible implementation, the size and / or number of fine-grained regions of the overall storage area can be determined based on the hardware characteristics of the storage device. That is, the size and / or number of fine-grained regions of the overall storage area can be determined based on at least one of the hardware computing power and hardware bandwidth of the storage device.

[0223] In this embodiment, the overall storage area containing the target storage area is divided into multiple fine-grained areas. Any operation on any target storage area within the overall storage area can be executed with the same fine-grained size. When different operations are performed in parallel according to the method in this embodiment, they can be synchronized more easily, improving the parallelism of operations and thus improving the processing efficiency of the processor.

[0224] In one possible implementation, the method may further include:

[0225] Based on the first fine-grained partitioning information carried in the first operation, the target storage area is divided into multiple fine-grained regions, and

[0226] Based on the second fine-grained partitioning information carried in the second operation, the storage area of ​​the operands of the second operation is divided into multiple fine-grained regions.

[0227] In one possible implementation, fine-grained partitioning information can be carried in the operation. This information may include the size and / or quantity of fine-grained elements. Different operations can carry different fine-grained partitioning information. Operations of the same type can carry the same fine-grained partitioning information. Fine-grained partitioning information can be carried at the setting position of the operand in the operation, or it can be carried in the opcode or operand to indicate whether fine-grained partitioning is performed. This disclosure does not limit the content or representation of the fine-grained partitioning information.

[0228] In one possible implementation, the target storage area is divided into multiple first fine-grained regions based on the first fine-grained partitioning information carried in the first operation. Other regions within the overall storage area where the data targeted by the first operation resides may not be fine-grained, or they may be fine-grained based on the fine-grained partitioning information carried by other operations. This disclosure does not limit this.

[0229] It is understood that the first and second fine-grained partitioning information can be consistent or inconsistent. When the first and second fine-grained partitioning information are inconsistent, the target storage area can be simultaneously partitioned according to the second fine-grained partitioning information. That is, for the target storage area, different operations can divide it into multiple fine-grained regions of different sizes or numbers. In this case, based on the physical address of the first fine-grained region in the target storage area currently targeted by the first operation and the physical address between the second fine-grained regions in the target storage area currently targeted by the second operation, it can be determined whether the first and second fine-grained regions overlap, and the first and second operations can be executed in parallel based on the determination result.

[0230] In one possible implementation, the fine-grained partitioning information carried in each operation may include the size and / or number of the fine-grained regions determined based on at least one of the regions where operation data of a set length is located and the regions where operands of a set dimension are located, so that the fine-grained partitioning results are more consistent with the type or attributes of operands in the operation.

[0231] In this embodiment, the target storage area is divided into multiple fine-grained regions based on the first fine-grained partitioning information carried in the first operation, and the storage area of ​​the second operation is divided into multiple fine-grained regions based on the second fine-grained partitioning information carried in the second operation. Performing fine-grained partitioning based on the fine-grained partitioning information carried in the operation makes the partitioning results more consistent with the processing requirements of each operation, and allows for more flexible parallel operation.

[0232] It should be understood that those skilled in the art can divide and set up the target storage area into fine-grained regions according to the actual situation, and this disclosure does not impose any restrictions on this.

[0233] It should be noted that although the multiply-accumulate instruction processing apparatus has been described above as an example, those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly configure each module according to their personal preferences and / or actual application scenarios, as long as it conforms to the technical solution of this disclosure.

[0234] Figure 10 A flowchart illustrating a multiply-accumulate instruction processing method according to an embodiment of the present disclosure is shown. Figure 10 As shown, the method is applied to the above-mentioned multiply-accumulate instruction processing device, and the method includes steps S51 and S52.

[0235] In step S51, the received multiply-accumulate instruction is parsed to obtain the opcode and operation field of the multiply-accumulate instruction. The multiply-accumulate operation processing corresponding to the multiply-accumulate instruction is determined according to the opcode. The first data, second data, third data and fourth storage area required to execute the multiply-accumulate instruction are obtained according to the operation field. The multiply-accumulate operation strategy is determined.

[0236] In step S52, the first data, the second data, and the third data are multiplied and added according to the multiplication-addition operation strategy to obtain the operation result, and the operation result is stored in the fourth storage area.

[0237] The opcode indicates that the multiply-accumulate instruction performs a multiply-accumulate operation on the data. The operation field includes a first storage area for storing the first data, a second storage area for storing the second data, a third storage area for storing the third data, and a fourth storage area.

[0238] In one possible implementation, the first data, the second data, and the third data are multiplied and added according to the multiplication-addition strategy to obtain the operation result, including:

[0239] According to the multiplication-addition operation strategy, the order of operation, the corresponding operation relationship, and the order of operation are determined from the first data, the second data, and the third data.

[0240] Based on the operational correspondence and operational processing order, the previously processed data is subjected to a first operational processing to obtain an intermediate result;

[0241] Based on the aforementioned operational correspondence and processing order, a second operational process is performed on the intermediate results and the subsequent operational data to obtain the operational result.

[0242] Wherein, the first operation processing is multiplication operation processing or addition operation processing, the second operation processing is the same as the multiplication operation processing or addition operation processing, and the first operation processing and the second operation processing are different.

[0243] In one possible implementation, the operation domain includes the multiply-accumulate operation strategy.

[0244] In one possible implementation, the opcode is also used to indicate the multiply-accumulate operation strategy.

[0245] In one possible implementation, performing multiplication and addition operations on the first data, the second data, and the third data according to the multiplication and addition strategy includes:

[0246] The multiplication operation in the multiply-add operation is performed using at least one multiplier.

[0247] The addition operation in the multiply-add operation is performed using at least one adder.

[0248] In one possible implementation, the opcode includes a preprocessing identifier, or the operation field includes the preprocessing identifier; the method further includes:

[0249] Determine the processing operation corresponding to the preprocessing identifier and the corresponding data to be processed, wherein the data to be processed includes at least one of the first data, the second data, and the third data;

[0250] Before performing multiplication and addition operations on the first data, the second data, and the third data, the corresponding data to be processed is preprocessed according to the processing operation corresponding to the preprocessing identifier.

[0251] In one possible implementation, the opcode includes a post-processing identifier, or the operation field includes the post-processing identifier; the method further includes:

[0252] Determine the processing operation corresponding to the post-processing identifier;

[0253] The calculation result is post-processed according to the processing operation corresponding to the post-processing identifier, and the post-processed calculation result is stored in the fourth storage area.

[0254] In one possible implementation, the processing operations include at least one of the following: data format conversion processing and data computation processing.

[0255] The data format conversion process includes at least one of the following: floating-point number conversion, fixed-point number conversion, and floating-to-fixed-point number conversion.

[0256] The data processing includes at least one of the following: trigonometric function processing, inverse trigonometric function processing, logarithmic processing, exponential processing, maximum value processing, minimum value processing, convolution processing, pooling processing, fully connected processing, and activation processing.

[0257] In one possible implementation, the method further includes:

[0258] Before the first operation, determine whether there is a second operation targeting the target storage area corresponding to the first operation;

[0259] When the second operation exists, it is determined whether there is an overlap between the first fine-grained region in the target storage area currently targeted by the first operation and the second fine-grained region in the target storage area targeted by the second operation;

[0260] When there is no overlap between the first fine-grained region and the second fine-grained region, the first operation is executed.

[0261] The first operation includes at least one of the following: reading first data from the first storage area, reading second data from the second storage area, reading third data from the third storage area, and storing the operation result in the fourth storage area.

[0262] In one possible implementation, the method further includes:

[0263] When there is overlap between the first fine-grained region and the second fine-grained region, the first operation is blocked.

[0264] In one possible implementation, at least one of the first operation and the second operation is a write operation.

[0265] In one possible implementation, the size and / or number of the fine-grained regions are determined based on at least one of the regions containing data of a set length and the regions containing data of a set dimension.

[0266] In one possible implementation, the size and / or number of the fine-grained regions are determined based on at least one of hardware computing power and hardware bandwidth.

[0267] In one possible implementation, the method further includes:

[0268] Store the first data, the second data, and the third data.

[0269] In one possible implementation, the received multiply-accumulate instruction is parsed to obtain its opcode and operation field, including:

[0270] Store the multiply-accumulate instructions;

[0271] The multiply-accumulate instruction is parsed to obtain its opcode and operation field.

[0272] A storage instruction queue, the instruction queue including a plurality of instructions to be executed arranged in the order of execution, the plurality of instructions to be executed including the multiply-accumulate instruction.

[0273] In one possible implementation, the method further includes:

[0274] When it is determined that the first instruction to be executed among the plurality of instructions to be executed has a dependency relationship with the zeroth instruction to be executed preceding the first instruction to be executed, the first instruction to be executed is cached, and after it is determined that the zeroth instruction to be executed has been executed, the execution of the first instruction to be executed is controlled.

[0275] The dependencies between the first instruction to be executed and the zeroth instruction to be executed preceding the first instruction to be executed include:

[0276] There is an overlapping area between the storage area storing the data required for the first instruction to be executed and the storage area storing the data required for the zeroth instruction to be executed.

[0277] The multiplication and addition instruction processing method provided in this disclosure can perform multiplication and addition operations between multiple data with a single multiplication and addition instruction. Compared with the process in related technologies that requires at least two instructions to perform multiplication and addition operations on data, the processing efficiency of multiplication and addition operations on data is high, the processing speed is fast, and the applicability is wide.

[0278] It should be noted that although the above embodiments have been used as examples to illustrate the multiplication-addition instruction processing method, those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly configure each module according to their personal preferences and / or actual application scenarios, as long as it conforms to the technical solution of this disclosure.

[0279] The multiplication and addition instruction processing method provided in this disclosure can perform multiplication and addition operations between multiple data with a single multiplication and addition instruction. Compared with the process in related technologies that requires at least two instructions to perform multiplication and addition operations on data, the processing efficiency of multiplication and addition operations on data is high, the processing speed is fast, and the applicability is wide.

[0280] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0281] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0282] In the embodiments provided in this disclosure, it should be understood that the disclosed systems and devices can be implemented in other ways. For example, the system and device embodiments described above are merely illustrative. For instance, the division of devices, apparatuses, and modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system or apparatus, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices, apparatuses, or modules may be electrical or other forms.

[0283] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0284] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software program modules.

[0285] If the integrated module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMSDD). Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0286] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0287] The following terms are provided to facilitate understanding of the technical solutions disclosed herein:

[0288] Clause A1, a multiply-accumulate instruction processing apparatus, the apparatus comprising:

[0289] The control module is used to parse the received multiply-accumulate instruction, obtain the opcode and operation field of the multiply-accumulate instruction, determine the multiply-accumulate operation processing corresponding to the multiply-accumulate instruction based on the opcode, obtain the first data, second data, third data and fourth storage area required to execute the multiply-accumulate instruction based on the operation field, and determine the multiply-accumulate operation strategy.

[0290] The processing module is configured to perform multiplication and addition operations on the first data, the second data, and the third data according to the multiplication and addition operation strategy, obtain the operation result, and store the operation result in the fourth storage area.

[0291] The opcode indicates that the multiply-accumulate instruction performs a multiply-accumulate operation on the data. The operation field includes a first storage area for storing the first data, a second storage area for storing the second data, a third storage area for storing the third data, and a fourth storage area.

[0292] Clause A2. The apparatus according to Clause A1 performs multiplication and addition operations on the first data, the second data, and the third data according to the multiplication and addition operation strategy to obtain the operation result, including:

[0293] According to the multiplication-addition operation strategy, the order of operation, the corresponding operation relationship, and the order of operation are determined from the first data, the second data, and the third data.

[0294] Based on the operational correspondence and operational processing order, the previously processed data is subjected to a first operational processing to obtain an intermediate result;

[0295] Based on the aforementioned operational correspondence and processing order, a second operational process is performed on the intermediate results and the subsequent operational data to obtain the operational result.

[0296] Wherein, the first operation processing is multiplication operation processing or addition operation processing, the second operation processing is the same as the multiplication operation processing or addition operation processing, and the first operation processing and the second operation processing are different.

[0297] Clause A3, the apparatus according to Clause A1, wherein the operating domain includes the multiply-accumulate operation strategy.

[0298] Clause A4. In the apparatus described in Clause A1, the opcode is also used to indicate the multiply-accumulate operation strategy.

[0299] Clause A5. The apparatus according to Clause A1, wherein the processing module includes at least one adder and at least one multiplier.

[0300] Each multiplier is used to perform the multiplication operation in the multiply-add operation process;

[0301] Each adder is used to perform the addition operation in the multiply-add operation.

[0302] Clause A6. In the apparatus described in Clause A1, the opcode includes a preprocessing identifier, or the operation field includes the preprocessing identifier.

[0303] The control module is further configured to determine the processing operation corresponding to the pre-processing identifier and the corresponding data to be processed, wherein the data to be processed includes at least one of the first data, the second data and the third data;

[0304] The processing module is further configured to preprocess the corresponding data to be processed according to the processing operation corresponding to the preprocessing identifier before performing multiplication and addition operations on the first data, the second data and the third data.

[0305] Clause A7. In the apparatus described in Clause A1, the opcode includes a post-processing identifier, or the operation field includes the post-processing identifier.

[0306] The control module is further configured to determine the processing operation corresponding to the post-processing identifier;

[0307] The processing module is further configured to perform post-processing on the calculation result according to the processing operation corresponding to the post-processing identifier, and store the post-processed calculation result in the fourth storage area.

[0308] Clause A8. The apparatus described in Clause A6 or Clause A7, wherein the processing operation includes at least one of the following: data format conversion processing and data computation processing.

[0309] The data format conversion process includes at least one of the following: floating-point number conversion, fixed-point number conversion, and floating-to-fixed-point number conversion.

[0310] The data processing includes at least one of the following: trigonometric function processing, inverse trigonometric function processing, logarithmic processing, exponential processing, maximum value processing, minimum value processing, convolution processing, pooling processing, fully connected processing, and activation processing.

[0311] Clause A9. The control module of the apparatus according to Clause A1 includes:

[0312] An operation judgment submodule is used to determine whether there is a second operation targeting the target storage area corresponding to the first operation before the control module or the processing module executes the first operation.

[0313] When the second operation exists, it is determined whether there is an overlap between the first fine-grained region in the target storage area currently targeted by the first operation and the second fine-grained region in the target storage area targeted by the second operation;

[0314] When there is no overlap between the first fine-grained region and the second fine-grained region, the control module or the processing module is controlled to perform the first operation.

[0315] The first operation includes at least one of the following: reading first data from the first storage area, reading second data from the second storage area, reading third data from the third storage area, and storing the operation result in the fourth storage area.

[0316] Clause A10, the apparatus described in Clause A9,

[0317] The operation judgment submodule is also used to block the first operation when there is an overlap between the first fine-grained region and the second fine-grained region.

[0318] Clause A11, the apparatus according to Clause A9, wherein at least one of the first operation and the second operation is a write operation.

[0319] Clause A12, the apparatus according to Clause A9, wherein the size and / or number of the fine-grained regions are determined based on at least one of a region containing data of a set length and a region containing data of a set dimension.

[0320] Clause A13, the size and / or number of the fine-grained regions in the apparatus described in Clause A9 are determined based on at least one of hardware computing power and hardware bandwidth.

[0321] Clause A14. The apparatus according to Clause A1, further comprising:

[0322] A storage module is used to store the first data, the second data, and the third data.

[0323] Clause A15. The control module of the apparatus according to Clause A1 includes:

[0324] The instruction storage submodule is used to store the multiply-accumulate instructions;

[0325] The instruction processing submodule is used to parse the multiply-accumulate instruction to obtain the opcode and operation field of the multiply-accumulate instruction;

[0326] The queue storage submodule is used to store an instruction queue, which includes multiple instructions to be executed arranged in execution order, including the multiply-accumulate instruction.

[0327] The control module further includes:

[0328] The first dependency processing submodule is used to cache the first instruction to be executed in the instruction storage submodule when it is determined that there is an association between the first instruction to be executed among the plurality of instructions to be executed and the zeroth instruction to be executed preceding the first instruction to be executed. After the zeroth instruction to be executed is completed, the first instruction to be executed is retrieved from the instruction storage submodule and sent to the processing module.

[0329] The relationship between the first instruction to be executed and the zeroth instruction to be executed preceding the first instruction to be executed includes:

[0330] There is an overlapping area between the storage area storing the data required for the first instruction to be executed and the storage area storing the data required for the zeroth instruction to be executed.

[0331] Clause A16, a machine learning computing apparatus, the apparatus comprising:

[0332] One or more multiply-accumulate instruction processing means as described in any one of Clauses A1-A15, for obtaining tensors to be processed and control information from other processing means, performing specified machine learning operations, and passing the execution results to other processing means through an I / O interface;

[0333] When the machine learning computing device includes multiple multiply-accumulate instruction processing devices, the multiple multiply-accumulate instruction processing devices can be connected and transmit data through a specific structure;

[0334] The multiple multiply-accumulate instruction processing devices are interconnected and transmit data through a PCIe bus to support larger-scale machine learning operations; the multiple multiply-accumulate instruction processing devices share the same control system or have their own control systems; the multiple multiply-accumulate instruction processing devices share memory or have their own memory; the interconnection method of the multiple multiply-accumulate instruction processing devices is any interconnection topology.

[0335] Clause A17. A combined processing apparatus, the combined processing apparatus comprising:

[0336] Machine learning computing devices, general interconnect interfaces and other processing devices as described in Clause A16;

[0337] The machine learning computing device interacts with the other processing devices to jointly complete the computational operations specified by the user.

[0338] The combined processing device further includes a storage device, which is connected to the machine learning computing device and the other processing devices respectively, and is used to store the data of the machine learning computing device and the other processing devices.

[0339] Clause A18. A machine learning chip, said machine learning chip comprising:

[0340] Machine learning computing apparatus as described in Clause A16 or combined processing apparatus as described in Clause A13.

[0341] Clause A19. An electronic device, said electronic device comprising:

[0342] Machine learning chips as described in Clause A18.

[0343] Clause A20, a board comprising: storage devices, interface devices, and control devices, as well as a machine learning chip as described in Clause A18;

[0344] The machine learning chip is connected to the storage device, the controller, and the interface device, respectively.

[0345] The storage device is used to store data;

[0346] The interface device is used to realize data transmission between the machine learning chip and external devices;

[0347] The controller is used to monitor the state of the machine learning chip.

[0348] Clause A21, a method for processing multiply-accumulate instructions, the method comprising:

[0349] The received multiply-accumulate instruction is parsed to obtain the opcode and operation field of the multiply-accumulate instruction. The multiply-accumulate operation processing corresponding to the multiply-accumulate instruction is determined according to the opcode. The first data, second data, third data and fourth storage area required to execute the multiply-accumulate instruction are obtained according to the operation field. The multiply-accumulate operation strategy is also determined.

[0350] According to the multiplication-addition operation strategy, the first data, the second data, and the third data are multiplied and added to obtain the operation result, and the operation result is stored in the fourth storage area.

[0351] The opcode indicates that the multiply-accumulate instruction performs a multiply-accumulate operation on the data. The operation field includes a first storage area for storing the first data, a second storage area for storing the second data, a third storage area for storing the third data, and a fourth storage area.

[0352] Clause A22. According to the method described in Clause A21, multiplying and adding the first data, the second data, and the third data are performed according to the multiply-add operation strategy to obtain the operation result, including:

[0353] According to the multiplication-addition operation strategy, the order of operation, the corresponding operation relationship, and the order of operation are determined from the first data, the second data, and the third data.

[0354] Based on the operational correspondence and operational processing order, the previously processed data is subjected to a first operational processing to obtain an intermediate result;

[0355] Based on the aforementioned operational correspondence and processing order, a second operational process is performed on the intermediate results and the subsequent operational data to obtain the operational result.

[0356] Wherein, the first operation processing is multiplication operation processing or addition operation processing, the second operation processing is the same as the multiplication operation processing or addition operation processing, and the first operation processing and the second operation processing are different.

[0357] Clause A23, the method described in Clause A21, wherein the operation domain includes the multiply-add strategy.

[0358] Clause A24, according to the method described in Clause A21, the opcode is also used to indicate the multiplication-addition operation strategy.

[0359] Clause A25. The method described in Clause A21, performing multiplication and addition operations on the first data, the second data, and the third data according to the multiplication and addition strategy, includes:

[0360] The multiplication operation in the multiply-add operation is performed using at least one multiplier.

[0361] The addition operation in the multiply-add operation is performed using at least one adder.

[0362] Clause A26. The method according to Clause A21, wherein the opcode includes a preprocessing identifier, or the operation field includes the preprocessing identifier, further comprises:

[0363] Determine the processing operation corresponding to the preprocessing identifier and the corresponding data to be processed, wherein the data to be processed includes at least one of the first data, the second data, and the third data;

[0364] Before performing multiplication and addition operations on the first data, the second data, and the third data, the corresponding data to be processed is preprocessed according to the processing operation corresponding to the preprocessing identifier.

[0365] Clause A27. The method according to Clause A21, wherein the opcode includes a post-processing identifier, or the operation field includes the post-processing identifier, the method further includes:

[0366] Determine the processing operation corresponding to the post-processing identifier;

[0367] The calculation result is post-processed according to the processing operation corresponding to the post-processing identifier, and the post-processed calculation result is stored in the fourth storage area.

[0368] Clause A28, the method described pursuant to Clause A26 or Clause A27, includes at least one of the following: data format conversion processing and data computation processing.

[0369] The data format conversion process includes at least one of the following: floating-point number conversion, fixed-point number conversion, and floating-to-fixed-point number conversion.

[0370] The data processing includes at least one of the following: trigonometric function processing, inverse trigonometric function processing, logarithmic processing, exponential processing, maximum value processing, minimum value processing, convolution processing, pooling processing, fully connected processing, and activation processing.

[0371] Clause A29. The method described in Clause A21 further includes:

[0372] Before the first operation, determine whether there is a second operation targeting the target storage area corresponding to the first operation;

[0373] When the second operation exists, it is determined whether there is an overlap between the first fine-grained region in the target storage area currently targeted by the first operation and the second fine-grained region in the target storage area targeted by the second operation;

[0374] When there is no overlap between the first fine-grained region and the second fine-grained region, the first operation is executed.

[0375] The first operation includes at least one of the following: reading first data from the first storage area, reading second data from the second storage area, reading third data from the third storage area, and storing the operation result in the fourth storage area.

[0376] Clause A30, the method described pursuant to Clause A29, further includes:

[0377] When there is overlap between the first fine-grained region and the second fine-grained region, the first operation is blocked.

[0378] Clause A 31. In the method described in Clause A29, at least one of the first operation and the second operation is a write operation.

[0379] Clause A32, the method described in Clause A29, wherein the size and / or number of the fine-grained regions are determined based on at least one of the regions containing data of a set length and the regions containing data of a set dimension.

[0380] Clause A 33. The size and / or number of the fine-grained regions described in Clause A29 are determined based on at least one of hardware computing power and hardware bandwidth.

[0381] Clause A 34. The method described in Clause A21 further includes:

[0382] Store the first data, the second data, and the third data.

[0383] Clause A 35. According to the method described in Clause A21, parsing a received multiply-accumulate instruction to obtain the opcode and operation field of the multiply-accumulate instruction includes:

[0384] Store the multiply-accumulate instructions;

[0385] The multiply-accumulate instruction is parsed to obtain its opcode and operation field.

[0386] A storage instruction queue, the instruction queue including a plurality of instructions to be executed arranged sequentially according to execution order, the plurality of instructions to be executed including the multiply-accumulate instruction.

[0387] The method further includes:

[0388] When it is determined that the first instruction to be executed among the plurality of instructions to be executed has a dependency relationship with the zeroth instruction to be executed preceding the first instruction to be executed, the first instruction to be executed is cached, and after it is determined that the zeroth instruction to be executed has been executed, the execution of the first instruction to be executed is controlled.

[0389] The dependencies between the first instruction to be executed and the zeroth instruction to be executed preceding the first instruction to be executed include:

[0390] There is an overlapping area between the storage area storing the data required for the first instruction to be executed and the storage area storing the data required for the zeroth instruction to be executed.

[0391] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A multiply-accumulate instruction processing device, characterized in that, The device includes: The control module is used to parse the received multiply-accumulate instruction, obtain the opcode and operation field of the multiply-accumulate instruction, determine the multiply-accumulate operation processing corresponding to the multiply-accumulate instruction based on the opcode, obtain the first data, second data, third data and fourth storage area required to execute the multiply-accumulate instruction based on the operation field, and determine the multiply-accumulate operation strategy. The processing module is configured to perform multiplication and addition operations on the first data, the second data, and the third data according to the multiplication and addition operation strategy, obtain the operation result, and store the operation result in the fourth storage area. The opcode is used to indicate that the processing of the data by the multiply-accumulate instruction is a multiply-accumulate operation. The operation field includes a first storage area for storing the first data, a second storage area for storing the second data, a third storage area for storing the third data, and a fourth storage area. The multiplication-addition strategy is used to indicate the order of addition and multiplication operations in the multiplication-addition process, as well as the data corresponding to the addition and multiplication operations. Wherein, the first data, the second data, and the third data each include at least one data; when at least one of the first data, the second data, and the third data includes multiple data, the multiply-add operation strategy also indicates the operation correspondence between the data to describe the order of the data obtained when the first data, the second data, and the third data are operated on.

2. The apparatus according to claim 1, characterized in that, According to the multiplication-addition operation strategy, the first data, the second data, and the third data are multiplied and added to obtain the operation result, including: According to the multiplication-addition operation strategy, the order of operation, the corresponding operation relationship, and the order of operation are determined from the first data, the second data, and the third data. Based on the operational correspondence and operational processing order, the previously processed data is subjected to a first operational processing to obtain an intermediate result; Based on the aforementioned operational correspondence and processing order, a second operational process is performed on the intermediate results and the subsequent operational data to obtain the operational result. Wherein, the first operation processing is multiplication operation processing or addition operation processing, the second operation processing is the same as the multiplication operation processing or addition operation processing, and the first operation processing and the second operation processing are different.

3. The apparatus according to claim 1, characterized in that, The operation domain includes the multiply-accumulate operation strategy.

4. The apparatus according to claim 1, characterized in that, The opcode is also used to indicate the multiply-add operation strategy.

5. The apparatus according to claim 1, characterized in that, The processing module includes at least one adder and at least one multiplier. Each multiplier is used to perform the multiplication operation in the multiply-add operation process; Each adder is used to perform the addition operation in the multiply-add operation.

6. The apparatus according to claim 1, characterized in that, The opcode contains a preprocessor identifier, or the operation field contains the preprocessor identifier. The control module is further configured to determine the processing operation corresponding to the pre-processing identifier and the corresponding data to be processed, wherein the data to be processed includes at least one of the first data, the second data and the third data; The processing module is further configured to preprocess the corresponding data to be processed according to the processing operation corresponding to the preprocessing identifier before performing multiplication and addition operations on the first data, the second data and the third data.

7. The apparatus according to claim 1, characterized in that, The opcode contains a post-processing identifier, or the operation field contains the post-processing identifier. The control module is further configured to determine the processing operation corresponding to the post-processing identifier; The processing module is further configured to perform post-processing on the calculation result according to the processing operation corresponding to the post-processing identifier, and store the post-processed calculation result in the fourth storage area.

8. The apparatus according to claim 6 or 7, characterized in that, The processing operations include at least one of the following: data format conversion processing and data computation processing. The data format conversion process includes at least one of the following: floating-point number conversion, fixed-point number conversion, and floating-to-fixed-point number conversion. The data processing includes at least one of the following: trigonometric function processing, inverse trigonometric function processing, logarithmic processing, exponential processing, maximum value processing, minimum value processing, convolution processing, pooling processing, fully connected processing, and activation processing.

9. The apparatus according to claim 1, characterized in that, The control module includes: An operation judgment submodule is used to determine whether there is a second operation targeting the target storage area corresponding to the first operation before the control module or the processing module executes the first operation. When the second operation exists, it is determined whether there is an overlap between the first fine-grained region in the target storage area currently targeted by the first operation and the second fine-grained region in the target storage area targeted by the second operation; When there is no overlap between the first fine-grained region and the second fine-grained region, the control module or the processing module is controlled to perform the first operation. The first operation includes at least one of the following: reading first data from the first storage area, reading second data from the second storage area, reading third data from the third storage area, and storing the operation result in the fourth storage area.

10. The apparatus according to claim 9, characterized in that, The operation judgment submodule is also used to block the first operation when there is an overlap between the first fine-grained region and the second fine-grained region.

11. The apparatus according to claim 9, characterized in that, At least one of the first operation and the second operation is a write operation.

12. The apparatus according to claim 9, characterized in that, The size and / or number of the fine-grained regions are determined based on at least one of the regions containing data of a set length and the regions containing data of a set dimension.

13. The apparatus according to claim 9, characterized in that, The size and / or number of the fine-grained regions are determined based on at least one of the hardware computing power and hardware bandwidth.

14. The apparatus according to claim 1, characterized in that, The device further includes: A storage module is used to store the first data, the second data, and the third data.

15. The apparatus according to claim 1, characterized in that, The control module includes: The instruction storage submodule is used to store the multiply-accumulate instructions; The instruction processing submodule is used to parse the multiply-accumulate instruction to obtain the opcode and operation field of the multiply-accumulate instruction; The queue storage submodule is used to store an instruction queue, which includes multiple instructions to be executed arranged in execution order, including the multiply-accumulate instruction. The control module further includes: The first dependency processing submodule is used to cache the first instruction to be executed in the instruction storage submodule when it is determined that there is an association between the first instruction to be executed among the plurality of instructions to be executed and the zeroth instruction to be executed preceding the first instruction to be executed. After the zeroth instruction to be executed is completed, the first instruction to be executed is retrieved from the instruction storage submodule and sent to the processing module. The relationship between the first instruction to be executed and the zeroth instruction to be executed preceding the first instruction to be executed includes: There is an overlapping area between the storage area storing the data required for the first instruction to be executed and the storage area storing the data required for the zeroth instruction to be executed.

16. A machine learning computing device, characterized in that, The device includes: One or more multiply-accumulate instruction processing devices as described in any one of claims 1-15 are configured to obtain tensors to be processed and control information from other processing devices, perform specified machine learning operations, and transmit the execution results to other processing devices through an I / O interface; When the machine learning computing device includes multiple multiply-accumulate instruction processing devices, the multiple multiply-accumulate instruction processing devices can be connected and transmit data through a specific structure; The multiple multiply-accumulate instruction processing devices are interconnected and transmit data through a PCIe bus to support larger-scale machine learning operations; the multiple multiply-accumulate instruction processing devices share the same control system or have their own control systems; the multiple multiply-accumulate instruction processing devices share memory or have their own memory; the interconnection method of the multiple multiply-accumulate instruction processing devices is any interconnection topology.

17. A combined processing apparatus, characterized in that, The combined processing device includes: The machine learning computing device, general interconnect interface, and other processing device as described in claim 16; The machine learning computing device interacts with the other processing devices to jointly complete the computational operations specified by the user. The combined processing device further includes a storage device, which is connected to the machine learning computing device and the other processing devices respectively, and is used to store the data of the machine learning computing device and the other processing devices.

18. A machine learning chip, characterized in that, The machine learning chip includes: The machine learning computing apparatus as described in claim 16 or the combined processing apparatus as described in claim 17.

19. An electronic device, characterized in that, The electronic device includes: The machine learning chip as described in claim 18.

20. A circuit board, characterized in that, The board includes: storage devices, interface devices, and control devices, as well as the machine learning chip as described in claim 18; The machine learning chip is connected to the storage device, the controller, and the interface device, respectively. The storage device is used to store data; The interface device is used to realize data transmission between the machine learning chip and external devices; The controller is used to monitor the state of the machine learning chip.

21. A method for processing multiply-accumulate instructions, characterized in that, The method includes: The received multiply-accumulate instruction is parsed to obtain the opcode and operation field of the multiply-accumulate instruction. The multiply-accumulate operation processing corresponding to the multiply-accumulate instruction is determined according to the opcode. The first data, second data, third data and fourth storage area required to execute the multiply-accumulate instruction are obtained according to the operation field. The multiply-accumulate operation strategy is also determined. According to the multiplication-addition operation strategy, the first data, the second data, and the third data are multiplied and added to obtain the operation result, and the operation result is stored in the fourth storage area. The opcode is used to indicate that the processing of the data by the multiply-accumulate instruction is a multiply-accumulate operation. The operation field includes a first storage area for storing the first data, a second storage area for storing the second data, a third storage area for storing the third data, and a fourth storage area. The multiplication-addition strategy is used to indicate the order of addition and multiplication operations in the multiplication-addition process, as well as the data corresponding to the addition and multiplication operations. Wherein, the first data, the second data, and the third data each include at least one data; when at least one of the first data, the second data, and the third data includes multiple data, the multiply-add operation strategy also indicates the operation correspondence between the data to describe the order of the data obtained when the first data, the second data, and the third data are operated on.

22. The method according to claim 21, characterized in that, According to the multiplication-addition operation strategy, the first data, the second data, and the third data are multiplied and added to obtain the operation result, including: According to the multiplication-addition operation strategy, the order of operation, the corresponding operation relationship, and the order of operation are determined from the first data, the second data, and the third data. Based on the operational correspondence and operational processing order, the previously processed data is subjected to a first operational processing to obtain an intermediate result; Based on the aforementioned operational correspondence and processing order, a second operational process is performed on the intermediate results and the subsequent operational data to obtain the operational result. Wherein, the first operation processing is multiplication operation processing or addition operation processing, the second operation processing is the same as the multiplication operation processing or addition operation processing, and the first operation processing and the second operation processing are different.

23. The method according to claim 21, characterized in that, The operation domain includes the multiply-accumulate operation strategy.

24. The method according to claim 21, characterized in that, The opcode is also used to indicate the multiply-add operation strategy.

25. The method according to claim 21, characterized in that, According to the multiplication-addition operation strategy, the first data, the second data, and the third data are subjected to multiplication-addition operations, including: The multiplication operation in the multiply-add operation is performed using at least one multiplier. The addition operation in the multiply-add operation is performed using at least one adder.

26. The method according to claim 21, characterized in that, The method further includes: The opcode contains a preprocessing identifier, or the operation field contains the preprocessing identifier; Determine the processing operation corresponding to the preprocessing identifier and the corresponding data to be processed, wherein the data to be processed includes at least one of the first data, the second data, and the third data; Before performing multiplication and addition operations on the first data, the second data, and the third data, the corresponding data to be processed is preprocessed according to the processing operation corresponding to the preprocessing identifier.

27. The method according to claim 21, characterized in that, The method further includes: The opcode contains a post-processing identifier, or the operation field contains the post-processing identifier; Determine the processing operation corresponding to the post-processing identifier; The calculation result is post-processed according to the processing operation corresponding to the post-processing identifier, and the post-processed calculation result is stored in the fourth storage area.

28. The method according to claim 26 or 27, characterized in that, The processing operations include at least one of the following: data format conversion processing and data computation processing. The data format conversion process includes at least one of the following: floating-point number conversion, fixed-point number conversion, and floating-to-fixed-point number conversion. The data processing includes at least one of the following: trigonometric function processing, inverse trigonometric function processing, logarithmic processing, exponential processing, maximum value processing, minimum value processing, convolution processing, pooling processing, fully connected processing, and activation processing.

29. The method according to claim 21, characterized in that, The method further includes: Before the first operation, determine whether there is a second operation targeting the target storage area corresponding to the first operation; When the second operation exists, it is determined whether there is an overlap between the first fine-grained region in the target storage area currently targeted by the first operation and the second fine-grained region in the target storage area targeted by the second operation; When there is no overlap between the first fine-grained region and the second fine-grained region, the first operation is executed. The first operation includes at least one of the following: reading first data from the first storage area, reading second data from the second storage area, reading third data from the third storage area, and storing the operation result in the fourth storage area.

30. The method according to claim 29, characterized in that, The method further includes: When there is overlap between the first fine-grained region and the second fine-grained region, the first operation is blocked.

31. The method according to claim 29, characterized in that, At least one of the first operation and the second operation is a write operation.

32. The method according to claim 29, characterized in that, The size and / or number of the fine-grained regions are determined based on at least one of the regions containing data of a set length and the regions containing data of a set dimension.

33. The method according to claim 29, characterized in that, The size and / or number of the fine-grained regions are determined based on at least one of the hardware computing power and hardware bandwidth.

34. The method according to claim 21, characterized in that, The method further includes: Store the first data, the second data, and the third data.

35. The method according to claim 21, characterized in that, The received multiply-accumulate instruction is parsed to obtain its opcode and operation field, including: Store the multiply-accumulate instructions; The multiply-accumulate instruction is parsed to obtain its opcode and operation field. A storage instruction queue, the instruction queue including a plurality of instructions to be executed arranged sequentially according to execution order, the plurality of instructions to be executed including the multiply-accumulate instruction. The method further includes: When it is determined that the first instruction to be executed among the plurality of instructions to be executed has a dependency relationship with the zeroth instruction to be executed preceding the first instruction to be executed, the first instruction to be executed is cached, and after it is determined that the zeroth instruction to be executed has been executed, the execution of the first instruction to be executed is controlled. The dependencies between the first instruction to be executed and the zeroth instruction to be executed preceding the first instruction to be executed include: There is an overlapping area between the storage area storing the data required for the first instruction to be executed and the storage area storing the data required for the zeroth instruction to be executed.

Images