Electronic device and processing method

Abstract

The application discloses an electronic device and a processing method. The application is provided with a first memory component for being accessed by a first processor and a second memory component for being accessed by a second processor. The first processor occupies at least part of the second memory component when a first condition is met, and / or the second processor occupies at least part of the first memory component when a second condition is met. That is, the first processor and the second processor can not only use the memory component set for itself, but also use the memory component of the other processor based on the condition. Therefore, the data processing performance of the processor is improved without additional physical memory components, and the purpose of ensuring / improving the performance of the device as much as possible under the premise of low space occupation is achieved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer, and particularly relates to an electronic device and a processing method. BACKGROUND

[0002] At present, slim performance electronic devices such as ultra-thin notebooks are very popular with users. Since they belong to the light and thin type, the design of device components will be limited to the system size, and it is required to ensure or improve the device performance as much as possible under the condition of low space occupation. The applicant finds that the component design of the current electronic device, especially the light and thin type device, is not optimized. Therefore, it is very necessary to provide a device design scheme with low space occupation and capable of ensuring / improving performance in the field. SUMMARY

[0003] To this end, the present application discloses the following technical solutions:

[0004] An electronic device comprises:

[0005] a first processor and a second processor;

[0006] a first memory component corresponding to the first processor and used for data access by the first processor;

[0007] a second memory component corresponding to the second processor and used for data access by the second processor;

[0008] wherein the first processor occupies at least part of the space of the second memory component in the case of meeting a first condition; and / or the second processor occupies at least part of the space of the first memory component in the case of meeting a second condition.

[0009] Optionally, the first processor is a central processor, the second processor is a graphics processor, the first memory component is a main memory of the electronic device, and the second memory component is a display memory.

[0010] Optionally, the graphics processor and the central processor are integrated; the main memory comprises a first main memory and a second main memory; and the electronic device further comprises a memory controller and a display memory controller.

[0011] The second condition is a load condition, and the graphics processor occupies the second main memory when the load condition is met; and the graphics processor, when occupying the second main memory, is specifically used for:

[0012] performing data access on the second main memory through the memory controller;

[0013] The first processor is specifically configured to:

[0014] The first processor is specifically configured to:

[0015] The first processor is specifically configured to:

[0016] The first processor is specifically configured to:

[0017] The first processor is specifically configured to:

[0018] The first processor is specifically configured to:

[0019] The load of the graphics processor in the first load state, the second load state and the third load state is sequentially increased; and the load condition comprises that the graphics processor is in the first load state or the third load state.

[0020] Optionally, the graphics processor and the central processor are integrated; the main memory components comprise third main memory and fourth main memory; the electronic device further comprises a memory controller and a graphics memory controller, and the memory controller comprises a first memory controller and a second memory controller.

[0021] The second condition is a load condition, and the graphics processor occupies the fourth main memory when the load condition is met; and the graphics processor is specifically configured to:

[0022] The second condition is a load condition, and the graphics processor occupies the fourth main memory when the load condition is met; and the graphics processor is specifically configured to:

[0023] The central processor is specifically configured to:

[0024] The central processor is specifically configured to:

[0025] The central processor is specifically configured to:

[0026] if the central processor is in a fourth load state, the central processor accesses the third main memory through the first memory controller;

[0027] if the central processor is in a fifth load state, the central processor accesses the third main memory through the first memory controller and accesses the fourth main memory through the second memory controller;

[0028] a load amount of the central processor in the fourth load state is lower than a load amount of the central processor in the fifth load state.

[0029] Optionally, the graphic processor, when accessing the graphic memory and / or accessing the fourth main memory, is specifically configured to:

[0030] if the graphic processor is in a sixth load state, the graphic processor accesses the graphic memory through the graphic memory controller;

[0031] if the graphic processor is in a seventh load state, the graphic processor accesses the graphic memory through the graphic memory controller and accesses the fourth main memory through the second memory controller;

[0032] a load amount of the graphic processor in the sixth load state is lower than a load amount of the graphic processor in the seventh load state; the load condition comprises that the graphic processor is in the seventh load state.

[0033] Optionally, the graphic processor and the central processor are not integrated; the electronic device further comprises a memory controller, a graphic memory controller, an embedded controller and a path switcher; the first condition comprises that the electronic device is in a second mode;

[0034] wherein the embedded controller is connected with the central processor and the path switcher and is connected to the graphic memory controller through the path switcher; the path switcher is connected with the central processor, the graphic processor and the graphic card controller and is configured to switch a path between a first communication path between the central processor and the graphic processor and a second communication path between the central processor and the graphic card controller;

[0035] in the first mode, the embedded controller controls the first communication path to be connected and the second communication path to be disconnected through the path switcher; in the second mode, the embedded controller controls the second communication path to be connected and the first communication path to be disconnected through the path switcher;

[0036] The memory capacity requirement of the central processor in the first mode is lower than that in the second mode.

[0037] Optionally, the central processor, when performing data access on the main memory and / or performing data access on the graphic memory, is specifically used for:

[0038] In the first mode, the central processor performs data access on the main memory through the memory controller;

[0039] In the second mode, the central processor performs data access on the main memory through the memory controller and can perform data access on the graphic memory through the graphic memory controller;

[0040] The graphic processor, when performing data access on the graphic memory component, is specifically used for:

[0041] In the first mode, the graphic processor performs data access on the graphic memory through the graphic memory controller;

[0042] In the second mode, the graphic processor is in a non-working state.

[0043] A processing method applied to an electronic device, the electronic device comprising a first processor and a second processor, and a first memory component corresponding to the first processor and used for data access by the first processor, and a second memory component corresponding to the second processor and used for data access by the second processor;

[0044] The method comprises:

[0045] In response to the first processor satisfying a first condition, the first processor occupies at least part of the space of the second memory component;

[0046] And / or, in response to the second processor satisfying a second condition, the second processor occupies at least part of the space of the first memory component.

[0047] From the above scheme, the electronic device and the processing method provided in the present application correspondingly set a first memory component for being accessed by a first processor for the first processor, correspondingly set a second memory component for being accessed by a second processor for the second processor, and the first processor occupies at least part of the space of the second memory component in the case of satisfying a first condition, and / or the second processor occupies at least part of the space of the first memory component in the case of satisfying a second condition. That is, the first processor and the second processor can not only use the memory component set for itself, but also use the memory component of the other processor based on the condition, so as to improve the data processing performance of the processor without additional increase of the physical memory component, and achieve the purpose of guaranteeing / improving the device performance as much as possible under the premise of low space occupation. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0049] Figure 1 is a component structure diagram of an electronic device provided by the present application;

[0050] Figure 2 is a component structure diagram of an electronic device based on a first graphics card architecture provided by the present application;

[0051] Figure 3 is an example of a component structure of an electronic device under the first graphics card architecture provided by the present application;

[0052] Figure 4 is an example of a use mode of a memory component by a graphics processor under the first graphics card architecture provided by the present application;

[0053] Figure 5 is a schematic diagram of monitoring a GPU load state and accessing a corresponding memory component based on the GPU load state under the first graphics card architecture provided by the present application;

[0054] Figure 6 is a component structure diagram of an electronic device based on a second graphics card architecture provided by the present application;

[0055] Figure 7 is an example of a component structure of an electronic device under the second graphics card architecture provided by the present application;

[0056] Figure 8is an example of a use mode of a memory component by a graphics processor / central processor under a second graphics card architecture provided in the present application;

[0057] Figure 9 is a schematic diagram of monitoring a GPU / CPU load state and accessing a corresponding memory component in a corresponding mode based on the GPU / CPU load state under a second graphics card architecture provided in the present application;

[0058] Figure 10 is a structural diagram of an electronic device based on a discrete graphics card architecture provided in the present application;

[0059] Figure 11 is an example of a structural diagram of an electronic device under a discrete graphics card architecture provided in the present application

[0060] Figure 12 is a flowchart of a processing method provided in the present application. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0062] To ensure / improve the performance of the electronic device as much as possible under the condition of low space occupation, the embodiments of the present application provide an electronic device and a processing method, which mainly optimize the memory component design and access function of different processors (such as central processors and graphics processors) of the electronic device, so as to ensure / improve the performance of the electronic device as much as possible under the condition of low space occupation.

[0063] The electronic device disclosed in the embodiments of the present application can be a device in a plurality of general-purpose or special-purpose computing device environments or configurations, such as a personal computer, a server computer, a handheld device or a portable device, a tablet device, a multi-processor device, and the like. In particular, when the electronic device is a thin and light product (such as a notebook computer), the scheme of the present application can better highlight its advantages.

[0064] The structural diagram of the electronic device disclosed in the embodiments of the present application is shown in Figure 1 , and specifically includes:

[0065] a first processor 10 and a second processor 20;

[0066] a first memory component 30 corresponding to the first processor 10 and used for data access by the first processor 10;

[0067] a second memory component 40 corresponding to the second processor 20 and configured to be accessed by the second processor 20;

[0068] The first processor 10 occupies at least part of the second memory component 40 when a first condition is met, and / or the second processor 20 occupies at least part of the first memory component 30 when a second condition is met.

[0069] The first processor 10 can be a central processing unit (CPU), and the second processor 20 can be a graphics processing unit (GPU). However, the first processor 10 and the second processor 20 can also be different CPUs in an electronic device, for example. The type of the first processor 10 and the second processor 20 can be flexibly set according to actual needs in implementation.

[0070] When the first processor 10 and the second processor 20 are central processing units and graphics processing units, respectively, the first memory component 30 can be the main memory of the electronic device, and the second memory component 40 can be the video memory of the electronic device. The main memory is a dedicated memory component of the central processing unit, which can be read and written by the central processing unit. The video memory is a dedicated memory component of the graphics processing unit (graphics card core), which can be read and written by the graphics processing unit.

[0071] In addition, in the embodiments of the present application, the first processor 10 occupies at least part of the second memory component 40 when a first condition is met, and / or the second processor 20 occupies at least part of the first memory component 30 when a second condition is met. In this way, the data processing performance of the first processor 10 and / or the second processor 20 can be improved without adding additional physical memory components.

[0072] The first condition can be a load condition representing the corresponding load / usage state of the first processor 10 / first memory component. For example, the first condition can be that the resource occupancy rate of the first processor reaches a certain threshold, which represents that the first processor 10 is in a heavy load state. Similarly, the second condition can be a load condition representing the corresponding load / usage state of the second processor 20 / second memory component. For example, the second condition can be that the resource occupancy rate of the second processor reaches a certain threshold, which represents that the second processor 20 is in a heavy load state.

[0073] The first processor 10 occupies at least part of the space of the second memory component 40, which can mean that the first processor 10 occupies all or part of the space of the second memory component 40, and is not limited.

[0074] In addition, the first processor 10 occupies at least part of the space of the second memory component 40 when the first condition is met, which can mean that the first processor 10 occupies both the memory space of the first memory component 30 and at least part of the space of the second memory component 40 when the first condition is met, or that the first processor 10 only occupies at least part of the space of the second memory component 40 when the first condition is met. Similarly, the second processor 20 occupies at least part of the space of the first memory component 30 when the second condition is met, which can mean that the second processor 20 occupies both the memory space of the second memory component 40 and at least part of the space of the first memory component 30 when the second condition is met, or that the second processor 20 only occupies at least part of the space of the first memory component 30 when the second condition is met, and the same is not limited.

[0075] From the above scheme, it can be seen that the electronic device disclosed in the present application is provided with a first memory component for being accessed by a first processor corresponding to the first processor, and a second memory component for being accessed by a second processor corresponding to the second processor, and the first processor occupies at least part of the space of the second memory component when a first condition is met, and / or the second processor occupies at least part of the space of the first memory component when a second condition is met. That is, the first processor and the second processor can not only use the memory component provided for itself, but also use the memory component of the other processor based on the condition, so as to improve the data processing performance of the processor without additional physical memory components, thereby achieving the purpose of guaranteeing / improving the performance of the device as much as possible under the premise of low space occupation.

[0076] In an embodiment, referring to Figure 2 The electronic device provided in the embodiment has a structure that the first processor and the second processor of the electronic device are a central processor 11 and a graphics processor 21 respectively, and the first memory component and the second memory component are a main memory 31 and a display memory 41 respectively, and the central processor and the graphics processor are integrated, that is, the embodiment adopts a graphics card design in the form of integrated graphics (integrated graphics card), and proposes a new integrated graphics architecture.

[0077] The graphics processor in the embodiment is an iGPU (integrated Graphics Processing Unit, integrated display core).

[0078] The embodiment mainly designs the main memory of the electronic device, so that the graphics processor can occupy part of the space of the main memory of the electronic device under the condition of meeting the second condition, and at the same time, sets the external display memory for the graphics processor iGPU under the integrated graphics mode, to improve the data processing performance of the graphics processor iGPU under the integrated graphics mode.

[0079] As Figure 3 The provided integrated graphics architecture example, in the integrated graphics architecture of the embodiment, the central processor CPU and the graphics processor iGPU are specifically set on the same SOC (System on Chip, system-level chip), and at the same time, the external display memory is specifically set for the graphics processor iGPU, that is, the integrated graphics architecture of the embodiment has independent external display memory (different from the existing technology, the integrated graphics shares the memory of the CPU, and does not have independent external display memory design), specifically as Figure 3 The L2 GPU VRAM (Video RAM, video random access memory) shown in

[0080] Combined with Figure 2 , the main memory 31 of the electronic device is further divided into a first main memory 311 for data access by the central processor and a second main memory 312 for data access by the graphics processor iGPU, so that the graphics processor can occupy the second main memory under the condition of meeting the second condition.

[0081] The electronic device further includes a memory controller 51 arranged in the central processor (as a whole CPU, different from the CPU core) and a display memory controller 61 arranged in the graphics processor (as a whole GPU, that is, integrated graphics, different from the integrated graphics core),

[0082] Among them, the first main memory 311 is specifically as the CPU RAM (Random Access Memory, Random Access Memory) shown in Figure 3 , the second main memory 312 is specifically as the L2 GPU VRAM shown in Figure 3 , the memory controller 51 and the display memory controller 61 are respectively as the CPU MEMORY MC (Memory Controller, Memory Controller) and VRAM MC shown in Figure 3 . Among them, when the graphics processor occupies the second main memory, the memory controller is specifically used for data access to the second main memory, and when the first processor accesses the main memory of the electronic device, the memory controller is specifically used for data access to the first main memory in the main memory. That is, the embodiment divides part of the space (second main memory) of the main memory of the electronic device for the graphics processor, and the remaining part (first main memory) is still used by the central processor.

[0083] The memory space size of the second main memory can be greater than, less than, or equal to the memory space size of the display memory, and the size relationship between the memory space sizes is not limited; and the types of the second main memory and the display memory can be the same or different. When the types are the same, the memory controller and the display memory controller respectively use the same access frequency to access the memory and the display memory. When the types are different, the memory controller and the display memory controller respectively use different access frequencies to access the second main memory and the display memory.

[0084] Preferably, the space size of the second main memory is less than the space size of the display memory, and the access frequency of the second main memory is lower than the access frequency of the display memory, so that the use of the display memory is given priority and the use of the second main memory is given priority. Based on the embodiment, the use mode of the graphics processor is controlled according to a predetermined strategy, so that the graphics processor respectively accesses the corresponding memory components in the display memory and the second main memory in different modes, as follows:

[0085] 11) If the graphics processor is in the first load state, the graphics processor accesses the second main memory through the memory controller.

[0086] 12) If the graphics processor is in the second load state, the graphics processor accesses the display memory through the display memory controller.

[0087] 13) If the graphics processor is in the third load state, the graphics processor accesses the display memory through the display memory controller and accesses the second main memory through the memory controller.

[0088] The load of the graphics processor in the first load state, the second load state, and the third load state is sequentially increased. For example, the first load state, the second load state, and the third load state can be light load, heavy load, and extremely heavy load of the graphics processor, respectively.

[0089] In the first load state, such as the light load state, the graphics processor does not access the display memory. For this case, the display memory is controlled to be in a non-working state, such as being controlled to enter a self-refresh mode, and the like. Figure 4 In the second load state, such as the heavy load state, the graphics processor does not access the second main memory. Similarly, for this case, the second main memory is controlled to be in a non-working state, such as being controlled to enter a self-refresh mode, and the like, so as to save energy and improve the battery life of the electronic device. In the third load state, such as the extremely heavy load state, the graphics processor occupies the display memory and the second main memory at the same time to ensure the data processing performance of the graphics processor in the extremely heavy load state.

[0090] In an implementation, as an optional implementation, the current load state of the graphics processor can be determined by detecting the resource occupancy of the graphics processor and according to a preset different state (light load, heavy load, super heavy load) and different correspondence relationship of the occupancy interval, and then the graphics processor accesses the corresponding memory component (video memory and / or second main memory) according to the use mode matched with the current load state.

[0091] In another implementation, as shown in Figure 5 the state (start, run, close) of each application installed on the electronic device can be detected in real time, each application in the running state in the electronic device is identified, and according to the pre-determined occupancy of the graphics processor resource when each application installed on the electronic device is running (such as heavy GPU occupancy, light GPU occupancy), it is determined that the resource occupancy of each application in the running state on the graphics processor will cause the graphics processor to be in which load state, and then the graphics processor accesses the corresponding memory component (video memory and / or second main memory) according to the use mode matched with the current load state.

[0092] In this embodiment, as the graphics processor as the second processor, when occupying at least part of the space of the first memory component (i.e., the second main memory), the second condition to be met is the load condition, which includes:

[0093] The graphics processor is in the first load state described above;

[0094] Or the graphics processor is in the third load state described above.

[0095] Among them, when the graphics processor is in the first load state, only the second main memory is used; when the graphics processor is in the third load state, both the video memory and the second main memory are used.

[0096] This embodiment integrates the graphics processor and the central processor into one by the integrated graphics mode, and sets the external video memory for the graphics processor in the integrated graphics mode, fully utilizes the space advantage of the integrated graphics mode and the high processing performance advantage of the discrete graphics mode (in the prior art, only for the discrete graphics, the external video memory is set for it), greatly improves the performance of the integrated graphics card on the premise of saving space occupation; and by the load state of the graphics processor, the graphics processor uses the corresponding memory component in the external video memory and part of the main memory (second main memory) according to different use modes, improves the performance of the integrated graphics card while taking into account the battery life of the electronic device, saves energy consumption, and improves the battery life of the electronic device.

[0097] Next, the present application provides another integrated graphics architecture in another embodiment, that is, in the present embodiment, the first processor and the second processor of the electronic device are also respectively a central processor and a graphics processor, such as the central processor 12 and the graphics processor 22 in Figure 6 , the first memory component and the second memory component are also respectively a main memory and a video memory, such as the main memory 32 and the video memory 42 in Figure 6 , and the graphics processor and the central processor in the electronic device are also integrated.

[0098] The present embodiment mainly designs the main memory and the memory controller of the electronic device, so that the graphics processor can occupy part of the space of the main memory of the electronic device under the condition of meeting the second condition, and at the same time, an external video memory is set for the graphics processor in the integrated graphics mode, so as to improve the data processing performance of the graphics processor in the integrated graphics mode.

[0099] Referring to the integrated graphics architecture example provided in Figure 7 , in the integrated graphics architecture of the present embodiment, the central processor CPU and the integrated graphics card IGPU are also arranged in the same SOC, and at the same time, an external video memory is also arranged for the integrated graphics card iGPU, that is, the iGPU in the integrated graphics architecture of the present embodiment also has an independent external video memory, which is specifically as shown in Figure 7 GPU VRAM.

[0100] In the present embodiment, the main memory of the electronic device is further divided into a third main memory 321 for data access by the central processor and a fourth main memory 322 for data access by the graphics processor iGPU and the central processor. Among them, the third main memory is specifically as shown in Figure 7 CPU RAM, and the fourth main memory is specifically as shown in Figure 7 Dynamic DRAM or VRAM.

[0101] The electronic device also includes a memory controller and a video memory controller, such as the memory controller 52 and the video memory controller 62 in Figure 6 , wherein the video memory controller is arranged inside the graphics processor, which is different from the previous embodiment. In the present embodiment, the dedicated memory controller of the central processor is separated from the central processor inside to the outside of the central processor, that is, in the present embodiment, the memory controller is arranged outside the central processor, and the memory controller arranged outside the central processor is further divided into a first memory controller 521 and a second memory controller 522, and the first memory controller, the second memory controller and the graphics processor are respectively as shown in Figure 7 CPU MC (MC1), Dynamic MC (MC3) and GPU MC (MC2) in

[0102] The first memory component includes a third main memory and a fourth main memory, and the second memory controller is configured to access the fourth main memory.

[0103] The central processor is configured to access the third main memory through the first memory controller and / or access the fourth main memory through the second memory controller when accessing the first memory component.

[0104] In the embodiment, the fourth main memory is dynamic and can be used by the central processor and the graphics processor after the main memory of the electronic device is divided into the third main memory and the fourth main memory, and the second memory controller is also dynamic and can be used by the central processor and the graphics processor. The fourth main memory / second memory controller is used by which processor at a certain time node depends on the actual load state of the central processor and the graphics processor.

[0105] The memory space size of the fourth main memory can be greater than, less than or equal to the memory space size of the display memory, and the size relationship between the memory space sizes is not limited; and the fourth main memory and the display memory can be of the same type or different types. When the types are the same, the second memory controller and the display memory controller access the fourth main memory and the display memory respectively using the same access frequency, and when the types are different, the second memory controller and the display memory controller access the fourth main memory and the display memory respectively using different access frequencies.

[0106] The embodiment controls the use modes of the graphics processor and the central processor according to a predetermined strategy, so that the graphics processor accesses corresponding memory components in the display memory and the fourth main memory in different modes, and the central processor accesses corresponding memory components in the third main memory and the fourth main memory in different modes.

[0107] The use mode of the central processor can be controlled according to the following strategy, so that the central processor accesses corresponding memory components in the third main memory and the fourth main memory in different modes.

[0108] 21) If the central processor is in the fourth load state, the central processor accesses the third main memory through the first memory controller;

[0109] 22) If the central processor is in the fifth load state, the central processor accesses the third main memory through the first memory controller and accesses the fourth main memory through the second memory controller.

[0110] The load amount of the central processor in the fourth load state is lower than the load amount in the fifth load state. Exemplarily, the fourth load state and the fifth load state can be respectively a light load state and a heavy load state of the central processor.

[0111] Meanwhile, the usage mode of the graphics processor can be controlled according to the following strategies, so that the graphics processor respectively accesses the corresponding memory components in the video memory and the fourth main memory in different modes:

[0112] 31) If the graphics processor is in the sixth load state, the graphics processor accesses the video memory through the video memory controller;

[0113] 32) If the graphics processor is in the seventh load state, the graphics processor accesses the video memory through the video memory controller, and accesses the fourth main memory through the second memory controller;

[0114] The load amount of the graphics processor in the sixth load state is lower than the load amount in the seventh load state; exemplarily, the sixth load state and the seventh load state can be respectively a light load state and a heavy load state of the graphics processor.

[0115] Based on the above usage modes of the central processor and the graphics processor, in the integrated graphics architecture of Figure 7 , referring to FIG. 1, the iGPU / CPU specifically corresponds to the following usage modes: Figure 8

[0116] 41) When the CPU is in a heavy load state, the CPU accesses the CPU RAM through MC1, and accesses the Dynamic DRAM or VRAM through MC3, in this case, the Dynamic DRAM or VRAM is occupied by the CPU, and the GPU accesses the GPU VRAM through MC2;

[0117] 42) When the GPU is in a heavy load state, the GPU accesses the GPU VRAM through MC2, and accesses the Dynamic DRAM or VRAM through MC3, in this case, the Dynamic DRAM or VRAM is occupied by the GPU, and the CPU accesses the CPU RAM through MC1;

[0118] 43) When the CPU is in a light load state, the CPU accesses the CPU RAM through MC1;

[0119] 44) When the GPU is in a light load state, the GPU accesses the GPU VRAM through MC2.

[0120] ​It should be noted that if the CPU and GPU are both under heavy load, further strategies can be used to determine which processor to allocate the fourth main memory (e.g., Dynamic DRAM or VRAM) to. For example, when both processors are under heavy load, the fourth main memory can be directly allocated to the CPU, or the fourth main memory can be allocated to the processor with the higher load.

[0121] Similarly, in this embodiment, the current load state of the graphics processor / central processing unit can be determined by detecting the resource utilization rate of the graphics processor / central processing unit and according to the different correspondences between different pre-set states (light load, heavy load) and utilization rate ranges. Then, the graphics processor / central processing unit can access the corresponding memory components (video memory, third main memory, fourth main memory) according to the usage mode that matches the current load state.

[0122] Alternatively, in another implementation, such as Figure 9 As shown, it can instantly detect the status (started, running, closed) of each application installed on an electronic device, identify each application running on the electronic device, and determine the load state of the CPU / GPU due to the resource usage of each application during operation (e.g., heavy GPU usage, light GPU usage) based on a pre-determined usage pattern of the CPU / GPU by each application. Then, the CPU / GPU accesses data to the corresponding memory components (video memory, third main memory, fourth main memory) according to the usage pattern matched to the current load state.

[0123] In this embodiment, when the graphics processor, as the second processor, occupies at least a portion of the space of the first memory component (i.e., the fourth main memory), the second condition that needs to be met is a load condition, which may refer to the graphics processor being in the aforementioned seventh load state.

[0124] Specifically, when the graphics processor is in the seventh load state, it uses video memory and the fourth main memory.

[0125] The embodiment integrates the graphic processor and the central processor in a set display mode, sets an external display memory for the graphic processor in the set display mode, fully utilizes the space advantage of the set display mode and the high processing performance advantage of the discrete display mode (in the prior art, only the discrete display is provided with the external display memory), greatly improves the performance of the integrated display card on the premise of saving space, and uses the corresponding memory components in the external display memory and part of the main memory (the fourth main memory) according to different use modes of the graphic processor based on the load state of the graphic processor, improves the performance of the integrated display card, and saves the energy consumption, prolongs the battery life of the electronic device, and improves the battery life of the electronic device. In addition, the fourth main memory is controlled in a dynamic mode, so that the central processor or the graphic processor can be occupied based on the actual load state of the central processor and the graphic processor at a specific time node, and the use flexibility of the memory components is further improved, and the processing performance of the central processor and the graphic processor is improved on the premise of a fixed number of memory components.

[0126] In an embodiment, the graphic processor and the central processor in the electronic device are not integrated, that is, the embodiment adopts a discrete display (independent display card) mode for display card design, and a new discrete display architecture is proposed. The graphic processor in the embodiment is a dGPU (discrete Graphics Orocessing Unit, independent graphic processor).

[0127] The electronic device is divided into a UMA (Unified Memory Access, unified memory access) mode and a dGPU mode in the embodiment, wherein the UMA mode is a mode in which the system of the electronic device mainly uses CPU performance and has a very high requirement on the use of the main memory, such as a mode in which the APP run by the user needs the extreme CPU performance; and the DGPU mode is a mode in which the system has a certain requirement on the graphic processor dGPU and can normally use the dGPU.

[0128] For the above two modes, the embodiment redefines a CPU / dGPU architecture, and cooperates with the hardware and software design of the system to expand the system memory capacity in the UMA mode, so as to maximize the performance of the CPU.

[0129] The discrete display architecture of the embodiment includes Figure 1 The components shown in the figure are the central processor and the graphic processor dGPU which are respectively the first processor and the second processor, the main memory and the display memory which are respectively the first memory component and the second memory component, and further include a memory controller and a display memory controller, which are respectively shown in Figure 10The central processor 13, the graphics processor 23, the main memory 33 and the video memory 43, the memory controller 53 and the video memory controller 63 shown.

[0130] The central processor can access the main memory through the memory controller, and the graphics processor dGPU can access the video memory through the video memory controller. Referring to Figure 11 An example of the independent graphics architecture provided in the embodiment is provided, in which the main memory and the video memory are CPU RAM and GPU VRAM respectively, and the memory controller and the video memory controller are CPUMC and dGPU MC respectively.

[0131] In addition, in the embodiment, the electronic device further includes an embedded controller (EC) 70 and a path switcher 80, respectively as Figure 11 The EC and PCIE Mux Unit shown in the independent graphics architecture example of

[0132] The embedded controller is connected to the central processor and the path switcher, and is connected to the video memory controller through the path switcher;

[0133] The path switcher is connected to the central processor, the graphics processor and the graphics card controller, and is used to switch the path between the first communication path between the central processor and the graphics processor and the second communication path between the central processor and the graphics card controller.

[0134] And in the first mode, the embedded controller controls the first communication path between the central processor and the graphics processor to be connected through the path switcher, and the second communication path between the central processor and the graphics card controller to be disconnected; in the second mode, the embedded controller controls the second communication path between the central processor and the graphics card controller to be connected through the path switcher, and the first communication path between the central processor and the graphics processor to be disconnected;

[0135] The memory capacity requirement of the central processor in the first mode is lower than that in the second mode. The first mode can be dGPU mode, and the second mode can be UMA mode.

[0136] In dGPU mode, the embedded controller uses a path switcher to connect the first communication path and disconnect the second communication path. The dGPU is in normal working condition, accessing data from the video memory via the video memory controller. The CPU accesses data from the main memory via the memory controller. In UMA mode, the embedded controller uses a path switcher to connect the second communication path and disconnect the first communication path. The dGPU is in a non-working state, and the CPU and video memory controller are connected. The CPU can access both main memory and video memory via the memory controller. In this mode, the system's main memory and video memory are used as the CPU's primary and secondary memory, respectively, effectively expanding the dGPU's video memory into the CPU's memory.

[0137] In addition, the electronic device in this embodiment also includes a bridging component and two power supply units, as shown below. Figure 11 The discrete graphics card architecture example shows a PCIE to MC bridge, and power supply units VR1 and FBVDD VR. The bridge connects the path switch and the memory controller to perform signal conversion between the path switch and the memory controller. One of the power supply units (such as VR1) is connected between the embedded controller and the path switch and the bridge to supply power to the path switch and the bridge when the embedded controller is enabled. The other power supply unit (such as FBVDD VR) is connected between the embedded controller and the memory controller and the memory to supply power to the memory controller and the memory when the embedded controller is enabled.

[0138] Based on the unique display architecture of the embodiment, when the system mainly uses CPU performance and has a high requirement on the use of main memory, such as an APP run by a system user requiring extreme CPU performance, the user can enter BIOS (Basic Input Output System, basic input output system) to set the system to UMA mode through BIOS, or the system enters BIOS and sets the system to UMA mode based on the event that the capacity usage rate of the system main memory monitored by the system reaches the required setting threshold corresponding to the UMA mode, and then in the system boot stage, BIOS notifies EC (the essence is that the CPU chip running the BIOS code notifies EC) that the current mode of the system is UMA mode, and EC enables the power supply unit of the path switcher and the bridge component to supply power to the path switcher and the bridge component in response to the notification information, and controls the path switcher to switch from the first communication path to the second communication path through the signal form of GPIO (General Purpose Input Output, general purpose input / output), so as to realize the switching of the dGPU mode to the UMA mode, and in the UMA mode, the graphics processor dGPU is in the off state (non-working state), the signals between the CPU and the memory controller are connected, and the CPU can access the main memory through the memory controller and access the display memory through the display memory controller, so as to realize the expansion of the display memory as the memory of the CPU.

[0139] Optionally, in the UMA mode, the system main memory and the display memory are set as the main memory and the auxiliary memory of the CPU respectively, and the device system monitors the capacity usage rate of the main memory in real time, and when it is monitored that the capacity usage rate of the main memory exceeds the setting threshold requiring the auxiliary memory to be enabled, the display memory is automatically enabled as the auxiliary memory and the CPU accesses the display memory through the display memory controller, so as to realize the expansion of the memory capacity of the CPU, and when it is monitored that the capacity usage rate of the memory (main memory+display memory) is lower than the setting threshold requiring the auxiliary memory to be closed, the auxiliary memory is automatically closed.

[0140] When it is monitored that the capacity usage rate of the main memory is lower than the setting threshold requiring the UMA mode to be ended, BIOS notifies EC (the essence is that the CPU chip running the BIOS code notifies EC) of the mode information of the dGPU mode, and EC controls the path switcher to switch from the second communication path to the first communication path through the signal form of GPIO, that is, controls the second communication path to be disconnected and the first communication path to be connected, and after the switching is completed, the power supply unit VR1 for supplying power to the path switcher and the bridge component is closed.

[0141] It should be noted that in the implementation, when switching to the UMA mode, it is not limited to the implementation manner of controlling the dGPU to be off as described above, and as another implementation manner, when the path switcher controls the second communication path to be connected, the first communication path can also be maintained in the connected state, and the CPU can be controlled to occupy a part of the space of the display memory through the display memory controller, and the remaining display memory space is still occupied by the graphics processor dGPU. In this implementation, when the display memory needs to be expanded to be used as the memory of the CPU when entering the UMA mode, the OS (Operating System, operating system) or the BIOS can notify the display memory controller of the size or proportion of the expanded display memory and the like, and the display memory controller can expand the display memory space of a certain size or proportion to be used as the memory of the CPU based on the notification information, and the remaining display memory space is still used by the graphics processor dGPU.

[0142] That is, when the display memory is expanded to be used as the memory of the CPU, all or part of the display memory space can be expanded to be used as the memory of the CPU, which is not limited herein.

[0143] In this embodiment, when the CPU as the first processor occupies at least part of the space of the display memory, the first condition to be met can be a load condition or a mode condition. The load condition can specifically include that the resource usage rate of the system main memory reaches a corresponding threshold value of the display memory space to be occupied, and the mode condition can specifically include that the electronic device is in the second mode (such as the UMA mode).

[0144] This embodiment redefines the CPU / DGPU architecture in a discrete graphics mode, and cooperates with the hardware and software design of the system to expand the system memory capacity in the UMA mode, greatly improves the performance of the CPU, and meets the use demand of the system on the extreme CPU performance without adding physical memory components to the device.

[0145] In addition, the embodiment of the present application also discloses a processing method, which is applicable to the electronic device provided by any of the above embodiments, that is, the electronic device to which the method disclosed by the present application is applicable, at least includes a first processor and a second processor, and a first memory component corresponding to the first processor for data access by the first processor, and a second memory component corresponding to the second processor for data access by the second processor.

[0146] Referring to Figure 12 The processing method provided by the flowchart, the processing method disclosed by the embodiment includes any one or more of the following steps:

[0147] Step 1201, in response to the first processor meeting the first condition, the first processor occupies at least part of the space of the second memory component;

[0148] In step 1202, in response to the second processor satisfying a second condition, the second processor occupies at least part of the space of the first memory component.

[0149] For example, the first processor and the second processor are respectively a central processor and a graphics processor of the electronic device, and the first memory component and the second memory component are respectively a main memory and a display memory of the electronic device.

[0150] The method of the embodiment can be applied to the electronic device in any of the two integrated graphics architectures and the one discrete graphics architecture provided in the above embodiments.

[0151] In step 1201, in response to the first processor satisfying a first condition, the first processor occupies at least part of the space of the second memory component, which can include but is not limited to: for the above-mentioned discrete graphics architecture, the central processor occupies all or part of the display memory space when in the UMA mode; in step 1202, in response to the second processor satisfying a second condition, the second processor occupies at least part of the space of the first memory component, which can include but is not limited to: for the above-mentioned two integrated graphics architectures, the graphics processor occupies part of the main memory space when in the first load state, the third load state or the seventh load state described above.

[0152] Under the corresponding architecture, the first processor and the second processor can not only use the memory component set for itself, but also use the memory component of the other processor based on the condition. For details, refer to the description of the above device embodiments, which will not be repeated here.

[0153] It should be noted that each embodiment in the present specification adopts a progressive manner for description, and each embodiment focuses on the difference from other embodiments. The same and similar parts between embodiments can be referred to each other.

[0154] For the convenience of description, the above system or device is described in various modules or units. Of course, in the implementation of the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0155] From the above description of the embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments of the present application.

[0156] Finally, it needs to be pointed out that, in this document, relational terms such as first, second, third, and fourth and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual relationship or order between or among such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0157] The above description is only the preferred embodiment of the present application, and it should be pointed out that, for those skilled in the art, some improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. An electronic device, comprising: First processor and second processor; A first memory component configured for data access by the first processor; The first memory component includes a first main memory and a second main memory; A second memory component provided for data access by the second processor; First memory controller and second memory controller; Wherein, when the first processor accesses data to the first memory component, it accesses data to the first main memory through the first memory controller; and / or, it accesses data to the second main memory through the second memory controller; The first processor occupies at least a portion of the space of the second memory component when a first condition is met; the first condition includes a load condition or a mode condition, wherein the mode condition is the mode in which the electronic device is located; and; When the second processor occupies at least a portion of the space of the first memory component under the condition that the second condition is met, it performs data access to the second main memory through the second memory controller, wherein the second condition includes a load condition.

2. The electronic device according to claim 1, wherein the first processor is a central processing unit, the second processor is a graphics processing unit; the first memory component is the main memory of the electronic device; and the second memory component is video memory.

3. The electronic device according to claim 2, wherein the graphics processor and the central processing unit are integrated into one unit; the electronic device further includes a video memory controller.

4. The electronic device according to claim 3, wherein when the graphics processor accesses the video memory and / or accesses the second main memory, it is specifically configured to: If the graphics processor is in a first load state, the graphics processor accesses the second main memory through the second memory controller; If the graphics processor is in the second load state, the graphics processor accesses the video memory through the video memory controller; If the graphics processor is in the third load state, the graphics processor accesses the video memory through the video memory controller and accesses the second main memory through the second memory controller; in, The load on the graphics processor increases sequentially in the first load state, the second load state, and the third load state; the load conditions include: the graphics processor is in the first load state or the third load state.

5. The electronic device according to claim 3, wherein when the central processing unit accesses data from the first main memory through the first memory controller; and / or accesses data from the second main memory through the second memory controller, it is specifically configured to: If the central processing unit is in the fourth load state, the central processing unit accesses the first main memory through the first memory controller; If the central processing unit is in the fifth load state, the central processing unit accesses the first main memory through the first memory controller and accesses the second main memory through the second memory controller; The load on the central processing unit in the fourth load state is lower than the load in the fifth load state.

6. The electronic device according to claim 3, wherein the graphics processor, when accessing the video memory and / or accessing the second main memory, is specifically configured to: If the graphics processor is in the sixth load state, the graphics processor accesses the video memory through the video memory controller; If the graphics processor is in the seventh load state, the graphics processor accesses the video memory through the video memory controller and accesses the second main memory through the second memory controller; The graphics processor experiences a lower load in the sixth load state than in the seventh load state; the load conditions include: The graphics processor is in the seventh load state.

7. The electronic device according to claim 2, wherein the graphics processor and the central processing unit are not integrated into one unit; the electronic device further includes a memory controller, a video memory controller, an embedded controller, and a path switcher; The first condition includes: The electronic device is in the second mode; The embedded controller is connected to the central processing unit and the path switcher, and is connected to the video memory controller through the path switcher; the path switcher is connected to the central processing unit, the graphics processing unit and the video memory controller, and is used to switch between the first communication path between the central processing unit and the graphics processing unit and the second communication path between the central processing unit and the video memory controller. In the first mode, the embedded controller controls the first communication path to be connected and the second communication path to be disconnected via the path switch; in the second mode, the embedded controller controls the second communication path to be connected and the first communication path to be disconnected via the path switch. The memory capacity requirement of the central processing unit in the first mode is lower than that in the second mode.

8. The electronic device according to claim 7, wherein the central processing unit, when accessing data from the main memory and / or the video memory, is specifically configured to: In the first mode, the central processing unit accesses the main memory through the memory controller; In the second mode, the central processing unit accesses the main memory through the memory controller and can access the video memory through the video memory controller; When the graphics processor accesses the video memory, it is specifically used for: In the first mode, the graphics processor accesses the video memory through the video memory controller; In the second mode, the graphics processor is in a non-working state.

9. A processing method applied to an electronic device, the electronic device including a first processor and a second processor, and a first memory component correspondingly provided for the first processor for data access by the first processor, the first memory component including a first main memory and a second main memory; And a second memory component provided for data access by the second processor; First memory controller and second memory controller; The method includes: When the first processor accesses data to the first memory component, it accesses data to the first main memory through the first memory controller; and / or, it accesses data to the second main memory through the second memory controller; The first processor occupies at least a portion of the space of the second memory component when a first condition is met; the first condition includes a load condition or a mode condition, wherein the mode condition is the mode in which the electronic device is located; and; When the second processor occupies at least a portion of the space of the first memory component under the condition that the second condition is met, it performs data access to the second main memory through the second memory controller, wherein the second condition includes a load condition.

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