Storage device, semiconductor system including the same, and operation method thereof

Abstract

The present application relates to a memory device, a semiconductor system including the same, and an operation method thereof. A semiconductor system includes a memory controller and a memory device. The memory controller provides at least first to third command address signals. The memory device performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory device continuously initializes an internal circuit that is performing a burst read operation in an interval in which the third command address signal is received twice.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 046,095 filed on June 30, 2020 and Korean Patent Application No. 10-2020-0149060 filed on November 10, 2020 in the Korean Intellectual Property Office, which are hereby incorporated by reference in their entireties as if fully set forth. Technical Field

[0003] Various embodiments relate generally to integrated circuit technology, and more particularly, to a memory device, a semiconductor system including the memory device, and an operating method thereof. Background Art

[0004] The electronic device includes a large number of electronic components, and the computer system as an electronic device includes a large number of semiconductor devices, each of which is composed of semiconductors. The semiconductor devices constituting the computer system can communicate with each other by transmitting and receiving clock signals and data. Each semiconductor device can operate synchronously with the clock signal. The computer system can be composed of various semiconductor systems. The storage device to be coupled to the processor or memory controller is a traditional element in the semiconductor system. Before performing normal operation, the memory controller and the storage device can perform training operations to adjust various parameters of data communication. The storage device may be equipped with a mode register set, and the mode register set may be used to perform training operations. During a specific training operation, the storage device can periodically generate an internal command signal even without receiving a command from the memory controller, and can periodically provide data to the memory controller based on the internal command signal. This operation is called a mode register burst read operation. Summary of the invention

[0005] In an embodiment, a semiconductor system may include a memory controller and a memory device. The memory controller may be configured to provide at least a first command address signal, a second command address signal, and a third command address signal. The memory device may be configured to perform a burst read operation based on the first command address signal and the second command address signal, configured to terminate the burst read operation when the third command address signal is received for the first time while the burst read operation is being performed, and configured to continuously initialize an internal circuit that is performing the burst read operation at least in a time period from the first time the third command address signal is received until the third command address signal is received for the second time.

[0006] In an embodiment, a semiconductor system may include a memory device and a memory controller. The memory controller may be configured to sequentially provide a first command address signal and a second command address signal to control the memory device to perform a burst read operation, and to provide a third command address signal at least twice to control the memory device to terminate the burst read operation. The memory device may be configured to enable a reset signal based on the third command address signal received for the first time to initialize an internal circuit that is performing the burst read operation, and to disable the reset signal based on the third command address signal received for the second time.

[0007] In an embodiment, an operating method of a semiconductor system may include performing a burst read operation by a memory device by sequentially receiving a first command address signal and a second command address signal from a memory controller. The operating method may include terminating the burst read operation by the memory device by receiving a third command address signal from the memory controller, and starting to initialize the operation of an internal circuit that is performing the burst read operation by the memory device. The operating method may include terminating the operation of initializing the internal circuit that is performing the burst read operation by the memory device by receiving another third command address signal from the memory controller.

[0008] In an embodiment, a semiconductor memory device may include a command address receiving circuit, a command decoder, a delay circuit, a data input / output circuit, and a mode register group. The command address receiving circuit may be configured to receive a command address signal. The command decoder may be configured to generate an internal read signal and an internal write pulse based on the command address signal, and to generate an internal read signal based on a burst read signal. The delay circuit may be configured to delay the internal read signal and the clock signal to generate a delayed command signal and a delayed clock signal. The data input / output circuit may be configured to output data based on the delayed command signal and the delayed clock signal, and to be initialized based on a reset signal. The mode register group may be configured to generate a burst read enable signal based on the command address signal, to generate a burst read signal based on the burst read enable signal, and to generate a reset signal based on the burst read enable signal and the internal write pulse.

[0009] In an embodiment, a semiconductor system may include a memory controller and a memory device. The memory controller may be configured to provide at least a first command address signal, a second command address signal, and a third command address signal. The memory device may be configured to perform a burst read operation based on the first command address signal and the second command address signal, to terminate the burst read operation when the third command address signal is received twice, and to continuously initialize an internal circuit that is performing the burst read operation in an interval in which the third command address signal is received twice. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a configuration of a semiconductor system according to an embodiment.

[0011] Figure 2 2 is a diagram illustrating an operation of a semiconductor system according to an embodiment.

[0012] Figure 3 2 is a diagram illustrating an operation of a semiconductor system according to an embodiment.

[0013] Figure 4 2 is a diagram illustrating an operation of a semiconductor system according to an embodiment.

[0014] Figure 5 is a diagram showing a configuration of a storage device according to an embodiment.

[0015] Figure 6 is a diagram showing a configuration of a mode register set according to an embodiment.

[0016] Figure 7 It is shown Figure 6 A diagram of the configuration of the reset signal generating circuit shown in .

[0017] Figure 8 It is shown Figure 6 A diagram of the configuration of the burst read generation circuit shown in .

[0018] Fig. 9 is a timing diagram illustrating the operation of a mode register set during a burst read operation according to an embodiment.

[0019] Fig.10 yes Figure 5 A diagram of the configuration of the delay circuit shown in .

[0020] Fig.11 2 is a diagram illustrating an operation of a semiconductor system according to an embodiment.

[0021] Fig.12 2 is a diagram illustrating an operation of a semiconductor system according to an embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0023] In the following description of the embodiments, when a parameter is referred to as being "predetermined", it is intended to mean that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter can be set when the process or algorithm starts, or it can be set during the period of execution of the process or algorithm.

[0024] It will be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the first element in some embodiments can be called the second element in other embodiments without departing from the teachings of the present disclosure.

[0025] In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0026] Figure 1 is a diagram showing a configuration of a semiconductor system 100 according to an embodiment. Figure 1, the semiconductor system 100 may include a memory controller 110 and a memory device 120. The memory controller 110 may be a host device configured to provide various control signals required for the operation of the memory device 120. The memory device 120 may be a slave device configured to perform various operations under the control of the memory controller 110. The memory device 120 may be coupled to the memory controller 110 through a plurality of buses. The plurality of buses may include a signal transmission path, a link, or a channel for signal transmission. The plurality of buses may include a command address bus 101, a clock bus 102, a chip select bus 103, a data bus 104, and a data strobe bus 105, etc. Each of the command address bus 101, the clock bus 102, and the chip select bus 103 may be a unidirectional bus, and each of the data bus 104 and the data strobe bus 105 may be a bidirectional bus. The memory device 120 may receive a command address signal CA through the command address bus 101. The command address signal CA may include a plurality of bits. The memory device 120 may receive a system clock signal CLK through the clock bus 102. The system clock signal CLK may be provided as a single-ended signal and may be provided as a differential signal together with a complementary signal. The command address signal CA may be transmitted from the memory controller 110 to the memory device 120 in synchronization with the system clock signal CLK. The memory device 120 may receive a chip select signal CS from the memory controller 110 via a chip select bus 103. The chip select signal CS may be transmitted in synchronization with the command address signal CA. The chip select signal CS may be used as a signal to confirm the validity of the command address signal CA. For example, when the memory device 120 receives an enabled chip select signal CS together with the command address signal CA, the memory device 120 may determine that the command address signal CA is valid and may perform various operations based on the command address signal CA. Through the data bus 104, the memory device 120 may receive data DQ from the memory controller 110 and may provide data DQ to the memory controller 110. Through the data strobe bus 105, the memory device 120 may receive a data strobe signal DQS from the memory controller 110 and may provide the data strobe signal DQS to the memory controller 110. The data strobe signal DQS may be a clock signal that toggles when data DQ is transmitted. The data DQ and the data strobe signal DQS may be synchronized with each other.

[0027] The memory device 120 may include a memory cell array 121, a data input / output (I / O) circuit 122, and a mode register group 123. The memory cell array 121 may include a plurality of memory cells and may store data transmitted from the memory controller 110. The data I / O circuit 122 may receive and transmit data DQ between the memory controller 110 and the memory device 120. During a read operation, the data I / O circuit 122 may read data stored in the memory cell array 121 and may provide the read data as data DQ to the memory controller 110. During a write operation, the data I / O circuit 122 may receive data DQ provided from the memory controller 110 and may store the received data DQ in the memory cell array 121. The memory cell array 121 and the data I / O circuit 122 may be coupled to each other through a data transmission line 124. Data may be transmitted between the memory cell array 121 and the data I / O circuit 122 through the data transmission line 124. During a read operation, the data I / O circuit 122 may provide data DQ together with a data strobe signal DQS that is a clock signal synchronized with the data DQ to the memory controller 110. During a write operation, the data I / O circuit 122 may receive the data DQ and the data strobe signal DQS provided from the memory controller 110.

[0028] The mode register group 123 may store various information related to the operation of the memory device 120. For example, the mode register group 123 may store information about setting a burst length, a burst chop, an operation mode, and a latency, etc. The information will not be limited thereto. The information about the burst length and the burst chop may be related to the bandwidth of the data DQ to be provided to or provided from the memory device 120. The information about the operation mode may include information related to the training operation and the test operation performed by the memory device 120. The information about the operation mode may also include information about enabling and disabling a delay locked loop circuit included in the memory device 120 and information about setting the on-resistance value of the data I / O circuit 122. The delay may include a column-address-strobe (CAS) delay, a read delay (Read Latency), a write delay (Write Latency), and an additive delay (Additive Latency), etc. These delays may represent the amount of delay time for the storage device 120 to perform an operation corresponding to the command address signal CA after the storage device 120 receives the command address signal CA from the memory controller 110. The mode register group 123 may store various data based on the command address signal CA provided from the memory controller 110. In the present disclosure, the mode register data may be various data that has been stored or is to be stored in the mode register group 123. The mode register group 123 may store the mode register data therein based on the command address signal CA. The mode register group 123 may control the storage device 120 to output the mode register data stored in the mode register group 123 or to output an arbitrary data pattern based on the command address signal CA. The arbitrary data pattern may be training data. Based on the command address signal CA, the mode register group 123 may output the mode register data stored in the mode register group 123 in the position corresponding to the command address signal CA. The mode register group 123 may be coupled to the data transmission line 124. The mode register group 123 may output the mode register data and / or the arbitrary data pattern to the data transmission line 124.

[0029] The memory device 120 may perform a training operation together with the memory controller 110 through the mode register group 123. The training operation may be an operation for setting various parameters for the memory controller 110 and the memory device 120 to perform smooth data communication before the semiconductor system 100 performs normal operation. During the training operation, the memory controller 110 may control the memory device 120 to store specific data therein, or may set a pattern of training data generated inside the memory device 120. The memory device 120 may output specific data or training data to the memory controller 110. For the training operation, the memory controller 110 may provide the memory device 120 with a first command address signal MRW1, a second command address signal MRR, and a third command address signal MRW2. The first to third command address signals MRW1, MRR, and MRW2 may be command address signals having different combinations from each other. The first command address signal MRW1 may be a command address signal CA in which the logic values ​​of a plurality of bits have a first combination. The second command address signal MRR may be a command address signal CA in which the logic values ​​of a plurality of bits have a second combination different from the first combination. The third command address signal MRW2 may be a command address signal CA in which logic values ​​of a plurality of bits have a third combination different from the first combination and the second combination. The first command address signal MRW1 may include information about controlling the memory device 120 to perform a burst read operation. The second command address signal MRR may include information about controlling the memory device 120 to perform a mode register read operation. The third command address signal MRW2 may include information about controlling the memory device 120 to perform a mode register write operation. The training operation may be performed by the memory controller 110 performing a burst read operation of the memory device 120, and then terminating the burst read operation of the memory device 120.

[0030] The memory device 120 may perform a burst read operation. Even if the memory controller 110 does not continuously provide the command address signal CA to the memory device 120, the burst read operation may still be performed, so that the memory device 120 repeatedly and periodically performs the mode register read operation internally. The memory controller 110 may sequentially provide the first command address signal MRW1 and the second command address signal MRR to the memory device 120 so that the memory device 120 performs the burst read operation. When the memory device 120 receives the first command address signal MRW1 from the memory controller 110, the mode register group 123 may be set to be ready for the burst read operation. When the memory device 120 receives the second command address signal MRR from the memory controller 110 after the memory device 120 is fully ready for the burst read operation, the mode register group 123 may periodically generate a signal related to the mode register read operation to control the memory device 120 to periodically perform the mode register read operation. The memory device 120 may periodically perform the mode register read operation and may periodically provide training data to the memory controller 110.

[0031] In order to terminate the burst read operation of the memory device 120, the memory controller 110 may provide the third command address signal MRW2 to the memory device 120. The memory controller 110 may terminate the burst read operation of the memory device 120 at any point in time. In a typical semiconductor system, a time interval from the provision of a single command address signal until the provision of a subsequent command address signal is defined. However, since the memory device 120 periodically performs a read operation without receiving the command address signal CA from the memory controller 110 during the burst read operation, a violation of the defined time interval may occur when the memory controller 110 terminates the burst read operation of the memory device 120. That is, the command address signal CA may be provided from the memory controller 110 to the memory device 120 before the memory device 120 completes the internal read operation. Therefore, the memory controller 110 may terminate the burst read operation of the memory device 120 by sequentially providing the third command address signal MRW2 to the memory device 120 twice. When the memory device 120 is performing a burst read operation, the mode register group 123 may terminate the burst read operation being performed by the memory device 120 when the memory device 120 receives the third command address signal MRW2 from the memory controller 110. When the memory device 120 receives the third command address signal MRW2, the mode register group 123 may initialize at least one internal circuit that is performing a burst read operation. For example, the internal circuit may be the data I / O circuit 122. When the memory device 120 receives the third command address signal MRW2, the mode register group 123 may generate a reset signal MRWRST to initialize at least one internal circuit. In an embodiment, whenever the third command address signal MRW2 is received, the mode register group 123 may enable the reset signal MRWRST having a predetermined pulse width. In an embodiment, in order to ensure sufficient time for the initialization of at least one internal circuit, the mode register group 123 may continuously initialize at least one internal circuit during at least a period of time from the first reception of the third command address signal MRW2 until the second reception of the third command address signal MRW2. For example, the mode register group 123 may enable the reset signal MRWRST based on the third command address signal MRW2 received for the first time, and may disable the reset signal MRWRST based on the third command address signal MRW2 received for the second time. By maintaining the reset signal MRWRST in an enabled state during a sufficient amount of time, the mode register group 123 may fully initialize the data I / O circuit 122 and may prevent invalid data from being output from the memory device 120 to the memory controller 110.

[0032] Figure 2 is a diagram illustrating the operation of the semiconductor system 100 according to an embodiment. Figure 2FIG. 1 shows a memory device 120 that sequentially receives a first command address signal MRW1 and a second command address signal MRR and performs a burst read operation. Figure 1 and Figure 2 , the first command address signal MRR1 and the second command address signal MRR may be provided to the memory device 120 in synchronization with the system clock signal CLK. The memory device 120 may divide the system clock signal CLK to generate an internal clock signal ICLK. The period of the internal clock signal ICLK may be twice the period of the system clock signal CLK. When the memory device 120 receives the first command address signal RRW1 from the memory controller 110, the memory device 120 may generate an internal write pulse MRWP in synchronization with the internal clock signal ICLK, and the mode register group 123 may enable the burst read enable signal MRBEN. The burst read enable signal MRBEN may be a signal for the memory device 120 to perform a burst read operation. Next will be a detailed description of the burst read enable signal MRBEN. When the memory device 120 receives the second command address signal MRR from the memory controller 110, the memory device 120 may generate an internal read signal IMRR based on the second command address signal MRR. The memory device 120 may perform a mode register read operation based on the internal read signal IMRR. The memory device 120 may perform a mode register read operation to provide training data as data DQ to the memory controller 110. The mode register group 123 may periodically generate an internal read signal IMRR when the burst read enable signal MRBEN is enabled. The period during which the internal read signal IMRR is generated may be a period corresponding to at least "tCCD". "tCCD" may be defined as a time interval from the receipt of a column command until the receipt of a subsequent column command. The period during which the internal read signal IMRR is generated may be a period corresponding to at least a burst length (BL). Based on the internal read signal IMRR, the mode register group 123 may provide training data to the data I / O circuit 122 through the data transmission line 124. Based on the training data, the data I / O circuit 122 may output data DQ to the data bus 104. When a period corresponding to the read delay (RL) elapses after receiving the second command address signal MRR, the data I / O circuit 122 of the memory device 120 may provide the training data output from the mode register group 123 to the memory controller 110 as data DQ. The data I / O circuit 122 of the memory device 120 may also output a data strobe signal DQS synchronized with the data DQ through the data strobe bus 105. During a burst read operation, the internal read signal IMRR may be periodically generated by the mode register set 123, and thus the memory device 120 may continuously output the data DQ and the data strobe signal DQS.

[0033] Figure 3is a diagram illustrating the operation of the semiconductor system 100 according to an embodiment. Figure 3 FIG. 1 shows a memory device 120 that receives a third command address signal MRW2 during a burst read operation and terminates the burst read operation. Figure 3 , the burst read enable signal MRBEN may remain enabled, and the memory device 120 may remain to perform a burst read operation. When the memory device 120 receives the third command address signal RRW2 from the memory controller 110, the memory device 120 may generate an internal write pulse MRWP. The memory device 120 may disable the burst read enable signal MRBEN based on the internal write pulse MRWP. Therefore, the burst read operation being performed by the memory device 120 may be terminated. The mode register group 123 may generate a reset signal MRWRST having a pulse width corresponding to the pulse width of the internal write pulse MRWP. When the reset signal MRWRST is enabled, the internal circuit that is performing the burst read operation may be initialized. When a time period corresponding to "tMRW" elapses after the third command address signal MRW2 is provided for the first time, the third command address signal MRW2 may be provided from the memory controller 110 to the memory device 120 for the second time. "tMRW" may be defined as a time interval from the time when the memory controller 110 provides any command address signal to the memory device 120 until the first command address signal MRW1 and / or the third command address signal MRW2 can be provided. The memory device 120 may generate an internal write pulse MRWP based on the third command address signal RRW2. The mode register group 123 may generate a reset signal MRWRST again based on the internal write pulse MRWP. When the reset signal MRWRST is enabled again, the internal circuit that is performing a burst read operation may be initialized again. When the reset signal MRWRST is enabled, the data I / O circuit 122 may be initialized, and the data I / O circuit 122 of the memory device 120 may stop outputting data DQ and data strobe signal DQS.

[0034] Figure 4 is a diagram illustrating the operation of the semiconductor system 100 according to an embodiment. Figure 4A memory device 120 is shown receiving a third command address signal MRW2 during a burst read operation and terminating the burst read operation. When the memory device 120 receives the third command address signal RRW2 from the memory controller 110 when performing a burst read operation, the memory device 120 may generate an internal write pulse MRWP. The memory device 120 may disable the burst read enable signal MRBEN based on the internal write pulse MRWP. When the internal write pulse MRWP is enabled, the mode register group 123 may enable the reset signal MRWRST and may keep the reset signal MRWRST in an enabled state. After a time period corresponding to "tMRW" has elapsed, the third command address signal MRW2 may be provided to the memory device 120 from the memory controller 110 for the second time. The memory device 120 may generate an internal write pulse MRWP based on the third command address signal RRW2. When the internal write pulse MRWP is disabled, the mode register group 123 may disable the reset signal MRWRST. The mode register group 123 may maintain the reset signal MRWRST in an enabled state during a period from when the internal write pulse MRWP generated from the third command address signal MRW2 received for the first time is enabled until the internal write pulse MRWP generated from the third command address signal MRW2 received for the second time is disabled. Therefore, the mode register group 123 may ensure a sufficient amount of time for completely initializing the internal circuit. The data I / O circuit 122 of the memory device 120 may be initialized and the output of the data DQ and the data strobe signal DQS may be interrupted.

[0035] After another time period corresponding to "tMRW" has elapsed, the third command address signal MRW2 may be provided from the memory controller 110 to the memory device 120 again. The memory device 120 may generate an internal write pulse MRWP based on the third command address signal RRW2. The mode register group 123 may generate a reset signal MRWRST based on the internal write pulse MRWP. Since the burst read enable signal MRBEN remains disabled, the mode register group 123 may generate a reset signal MRWRST having a pulse width corresponding to the pulse width of the internal write pulse MRWP. Before receiving the third command address signal MRW2, the memory device 120 may be relatively stable without performing a burst read operation, and as long as the pulse width corresponds to the pulse width of the internal write pulse MRWP, the memory device 120 may fully initialize the internal circuit even if the reset signal MRWRST is enabled.

[0036] Figure 5 is a diagram showing a configuration of a storage device 500 according to an embodiment. The storage device 500 may be used as Figure 1The memory device 120 shown is applied. The memory device 500 may include a memory cell array 511, a row decoder 512, a column decoder 513, a read / write circuit 514, a command address receiving circuit 520, a clock receiving circuit 530, a command decoder 540, an address decoder 550, a delay circuit 560, a data input / output (I / O) circuit 570, and a mode register group 580. In the memory cell array 511, a plurality of word lines WL may be arranged in a row direction, and a plurality of bit lines BL may be arranged in a column direction. A plurality of memory cells MC may be coupled to corresponding word lines and bit lines at each intersection between a plurality of word lines WL and a plurality of bit lines BL. When a specific word line and a specific bit line are selected, a memory cell coupled to the specific word line and bit line may be accessed. Based on a row address signal RADD, the row decoder 512 may select a specific word line among the plurality of word lines WL. The row decoder 512 may decode the row address signal RADD to generate a row selection signal, and may select a specific word line based on the row selection signal. Based on the column address signal CADD, the column decoder 513 can select a specific bit line among the plurality of bit lines BL. The column decoder 513 can decode the column address signal CADD to generate a column selection signal, and can select a specific bit line based on the column selection signal. The memory cell MC coupled to the specific word line and bit line selected by the row decoder 512 and the column decoder 513 can be coupled to the read / write circuit 514. The read / write circuit 514 can read the data stored in the memory cell accessed by the row decoder 512 and the read / write circuit 514, and can store the data in the accessed memory cell. The read / write circuit 514 can be coupled to the data I / O circuit 570 through the data transmission line 501. During a normal read operation of the memory device 500, the read / write circuit 514 can read data from the accessed memory cell, and can provide the read data to the data I / O circuit 570 through the data transmission line 501. During a normal write operation of the memory device 500 , the read / write circuit 514 may store data provided from the data I / O circuit 570 through the data transmission line 501 into an accessed memory cell.

[0037] The command address receiving circuit 520 can receive the command address signal CA<1:n> and the chip selection signal CS, where “n” is an integer equal to or greater than 4. Figure 1The command address bus 101 and the chip selection bus 103 shown in the figure are coupled, and can receive the command address signal CA<1:n> and the chip selection signal CS. The command address receiving circuit 520 can determine the command address signal CA<1:n> as valid when receiving the enabled chip selection signal CS. The command address receiving circuit 520 can latch the command address signal CA<1:n> based on the internal clock signal ICLK, and can output the latched command address signal. At least a portion of the command address signal CA<1:n> can be used to generate an internal command signal. At least a portion or all of the command address signal CA<1:n> can be used to generate an internal address signal. The command address receiving circuit 520 can provide at least a portion of the command address signal CA<1:n> to be used to generate the internal command signal to the command decoder 540. The command address receiving circuit 520 can provide at least a portion of the command address signal CA<1:n> to be used to generate the internal address signal to the address decoder 550. The command address receiving circuit 520 may provide the mode register group 580 with all of the command address signals CA<1:n> to be utilized to generate the internal address signal.

[0038] The clock receiving circuit 530 can receive the system clock signal CLK. The clock receiving circuit 530 can receive the system clock signal CLK by Figure 1 The clock bus 102 shown in FIG. receives the system clock signal CLK. The clock receiving circuit 530 may receive the system clock signal CLK to generate an internal clock signal ICLK. When the frequency of the system clock signal CLK is large, the clock receiving circuit 530 may divide the frequency of the system clock signal CLK to generate the internal clock signal ICLK. The clock receiving circuit 530 may divide the frequency of the system clock signal CLK to generate an internal clock signal ICLK having a larger swing range and a larger pulse width, thereby improving the operation timing margin of the storage device 500. For example, the clock receiving circuit 530 may divide the frequency of the system clock signal CLK by two to generate an internal clock signal ICLK having a period that is twice as long as the period of the system clock signal CLK. Although not shown, the clock receiving circuit 530 may include a frequency divider configured to divide the frequency of the system clock signal CLK to generate the internal clock signal ICLK. The internal clock signal ICLK may be provided to the receiving circuit 520, the command decoder 540, the delay circuit 560, and the mode register group 580.

[0039] The command decoder 540 may generate an internal command signal ICMD based on the command address signal CA<1:n> received from the command address receiving circuit 520. The command decoder 540 may decode at least a portion of the command address signal CA<1:n> to generate the internal command signal ICMD. For example, the command decoder 540 may decode the first to mth bits CA<1:m> of the command address signal CA<1:n> to generate the internal command signal ICMD, where “m” is an integer between 1 and “n”. The bits to be selected and the number of bits to be selected in the command address signal CA<1:n> for the command decoder 540 to generate the internal command signal ICMD may vary. The internal command signal ICMD may include various signals. For example, the internal command signal ICMD may include an activation signal, a precharge signal, a normal read signal, a normal write signal, a non-target read signal, a non-target write signal, and a refresh signal, etc. Based on the normal read signal, the read / write circuit 514 and the data I / O circuit 570 may perform a normal read operation of the storage device 500. Based on the normal write signal, the read / write circuit 514 and the data I / O circuit 570 may perform a normal write operation of the memory device 500. When the command address signal CA<1:n> has a combination corresponding to the first command address signal MRW1 and the third command address signal MRW2, the command decoder 540 may generate an internal write pulse MRWP based on a portion CA<1:m> of the command address signal CA<1:n>. When the command address signal CA<1:n> has a combination corresponding to the second command address signal MRR, the command decoder 540 may generate an internal read signal IMRR based on a portion CA<1:m> of the command address signal CA<1:n>. The internal write pulse MRWP and the internal read signal IMRR may be signals for controlling the operation of the mode register group 580. The command decoder 540 may receive an internal clock signal ICLK. In synchronization with the internal clock signal ICLK, the command decoder 540 may latch at least a portion of the command address signal CA<1:n> and may decode the latched signal. In an embodiment, the command decoder 540 may generate an internal read signal IMRR in synchronization with the internal clock signal ICLK. For example, the pulse width of the internal read signal IMRR may correspond to a single cycle of the internal clock signal ICLK. That is, when 1tCK is a time period corresponding to a single cycle of the system clock signal CLK, the pulse width of the internal read signal IMRR may correspond to 2tCK. In an embodiment, the command decoder 540 may generate an internal write pulse MRWP in synchronization with the internal clock signal ICLK. The pulse width of the internal write pulse MRWP may not be synchronized with the internal clock signal ICLK, and may vary asynchronously with respect to the internal clock signal ICLK. The pulse width of the internal write pulse MRWP may vary in various ways.For example, the pulse width of the internal write pulse MRWP may correspond to a period between 2 tCK and 4 tCK.

[0040] The address decoder 550 may generate a row address signal RADD and a column address signal CADD based on the internal command signal ICMD and at least a portion of the command address signal CA<1:n> received from the command address receiving circuit 520. When the internal command signal ICMD is a row-related command signal, the address decoder 550 may generate a row address signal RADD and a column address signal CADD based on the internal command signal ICMD and at least a portion of the command address signal CA<1:n> received from the command address receiving circuit 520.<m+1:n> Generates a row address signal RADD. For example, the row-related command signal may include an activation signal and a refresh signal. When the internal command signal ICMD is a column-related command signal, the address decoder 550 may select at least a portion of the command address signals CA<1:n> from CA<1:n>.<m+1:n> A column address signal CADD is generated. For example, the column-related command signal may include a normal read signal and a normal write signal.

[0041] The delay circuit 560 may receive an internal clock signal ICLK and an internal command signal ICMD. The delay circuit 560 may perform a delay locking operation on the internal clock signal ICLK to generate a delayed clock signal DCLK. In order to delay the internal clock signal ICLK, the delay circuit 560 may include a delay locked loop having a clock delay line. The delay circuit 560 may delay the internal command signal ICMD to generate a delayed command signal DCMD. In order to generate the delayed command signal DCMD, the delay circuit 560 may include a command delay line. The delay amount of the command delay line and the delay amount of the clock delay line may be set to be substantially the same. The internal command signal ICMD to be provided to the delay circuit 560 may include a normal read signal, a normal write signal, a non-target read signal, and a non-target write signal. The delay circuit 560 may also receive an internal read signal IMRR. The delay circuit 560 may delay the internal read signal IMRR to output the delayed internal read signal IMRR as the delayed command signal DCMD. When any signal of the internal command signal ICMD and the internal read signal IMRR is received, the delay circuit 560 may delay the received signal to generate the delayed command signal DCMD.

[0042] The data I / O circuit 570 may be coupled between the data transmission line 501 and the data bus 104. During a normal read operation of the memory device 500, the data I / O circuit 570 may receive data provided from the read / write circuit 514 through the data transmission line 501, and may output the received data as data DQ through the data bus 104. The data I / O circuit 570 may include a data transmitter configured to drive the data bus 104 based on the data provided through the data transmission line 501. During a normal write operation of the memory device 500, the data I / O circuit 570 may receive data DQ provided through the data bus 104, and may output the received data to the read / write circuit 514 through the data transmission line 501. The data I / O circuit 570 may include a data receiver configured to drive the data transmission line 501 based on the data DQ provided through the data bus 104. For example, the data transmitted through the data transmission line 501 may be parallel data, and the data transmitted through the data bus 104 may be serial data. The data I / O circuit 570 may further include a parallel-to-serial converter configured to convert parallel data into serial data and a serial-to-parallel converter configured to convert serial data into parallel data.

[0043] The data I / O circuit 570 may receive a delayed clock signal DCLK, a delayed command signal DCMD, and a reset signal MRWRST. The data I / O circuit 570 may receive information about the delay and the operation mode from the mode register group 580. In synchronization with the delayed clock signal DCLK, the data I / O circuit 570 may delay the delayed command signal DCMD by a time period corresponding to the delay and may perform various operations based on the delayed signal. For example, when the delayed command signal DCMD is generated based on a normal read signal, the data I / O circuit 570 may output the data as data DQ through the data transmitter to perform a normal read operation, the data being provided from the data transmission line 501. When the delayed command signal DCMD is generated based on a normal write signal, the data I / O circuit 570 may set the on-resistance value of the data transmitter and may receive the data DQ through the data receiver to perform a normal write operation. When the delayed command signal DCMD is generated based on a non-target read signal and a non-target write signal, the data I / O circuit 570 may set the on-resistance value of the data transmitter without performing a normal read operation or a normal write operation.

[0044] When the delay command signal DCMD is generated based on the internal read signal IMRR, the data I / O circuit 570 may perform a mode register read operation of outputting the mode register data MRD and / or the training data RDP output from the mode register group 580. The data I / O circuit 570 may be initialized based on the reset signal MRWRST. When the reset signal MRWRST is enabled, all signals generated and processed inside the data I / O circuit 570 may be initialized. Based on the reset signal MRWRST, the data I / O circuit 570 may initialize a signal for setting an on-resistance value of a data transmitter.

[0045] The mode register group 580 may receive an internal read signal IMRR, an internal write pulse MRWP, and a command address signal CA<1:n> to generate a burst read signal BR and a reset signal MRWRST. The mode register group 580 may include a register configured to store mode register data MRD related to various operations of the memory device 500. Based on the internal read signal IMRR and the command address signal CA<1:n>, the mode register group 580 may provide the data I / O circuit 570 with mode register data MRD regarding specific information among the information stored in the register. Based on the internal write pulse MRWP and the command address signal CA<1:n>, the mode register group 580 may select a specific storage space in the register, and may store the mode register data MRD included in the command address signal CA<1:n> in the selected storage space.

[0046] When the internal write pulse MRWP is received and the first command address signal MRW1 is received, the mode register set 580 may set the memory device 500 to perform a burst read operation. Based on the internal write pulse MRWP and the first command address signal MRW1, the mode register set 580 may generate Figures 2 to 4 . When the internal read signal IMRR is received after the burst read enable signal MRBEN is enabled, the mode register group 580 may periodically generate a burst read signal BR. The burst read signal BR may be provided to the command decoder 540. Even when the second command address signal MRR is not received, the command decoder 540 may periodically enable the internal read signal IMRR based on the burst read signal BR. For example, based on the burst read signal BR, the command decoder 540 may periodically enable the internal read signal IMRR at a time interval corresponding to at least tCCD or the burst length BL.

[0047] When the memory device 500 is performing a burst read operation, the mode register set 580 may terminate the burst read operation and may generate a reset signal MRWRST when receiving the internal write pulse MRWP and the third command address signal MRW2. Based on the internal write pulse MRWP and the third command address signal MRW2, the mode register set 580 may disable the burst read enable signal MRBEN and may enable the reset signal MRWRST. When the internal write pulse MRWP and the third command address signal MRW2 are received again, the mode register set 580 may disable the reset signal MRWRST.

[0048] Figure 6 6 is a diagram showing a configuration of a mode register set 600 according to an embodiment. The mode register set 600 may be used as Figure 5 The mode register set 580 shown in FIG. 5 is applied. Figure 5 and Figure 6 , the mode register group 600 may include a latch enable control circuit 610, a mode register control circuit 620, a register 630, a training data generation circuit 640, a reset signal generation circuit 650, and a burst read generation circuit 660. The latch enable control circuit 610 may receive an internal read signal IMRR, an internal write pulse MRWP, and a burst read enable signal MRBEN to generate a latch enable signal LATEN. When the burst read enable signal MRBEN remains disabled, the latch enable control circuit 610 may provide any one of the internal read signal IMRR and the internal write pulse MRWP as the latch enable signal LATEN to enable the latch enable signal LATEN. When the burst read enable signal MRBEN is enabled, the latch enable control circuit 610 may generate the latch enable signal LATEN not based on the internal read signal IMRR but only based on the internal write pulse MRWP.

[0049] The latch enable control circuit 610 may include a first inverter 611, a first NAND gate 612, a second inverter 613, and a second NAND gate 614. The first inverter 611 may receive a burst read enable signal MRBEN to reversely drive the burst read enable signal MRBEN. The first NAND gate 612 may receive an internal read signal IMRR and an output of the first inverter 611. When the burst read enable signal MRBEN is enabled to a logic high level, the first NAND gate 612 may output a signal of a logic high level regardless of the logic level of the internal read signal IMRR. When the burst read enable signal MRBEN is disabled to a logic low level and the internal read signal IMRR is enabled to a logic high level, the first NAND gate 612 may output a signal of a logic low level. The second inverter 613 may receive an internal write pulse MRWP to reversely drive the internal write pulse MRWP. The second NAND gate 614 may receive the outputs of the first NAND gate 612 and the second inverter 613 to output a latch enable signal LATEN. When the first NAND gate 612 outputs a signal of a logic low level or the second inverter 613 outputs a signal of a logic low level (ie, the internal write pulse MRWP is enabled to a logic high level), the second NAND gate 614 may output a latch enable signal LATEN of a logic high level.

[0050] The mode register control circuit 620 may receive a latch enable signal from the latch enable control circuit 610, and may receive a command address signal CA<1:n> from the command address receiving circuit 520. When the latch enable signal LATEN is enabled, the mode register control circuit 620 may latch the command address signal CA<1:n> and may generate various control signals by decoding the latched command address signal. The various control signals may include a signal for controlling the operation of the register 630 and the training data generating circuit 640, the mode register data MRD, the address information of the register 630 in which the mode register data MRD is stored or outputted, or a burst read enable signal MRBEN. The register 630 may store the mode register data MRD therein. During a mode register read operation, the register 630 may output the mode register data MRD stored in the storage space corresponding to the address information to the data transmission line 501. During a mode register write operation, the register 630 may store the mode register data MRD in the storage space corresponding to the address information. The training data generation circuit 640 may receive the burst read enable signal MRBEN and the internal read signal IMRR to generate the training data RDP. Based on the control signal output from the mode register control circuit 620, the training data generation circuit 640 may set the pattern of the training data RDP. Based on the burst read enable signal MRBEN and the internal read signal IMRR, the training data generation circuit 640 may output the training data RDP to the data transmission line 501. When the burst read enable signal MRBEN remains enabled, the training data generation circuit 640 may output the training data RDP having the set pattern to the data transmission line 501 whenever the internal read signal IMRR is enabled.

[0051] When the first command address signal MWR1 is received, the mode register control circuit 620 may decode the first command address signal MWR1 to enable the burst read enable signal MRBEN. When the second command address signal MRR is received while the burst read enable signal MRBEN remains disabled, the mode register control circuit 620 may decode the second command address signal MRR to control the register 630 and may control the register 630 to output the mode register data MRD stored therein to the data transmission line 501. When the third command address signal MRW2 is received, the mode register control circuit 620 may decode the third command address signal MRW2 to control the register 630 and may control the register 630 to store therein the mode register data MRD included in the third command address signal MRW2.

[0052] The mode register control circuit 620 may include an address latch circuit 621 and a decoding circuit 622. When the latch enable signal LATEN is enabled, the address latch circuit 621 may latch the command address signal CA<1:n>. The address latch circuit 621 may output a portion of the latched command address signal CA<1:n> as the mode register address signal MRA<1:k>, and may output the remaining portion of the latched command address signal CA<1:n> as the operation code MROP<1:k>, where “k” is an integer corresponding to half of “n”. The mode register address signal MRA<1:k> and the operation code MROP<1:k> may have different numbers of bits, although they are illustrated as having the same number of bits. The mode register address signal MRA<1:k> may include mode register data MRD and address information indicating a storage space in which the mode register data MRD is stored in the register 630. The operation code MROP<1:k> may be used as a signal indicating various operations of the mode register group 600. The decoding circuit 622 may decode the mode register address signal MRA<1:k> and the operation code MROP<1:k> to generate various signals for controlling the operation of the mode register group 600. Based on the operation code MROP<1:k>, the mode register group 600 may store the mode register data MRD generated from the mode register address signal MRA<1:k> into the register 630. Based on the operation code MROP<1:k>, the mode register group 600 may output the mode register data MRD stored in the register 630 to the data transmission line 501. Based on the operation code MROP<1:k>, the mode register group 600 may set the pattern of the training data RDP generated by the training data generation circuit 640. Based on the operation code MROP<1:k>, the mode register group 600 may enable the burst read enable signal MRBEN.

[0053] The reset signal generating circuit 650 may receive the internal write pulse MRWP and the burst read enable signal MRBEN to generate the reset signal MRWRST. Based on the internal write pulse MRWP and the burst read enable signal MRBEN, the reset signal generating circuit 650 may generate the reset signal MRWRST. The reset signal generating circuit 650 may provide the internal write pulse MRWP as the reset signal MRWRST, and may provide the burst read enable signal MRBEN as the reset signal MRWRST in synchronization with the internal write pulse MRWP. After the burst read enable signal MRBEN is enabled, the reset signal generating circuit 650 may keep the reset signal MRWRST in an enabled state during a period from when the first generated internal write pulse MRWP is enabled until the second generated internal write pulse MRWP is disabled.

[0054] The burst read generation circuit 660 may receive the internal read signal IMRR, the burst read enable signal MRBEN, and the internal clock signal ICLK to generate the burst read signal BR. When the burst read enable signal MRBEN is enabled, the burst read generation circuit 660 may generate the burst read signal BR by delaying the internal read signal IMRR by a predetermined amount of time. In synchronization with the internal clock signal ICLK, the burst read generation circuit 660 may delay the internal read signal IMRR. The sum of the predetermined amount of time and the amount of time required for the command decoder 540 to generate the internal read signal IMRR based on the burst read signal BR may correspond to "tCCD" or the burst length BL.

[0055] Figure 7 It is shown Figure 6 , which is a diagram showing a configuration of a reset signal generating circuit 650 shown in FIG. Figure 7 , the reset signal generating circuit 650 may include a flip-flop 710 and an OR gate 720. The flip-flop 710 may be a D flip-flop. The flip-flop 710 may receive a burst read enable signal MRBEN through its input node D, may receive an internal write pulse MRWP through its clock node, and may output a burst reset signal BRRST through its output node Q. In synchronization with the rising edge of the internal write pulse MRWP, the flip-flop 710 may output the burst read enable signal MRBEN as a burst reset signal BRRST. The OR gate 720 may receive the burst reset signal BRRST and the internal write pulse MRWP. The OR gate 720 may perform an OR gating operation on the burst reset signal BRRST and the internal write pulse MRWP to generate a reset signal MRWRST. When the burst read enable signal MRBEN remains enabled, the reset signal generating circuit 650 may enable the reset signal MRWRST when the internal write pulse MRWP generated for the first time is enabled, and may disable the reset signal MRWRST when the internal write pulse MRWP generated for the second time is disabled. To ensure a timing margin for the flip-flop 710 to sample the burst read enable signal MRBEN, the reset signal generating circuit 650 may further include a delayer 730 configured to delay the burst read enable signal MRBEN. The flip-flop 710 may receive a signal output from the delayer 730 through an input node D thereof.

[0056] Figure 8 It is shown Figure 6 FIG. 6 is a diagram showing a configuration of the burst read generation circuit 660 shown in FIG. Figure 8, the burst read generation circuit 660 may include a clock gating circuit 810, a plurality of flip-flops, and a latch driving circuit 830. The clock gating circuit 810 may receive an internal clock signal ICLK and a burst read enable signal MRBEN. Based on the burst read enable signal MRBEN, the clock gating circuit 810 may perform a gating operation on the internal clock signal ICLK to generate a gated clock signal GCLK. When the burst read enable signal MRBEN is enabled, the clock gating circuit 810 may output the internal clock signal ICLK as the gated clock signal GCLK. When the burst read enable signal MRBEN is disabled, the clock gating circuit 810 may interrupt the output of the internal clock signal ICLK as the gated clock signal GCLK.

[0057] The clock gating circuit 810 may include a NAND gate 811 and an inverter 812. The NAND gate 811 may receive an internal clock signal ICLK and a burst read enable signal MRBEN. The inverter 812 may reversely drive a signal output from the NAND gate 811 to output a gated clock signal GCLK. When the burst read enable signal MRBEN is enabled, the NAND gate 811 may operate as an inverter, and the internal clock signal ICLK may be provided as a gated clock signal GCLK.

[0058] In synchronization with the gated clock signal GCLK, a plurality of flip-flops may sequentially delay the internal read signal IMRR. For example, a plurality of flip-flops may include a first flip-flop 821, a second flip-flop 822, and a third flip-flop 823. Each of the first to third flip-flops 821 to 823 may be a D flip-flop. The first flip-flop 821 may receive the internal read signal IMRR through its input node D, and may receive the gated clock signal GCLK through its clock node. The second flip-flop 822 may be coupled to the output node Q of the first flip-flop 821 at its input node D, and may receive the output signal N1 of the first flip-flop 821. The second flip-flop 822 may receive the gated clock signal GCLK through its clock node. The third flip-flop 823 may be coupled to the output node Q of the second flip-flop 822 at its input node D, and may receive the output signal N2 of the second flip-flop 822. The third flip-flop 823 may receive the gated clock signal GCLK through its clock node. The third flip-flop 823 may output the output signal N3 through its output node Q. Since the cycle of the gated clock signal GCLK may correspond to the internal clock signal ICLK, the output signals N1 to N3 of the first to third flip-flops 821 to 823 may sequentially have a phase difference corresponding to "2tCK", and the time period during which the internal read signal IMRR is delayed by the first to third flip-flops 821 to 823 may correspond to "6tCK". Each of the first to third flip-flops 821 to 823 may receive the complementary signal MRBENB of the burst read enable signal MRBEN through its reset node RST, and may be reset based on the complementary signal MRBENB of the burst read enable signal MRBEN. The inverter 841 may reversely drive the burst read enable signal MRBEN to generate the complementary signal MRBENB of the burst read enable signal MRBEN. The number of the plurality of flip-flops may be less than or greater than 3 in order to change the cycle of generating the internal read signal IMRR based on the burst read signal BR.

[0059] The latch driving circuit 830 may drive and latch the signals output from the plurality of flip-flops to generate a burst read signal BR. Based on the gated clock signal GCLK, the latch driving circuit 830 may perform driving and latching operations. For example, the latch driving circuit 830 may drive the signals output from the plurality of flip-flops to generate a burst read signal BR when the gated clock signal GCLK has a logic low level, and may latch the logic level of the burst read signal BR when the gated clock signal GCLK has a logic high level. Therefore, the amount of time required for the latch driving circuit 830 to generate the burst read signal BR by driving and latching the signals output from the plurality of flip-flops may be set to "1tCK".

[0060] The latch driving circuit 830 may include a first control inverter 831, an inverter 832, and a second control inverter 833. The first control inverter 831 may be activated based on a gated clock signal GCLK and a complementary signal GCLKB of the gated clock signal GCLK and may reversely drive an output signal N3 of the third flip-flop 823. When the gated clock signal GCLK has a logic low level, the first control inverter 831 may be activated. The inverter 832 may reversely drive a signal output from the first control inverter 831 to generate a burst read signal BR. The second control inverter 833 may be coupled to an output node of the inverter 832 through its input node and may be coupled to an input node of the inverter 832 through its output node. The second control inverter 833 may be activated based on a gated clock signal GCLK and a complementary signal GCLKB of the gated clock signal GCLK. When the gated clock signal GCLK has a logic high level, the second control inverter 833 may be activated and may form a latch together with the inverter 832 to maintain the logic level of the burst read signal BR.

[0061] Fig. 9 is a timing diagram illustrating the operation of a mode register set during a burst read operation according to an embodiment. Figure 1 , Figure 5 , Figure 6 , Figure 8 and Fig. 9, when the memory device 120 receives the first command address signal MRW1 from the memory controller 110, an internal write pulse MRWP may be generated and a latch enable signal LATEN may be enabled based on the internal write pulse MRWP. When the latch enable signal LATEN is enabled, the mode register control circuit 620 may enable a burst read enable signal MRBEN based on the first command address signal MRW1. Then, when the memory device 120 receives the second command address signal RR from the memory controller 110, an internal read signal IMRR may be generated. Since the burst read enable signal MRBEN remains enabled, the latch enable control circuit 610 may not enable the latch enable signal LATEN even when the internal read signal IMRR is generated. The internal read signal IMRR may be provided to the burst read generation circuit 660. The clock gating circuit 810 may provide an internal clock signal ICLK as a gated clock signal GCLK, and the internal read signal IMRR may be sequentially delayed by the first to third flip-flops 821 to 823. The output signal N1 of the first flip-flop 821 may be delayed by a phase amount corresponding to "2tCK" compared to the internal read signal IMRR. The output signal N2 of the second flip-flop 822 may be delayed by a phase amount corresponding to "4tCK" compared to the internal read signal IMRR. The output signal N3 of the third flip-flop 823 may be delayed by a phase amount corresponding to "6tCK" compared to the internal read signal IMRR. The latch drive circuit 830 may drive and latch the output signal N3 of the third flip-flop 823 to generate a burst read signal BR. The burst read signal BR may be delayed by a phase amount corresponding to "7tCK" compared to the internal read signal IMRR. The burst read signal BR may be provided to the command decoder 540. In synchronization with the internal clock signal ICLK, the command decoder 540 may generate the internal read signal IMRR from the burst read signal BR. Therefore, after a period of "8tCK" from when the internal read signal IMRR generated for the first time is enabled, the internal read signal IMRR generated for the second time may be enabled. The internal read signal IMRR may be provided again to the burst read generation circuit 660, and the burst read generation circuit 660 may periodically generate the burst read signal BR after a period of “7tCK” starting from the burst read generation circuit 660 receiving the internal read signal IMRR. Therefore, the internal read signal IMRR may be periodically generated at time intervals of “8tCK”.

[0062] Fig.10 It is like Figure 5 FIG. 5 is a diagram showing a configuration of a delay circuit 560 shown in FIG. Fig.10, the delay circuit 560 may perform a delayed latch operation on the internal clock signal ICLK. The delay circuit 560 may delay the internal clock signal ICLK to generate a delayed clock signal DCLK. The delay circuit 560 may receive an internal command signal ICMD and an internal read signal IMRR. The delay circuit 560 may delay at least one of the internal command signal ICMD and the internal read signal IMRR by as much time as the internal clock signal ICLK is delayed, thereby generating a delayed command signal DCMD. The delay circuit 560 may include a gating circuit 1010 and a delay locked loop 1020. The gating circuit 1010 may receive the internal command signal ICMD and the internal read signal IMRR. The gating circuit 1010 may provide both the internal command signal ICMD and the internal read signal IMRR to the delay locked loop 1020. The gating circuit 1010 may include an OR gate. When either of the internal command signal ICMD and the internal read signal IMRR is enabled, the gating circuit 1010 may provide an enabled signal to the delay locked loop 1020. The delay locked loop 1020 may include a clock delay line 1021 and a command delay line 1022. Although not shown, the delay locked loop 1020 may also include various elements configured to perform a delay latch operation. Through the delay latch operation on the internal clock signal ICLK, the delay amounts of the clock delay line 1021 and the command delay line 1022 may be set to be the same as each other. That is, the delay time of the clock delay line 1021 may be the same as the delay time of the command delay line 1022. The clock delay line 1021 may delay the internal clock signal ICLK to generate a delayed clock signal DCLK. The command delay line 1022 may delay the output of the gating circuit 1010 to generate a delayed command signal DCMD. The delay circuit 560 may generate a delayed command signal DCMD based on the internal command signal ICMD during a normal read operation and a normal write operation of the memory device 500, and further, may generate a delayed command signal DCMD based on the internal read signal IMRR during a mode register read operation.

[0063] Fig.11 and Fig.12 2 is a diagram illustrating an operation of a semiconductor system according to an embodiment. Fig.11 and Fig.12 A memory device 500 ( Figure 5 ). Fig.11 1 shows an operation in the case where the reset signal MRWRST is enabled only when the internal write pulse MRWP is generated, as shown in FIG. Figure 3 As discussed. Fig.12 shows the operation in the case where the internal write pulse MRWP remains enabled, as shown in FIG. Figure 4 In the following, reference will be made to Figures 1 to 12The operation of the semiconductor system 100 according to the embodiment is described. Based on the internal read signal IMRR periodically generated during the burst read operation, the memory device 120 may output the data DQ and the data strobe signal DQS. In order to terminate the burst read operation being performed by the memory device 120, the memory controller 110 may sequentially provide the third command address signal MRW2 twice to the memory device 120. Fig.11 , based on the third command address signal MRW2 received for the first time, the memory device 120 may generate an internal write pulse MRWP. When the internal write pulse MRWP is enabled, the burst read enable signal MRBEN is disabled and the burst read operation may be terminated. Based on the internal write pulse MRWP, the reset signal MRWRST may be enabled to have a pulse width corresponding to the internal write pulse MRWP. Based on the reset signal MRWRST, the internal circuit that is performing the burst read operation may be initialized. When a time period corresponding to "tMRW" elapses after the third command address signal MRW2 is transmitted for the first time, the third command address signal MRW2 may be transmitted for the second time. The memory device 120 may generate an internal write pulse MRWP based on the third command address signal MRW2 received for the second time, and the reset signal MRWRST may be enabled again based on the internal write pulse MRWP. Therefore, the internal circuit may be initialized in the time period in which the reset signal MRWRST is enabled. However, the sum of the time periods in which the reset signal MRWRST is enabled may be approximately twice the pulse width of the internal write pulse MRWP, which may not be sufficient to fully initialize the internal circuit that continuously outputs data DQ when performing a burst read operation. When the internal circuit is not completely initialized, although a normal read operation or a normal write operation is not performed, invalid data DQ and a data strobe signal DQS (such as DQS) may be provided from the memory device 120 to the memory controller 110 due to energy still retained in the internal circuit. Fig.11 Therefore, a failure may occur between the memory controller 110 and the memory device 120.

[0064] Reference Fig.12 , the memory device 120 may maintain the reset signal MRWRST in an enabled state during a period starting from when the internal write pulse MRWP generated based on the third command address signal MRW2 received for the first time is enabled until the internal write pulse MRWP generated based on the third command address signal MRW2 received for the second time is disabled. When the reset signal MRWRST remains enabled for a sufficient amount of time, the internal circuit may be fully initialized and invalid data DQ and data strobe signal DQS (such as Fig.11 ”A” in the figure).

[0065] Although certain embodiments have been described above, those skilled in the art will appreciate that the described embodiments are only examples. Therefore, the memory device, the semiconductor system including the memory device, and the operating method thereof should not be limited based on the described embodiments. On the contrary, the memory device, the semiconductor system including the memory device, and the operating method thereof should only be limited according to the attached claims in combination with the above description and the accompanying drawings.

Claims

1. A semiconductor system comprising: a memory controller configured to provide at least a first command address signal, a second command address signal, and a third command address signal; A storage device configured to perform a burst read operation based on the first command address signal and the second command address signal, configured to terminate the burst read operation when the third command address signal is received for the first time while the burst read operation is being performed, and configured to continuously initialize an internal circuit that is performing the burst read operation at least in a time period from the first time the third command address signal is received until the second time the third command address signal is received.

2. The semiconductor system according to claim 1, wherein: The memory device is configured to generate a burst read enable signal based on the first command address signal, and is configured to periodically generate an internal read signal based on the second command address signal when the memory device receives the second command address signal after the burst read enable signal is enabled.

3. The semiconductor system according to claim 1, wherein: The memory device is configured to enable a reset signal to initialize the internal circuit when the third command address signal is received for the first time, and is configured to keep the reset signal in an enabled state at least until the third command address signal is received for the second time.

4. A semiconductor system comprising: Storage device; as well as a memory controller configured to sequentially provide a first command address signal and a second command address signal to control the memory device to perform a burst read operation, and configured to provide a third command address signal at least twice to control the memory device to terminate the burst read operation, The storage device is configured to enable a reset signal to initialize an internal circuit that is performing the burst read operation based on a third command address signal received for the first time, and is configured to disable the reset signal based on a third command address signal received for the second time.

5. The semiconductor system according to claim 4, wherein: The memory device is configured to generate a burst read enable signal based on the first command address signal, and is configured to periodically generate an internal read signal based on the second command address signal when the memory device receives the second command address signal after the burst read enable signal is enabled.

6. The semiconductor system according to claim 4, wherein: The memory device is configured to maintain the reset signal in an enabled state during a period from when an internal write pulse generated based on a third command address signal received for a first time is enabled until when the internal write pulse generated based on a third command address signal received for a second time is disabled.

7. A method for operating a semiconductor system, the method comprising: performing, by the memory device, a burst read operation by sequentially receiving a first command address signal and a second command address signal from the memory controller; The memory device terminates the burst read operation by receiving a third command address signal from the memory controller, and the memory device starts initializing the operation of an internal circuit that is performing the burst read operation; as well as An operation of initializing an internal circuit that is performing the burst read operation is terminated by the memory device by receiving another third command address signal from the memory controller.

8. The operating method according to claim 7, wherein: Executing the burst read operation includes: enabling a burst read enable signal based on the first command address signal; and After the internal read signal is enabled based on the second command address signal, the internal read signal is periodically and repeatedly enabled.

9. A semiconductor storage device comprising: A command address receiving circuit configured to receive a command address signal; a command decoder configured to generate an internal read signal and an internal write pulse based on the command address signal, and configured to generate the internal read signal based on a burst read signal; a delay circuit configured to delay the internal read signal and the clock signal to generate a delayed command signal and a delayed clock signal; a data input / output circuit configured to output data based on the delayed command signal and the delayed clock signal, and configured to be initialized based on a reset signal; as well as A mode register set is configured to generate a burst read enable signal based on the command address signal, configured to generate the burst read signal based on the burst read enable signal, and configured to generate the reset signal based on the burst read enable signal and the internal write pulse.

10. The semiconductor memory device according to claim 9, wherein: The command decoder is configured to periodically generate the internal read signal until the internal write pulse is generated after the burst read signal is enabled.

11. The semiconductor memory device according to claim 9, in, The command decoder is configured to also generate a normal operation signal based on the command address signal, and The delay circuit is configured to generate the delay command signal based on at least one of the internal read signal and the normal operation signal.

12. The semiconductor memory device according to claim 11, wherein: The normal operation signal includes at least one of a read signal, a write signal, a non-target read signal, and a non-target write signal.

13. The semiconductor memory device according to claim 9, wherein: The data input / output circuit is configured to synchronize the timing of the delayed command signal and the delayed clock signal, to generate an output enable signal after a time period corresponding to the delay, and to output the data by synchronizing the data with the delayed clock signal when the output enable signal is enabled.

14. The semiconductor memory device according to claim 9, wherein: The mode register group is configured to enable the burst read enable signal when the command address signal has a first combination, to enable the reset signal if an internal write pulse is generated for the first time when the burst read enable signal is enabled, and to disable the reset signal when the internal write pulse is generated for the second time.

15. The semiconductor memory device according to claim 9, wherein: The mode register set includes: a latch enable control circuit configured to generate a latch enable signal based on the internal read signal, the internal write pulse, and the burst read enable signal; and The mode register control circuit is configured to decode the command address signal based on the latch enable signal to generate mode register data and the burst read enable signal.

16. The semiconductor memory device according to claim 15, wherein: The latch enable control circuit is configured to enable the latch enable signal based on any one of the internal read signal and the internal write pulse, and is configured to maintain the latch enable signal in a disabled state when the burst read enable signal is enabled.

17. The semiconductor memory device according to claim 9, wherein: The mode register set includes: a reset signal generating circuit configured to generate the reset signal based on the internal write pulse and the burst read enable signal; and The burst read generation circuit is configured to generate the burst read signal based on the burst read enable signal and the internal read signal.

18. The semiconductor memory device according to claim 17, wherein: The reset signal generation circuit is configured to output the internal write pulse as the reset signal, and is configured to output the burst read enable signal as the reset signal in synchronization with the internal write pulse.

19. The semiconductor memory device according to claim 17, wherein: The reset signal generating circuit comprises: a flip-flop configured to receive the burst read enable signal through an input node thereof, configured to receive the internal write pulse through a clock node thereof, and configured to output a burst reset signal through an output node thereof; and An OR gate is configured to perform an OR gating operation on the internal write pulse and the burst reset signal to generate the reset signal.

20. The semiconductor memory device according to claim 17, wherein: The burst read generation circuit is configured to delay the internal read signal by a predetermined amount of time to generate the burst read signal when the burst read enable signal is enabled.

21. The semiconductor memory device according to claim 20, wherein: The sum of the predetermined amount of time and the amount of time required for the command decoder to generate the internal read signal based on the burst read signal is a time period corresponding to a burst length.

22. The semiconductor memory device according to claim 20, wherein: The burst read generation circuit includes: a clock gating circuit configured to perform a gating operation on the clock signal based on the burst read enable signal to generate a gated clock signal; a plurality of flip-flops configured to sequentially delay the internal read signal in synchronization with the gated clock signal; and The latch driving circuit is configured to drive and latch the delayed internal read signal based on the gated clock signal to generate the burst read signal.

23. A semiconductor system comprising: a memory controller configured to provide at least a first command address signal, a second command address signal, and a third command address signal; as well as A storage device is configured to perform a burst read operation based on the first command address signal and the second command address signal, is configured to terminate the burst read operation when the third command address signal is received twice, and is configured to continuously initialize an internal circuit that is performing the burst read operation in an interval in which the third command address signal is received twice.

24. The semiconductor system according to claim 23, wherein: The memory device is configured to generate a burst read enable signal based on the first command address signal, and is configured to periodically generate an internal read signal based on the second command address signal when the memory device receives the second command address signal after the burst read enable signal is enabled.

25. The semiconductor system according to claim 23, wherein: The memory device is configured to enable a reset signal to initialize the internal circuit when the third command address signal is received for the first time, and is configured to keep the reset signal in an enabled state at least until the third command address signal is received for the second time.

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