Memory device and method of pre-charge operation thereof

Abstract

Embodiments of a memory device having a pre-charge circuit are described. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source / drain (S / D) terminal coupled to a reference voltage, and a second S / D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S / D terminal coupled to the reference voltage, and a fourth S / D terminal coupled to a second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to applying control signals to the first and second gate terminals, respectively. Embodiments of the invention also relate to methods of a memory device and its pre-charge operation.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a memory device and a method of pre-charge operation thereof. BACKGROUND

[0002] Static random access memory (SRAM) is a type of semiconductor memory used in computing applications requiring, for example, high speed data access. For example, cache memory applications use SRAM to store frequently accessed data, such as data accessed by a central processing unit.

[0003] The cell structure and architecture of SRAM enable high speed data access. An SRAM cell can include a bistable flip-flop structure having, for example, four to ten transistors. An SRAM architecture can include one or more arrays of memory cells and support circuitry. Each SRAM array is arranged in rows and columns, respectively referred to as "word lines" and "bit lines." The support circuitry includes address and driver circuitry for accessing each SRAM cell via the word lines and bit lines for various SRAM operations. SUMMARY

[0004] According to an aspect of an embodiment of the present application, there is provided a memory device, comprising: a memory cell including a first terminal and a second terminal; a first transistor having a first gate terminal, a first source / drain (S / D) terminal coupled to a reference voltage, and a second S / D terminal coupled to the first S / D terminal of the memory cell, wherein the first transistor is configured to transfer the reference voltage from the first S / D terminal to the second S / D terminal in response to applying a control signal to the first gate terminal; and a second transistor having a second gate terminal, a third S / D terminal coupled to the reference voltage, and a fourth S / D terminal coupled to the second terminal of the memory cell, wherein the second transistor is configured to transfer the reference voltage from the third S / D terminal to the fourth S / D terminal in response to applying the control signal to the second gate terminal.

[0005] According to another aspect of the embodiments of the present application, there is provided a memory device, comprising: a memory cell array including a first memory cell and a second memory cell, wherein each of the first memory cell and the second memory cell includes a first terminal and a second terminal; and a pre-charge circuit coupled to the memory cell array and including a first pre-charge cell and a second pre-charge cell, wherein: the first pre-charge cell is configured to transmit a reference voltage to the first terminal and the second terminal of the first memory cell based on a first control signal; and the second pre-charge cell is configured to transmit the reference voltage to the first terminal and the second terminal of the second memory cell based on a second control signal, wherein each of the first pre-charge cell and the second pre-charge cell includes: a first transistor having: a first gate terminal; a first source / drain (S / D) terminal coupled to the reference voltage; and a second S / D terminal coupled to the first terminal of the first memory cell or the second memory cell, wherein the first transistor is configured to transmit the reference voltage from the first S / D terminal to the second S / D terminal; and a second transistor having: a second gate terminal; a third S / D terminal coupled to the reference voltage; and a fourth S / D terminal coupled to the second terminal of the first memory cell or the second memory cell, wherein the second transistor is configured to transmit the reference voltage from the third S / D terminal to the fourth S / D terminal.

[0006] According to yet another aspect of the embodiments of the present application, there is provided a method of performing a pre-charge operation, comprising: selecting a memory cell in a memory cell array to perform a memory operation using a first terminal and a second terminal of the memory cell; and activating a pre-charge cell to charge the first terminal and the second terminal of the memory cell to a reference voltage when the memory cell is deselected, wherein the pre-charge cell includes a transistor having: a gate terminal; a first source / drain (S / D) terminal coupled to the reference voltage; and a second S / D terminal coupled to the first terminal or the second terminal of the memory cell, wherein the transistor is configured to transmit the reference voltage from the first S / D terminal to the second S / D terminal in response to applying a control signal to the gate terminal. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the application can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to the judgment of the inventor, various components are not drawn to scale and are merely intended for use in illustration. In fact, the dimensions of the various components can be arbitrarily increased or decreased for the purpose of a clear discussion.

[0008] Figure 1 is an illustration of a static random access memory with a pre-charge circuit according to some embodiments of the present disclosure.

[0009] Figure 2is an illustration of an example static random access memory circuit topology.

[0010] Figure 3 is an illustration of a first pre-charge unit topology according to some embodiments of the disclosure.

[0011] Figure 4A and Figure 4B are illustrations of a second pre-charge unit topology and associated layout, respectively, according to some embodiments of the disclosure.

[0012] Figure 5A and Figure 5B are illustrations of a third pre-charge unit topology and associated layout, respectively, according to some embodiments of the disclosure.

[0013] Figure 6 is an illustration of a fourth pre-charge unit topology according to some embodiments of the disclosure.

[0014] Figure 7 is an illustration of a fifth pre-charge unit topology according to some embodiments of the disclosure.

[0015] Figure 8 is an illustration of a first pre-charge circuit architecture having multiple pre-charge units and write assist units according to some embodiments of the disclosure.

[0016] Figure 9 is an illustration of a second pre-charge circuit architecture having multiple pre-charge units and multiple write assist units according to some embodiments of the disclosure.

[0017] Figure 10 is an illustration of a third pre-charge circuit architecture having multiple pre-charge units and multiple write assist units according to some embodiments of the disclosure.

[0018] Figure 11A and Figure 11B are illustrations of a combined pre-charge unit and write assist unit and associated layout, respectively, according to some embodiments of the disclosure.

[0019] Figure 12 is an illustration of a memory system having a pre-charge unit for each column of memory cells in a memory array according to some embodiments of the disclosure.

[0020] Figure 13 is an illustration of a memory system having multiple pre-charge units for each column of memory cells in a memory array according to some embodiments of the disclosure.

[0021] Figure 14 is an illustration of example waveforms related to operation of a memory system having a pre-charge circuit according to some embodiments of the disclosure.

[0022] Figure 15 is an illustration of a method for a precharge operation performed on a memory system according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Specific embodiments or examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. Moreover, the application can be used in various examples without departing from the spirit or scope of the system and / or method. Furthermore, the

[0024] The following disclosure describes aspects of static random access memory (SRAM). In particular, the disclosure describes different embodiments related to SRAM precharge circuits. To facilitate explanation, certain SRAM circuit elements and control circuits are disclosed to facilitate description of the different embodiments. The SRAM can also include other circuit elements and control circuits. These other circuit elements and control circuits are within the spirit and scope of the present disclosure.

[0025] Figure 1 is an illustration of a static random access memory (SRAM) device 100 having a precharge circuit 110 according to some embodiments of the present disclosure. The SRAM device 100 also includes a row decoder 120, a word line driver 130, a column decoder 140, a column multiplexer (MUX) 150, a read / write circuit 160, and an SRAM array 180. The SRAM array 180 includes columns 1700-170 N .

[0026] Each SRAM cell in the SRAM array 180 is accessed using a memory address - e.g., for memory read and memory write operations. Based on the memory address, the row decoder 120 selects a row of memory cells to be accessed via the word line driver 130. Further, based on the memory address, the column decoder 140 selects a column 1700-170 N of memory cells to be accessed via the column MUX 150. In a memory read operation, the read / write circuit 160 senses a voltage level on a bit line pair BL / BLB. For a memory write operation, the read / write circuit 160 generates a voltage for the bit line pair BL / BLB in a column 1700-170 N of memory cells. The symbol "BL" refers to a bit line and the symbol "BLB" refers to the complement of BL. The intersection of the accessed row and the accessed column of memory cells results in access to a single memory cell 190.

[0027] The columns 1700-170N Each of the SRAM cells 190 can be arranged in one or more arrays in the SRAM device 100. In this disclosure, a single SRAM array 180 is shown to simplify the description of the disclosed embodiments. The SRAM array 180 has a number of rows "M" and a number of columns "N". The notation "190 00 " refers to a memory cell 190 located in row "0", column 1700. Similarly, the notation "190 MN " refers to a memory cell 190 located in row "M", column 170 N ".

[0028] In some embodiments, the memory cells 190 can have a six-transistor ("6T") circuit topology. Figure 2 is an illustration of an example 6T circuit topology for a memory cell 190. The 6T circuit topology includes n-type field effect transistor (NFET) pass devices 220 and 230, NFET pull-down devices 240 and 250, and p-type FET (PFET) pull-up devices 260 and 270. The FET devices (e.g., NFET devices and PFET devices) can be planar metal-oxide semiconductor FETs, finFETs, all-around gate FETs, any suitable FET, or combinations thereof. Other memory cell topologies, such as four-transistor ("4T"), eight-transistor ("8T"), and ten-transistor ("10T") circuit topologies, are within the spirit and scope of this disclosure.

[0029] Voltage-controlled NFET devices 220 and 230 from word line driver 130 transfer voltage from bit line pair BL / BLB to a bistable flip-flop structure formed by NFET devices 240 and 250 and PFET devices 260 and 270. The bit line pair BL / BLB voltage can be used during memory read and write operations. During a memory read operation, the voltage applied by word line driver 130 to the gate terminals of NFET transfer devices 220 and 230 can be at a sufficient voltage level to transfer the voltage stored in the bistable flip-flop structure to BL and BLB. For example, if a "1" or logic high value (e.g., a supply voltage, such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage) is transferred to BL and a "0" or logic low value (e.g., ground or 0V) is transferred to BLB, the read / write circuitry 160 can sense (or read) these values. During a memory write operation, if BL is "1" or a logic high value and BLB is "0" or a logic low value, the voltage applied by word line driver 130 to the gate terminals of NFET transmission devices 220 and 230 can be at a sufficient voltage level to transfer the logic high value of BL and the logic low value of BLB to the bistable flip-flop structure. As a result, these logic values ​​are written (or programmed) into the bistable flip-flop structure.

[0030] In some embodiments, such as Figure 1 As shown, the precharge circuit 110 is located adjacent to the upper portion of the SRAM array 180. The adjacent location of the precharge circuit 110 can be other locations on the SRAM device 100, such as adjacent to the lower portion of the SRAM array 180. In some embodiments, the precharge circuit 110 includes columns 1700-170, respectively connected to memory cells. N Multiple pre-charge units 1150-115 N Before performing memory read and / or memory write operations, the precharge units 1150-115... N Columns 1700-170 of the memory cells N Each memory cell 190 in the memory cell has its bit line pairs BL / BLB charged to a reference voltage, such as a power supply voltage (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V and other suitable voltages).

[0031] Figure 3 This is an illustration of a pre-charge unit 315 according to some embodiments. In some embodiments, Figure 1 Pre-charge unit 1150-115 N Each can have the same circuit topology as the pre-charge unit 315. For the purposes of simplification and explanation,Figure 3 A pre-charge unit 315 is shown coupled to one memory cell 190. Based on the description herein, the pre-charge unit 315 can be coupled to more than one memory cell 190, such as the memory cells 190 in column “0” of the SRAM array 180 00 -190 M0 For simplicity, other elements of the SRAM device 100 are not shown in Figure 3 FIG. 1.

[0032] According to some embodiments, the pre-charge unit 315 charges the bit line pair BL / BLB of one or more memory cells to a first reference voltage 314, such as a supply voltage (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage) prior to a memory read operation and / or a memory write operation. In some embodiments, the pre-charge unit 315 includes a PFET device 302, an NFET device 304, a PFET pass device 306, a PFET device 308, an NFET device 310, and a PFET pass device 312. The FET devices (e.g., NFET devices and PFET devices) can be planar metal oxide semiconductor FETs, finFETs, all-around gate FETs, any suitable FET, or a combination thereof.

[0033] The PFET device 302 includes a gate terminal, a first source / drain (S / D) terminal, and a second S / D terminal. The gate terminal of the PFET device 302 is electrically coupled to a control signal 320 (e.g., an enable signal). The control signal 320 can be generated (not shown) by a control circuit in the pre-charge circuit 110 of FIG. 1. If the control signal 320 is “0” or a logic low value (e.g., ground or 0V), the PFET device 302 can be “on.” The first S / D terminal of the PFET device 302 is electrically coupled (e.g., directly connected) to the first reference voltage 314. The second S / D terminal of the PFET device 302 is connected to the second S / D terminal of the NFET device 304 and the second S / D terminal of one PFET pass device 306. Figure 1

[0034] ​The NFET device 304 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET device 304 is electrically coupled to the control signal 320. The NFET device 304 can be“turned on” if the control signal 320 is a“1” or a logic high value (e.g., a supply voltage such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage). The first S / D terminal of the NFET device 304 is electrically coupled (e.g., directly connected) to the second reference voltage 316, such as ground or 0V. The second S / D terminal of the NFET device 304 is connected to the second S / D terminal of the PFET device 302 and the second S / D terminal of the PFET pass device 306.

[0035] The PFET pass device 306 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the PFET pass device 306 is electrically coupled to the control signal 320. The PFET pass device 306 can be“turned on” if the control signal 320 is a“0” or a logic low value. The first S / D terminal of the PFET pass device 306 is electrically coupled (e.g., directly connected) to the BL of the memory cell 190. The second S / D terminal of the PFET pass device 306 is connected to the second S / D terminal of the PFET device 302 and the second S / D terminal of the NFET device 304.

[0036] The PFET device 308 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the PFET device 308 is electrically coupled to the control signal 320. The PFET device 308 can be“turned on” if the control signal 320 is a“0” or a logic low value. The first S / D terminal of the PFET device 308 is electrically coupled (e.g., directly connected) to the first reference voltage 314. The second S / D terminal of the PFET device 308 is connected to the second S / D terminal of the NFET device 310 and the second S / D terminal of the PFET pass device 312.

[0037] The NFET device 310 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET device 310 is electrically coupled to the control signal 320. The NFET device 310 can be“turned on” if the control signal 320 is a“1” or a logic high value. The first S / D terminal of the NFET device 310 is electrically coupled (e.g., directly connected) to the second reference voltage 316. The second S / D terminal of the NFET device 310 is connected to the second terminal of the PFET device 308 and the second S / D terminal of the PFET pass device 312.

[0038] PFET pass device 312 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of PFET device 312 is electrically coupled to control signal 320. PFET pass device 312 can be“turned on” if control signal 320 is“0” or a logical low value. The first S / D terminal of PFET pass device 312 is electrically coupled (e.g., directly connected) to BLB of memory cell 190. The second S / D terminal of PFET pass device 312 is connected to the second S / D terminal of PFET device 308 and the second S / D terminal of NFET device 310.

[0039] During operation, if control signal 320 is“0” or a logical low value, PFET devices 302 and 308 and PFET pass devices 306 and 312 are turned on, while NFET devices 304 and 310 are turned off. As a result, precharge unit 315 transfers first reference voltage 314 to bit line pair BL / BLB of memory cell 190, thereby charging bit line pair BL / BLB to a voltage level at or near first reference voltage 314. If control signal 320 is“1” or a logical high value, PFET devices 302 and 308 and PFET pass devices 306 and 312 are turned off, while NFET devices 304 and 310 are turned on. As a result, precharge unit 315 does not transfer first reference voltage 314 to bit line pair BL / BLB of memory cell 190, and sets an internal node (the internal node connecting the second S / D terminals of PFET device 302, PFET device 304, and PFET pass device 306). PFET pass device 306 and another internal node connecting the second S / D terminals of PFET device 308, PFET device 310, and PFET pass device 312 - second reference voltage 316 (e.g., ground or 0 V).

[0040] Figure 4A and Figure 4B are illustrations of a precharge unit 415 and associated layout, respectively, in accordance with some embodiments. In some embodiments, precharge unit 415 can be coupled to one or more memory cells, such as memory cells 190 in the“0” column of SRAM array 180 Figure 1 Precharge units 1150-115 N may each have the same circuit topology as precharge unit 415. In some embodiments, precharge unit 415 can be coupled to one or more memory cells, such as memory cells 190 in the“0” column of SRAM array 180 00 -190 M0 .

[0041] According to some embodiments, prior to a memory read operation and / or a memory write operation, a precharge unit 415 charges the bit line pairs BL / BLB of one or more memory cells to a first reference voltage 314, such as a power supply voltage (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage). In some embodiments, the precharge unit 415 includes a PFET device 302, a PFET transfer device 306, a PFET device 308, and a PFET transfer device 312.

[0042] refer to Figure 4A The PFET device 302 is included in the circuit. The gate terminal of the PFET device 302 is electrically coupled to the control signal 320. If the control signal 320 is "0" or a logic low value, the PFET device 302 can be "turned on". The first S / D terminal of the PFET device 302 is electrically coupled (e.g., directly connected) to the first reference voltage 314, and the second S / D terminal of the PFET device 302 is connected to the second S / D terminal of the PFET transmission device 306.

[0043] Referring to PFET transfer device 306, the gate terminal of PFET device 306 is electrically coupled to control signal 320. If control signal 320 is "0" or a logic low value, PFET transfer device 306 can be "turned on". The first S / D terminal of PFET transfer device 306 is electrically coupled (e.g., directly connected) to BL of memory cell (e.g., memory cell 190). The second S / D terminal of PFET transfer device 306 is connected to the second S / D terminal of PFET device 302.

[0044] Referring to PFET device 308, the gate of PFET device 308 is electrically coupled to control signal 320. If control signal 320 is "0" or a logic low value, PFET device 308 can be "turned on". The first S / D terminal of PFET device 308 is electrically coupled (e.g., directly connected) to a first reference voltage 314. The second S / D terminal of PFET device 308 is connected to the second S / D terminal of PFET transfer device 312.

[0045] Referring to PFET transfer device 312, the gate terminal of PFET device 312 is electrically coupled to control signal 320. If control signal 320 is "0" or a logic low value, PFET transfer device 312 can be "turned on". The first S / D terminal of PFET transfer device 312 is electrically coupled (e.g., directly connected) to the BLB of memory cell (e.g., memory cell 190). The second S / D terminal of PFET transfer device 312 is connected to the second S / D terminal of PFET device 308.

[0046] During operation, if the control signal 320 is a "0" or a logical low value, the PFET devices 302 and 308 and the PFET pass devices 306 and 312 are "turned on." As a result, the pre-charge unit 415 transfers the first reference voltage 314 to the bit line pair BL / BLB of the memory cell, thereby charging the bit line pair BL / BLB to a voltage level at or near the first reference voltage 314. If the control signal 320 is a "1" or a logical high value, the PFET devices 302 and 308 and the PFET pass devices 306 and 312 are "turned off." As a result, the pre-charge unit 415 does not transfer the first reference voltage 314 to the bit line pair BL / BLB of the memory cell. In some embodiments, compared to the pre-charge unit 315 of Figure 3 the pre-charge unit 415 can have lower power consumption than the pre-charge unit 315 because the NFET devices connected to the second reference voltage 316 do not draw current when the control signal 320 is toggled between "0" and "1."

[0047] Referring to Figure 4B FIG. 4B, a layout 420 of the pre-charge unit 415 and a related layout legend 430 are shown in accordance with some embodiments. In some embodiments, the layout legend 430 identifies various layers of the pre-charge unit 415 and includes the following layers: prBndry (cell boundary layer); NW (N-well layer); OD (gate oxide and diffusion layer); MD (interconnect layer between OD and VD); PO (poly layer); VD (via layer on MD); VD2 (via layer 2 on MD); VG (via layer on gate); M0 (metal 0 layer); CM0A (cut metal 0 color A layer); CM0B (cut metal 0 color B layer); and CMD (cut MD layer).

[0048] Layout 420 is covered by FET devices of pre-charge unit 415: PFET device 302, PFET pass device 306, PFET device 308, and PFET pass device 312. In layout 420, according to some embodiments, control signal 320 is connected through a polysilicon layer (PO layer) to the gate terminal of all PFET devices. Further, in some embodiments, a cut metal line (e.g., cut MD) is between BL and BLB to provide first reference voltage 314 (e.g., a supply voltage, such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage) transmission to the S / D terminals of PFET devices 302 and 308. Further, according to some embodiments, since a single reference voltage (e.g., first reference voltage 314) is provided for pre-charge unit 415, layout 420 does not include multiple metal lines to provide other reference voltages (e.g., ground or 0V).

[0049] Figure 5A and Figure 5B are illustrations of a pre-charge unit 515 and associated layout, respectively, according to some embodiments. In some embodiments, pre-charge unit 515 can be coupled to one or more memory cells, such as memory cells 190 in the “0” column of SRAM array 180 Figure 1 Pre-charge units 1150-115 N may each have the same circuit topology as pre-charge unit 515. In some embodiments, pre-charge unit 515 can be coupled to one or more memory cells, such as memory cells 190 in the “0” column of SRAM array 180 00 -190 M0 .

[0050] According to some embodiments, prior to a memory read operation and / or a memory write operation, pre-charge unit 515 charges bit line pair BL / BLB of one or more memory cells to first reference voltage 314, such as a supply voltage (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage). In some embodiments, pre-charge unit 515 includes PFET device 302 and PFET device 308.

[0051] Referring to PFET device 302 in Figure 5A , the gate terminal of PFET device 302 is electrically coupled to control signal 320. If control signal 320 is “0” or a logic low value, PFET device 302 can be “on”. The first S / D terminal of PFET device 302 is electrically coupled (e.g., directly connected) to first reference voltage 314. The second S / D terminal of PFET device 302 is connected to BL of a memory cell (e.g., memory cell 190).

[0052] Referring to PFET device 308, the gate terminal of PFET device 308 is electrically coupled to control signal 320. If control signal 320 is a “0” or logical low value, PFET device 308 can be “turned on.” The first S / D terminal of PFET device 308 is electrically coupled (e.g., directly connected) to first reference voltage 314. The second S / D terminal of PFET device 308 is connected to the BLB of a memory cell (e.g., memory cell 190).

[0053] During operation, if control signal 320 is a “0” or logical low value, PFET devices 302 and 308 are “turned on.” As a result, pre-charge unit 515 transmits first reference voltage 314 to the bit line pair BL / BLB of a memory cell, thereby charging the bit line pair BL / BLB to a voltage level at or near first reference voltage 314. If control signal 320 is a “1” or logical high value, PFET devices 302 and 308 are “turned off.” As a result, pre-charge unit 515 does not transmit first reference voltage 314 to the bit line pair BL / BLB of a memory cell. In some embodiments, in comparison to pre-charge unit 315 of Figure 3

[0054] Referring to Figure 5B According to some embodiments, a layout 520 of pre-charge unit 515 and a related layout legend 530 are shown. In some embodiments, layout legend 530 identifies various layers of pre-charge unit 515 and includes the following layers: prBndry (cell boundary layer); NW (N-well layer); OD (gate oxide and diffusion layer); MD (interconnect layer between OD and VD); PO (poly layer); VD (via layer on MD); VD2 (via layer 2 on MD); VG (via layer on gate); M0 (metal 0 layer); CM0A (cut metal 0 color A layer); and CM0B (cut metal 0 color B layer).

[0055] ​Layout 520 is covered by FET devices of precharge unit 515: PFET devices 302 and 308. According to some embodiments, in layout 520, control signal 320 is connected to gate terminals of all PFET devices through a polysilicon layer (PO layer). According to some embodiments, because a single reference voltage (e.g., first reference voltage 314) is provided to precharge unit 515, layout 520 does not include multiple metal lines that provide other reference voltages (e.g., ground or 0V). In some embodiments, compared to precharge unit 415 of Figure 4B Layout of precharge unit 515 can be smaller than precharge unit 415 because precharge unit 515 does not include PFET pass devices (e.g., PFET pass devices 306 and 312).

[0056] Figure 6 is an illustration of a precharge unit 615 according to some embodiments. In some embodiments, precharge unit 615 can be coupled to one or more memory cells, such as cells 190 in the “0” column of SRAM memory array 180 Figure 1 Precharge unit 1150-115 N may each have the same circuit topology as precharge unit 615. In some embodiments, precharge unit 415 can be coupled to one or more memory cells, such as cells 190 in the “0” column of SRAM memory array 180 00 -190 M0 .

[0057] According to some embodiments, prior to a memory read operation and / or a memory write operation, precharge unit 615 charges bit lines pair BL / BLB of one or more memory cells to first reference voltage 314, e.g., a power supply voltage (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage). In some embodiments, precharge unit 615 includes NFET device 602, NFET pass device 606, NFET device 608, and NFET pass device 612. The NFET devices can be planar metal oxide semiconductor FETs, finFETs, all-around gate FETs, any suitable FET, or combinations thereof.

[0058] NFET device 602 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of NFET device 602 is electrically coupled to control signal 620 (e.g., an enable signal). Control signal 620 can be provided by a memory controller (e.g., memory controller 110 of FIG. 1) or any other suitable device. In some embodiments, control signal 620 is a high voltage signal (e.g., 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage). Figure 1The control circuit (not shown) in the pre-charge circuit 110 generates the control signal 620. If the control signal 620 is a “1” or a logic high value, the NFET device 602 can be “on.” In some embodiments, the voltage level of the “1” or logic high value can be at a voltage level higher than the first reference voltage 314, such that a voltage at or near the first reference voltage 314 is transmitted from the first S / D terminal of the NFET device 602 to the second S / D terminal of the NFET device 602. The first S / D terminal of the NFET device 602 is electrically coupled (e.g., directly connected) to the first reference voltage 314. The second S / D terminal of the NFET device 602 is connected to the second S / D terminal of the NFET pass device 606.

[0059] The NFET pass device 606 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET pass device 606 is electrically coupled to the control signal 620. If the control signal 620 is a “1” or a logic high value (e.g., a voltage level higher than the first reference voltage 314, such that a voltage at or near the reference voltage 314 is transmitted from the second S / D terminal of the NFET pass device 606 to the first S / D terminal of the NFET pass device 606), the NFET pass device 606 can be “on.” The first S / D terminal of the NFET pass device 602 is electrically coupled (e.g., directly connected) to the BL of a memory cell (e.g., the memory cell 190). The second S / D terminal of the NFET pass device 606 is connected to the second S / D terminal of the NFET device 602.

[0060] The NFET device 608 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET device 608 is electrically coupled to the control signal 620. If the control signal 620 is a “1” or a logic high value (e.g., a voltage level higher than the first reference voltage 314, such that a voltage at or near the reference voltage 314 is transmitted from the first S / D terminal of the NFET device 608 to the second S / D terminal of the NFET device 608), the NFET device 608 can be “on.” The first S / D terminal of the NFET device 608 is electrically coupled (e.g., directly connected) to the first reference voltage 314. The second S / D terminal of the NFET device 608 is connected to the second S / D terminal of the NFET pass device 612.

[0061] The NFET pass device 612 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET device 612 is electrically coupled to the control signal 620. The NFET pass device 612 can be“turned on” if the control signal 620 is a“1” or a logic high value (e.g., a voltage level higher than the first reference voltage 314 such that a voltage at or near the reference voltage 314 is transferred from the second S / D terminal of the NFET pass device 612 to the first S / D terminal of the NFET pass device 612). The first S / D terminal of the NFET pass device 612 is electrically coupled (e.g., directly connected) to the BLB of a memory cell (e.g., the memory cell 190). The second S / D terminal of the NFET pass device 612 is connected to the second S / D terminal of the NFET device 608.

[0062] During operation, the NFET devices 602 and 608 and the NFET pass devices 606 and 612 are“turned on” if the control signal 620 is a“1” or a logic high value (e.g., a voltage level higher than the first reference voltage 314, such as a voltage level higher than the first reference voltage 314 such that a voltage at or near the reference voltage 314 is transferred from the first S / D terminals of the NFET devices 602 and 608 to the first S / D terminals of the NFET pass devices 606 and 612). As a result, the precharge unit 615 transfers the first reference voltage 314 to the bit line pair BL / BLB of the memory cell, thereby charging the bit line pair BL / BLB to a voltage level at or near the first reference voltage 314. The NFET devices 602 and 608 and the NFET pass devices 606 and 612 are“turned off” if the control signal 620 is a“0” or a logic low value (e.g., ground or 0 V). As a result, the precharge unit 615 does not transfer the first reference voltage 314 to the bit line pair BL / BLB of the memory cell. In some embodiments, the precharge unit 615 can have lower power consumption than the precharge unit 315 of Figure 3 As compared to the precharge unit 315 of

[0063] Figure 7 is a diagram of a precharge unit 715 in accordance with some embodiments. In some embodiments, the precharge unit 715 can be coupled to one or more memory cells, such as the memory cells 190 in column“0” of the SRAM array 180 Figure 1 the precharge unit 1150-115 N may each have the same circuit topology as the precharge unit 715. In some embodiments, the precharge unit 715 can be coupled to one or more memory cells, such as the memory cells 190 in column“0” of the SRAM array 18000 -190 M0 .

[0064] According to some embodiments, prior to a memory read operation and / or a memory write operation, the pre-charge unit 715 charges the bit line pair BL / BLB of one or more memory cells to a first reference voltage 314, such as a supply voltage (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage). In some embodiments, the pre-charge unit 715 includes the NFET device 602 and the NFET device 608.

[0065] Referring to the NFET device 602, the gate terminal of the NFET device 602 is electrically coupled to the control signal 620. If the control signal 620 is a “1” or a logic high value (e.g., a voltage level higher than the first reference voltage 314 such that a voltage at or near the first reference voltage 314 is transmitted from the first S / D terminal of the NFET device 602 to the second S / D terminal of the NFET device 602), the NFET device 602 can be “turned on.” The first S / D terminal of the NFET device 602 is electrically coupled (e.g., directly connected) to the first reference voltage 314. The second S / D terminal of the NFET device 602 is connected to the BL of a memory cell (e.g., the memory cell 190).

[0066] Referring to the NFET device 608, the gate terminal of the NFET device is electrically coupled to the control signal 620. If the control signal 620 is a “1” or a logic high value (e.g., a voltage level higher than the first reference voltage 314 such that a voltage at or near the first reference voltage 314 is transmitted from the first S / D terminal of the NFET device 608 to the second S / D terminal of the NFET device 608), the NFET device 608 can be “turned on.” The first S / D terminal of the NFET device 608 is electrically coupled (e.g., directly connected) to the first reference voltage 314. The second S / D terminal of the NFET device 608 is connected to the BLB of a memory cell (e.g., the memory cell 190).

[0067] During operation, if control signal 620 is "1" or a logic high value (e.g., a voltage level higher than the first reference voltage 314, such that a voltage at or near the first reference voltage 314 is transferred from the first S / D terminals of NFET devices 602 and 608 to the second S / D terminals of NFET devices 602 and 618), then NFET devices 602 and 608 are "turned on". As a result, precharge unit 715 transfers the first reference voltage 314 to the bit line pair BL / BLB of the memory cell, thereby charging the bit line pair BL / BLB to a voltage level at or near the first reference voltage 314. If control signal 620 is "0" or a logic low value (e.g., ground or 0V), then NFET devices 602 and 608 are "turned off". As a result, precharge unit 715 does not transfer the first reference voltage 314 to the bit line pair BL / BLB of the memory cell. In some embodiments, with Figure 3 Compared to the precharge unit 315, and because the precharge unit 715 does not include an NFET device connected to the second reference voltage 316 (e.g., ground or 0V) for on / off switching, the precharge unit 715 can have lower power consumption than the precharge unit 315 because the NFET device connected to the second reference voltage 316 does not draw current when the control signal 620 switches between "0" and "1". Furthermore, compared to... Figure 6 Compared to the precharge unit 615, since the precharge unit 715 does not include NFET transmission devices (e.g., NFET transmission devices 606 and 612), the layout of the precharge unit 715 can be smaller than that of the precharge unit 615 according to some embodiments.

[0068] Figure 8 This is an illustration of a precharge circuit architecture 800 having multiple precharge units and write assist units according to some embodiments. The precharge circuit architecture 800 includes a write assist unit 830, a precharge unit 4150, and a precharge unit 4151. (As...) Figure 8 As shown, write assist unit 830 and precharge units 4150 and 4151 can be stacked and coupled to bit line pairs BL / BLB of memory cells (e.g., memory cell 190). In some embodiments, the stacked configuration of write assist unit 830 and precharge units 4150 and 4151 can be coupled to more than one memory cell, such as memory cell 190 in column "0" of SRAM array 180. 00 -190 M0 .

[0069] The write assist unit 830 sets the bit line pair BL / BLB of one or more memory cells to a predetermined voltage to assist a storage write operation. In some embodiments, the predetermined voltage can be a ground or a voltage close to ground or 0V. In some embodiments, the predetermined voltage can be a voltage less than a threshold voltage of NFET devices (e.g., NFET devices 804 and 810 discussed below). In some embodiments, the predetermined voltage can be a voltage lower than ground or 0V. In some embodiments, the write assist unit 830 includes NFET device 804, NFET pass device 806, NFET device 810, and NFET pass device 812. The NFET devices can be planar metal oxide semiconductor FETs, finFETs, all-around gate FETs, any suitable FETs, or combinations thereof.

[0070] The NFET device 804 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET device 804 is electrically coupled (e.g., directly connected) to the BLB of a memory cell (e.g., memory cell 190). The first S / D terminal of the NFET device 804 is electrically coupled to a reference voltage 816, such as ground or 0V and a voltage less than 0V. The second S / D terminal of the NFET device 804 is connected to the second S / D terminal of the NFET pass device 806.

[0071] The NFET pass device 806 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET pass device 806 is electrically connected to a control signal 820 (e.g., an enable signal). The control signal 820 can be generated by a controller (e.g., controller 110) or any suitable device. The first S / D terminal of the NFET pass device 806 is electrically connected to the second S / D terminal of the NFET device 804. The second S / D terminal of the NFET pass device 806 is electrically connected to the first S / D terminal of the NFET device 810. Figure 1The control circuit (not shown) in the pre-charge circuit 110 generates a control signal 820. The NFET pass device 806 can be “on” if the control signal 820 is “1” or a logical high value (e.g., a supply voltage, such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage). In some embodiments, the control signal 820 to the write assist unit 830 can be the same as the control signal 320 to the pre-charge units 4150 and 4151, such that (i) the PFET devices 302 and 308 of the pre-charge units 4150 and 4151 are “off” if the control signal 820 is “1” or a logical high value, and (ii) the PFET devices 302 and 308 of the pre-charge units 4150 and 4151 are “on” and the NFET pass devices 806 and 812 of the write assist unit 830 are “off” if the control signal 820 is “0” or a logical low value (e.g., ground or 0V). The first S / D terminal of the NFET pass device 806 is electrically coupled (e.g., directly connected) to the BL of the memory cell (e.g., memory cell 190). The second S / D terminal of the NFET pass device 806 is connected to the second S / D terminal of the NFET device 804.

[0072] The NFET device 810 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET device 810 is electrically coupled (e.g., directly connected) to the BLB of the memory cell (e.g., memory cell 190). The first S / D terminal of the NFET device 810 is electrically connected to the reference voltage 816. The second S / D terminal of the NFET device 810 is connected to the second S / D terminal of the NFET pass device 812.

[0073] The NFET pass device 812 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET pass device 823 is electrically connected to the control signal 820. The NFET pass device 812 can be “on” if the control signal 820 is “1” or a logical high value. The first S / D terminal of the NFET pass device 812 is electrically coupled (e.g., directly connected) to the BLB of the memory cell (e.g., memory cell 190). The second S / D terminal of the NFET pass device 812 is connected to the second S / D terminal of the NFET device 810.

[0074] The S / D terminal connections with respect to the pre-charge units 4150 and 4151, the PFET device 302, the PFET pass device 306, the PFET device 308, and the PFET pass device 312 are the same as described above with respect to the pre-charge units 4100 and 4101, the PFET device 300, the PFET pass device 304, the PFET device 306, and the PFET pass device 310, respectively. Figure 4AThe connections are the same as described above. In some embodiments, the gate terminals of PFET device 302, PFET pass device 306, PFET device 308, and PFET pass device 312 are connected with Figure 4A The connections are different as shown. For example, the gate terminals of PFET devices 302 and 308 are electrically coupled to control signal 820. In addition, in some embodiments, the gate terminals of PFET pass devices 306 and 312 are connected to nodes 805 and 811, respectively. Referring to Figure 8 , node 805 is a circuit node electrically connected to the second S / D terminals of NFET device 804 and NFET pass device 806. Node 811 is a circuit node electrically connected to the second S / D terminals of NFET device 810 and NFET pass device 812.

[0075] During operation, if control signal 820 is a “1” or a logical high value, then NFET pass devices 806 and 812 in write assist unit 830 are “on” and PFET devices 302 and 308 in pre-charge units 4150 and 4151 are “off”. If the voltage level on bit line pair BL / BLB is at a voltage level sufficient to turn on NFET devices 804 and 810 in write assist unit 830 (e.g., the gate-source voltage of NFET devices 804 and 810 is above the threshold voltage of NFET devices 804 and 810), then the voltage level on bit line pair BL / BLB will be set to a voltage level at or near the voltage level of reference voltage 816 (e.g., ground or 0V or a voltage less than 0V) or a voltage level less than the threshold voltage of NFET devices 804 and 810. If control signal 820 is a “0” or a logical low value, then NFET pass devices 806 and 812 in write assist unit 830 are “off” and PFET devices 302 and 308 in pre-charge units 4150 and 4151 are “on”. If the voltage levels at nodes 805 and 811 are sufficient to turn on PFET pass devices 306 and 312 in pre-charge units 4150 and 4151 (e.g., the gate-source voltage of PFET pass devices 306 and 312 is less than the threshold voltage of PFET pass devices 306 and 312), then the voltage level on bit line pair BL / BLB will be set to a voltage level at or near the voltage level of first reference voltage 314.

[0076] The pre-charge circuit architecture is not limited to Figure 8 the stack configuration of one write assist unit and two pre-charge units as shown. In some embodiments, the pre-charge circuit architecture can include multiple pre-charge units and multiple write assist units to pre-charge one or more memory cells (e.g., memory cells 190 in column “0” of SRAM array 180 00 -190M0 It provides adjustable precharge and write assist strength. Figure 9 This is an illustration of a precharge circuit architecture 900 having multiple precharge units and multiple write assist units according to some embodiments. The precharge circuit architecture 900 includes write assist unit 8300, write assist unit 8301, precharge unit 4150, and precharge unit 4151. (As...) Figure 9 As shown, write auxiliary units 8300 and 8301 and precharge units 4150 and 4151 can be arranged in a stacked configuration and coupled to bit line pairs BL / BLB of memory cells (e.g., memory cell 190). In some embodiments, the stacked configuration of write auxiliary units 8300 and 8301 and precharge units 4150 and 4151 can be coupled to more than one memory cell, such as memory cell 190 in column "0" of SRAM array 180. 00 -190 M0 The gate and S / D terminals in the write auxiliary units 8300 and 8301 and the precharge units 4150 and 4151 are connected to the above-mentioned... Figure 8 The connections described are similar.

[0077] Furthermore, the pre-charge circuit architecture is not limited to Figure 8 The pre-charging unit is shown. In some embodiments, other pre-charging units may be used, such as those described above. Figure 3 , Figure 5A , Figure 6 and Figure 7 The pre-charge units 315, 515, 615, and 715 are described. For example, Figure 10 This is an illustration of a precharge circuit architecture 1000 having multiple precharge units 515 and multiple write assist units 830 according to some embodiments. The precharge circuit architecture 1000 includes write assist units 8300, write assist units 8301, precharge units 5150 and 5151.

[0078] The S / D terminal connections of reference precharge units 5150 and 5151, and PFET devices 302 and 308 are related to the above. Figure 5A The same as described. In some embodiments, the gate terminals of PFET devices 302 and 308 are connected to... Figure 5AThe connections are shown differently. In some embodiments, the gate terminals of the PFET devices 302 and 308 are electrically coupled to a control signal 820. During operation, if the control signal 820 is a “1” or a logical high value, the NFET pass devices 806 and 812 in the write assist unit 830 are “on,” and the PFET devices 302 and 308 in the precharge units 5150 and 5151 are “off.” If the voltage level on the bit line pair BL / BLB is a voltage level sufficient to turn the NFET devices 804 and 810 in the write assist unit 830 “on” (e.g., the gate-source voltage of the NFET devices 804 and 810 is above the threshold voltage of the NFET devices 804 and 810), the voltage level on the bit line pair BL / BLB will be set to a voltage level at or near the voltage level of the reference voltage 816 (e.g., ground or 0 V or a voltage less than 0 V) or a voltage level less than the threshold voltage of the NFET devices 804 and 810. If the control signal 820 is a “0” or a logical low value, the NFET pass devices 806 and 812 in the write assist unit 830 are “off,” the PFET devices 302 and 308 in the precharge units 4150 and 4151 are “on,” setting the voltage level on the bit line pair BL / BLB to a voltage level at or near the first reference voltage 314.

[0079] Furthermore, in some embodiments, the precharge unit and the write assist unit can be combined into a single unit. Figure 11A and Figure 11B are illustrations of a combined precharge unit and write assist unit 1100 and an associated layout, respectively, according to some embodiments. The combined precharge unit and write assist unit is also referred to herein as a “combined precharge / write assist unit 1100.” In some embodiments, the combined precharge / write assist unit 1100 can be coupled to one or more memory cells, such as the memory cells 190 in column “0” of the SRAM array 180 00 -190 M0 The combined precharge / write assist unit 1100 includes a PFET device 1102, an NFET device 1104, an NFET pass device 1106, a PFET device 1108, an NFET device 1110, and an NFET pass device 1112. The FET devices (e.g., NFET devices and PFET devices) can be planar metal oxide semiconductor FETs, finFETs, all-around gate FETs, any suitable FET, or combinations thereof.

[0080] The PFET device 1102 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the PFET device 1102 is electrically coupled to a control signal 1120 (e.g., an enable signal). The control signal 1120 can be provided by a controller (e.g., the controller 120) or any suitable component. Figure 1The control circuit in the pre-charge circuit 110 generates (not shown) a control signal 1120. If the control signal 1120 is “0” or a logical low value (e.g., ground or 0 V), then the PFET device 1102 can be “on.” The first S / D terminal of the PFET device 1102 is electrically coupled (e.g., directly connected) to the BL of a memory cell (e.g., memory cell 190). The second S / D terminal of the PFET device 1102 is electrically coupled to a first reference voltage 1114, such as a supply voltage (e.g., 0.4 V, 0.6 V, 0.7 V, 1.0 V, 1.2 V, 1.8 V, 2.4 V, 3.3 V, 5 V, and any other suitable voltage).

[0081] The NFET device 1104 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET device 1104 is electrically coupled (e.g., directly connected) to the BLB of a memory cell (e.g., memory cell 190). The first S / D terminal of the NFET device 1104 is electrically connected to a second reference voltage 1116, e.g., ground or 0 V. The second S / D terminal of the NFET device 1104 is connected to the second S / D terminal of the NFET pass device 1106.

[0082] The NFET pass device 1106 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET pass device 1106 is electrically coupled to the control signal 1120. If the control signal 1120 is “1” or a logical high value (e.g., a supply voltage, such as 0.4 V, 0.6 V, 0.7 V, 1.0 V, 1.2 V, 1.8 V, 2.4 V, 3.3 V, 5 V, and any other suitable voltage), then the NFET pass device 1106 can be “on.” The first S / D terminal of the NFET pass device 1106 is connected to the BL of a memory cell (e.g., memory cell 190). The second S / D terminal of the NFET pass device 1106 is connected to the second S / D terminal of the NFET device 1104.

[0083] The PFET device 1108 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the PFET device 1108 is electrically coupled to the control signal 1120. If the control signal is “0” or a logical low value (e.g., ground or 0 V), then the PFET device 1108 can be “on.” The first S / D terminal of the PFET device 1108 is electrically coupled (e.g., directly connected) to the BLB of a memory cell (e.g., memory cell 190). The second S / D terminal of the PFET device 1108 is electrically coupled to the first reference voltage 1114.

[0084] The NFET device 1110 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET device 1110 is electrically coupled (e.g., directly connected) to the BL of the memory cell (e.g., memory cell 190). The first S / D terminal of the NFET device 1110 is electrically coupled to the second reference voltage 1116. The second S / D terminal of the NFET device 1110 is connected to the second S / D terminal of the NFET pass device 1112.

[0085] The NFET pass device 1112 includes a gate terminal, a first S / D terminal, and a second S / D terminal. The gate terminal of the NFET pass device 1112 is electrically coupled to the control signal 1120. The NFET pass device 1112 can be“turned on” if the control signal 1120 is“1” or a logic high value. The first S / D terminal of the NFET pass device 1112 is connected to the BLB of the memory cell (e.g., memory cell 190). The second S / D terminal of the NFET pass device 1112 is connected to the second S / D terminal of the NFET device 1110.

[0086] During operation, if the control signal 1120 is“1” or a logic high value, the PFET devices 1102 and 1108 are“turned off” and the NFET pass devices 1106 and 1112 are“turned on”. If the voltage level on the bit line pair BL / BLB of the memory cell is a voltage level sufficient to turn on the NFET devices 1104 and 1110 (e.g., the gate-source voltage of the NFET devices 1104 and 1110 is higher than the threshold voltage of the NFET devices 1104 and 1110), the voltage level on the bit line pair BL / BLB will be set to a voltage level at or near the voltage level of the reference voltage 1116 (e.g., ground or 0 V) or less than the threshold voltage of the NFET devices 1104 and 1110. If the control signal 1120 is“0” or a logic low value, the NFET pass devices 1106 and 1112 are“turned off” and the PFET devices 1102 and 1108 are“turned on”. As a result, the first reference voltage 1114 is passed to the bit line pair BL / BLB.

[0087] Reference Figure 11BAccording to some embodiments, a layout 1130 of a combined precharge / write assist unit 1100 and a related layout legend 1130 are shown. In some embodiments, the layout legend 1130 identifies various layers of the combined precharge / write assist unit 1100 and includes the following layers: prBndry (unit boundary layer); NW (N-well layer); OD (gate oxide and diffusion layer); MD (interconnect layer between OD and VD); PO (poly layer); VD (via layer on MD); VD2 (via layer 2 on MD); VG (via layer on gate); M0 (metal 0 layer); CM0A (cut metal 0 color A layer); and CM0B (cut metal 0 color B layer).

[0088] The layout 1130 is covered by FET devices of the combined precharge / write assist unit 1100: PFET devices 1102, NFET devices 1104, NFET pass devices 1106, PFET devices 1108, NFET devices 1110, and NFET pass devices 1112. According to some embodiments, in the layout 1130, the control signal 1120 is connected to the gate terminals of the PFET devices 1102 and 1108 through a poly layer (PO layer). Further, in some embodiments, a cut metal line (e.g., cut MD) is between BL and BLB to provide a first reference voltage 1114 (e.g., a power supply voltage, such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage) to the S / D terminals of the PFET devices 1102 and 1108.

[0089] Figure 12 is an illustration of a memory system 1200 having a precharge unit for each column of memory cells in a memory array, according to some embodiments. The memory system 1200 includes a precharge circuit 1210 and an array of memory cells 1280.

[0090] In some embodiments, the memory cells in the array of memory cells 1280 can be SRAM cells. According to some embodiments, each SRAM cell can have a 6T circuit topology, as shown in Figure 2 Referring to Figure 12 , the array of memory cells 1280 has a number of rows “M” and a number of columns “N”. Similar to the description of the SRAM array 180 Figure 1 , each memory cell 190 in the array of memory cells 1280 can be accessed using a memory address, e.g., for memory read and memory write operations. Based on the memory address, a memory cell (e.g., memory cell 190 00 -190 0N) can be accessed by one of the bit lines BL[0] / BLB[0] - BL[N] / BLB[N] (e.g., memory cells 190 00 - 190 M0 ) of the row.

[0091] In some embodiments, the precharge circuit 1210 includes a row of precharge cells 1215[0] - 1215[N], where the precharge cells 1215 are coupled to a column of memory cells in the memory cell array 1280. For example, as shown in FIG. 12, the precharge cell 1215[0] is coupled to the memory cells 190

[0092] - 190 Figure 12 in column “0” of the memory cell array 1280, and the precharge cell 1215[N] is coupled to the memory cells 190 Figure 3 - 190 Figure 4A in column “N” of the memory cell array 1280. In some embodiments, the precharge cells 1215 can have any one of the precharge cell topologies described herein, such as the precharge cell 315 of Figure 5A , Figure 6 the precharge cell 415 of Figure 7 , the precharge cell 515 of

[0093] , Figure 13 the precharge cell 615 of Figure 8-10 , or the precharge cell 715 of .

[0094] The precharge circuit in a memory system is not limited to a single row of precharge cells. In some embodiments, with reference to Figure 12 , the precharge circuit 1210 includes multiple rows of precharge cells, where multiple precharge cells 1215 are coupled to each column of memory cells in the memory cell array 1280. The multiple precharge cells 1215 coupled to each column of memory cells are arranged in a stacked configuration, such as the stacked configuration of precharge cells shown in Figure 13 . In some embodiments, any number of precharge cells can be arranged in a stacked configuration based on the desired precharge strength for each column of memory cells. Figure 8-10 Figure 8 Furthermore, for each column of memory cells in the memory cell array 1280, the precharge circuit 1210 can include one or more write assist cells (not shown in Figure 9 and Figure 10 ), such as the write assist cell 830 described above with reference to Figure 11A . In some embodiments, the precharge circuit architecture 800 of Figure 11B , the precharge circuit architecture 900 of Figure 12 ,Figure 10 The precharge circuit architecture 1000 and Figure 11A and Figure 11B Each of the combined precharge / write auxiliary units 1100 can be coupled to Figure 12 Each column of memory cells in the memory cell array 1280. In some embodiments, any number of precharge units, write assist units, and combined precharge / write assist units can be arranged in a memory cell based on the desired precharge and write assist strength for each column of the memory cell, wherein the configuration of each stack is coupled to each column of memory cells in the memory cell array 1280.

[0095] In some embodiments, the memory system 1300 includes power supplies 1330 and 1340 respectively provided to the precharge circuit 1210 and the memory cell array 1280. In some embodiments, power supplies 1330 and 1340 may be one or more of 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable power supply voltage. According to some embodiments, power supply 1330 may provide power voltages to the precharge cells and / or write auxiliary cells in the precharge circuit 1210 (e.g., ...). Figure 3 , Figure 4A , Figure 5A and Figure 6-10 The first reference voltage 314 and Figure 11A The first reference voltage 1114 in the memory can be kept "on" to reduce pre-charge time. According to some embodiments, the power supply 1340 can be switched to "on" and "off" depending on the activation state of the memory cells to reduce power consumption. For example, if one or more memory cells 190 are active (e.g., one or more memory cells undergo a memory read operation or a memory write operation), the power supply 1340 can be turned on for one or more memory cells 190. Conversely, if one or more memory cells 190 are inactive (e.g., one or more memory cells do not undergo a memory read operation or a memory write operation), the power supply 1340 can be "off" for one or more memory cells 190.

[0096] Figure 14 This is an illustration of an example waveform 1400 associated with the operation of a memory system having a pre-charge circuit according to some embodiments. For illustrative purposes, memory system 1200 will be used to facilitate the description of waveform 1400. Waveform 1400 is also applicable to other memory systems, such as Figure 1 SRAM device 100 and Figure 13 The memory systems 1300 are within the spirit and scope of this disclosure.

[0097] At time tO, the memory system 1200 is in a standby state. The control signal CTRL[0] activates the pre-charge unit 1215[0] of the memory cell 190 00 - 190 M0 The pre-charge unit 1215[N] of column “N”, and the memory cell 190 0N - 190 MN The pre-charge unit 1215[N] of column “N”, and the memory cell 190 00 - 190 0N The word line signal (WL[0]) of row “0” of the memory cell 190 is deactivated (or turned off). In some embodiments, the control signal CTRL[0] and the control signal CTRL[N] are low-active signals, meaning that a logic low value (e.g., ground or OV) activates the pre-charge unit 1215[0] and the pre-charge unit 1215[N], respectively, and a logic high value (e.g., a supply voltage) deactivates the pre-charge units. According to some embodiments, the voltages on the bit line pairs BL / BLB of columns “0” and “N” are initialized to a predetermined voltage, such as a supply voltage (e.g., Figure 3 the first reference voltage 314 of the memory cell 190, and Figure 11A the first reference voltage 1114 of the memory cell 190).

[0098] Although two columns of memory cells (column “0” and “N”) are described with respect to the waveform 1400, the voltages on the bit line pairs BL / BLB of other columns of memory cells (columns “1” through “N-1”) follow the same or similar voltage characteristics as the bit line pairs BL / BLB of column “N”. Furthermore, although two pre-charge units (pre-charge units 1215[0] and 1215[N]) are described with respect to the waveform 1400, the control signals (corresponding to control signal CTRL[1] - control signal CTRL[N-1], respectively) of other pre-charge units 1215[1] through 1215[N-1] follow the same waveform pattern as the control signal CTRL[N]. With respect to the word line signals of rows “1” through “M-1”, these word line signals are deactivated (or turned off).

[0099] At time tl, the memory system 1200 transitions to a memory operation state, e.g., a read operation or a write operation. The control signal CTRL[0] and the control signal CTRL[N] remain in the off state; thus, the pre-charge unit 1215[0] and the pre-charge unit 1215[N] remain deactivated (or remain turned off). At this time, the word line signal WL[0] is activated, e.g., transitions from a logic low value to a logic high value. Although not shown in the waveform 1400, column “0” is decoded by a column decoder (e.g., Figure 1The column decoder 140 is activated (or selected). Since row "0" and column "0" are activated (or selected), this is possible in memory cell 190. 00 Memory operations (e.g., memory read or memory write operations) are performed at this location. Subsequently, memory cell 190... 00 BL[0] / BLB[0] can be converted. For example, as shown in waveform 1400, bit line BL[0] can be converted from a logic high value to a logic low value. Furthermore, although bit line BLB[0] is the complement of BL[0], the voltage level on bit line BLB[0] may not remain at the ideal logic high voltage level (e.g., the supply voltage) due to the PFET pull-up devices in the SRAM cell (e.g., ...). Figure 2 The strength of the transmission logic high voltage level of the PFET pull-up devices 260 and 270. Therefore, as shown in waveform 1400, at time t1, the voltage level on bit line BLB[0] decreases. In addition, regarding bit line pair BL[N] / BLB[N], due to the parasitic coupling effect that may occur when bit line BL[0] transitions from a logic high value to a logic low value, the voltage level on this bit line pair may also decrease at time t1.

[0100] At time t2, after the memory operation is completed, the memory system 1200 is in a precharge operation state. The word line signal WL[0] is deactivated, for example, changed from a logic high value to a logic low value. At this time, the control signal CTRL[0] and the control signal CTRL[N] are activated; therefore, the precharge unit 1215[0] and the precharge unit 1215[N] are activated (or turned on). As a result, according to some embodiments, the bit line pairs BL[0] / BLB[0] and BL[N] / BLB[N] are charged to a predetermined voltage, such as the power supply voltage (e.g., Figure 3 The first reference voltage 314 and Figure 11A The first reference voltage is 1114).

[0101] At time t3, the memory system 1200 is in a standby state, for example, similar to the state at time t0. Control signals CTRL[0] and CTRL[N] are deactivated; therefore, precharge units 1215[0] and 1215[N] are deactivated (or "turned off"). At this time, bit line pairs BL[0] / BLB[0] and BL[N] / BLB[N] are precharged to a predetermined voltage, and another memory operation, such as a memory read operation and a memory write operation, can be performed. For multiple memory read operations and / or multiple memory write operations, the above cycle (e.g., the operation at times t0 to t3) can be repeated.

[0102] The various embodiments of the precharge unit described herein can have different performance characteristics. For example, for a given memory array architecture, a combined precharge / write assist unit (e.g., the combined precharge / write assist unit 1100 of Figure 11A and Figure 11B The combined precharge / write assist unit 1100 can charge the bit line pair BL / BLB for a column of memory cells faster than the precharge circuit architecture with a write assist unit and a precharge unit in a stacked configuration (e.g., the precharge circuit architecture 800 of Figure 8 the precharge circuit architecture 900 of Figure 9 and the circuit architecture 1000 of Figure 10 In addition, certain stacked configurations can have different performance characteristics than other stacked configurations. For example, a stacked configuration with the write assist unit 830 and the precharge unit 515 can charge the bit line pair BL / BLB for a column of memory cells faster than a stacked configuration with the write assist unit 830 and the precharge unit 415.

[0103] Figure 15 is an illustration of a method 1500 for a precharge operation performed on a memory system in accordance with some embodiments. The method 1500 is applicable to the precharge unit embodiments described herein. For illustrative purposes, the operations of the method 1500 will be described with reference to the memory system 1200 of Figure 12 In some embodiments, the operations can be performed with other precharge circuit architectures, such as the SRAM device 100 of Figure 1 and the memory system 1300 of Figure 13 In some embodiments, the operations can be performed in a different order, or not at all, depending on the particular application.

[0104] In operation 1510, a memory cell in a memory cell array is selected to perform a memory operation using a first terminal and a second terminal of the memory cell. In some embodiments, the memory cell 190 can be selected using a word line and a column from the memory array 1280 of the memory system 1200. In some embodiments, the memory operation can be a memory read operation or a memory write operation. The first terminal and the second terminal of the memory cell can be a bit line pair BL / BLB of the memory cell. An example of operation 1510 is the memory operation (e.g., a memory read operation or a memory write operation) performed in the waveform 1400 at time tl of Figure 14

[0105] ​In operation 1520, a pre-charge unit is activated to charge the first and second terminals of the memory cell to a reference voltage (e.g., a power supply voltage, such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage) while the memory cell is deselected. In some embodiments, the reference Figure 12 voltage can be a power supply voltage, such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage. In some embodiments, the second control signal can be a control signal CTRL[0] that activates a pre-charge unit 1215[0] for column “0” of the memory cells 190 00 -190 M0 The pre-charge unit can include a transistor having a gate terminal, a first source / drain (S / D) terminal coupled to a reference voltage, and a second S / D terminal coupled to the first or second terminal of the memory cell, where the transistor is configured to transfer the reference voltage from the first S / D terminal to the second S / D terminal in response to a second control signal applied to the gate terminal. An example of the memory operation 1520 is a memory system operation performed at time t2 with the waveform 1400 of Figure 14

[0106] In operation 1530, after the first and second terminals of the memory cell have been charged to the reference voltage, the pre-charge unit is deactivated. An example of the memory operation 1530 is a memory system operation performed at time t3 with the waveform 1400 of Figure 14

[0107] Embodiments of the present disclosure describe a memory system having a pre-charge circuit configured to charge a bit line pair BL / BLB. In some embodiments, the pre-charge circuit includes a pre-charge unit, where each pre-charge unit can be coupled to a column of memory cells in a memory cell array. Depending on the desired pre-charge strength, multiple pre-charge units can be arranged in a stacked configuration. Additionally, in some embodiments, a write assist unit can be coupled to one or more pre-charge units in a stacked configuration. And depending on the desired write assist strength, multiple write assist units can be coupled to one or more pre-charge units in a stacked configuration. In some embodiments, a combined pre-charge unit and write assist unit can be implemented to provide write assist and pre-charge functionality.

[0108] ​​A memory device of embodiments of the present disclosure includes a memory device having a memory cell, a first transistor, and a second transistor. The memory cell includes a first terminal and a second terminal. The first transistor includes a first gate terminal, a first S / D terminal coupled to a reference voltage, and a second S / D terminal coupled to the first terminal of the memory cell. The first transistor is configured to transfer the reference voltage from the first S / D terminal to the second S / D terminal in response to applying a control signal to the first gate terminal. Further, the second transistor includes a second gate terminal, a third S / D terminal coupled to the reference voltage, and a fourth S / D terminal coupled to the second terminal of the memory cell. The second transistor is configured to transfer the reference voltage from the third S / D terminal to the fourth S / D terminal in response to applying the control signal to the second gate terminal.

[0109] In the above memory device, further comprising: a third transistor having a third gate terminal connected to the first gate terminal, a fifth S / D terminal connected to another reference voltage, and a sixth S / D terminal connected to the second S / D terminal, wherein the third transistor is configured to transfer the another reference voltage from the fifth S / D terminal to the sixth S / D terminal; and a first transfer transistor having a fourth gate terminal, a seventh S / D terminal connected to the first terminal of the memory cell, and an eighth S / D terminal connected to the second S / D terminal and the sixth S / D terminal.

[0110] In the above memory device, further comprising: a fourth transistor having a fifth gate terminal connected to the second gate terminal, a ninth S / D terminal connected to another reference voltage, and a tenth S / D terminal connected to the fourth S / D terminal, wherein the fourth transistor is configured to transfer the another reference voltage from the another ninth S / D terminal to the another tenth S / D terminal; and a second transfer transistor having a sixth gate terminal, an eleventh S / D terminal connected to the second terminal of the memory cell, and a twelfth S / D terminal connected to the fourth S / D terminal and the tenth S / D terminal.

[0111] In the above memory device, the first transistor, the first transfer transistor, the second transistor, and the second transfer transistor are p-type field effect transistors; and the third transistor and the fourth transistor are n-type field effect transistors.

[0112] In the above memory device, further comprising: a first transfer transistor having a third gate terminal, a fifth S / D terminal connected to the first terminal of the memory cell, and a sixth S / D terminal connected to the second S / D terminal; and a second transfer transistor having a fourth gate terminal, a seventh S / D terminal connected to the second terminal of the memory cell, and an eighth S / D terminal connected to the fourth S / D terminal.

[0113] In the above memory device, the first transistor, the first transfer transistor, the second transistor, and the second transfer transistor are n-type field effect transistors.

[0114] In the above memory device, the first transistor, the first transfer transistor, the second transistor, and the second transfer transistor are p-type field effect transistors.

[0115] In the above memory device, the first transistor and the second transistor are p-type field effect transistors.

[0116] In the above memory device, the first transistor and the second transistor are n-type field effect transistors.

[0117] Embodiments of the present disclosure include a memory device having an array of memory cells and a pre-charge circuit. The array of memory cells includes a first memory cell and a second memory cell. Each of the first and second memory cells includes a first terminal and a second terminal. Further, the pre-charge circuit is coupled to the array of memory cells and includes a first pre-charge cell and a second pre-charge cell. The first pre-charge cell is configured to transfer a reference voltage to the first terminal and the second terminal of the first memory cell based on a first control signal. The second pre-charge cell is configured to transfer the reference voltage to the first terminal and the second terminal of the second memory cell based on a second control signal. Each of the first and second pre-charge cells includes a first transistor and a second transistor. The first transistor includes a first gate terminal, a first S / D terminal coupled to the reference voltage, and a second S / D terminal coupled to the first terminal of the first or second memory cell. The first transistor is configured to transfer the reference voltage from the first S / D terminal to the second S / D terminal. The second transistor includes a second gate terminal, a third S / D terminal coupled to the reference voltage, and a fourth S / D terminal coupled to the second terminal of the first or second memory cell. The second transistor is configured to transfer the reference voltage from the third S / D terminal to the fourth S / D terminal.

[0118] In the above memory device, the first pre-charge cell, the second pre-charge cell, and the array of memory cells are arranged in rows and columns, and wherein: the first pre-charge cell and the second pre-charge cell are located in a first row and in a first column and a second column, respectively; and the first memory cell and the second memory cell are located in a second row below the first row and in the first column and the second column, respectively.

[0119] In the above memory device, the pre-charge circuit further includes: a third pre-charge unit coupled to the first pre-charge unit and configured to transmit the reference voltage to the first terminal and the second terminal of the first memory cell based on the first control signal; and a fourth pre-charge unit coupled to the second pre-charge unit and configured to transmit the reference voltage to the first terminal and the second terminal of the second memory cell based on the second control signal; wherein the first pre-charge unit, the second pre-charge unit, the third pre-charge unit, and the fourth pre-charge unit and the array of memory cells are arranged in rows and columns, wherein: the first pre-charge unit and the second pre-charge unit are located in a first row and in a first column and a second column, respectively; and the third pre-charge unit and the fourth pre-charge unit are located in a second row below the first row and in the first column and the second column, respectively; and the first memory cell and the second memory cell are located in a third row below the second row and in the first column and the second column, respectively.

[0120] In the above memory device, the pre-charge circuit further includes: a third pre-charge unit coupled to the first pre-charge unit and configured to transmit the reference voltage to the first terminal and the second terminal of the first memory cell based on the first control signal; and one or more write assist units coupled to the first pre-charge unit and the third pre-charge unit.

[0121] In the above memory device, the first pre-charge unit further includes a third transistor having a third gate terminal, a fifth S / D terminal connected to the second S / D terminal, and a sixth S / D terminal connected to the first terminal of the first memory cell or the second memory cell.

[0122] In the above memory device, the second S / D terminal of the first pre-charge unit is connected to the first terminal of the first memory cell or the second memory cell.

[0123] In the above memory device, the first pre-charge unit further includes one or more write assist circuits coupled to the first terminal and the second terminal of the first memory cell.

[0124] In the above memory device, further comprising: a first power supply configured to provide a power supply to the array of memory cells; and a second power supply coupled to the reference voltage.

[0125] Embodiments of the present disclosure include a method for a pre-charge operation performed on a static random access memory. The method includes: (i) selecting one memory cell in an array of memory cells to perform a memory operation using first and second terminals of the memory cell; (ii) activating a pre-charge cell to charge the first and second terminals of the memory cell to a reference voltage upon de-selecting the memory cell. The pre-charge cell includes a transistor having a gate terminal, a first S / D terminal coupled to the reference voltage, and a second S / D terminal coupled to the first or second terminal of the memory cell. The transistor is configured to transfer the reference voltage from the first S / D terminal to the second S / D terminal in response to applying a control signal to the gate terminal.

[0126] In the above method, further comprising: deactivating the pre-charge cell after the first and second terminals of the memory cell have been charged to the reference voltage.

[0127] In the above method, the memory operation includes at least one of a memory read operation and a memory write operation.

[0128] It should be understood that the “detailed description” section, and not the summary and abstract sections, is intended to explain the claimed disclosure. As such, the summary of the disclosure can set forth one or more but not all possible embodiments from a perspective of the inventor, and thus is not intended to limit the claimed disclosure in any way.

[0129] The foregoing has outlined rather broadly the features of several embodiments so that those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: The memory cell includes a first terminal and a second terminal; A first transistor has a first gate terminal, a first S / D (source / drain) terminal coupled to a reference voltage, and a second S / D terminal coupled to the first terminal of the memory cell, wherein the first transistor is configured to transfer the reference voltage from the first S / D terminal to the second S / D terminal in response to applying a control signal to the first gate terminal; and The second transistor has a second gate terminal, a third S / D terminal coupled to the reference voltage, and a fourth S / D terminal coupled to the second terminal of the memory cell, wherein the second transistor is configured to transfer the reference voltage from the third S / D terminal to the fourth S / D terminal in response to applying the control signal to the second gate terminal; A third transistor has a third gate terminal connected to the first gate terminal, a fifth S / D terminal connected to an additional reference voltage, and a sixth S / D terminal connected to the second S / D terminal, wherein the third transistor is configured to transfer the additional reference voltage from the fifth S / D terminal to the sixth S / D terminal; and The first transmission transistor has a fourth gate terminal, a seventh S / D terminal connected to the first terminal of the memory cell, and an eighth S / D terminal connected to the second S / D terminal and the sixth S / D terminal.

2. The memory device according to claim 1, wherein, The memory device is a static random access memory device.

3. The memory device according to claim 1, further comprising: A fourth transistor has a fifth gate terminal connected to the second gate terminal, a ninth S / D terminal connected to the other reference voltage, and a tenth S / D terminal connected to the fourth S / D terminal, wherein the fourth transistor is configured to transfer the other reference voltage from the ninth S / D terminal to the tenth S / D terminal; and The second transmission transistor has a sixth gate terminal, an eleventh S / D terminal connected to the second terminal of the memory cell, and a twelfth S / D terminal connected to the fourth S / D terminal and the tenth S / D terminal.

4. The memory device according to claim 3, wherein: The first transistor, the first transfer transistor, the second transistor, and the second transfer transistor are p-type field-effect transistors; as well as The third transistor and the fourth transistor are n-type field-effect transistors.

5. The memory device according to claim 1, further comprising: The second transmission transistor has a fifth gate terminal, a seventh S / D terminal connected to the second terminal of the memory cell, and an eighth S / D terminal connected to the fourth S / D terminal.

6. The memory device according to claim 5, wherein, The first transistor, the first transmission transistor, the second transistor, and the second transmission transistor are n-type field-effect transistors.

7. The memory device according to claim 5, wherein, The first transistor, the first transmission transistor, the second transistor, and the second transmission transistor are p-type field-effect transistors.

8. The memory device according to claim 1, wherein, The first transistor and the second transistor are p-type field-effect transistors.

9. The device according to claim 1, wherein, The first transistor and the second transistor are n-type field-effect transistors.

10. A memory device, comprising: A memory cell array includes a first memory cell and a second memory cell, wherein each of the first memory cell and the second memory cell includes a first terminal and a second terminal; and A pre-charge circuit, coupled to the memory cell array, includes a first pre-charge unit and a second pre-charge unit, wherein: The first pre-charge unit is configured to transmit a reference voltage to the first and second terminals of the first memory unit based on a first control signal; and The second pre-charge unit is configured to transmit the reference voltage to the first and second terminals of the second memory unit based on a second control signal, wherein each of the first and second pre-charge units includes: The first transistor has: First gate terminal; The first S / D (source / drain) terminal is coupled to the reference voltage; and A second S / D terminal is coupled to the first terminal of the first memory cell or the second memory cell, wherein the first transistor is configured to transfer the reference voltage from the first S / D terminal to the second S / D terminal; The second transistor has: Second gate terminal; The third S / D terminal is coupled to the reference voltage; and A fourth S / D terminal is coupled to the second terminal of the first memory cell or the second memory cell, wherein the second transistor is configured to transfer the reference voltage from the third S / D terminal to the fourth S / D terminal; A third transistor has a third gate terminal connected to the first gate terminal, a fifth S / D terminal connected to an additional reference voltage, and a sixth S / D terminal connected to the second S / D terminal, wherein the third transistor is configured to transfer the additional reference voltage from the fifth S / D terminal to the sixth S / D terminal; and The first transmission transistor has a fourth gate terminal, a seventh S / D terminal connected to the first terminal of the memory cell, and an eighth S / D terminal connected to the second S / D terminal and the sixth S / D terminal.

11. The memory device according to claim 10, wherein, The first precharge unit, the second precharge unit, and the memory cell array are arranged in rows and columns, and wherein: The first pre-charge unit and the second pre-charge unit are located in the first row and in the first and second columns, respectively; and The first memory cell and the second memory cell are located in the second row below the first row and in the first column and the second column, respectively.

12. The memory device according to claim 10, wherein, The pre-charging circuit also includes: A third pre-charge unit, coupled to the first pre-charge unit, is configured to transmit the reference voltage to the first and second terminals of the first memory unit based on the first control signal; and A fourth pre-charge unit is coupled to the second pre-charge unit and configured to transmit the reference voltage to the first and second terminals of the second memory unit based on the second control signal; The first pre-charge unit, the second pre-charge unit, the third pre-charge unit, the fourth pre-charge unit, and the memory cell array are arranged in rows and columns, and wherein: The first pre-charge unit and the second pre-charge unit are located in the first row and in the first and second columns, respectively; and The third pre-charging unit and the fourth pre-charging unit are located in the second row below the first row and are respectively located in the first column and the second column; and The first memory cell and the second memory cell are located in the third row below the second row and are respectively located in the first column and the second column.

13. The memory device according to claim 10, wherein, The pre-charging circuit also includes: A third pre-charge unit, coupled to the first pre-charge unit, is configured to transmit the reference voltage to the first and second terminals of the first memory unit based on the first control signal; and One or more write auxiliary units are coupled to the first precharge unit and the third precharge unit.

14. The memory device according to claim 10, wherein, The memory device is a static random access memory device.

15. The memory device according to claim 13, wherein, The second S / D terminal of the first precharge unit is connected to the first memory unit or the first terminal of the second memory unit.

16. The memory device according to claim 10, wherein, The first precharge unit further includes one or more write auxiliary circuits coupled to the first terminal and the second terminal of the first memory unit.

17. The memory device of claim 10, further comprising: A first power source is configured to provide power to the memory cell array; and A second power source is coupled to the reference voltage.

18. A method for performing a pre-charge operation, comprising: Select a memory cell in the memory cell array to perform a memory operation using the first and second terminals of the memory cell; as well as When the memory cell is deselected, a pre-charge unit is activated to charge the first and second terminals of the memory cell to a reference voltage, wherein the pre-charge unit includes: A first transistor having a first gate terminal, a first S / D (source / drain) terminal coupled to the reference voltage, and a second S / D terminal coupled to the first or second terminal of the memory cell, wherein the transistor is configured to transfer the reference voltage from the first S / D terminal to the second S / D terminal in response to applying a control signal to the first gate terminal; The second transistor has a second gate terminal, a third S / D terminal coupled to the reference voltage, and a fourth S / D terminal coupled to the second terminal of the memory cell, wherein the second transistor is configured to transfer the reference voltage from the third S / D terminal to the fourth S / D terminal in response to applying the control signal to the second gate terminal; A third transistor has a third gate terminal connected to the first gate terminal, a fifth S / D terminal connected to an additional reference voltage, and a sixth S / D terminal connected to the second S / D terminal, wherein the third transistor is configured to transfer the additional reference voltage from the fifth S / D terminal to the sixth S / D terminal; and The first transmission transistor has a fourth gate terminal, a seventh S / D terminal connected to the first terminal of the memory cell, and an eighth S / D terminal connected to the second S / D terminal and the sixth S / D terminal.

19. The method of claim 18, further comprising: After the first and second terminals of the memory cell are charged to the reference voltage, the pre-charged cell is deactivated.

20. The method according to claim 18, wherein, The memory operation includes at least one of a memory read operation and a memory write operation.

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