Power endurance mode for data center solid state drives

Abstract

An apparatus includes a memory array and a power performance endurance manager module. The power performance endurance manager module stores a power endurance state descriptor data structure that includes an endurance level associated with a power endurance mode. The manager module dynamically configures the apparatus to operate the memory array according to one of the power endurance modes based on the desired endurance level.

Description

Background Art

[0001] The present disclosure relates generally to solid-state drives (SSDs), and more particularly to a power endurance mode for data center SSDs.

[0002] Generally speaking, a data center is a dedicated space that houses computers and storage systems, which may include SSDs and hosts. An SSD may include an integrated circuit assembly to persistently store data, typically using flash memory (i.e., electronic non-volatile computer memory storage media that can be electrically erased and reprogrammed). A host may be an interface or backplane (e.g., a host interface control block) that manages the operation of one or more SSDs connected to it. For example, a group of SSDs connected to a host stores programs and applications, as well as data used by those programs and applications, according to instructions from the host. In addition, the host can control the power consumption and memory performance of the SSD relative to storing programs, applications, and data.

[0003] Conventionally, to manage the power consumption and performance of SSDs, hosts use the Non-Volatile Memory Express (NVMe) standard, which defines power states. Based on the needs of the data center and / or the programs and applications being executed, the host can prioritize power consumption and memory performance when selecting a power state from the NVMe standard. However, currently, the power states of the NVMe standard do not take into account SSD "device endurance." Device endurance is an unconventional characteristic of an SSD that describes its ability to remain active for an extended period of time. Due to device wear and in view of conventional NVMe standards, there is a need to provide improved data center operations by managing the power consumption and memory performance of SSDs while taking device endurance into account. Summary of the Invention

[0004] Various embodiments of an SSD are disclosed. Broadly speaking, a device is provided that includes a memory array and a power-performance-endurance manager (PPEM) module. The PPEM module stores a power-endurance state descriptor data structure that includes endurance levels associated with power-endurance modes. The PPEM module dynamically configures the device to operate the memory array according to one of the power-endurance modes based on a desired one of the endurance levels.

[0005] According to one or more embodiments, the apparatus may be implemented as a method, a computing device, a system, and / or a computer program product. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A more detailed understanding may be obtained from the following description, given by way of example in conjunction with the accompanying drawings, in which like reference numerals indicate like elements in the various views, and in which:

[0007] Figure 1is a generalized block diagram depicting a system including a solid-state device according to one or more embodiments;

[0008] Figure 2 is a table illustrating a power endurance state descriptor data structure according to one or more embodiments;

[0009] Figure 3 is a flow chart depicting a method for implementing a power endurance mode for a data center SSD according to one or more embodiments;

[0010] Figure 4 is a flow chart depicting a method for implementing a power endurance mode for a data center SSD according to one or more embodiments; and

[0011] Figure 5 is a table depicting the operation of the system according to one or more embodiments. DETAILED DESCRIPTION

[0012] Disclosed herein are methods and systems for implementing a power endurance mode for a data center SSD. More specifically, the present disclosure relates to including a PPEM module in a data center SSD that correlates device endurance with power consumption and memory performance to increase the terabytes written (TBW) of the data center SSD and reduce management and power costs for data center providers.

[0013] For example, according to one or more embodiments, a data center SSD includes a PPEM module that stores a power-endurance state descriptor data structure. The power-endurance state descriptor data structure associates an endurance level with a power-endurance mode. The PPEM module then dynamically configures its corresponding data center SSD to operate its memory array using the power-endurance state descriptor data structure by selecting one of the power-endurance modes based on the desired endurance level. The PPEM module can receive instructions from a host that identify the desired endurance level and cause the power-endurance mode to be selected. The PPEM module can also directly select a power-endurance mode based on the operation of the corresponding data center SSD without host instructions.

[0014] Technical effects and benefits of the PPEM module (e.g., and implementations of a power endurance state descriptor data structure that associates endurance levels with power endurance modes) include reducing the cumulative stress on cells of an SSD and increasing the program erase cycles (PEC) of programmed cells of the SSD, which translates to a longer lifespan (e.g., useful life) of the SSD. Implementations of the PPEM module and power endurance state descriptor data structure can be practically applied to and used for efficient management of data centers and components therein.

[0015] Figure 1 1 is a generalized block diagram depicting a system 100 (e.g., a memory system) according to one or more embodiments. System 100 includes components including hardware and / or software, such as a host 102. Host 102 may include several hardware and / or software components, such as host memory 104. Host memory 104 may have several regions, such as physical region pages (PRPs) 106 (e.g., pointers to host addresses reflecting data placement) and data buffers 108 (e.g., regions of host memory 104 used to temporarily store data while the data is being moved).

[0016] The host 102 communicates with at least one solid-state device 110 (e.g., a data center SSD) and manages operations into (incoming arrows) and out (outgoing arrows) the at least one solid-state device. According to one or more embodiments, the host 102 may provide and configure a transition table to the SSD 110 (or even generate and provide a transition state machine, which may include conditional transition regions that also depend on the previous state). The host 102 may directly manage and set the power endurance mode of the SSD 110. According to embodiments, multiple SSDs 110 may be provided; however, for the sake of brevity, a single SSD 110 is described herein. Furthermore, it should be understood that any single item of the system 100 may represent multiple instances of that item.

[0017] SSD 110 includes components including hardware and / or software, such as a controller 112 that communicates with dynamic random access memory (DRAM) 114 and a memory array 116 (e.g., a flash memory array or multiple memory arrays). Memory array 116 can be formed using various technologies, such as NAND and NOR logic circuitry, and can include one or more dies, as is known in the art. Memory array 116 can also store one or more bits of data per cell. That is, memory array 116 can include SLC (single-level cell), MLC (multi-level cell), TLC (triple-level cell), or QLC (quad-level cell), as is known in the art. SSD 110 integrates controller 112 and memory array 116 to persistently store data.

[0018] Generally, controller 112 is circuitry used to control and manage the operation of SSD 110. Controller 112 can also include DRAM 114, which can be used as a cache for managing data reads and writes to memory array 116. Controller 112 includes components including hardware and / or software, such as interface bus 118, direct memory access (DMA) 120, control path 122, command parser 124, command executor 126, flash interface module 128, scheduler 130, error correction engine 132, processor 134, and PPEM module 140. According to one or more embodiments, in operation, controller 112 uses these components to implement one or more configurations (e.g., power endurance mode selection) with respect to different dies of SSD 110 and / or memory array 116 and / or directly implement autonomous power performance endurance state transitions. For example, one or more dies of memory array 116 can be managed individually by the controller (or host) using power endurance modes. In this regard, within the same memory array 116, a first set of dies supporting a first application can be executed according to a first power endurance mode, while a second set of dies supporting a second application can be executed according to a different power endurance mode.

[0019] According to one or more embodiments, SSD 110 (and more specifically, controller 112) can have a state machine that autonomously controls power endurance mode transitions. In this regard, controller 112 and / or PPEM module 140 can perform a self-passing “autonomous mode” for SSD 110 between preconfigured power endurance modes and be directly managed and set / configured by host 102 (or any combination thereof). For example, controller 112 can support autonomous power endurance mode transitions. Autonomous power endurance mode transitions provide host 102 with a mechanism to configure controller 112 to automatically transition between power endurance modes based on certain conditions without software intervention (or intervention by host 102). For example, an entry condition to transition to an idle transition power endurance mode is that controller 112 has been in an idle state for a contiguous period of time that exceeds an idle time before a specified transition time. Controller 112 is idle when there are no input / output (I / O) submission queues outstanding commands. If controller 112 has in-process operations (e.g., device self-test operations) that would cause the power of controller 112 to exceed the power advertised for the proposed non-operation power endurance mode, then controller 112 should not autonomously transition to that state. The power endurance mode to transition to would be a non-operation power endurance mode (one non-operation power endurance mode can autonomously transition to another non-operation power endurance mode). If a specified operation power endurance mode, then the controller should abort the command.

[0020] DRAM 114 is a type of random access semiconductor memory that stores each data bit in a memory cell composed of a capacitor and a transistor. Memory array 116 includes an array of bit cells, each of which stores one data bit, connected to word lines and bit lines so that a single word line activates a bit cell in the row for each combination of address bits.

[0021] The interface bus 118 may be a Peripheral Component Interconnect Express (PCIe) device, which is a high-speed serial computer expansion bus that includes a physical interface (PHY) for encoding, scrambling, byte striping, differential functionality on the transmitter side, and inversion operations on the physical receiver side. PCIe may further include logical sublayers corresponding to electrical and logical specifications. For example, PCIe may include logical sub-blocks, such as a media access control (MAC) sub-block.

[0022] DMA 120 is a hardware / software feature that enables direct access to memory array 116 independently of processor 134. Control path 122, command parser 124, and command executor 126 collectively provide command interpretation. Scheduler 130 controls data transfer while activating control path 122 for fetching PRP lists, issuing completions and interrupts, and activating DMA for actual data transfer between host 102 and SSD 110.

[0023] Flash interface module 128 interacts with memory array 116 (e.g., such as for read and write operations). Error correction engine 132 is responsible for correcting data retrieved from memory array 116. Processor 134 is the electronic circuitry within SSD 110 that executes instructions / commands by performing arithmetic, logic, control, and input / output operations specified by the instructions / commands.

[0024] The power-performance-endurance PPEM module 140 (hereinafter, PPEM module 140) is responsible for compromising between power-performance-endurance parameters by configuring the SSD 110 to operate under selected conditions. The PPEM module 140 may receive instructions / commands from the host 102 and act accordingly. The PPEM module 140 may also act independently of instructions / commands from the host 102. The PPEM module 140 monitors at least power consumption, memory performance, and device endurance. Device endurance is a non-standard characteristic of the SSD 110 that describes its ability to remain active for an extended period of time. Specifically, the PPEM module 140 may monitor device endurance using an endurance level, which is a degree or level of operation relative to the lifespan of the SSD 110.

[0025] According to one or more embodiments, the PPEM module 140 implements an autonomous power-performance-endurance state transition feature to define and use multiple endurance levels, which in turn take into account a wide variety of events that can cause the SSD 110 to switch from one power-endurance mode to another. For example, conventionally, switching between power states is based on timing. In contrast, the autonomous power-performance-endurance state transition feature can base transitions between power-endurance modes on an average bit error rate (BER) threshold (e.g., noise level, rather than a timing criterion) that triggers the switch.

[0026] According to one or more embodiments, the autonomous power-performance-endurance state transition feature adds an endurance level to the SSD 110 so that the host 102 (e.g., a data center provider controlling the host 102) can dynamically configure the SSD 110 to different power-endurance modes. Once configured into a power-endurance mode, the autonomous power-performance-endurance state transition feature further provides the ability to tune the SSD 110 to different power-endurance modes as a flexible trade-off between power consumption, memory performance, and device endurance. It should be noted that device endurance can be critical to data centers because a goal of data centers is to reduce operating costs, for example, by increasing the lifespan of the SSDs therein. In this regard, tuning the SSD 110 based on the endurance level increases the terabytes written (TBW) of the SSD 110.

[0027] For example, in situations where performance may be compromised, the autonomous power-performance-endurance state transition feature provides one or more options for extending endurance (e.g., thereby extending service life). As an example option, when the SSD 110 can tolerate a slower programming procedure, the PPEM module 140 using the autonomous power-performance-endurance state transition feature can reduce the programming voltage window size (e.g., at the expense of a longer programming duration) by programming with a smaller voltage step size or number of programming pulses. Consequently, technical effects and benefits include reducing the cumulative stress on the cells of the memory array 116 and increasing the PEC of any programmed cell (e.g., which translates into a longer service life for the SSD 110).

[0028] As another example option, when applying (i.e., accessing the memory array 116) allows for reduced export capacity, the PPEM module 140 using the autonomous power-performance-endurance state transition feature can increase overall TBW by reducing write amplification. As another example option, the PPEM module 140 using the autonomous power-performance-endurance state transition feature can apply shaping of the program data so that the program data utilizes a power endurance mode that consumes less voltage. It should be noted that the shaping performed by the PPEM module 140 can be due to the internal compressibility of the input data or by allocating additional data at the SSD 110 to include a longer shape word.

[0029] According to one or more embodiments, the autonomous power-performance-endurance state transition feature of the PPEM module 140 can be implemented as any data organization, management, and storage format that enables efficient access, use, and / or modification of data therein. In one example, the autonomous power-performance-endurance state transition feature is implemented as a power-endurance state descriptor data structure (e.g., a transition table or a transition state machine). The power-endurance state descriptor data structure can be stored in the PPEM module 140 (and / or in the memory 104 of the host 102). Using the power-endurance state descriptor data structure, the SSD 110 and / or the PPEM module 140 can notify the host 102 of operating conditions (e.g., current power consumption, throughput, memory state, endurance level, etc.). For example, for the same power consumption, the SSD 110 can trade off between throughput and endurance.

[0030] 现在转而参看 Figure 2 , a table 200 showing a power endurance state descriptor data structure is provided according to one or more embodiments. Table 200 defines a power endurance mode, which can be configured in Figure 1 to allow operating modes with different power consumption within the SSD 110. In this regard, table 200 implements Figure 1 The power endurance state descriptor data structure may support at least one power endurance mode, and may optionally support up to 32 power endurance modes in total. The power endurance modes may be numbered contiguously starting from zero, such that each subsequent power endurance mode consumes less than or equal to the maximum power consumed in the previous state. Thus, power endurance mode zero indicates the maximum power that the system 100 is capable of consuming.

[0031] Table 200 includes nine columns and nine rows (including a header row) depicting eight power endurance modes defined according to several metrics (e.g., which allow the host 102 to make a trade-off determination between endurance operation and power consumption). It should be noted that Table 200 is illustrative and may include more or fewer fields in the power endurance state descriptor. More specifically, column 201 of Table 200 identifies power modes 0-7. Power endurance mode 0 is the "extreme power, endurance, and BW" mode, where BW represents bandwidth. Power endurance mode 1 is the "high power and endurance, low BW" mode. Power endurance mode 2 is the "high power and BW, low endurance" mode. Power endurance mode 3 is the "high power, medium BW, medium endurance" mode. Power endurance mode 4 is the "medium power, high BW, low endurance" mode. Power endurance mode 5 is the "medium power, medium BW, medium endurance" mode. Power-endurance mode 6 is a "medium power, low BW, high endurance" mode. Power-endurance mode 7 is a "low power, BW, and endurance" mode. In an example embodiment, host 102 can dynamically configure each SSD 110 to operate in one of these power-endurance modes. It should be noted that "high power" can include programming data at five volts, while "low power" can include programming data at approximately one volt.

[0032] The eight power endurance modes in column 201 implement power management relative to the power consumption of SSD 110. Generally speaking, this power management allows host 102 to statically or dynamically manage the power of SSD 110. Static power management includes when host 102 determines the maximum power that can be allocated to SSD 110 and sets the power endurance mode to a power endurance mode that consumes this amount of power or less. Dynamic power management includes when host 102 modifies the power endurance mode to best meet changing power and performance goals. It should be noted that the power management mechanisms performed by host 102 described herein are intended to supplement, not replace, the autonomous power management or thermal management performed by controller 112 of SSD 110.

[0033] At column 202, the Maximum (MAX) Power field indicates the sustained maximum power that can be consumed in the state. Controller 112 may employ autonomous power management techniques to reduce power consumption below this level, but under no circumstances should power be allowed to exceed this level except in a non-operational power endurance mode. At column 203, the Entry Delay field indicates the maximum amount of time (in microseconds) to enter the power endurance mode. At column 204, the Exit Delay field indicates the maximum amount of time (in microseconds) to exit the state.

[0034] In addition, the remaining columns of table 200 depict relative endurance level, relative read throughput, relative read latency, relative write throughput, and relative write latency fields that provide an indication of relative performance in the power endurance mode. The relative performance values ​​provide a ranking of performance characteristics between power endurance modes. Relative performance values ​​can be repeated, skipped, and assigned in any order (i.e., increasing power endurance modes do not necessarily have increasing relative performance values).

[0035] A lower relative performance value indicates better performance (eg, better endurance, higher throughput, or lower latency). For example, power endurance mode 1 has higher read throughput than power endurance mode 2, and power endurance modes 0 through 3 all have the same read latency.

[0036] In this regard, column 205 of table 200 identifies relative durability levels 0-3 (e.g., a plurality of durability levels). Each relative durability level 0-3 reflects a priority for durability. Generally speaking, lower relative durability levels place a higher priority on durability. Conversely, higher relative durability levels place a lower priority on durability. As an example, as shown in column 201, if the desired relative durability level is 3, the selected mode may be power durability mode 4. As another example, if the desired relative durability level is 1, the selected mode may be power durability mode 3 or 5.

[0037] Relative performance rankings are relative to a single performance characteristic only. Thus, even though the relative read throughput value of one power endurance mode may be equal to the relative write throughput value of another power endurance mode, this does not imply that the actual read and write performance of the two power endurance modes are equal.

[0038] 现在转而参看 Figure 3 , a flowchart depicting a method 300 for implementing a power endurance mode for a data center SSD is provided according to one or more embodiments. Figure 1-2 Method 300 is described. In general, method 300 increases SSD TBW by taking device endurance into account so that data center providers can reduce costs for managing and operating data centers.

[0039] Method 300 begins at dashed box 310 where the endurance level is added to the power state descriptor data structure. It should be noted that dashed box 310 is optional. That is, in cases where the host or data center SSD currently utilizes NVMe standards, the endurance level can be added to those NVMe standards. In other cases where the host or data center SSD currently does not have any power consumption and memory performance, the entire power state descriptor data structure with the endurance level can be provided. Figure 1In an example of , the host 102 may have a power state descriptor data structure that does not include an endurance level. The host 102 then compares the endurance level (e.g., Figure 2 as shown) is added to the power state descriptor data structure.

[0040] At block 320, a power state descriptor data structure is stored. The power state descriptor data structure may be located in memory of the host and / or the data center SSD. Figure 1 For example, host 102 may provide a power state descriptor data structure with the relative endurance level added to SSD 110. SSD 110 then stores the power state descriptor data structure with the added relative endurance level in PPEM module 140.

[0041] At block 330, the data center SSD dynamically configures a power endurance mode based on the desired endurance level. The data center SSD may automatically configure the power endurance mode based on a default configuration. The default configuration may correspond to a state that consumes no more power than the minimum value specified in the power state descriptor data structure (e.g., thereby selecting the highest endurance level). The host may directly instruct the data center SSD to select a power endurance mode corresponding to a particular desired endurance level. Continuing with respect to Figure 1 In an example, host 102 may use a Get Features command to determine the current power endurance mode (e.g., the default configuration of SSD 110), and / or use a Set Features command (which identifies a desired endurance level and an associated power endurance mode) to dynamically modify the power endurance mode.

[0042] At block 340, the power endurance mode is tuned based on a tradeoff determination between the device's endurance operation and power consumption. That is, when the data center SSD is operating, the host or data center SSD can determine whether performance may be compromised, when to apply a reduction in export capacity, and / or when programming data shaping may be applied. Based on these determinations, a new power endurance mode can be selected that enables the host or data center SSD to reduce the programming voltage window size, increase the overall TBW, and / or apply shaping.

[0043] According to one or more embodiments, a host can directly transition between any two supported power endurance modes, or cause a data center SSD to transition between any two supported power endurance modes. The maximum amount of time to transition between any two power endurance modes is equal to the sum of the old state exit latency and the new state entry latency. The host does not need to wait for a previously submitted power endurance mode transition to complete before initiating a new transition. The maximum amount of time to complete a series of power endurance mode transitions is equal to the sum of the transition times for each individual power endurance mode transition in the series.

[0044] Figure 4 is a flow chart depicting a method 400 for implementing a power endurance mode for a data center SSD according to one or more embodiments. Figure 5 Method 400 is described. In general, method 400 increases SSD TBW by taking device endurance into account so that data center providers can reduce costs for managing and operating data centers.

[0045] Method 300 begins at block 410, where the host stores a power state descriptor data structure in an SSD connected to the host. At block 420, the host adds an endurance level to the power state descriptor data structure. At block 430, the host monitors the data and workload of the SSD to determine a desired endurance level. It should be noted that the SSD can be automatically configured to a power endurance mode based on a default configuration. As mentioned herein, the default configuration can correspond to a state where the power consumed is no greater than the minimum value specified in the power state descriptor data structure (e.g., thereby selecting the highest endurance level).

[0046] At block 440, the host dynamically configures the SSD to a power endurance mode based on the desired endurance level. In this regard, as indicated by circle 445, the host may issue a command directly to the SSD that causes the SSD to select a power endurance mode corresponding to the desired endurance level specified by the command. If more than one power endurance mode corresponds to the desired endurance level, the SSD may select the power endurance mode with the lowest relative endurance value (e.g., thereby implementing the highest endurance operation).

[0047] At block 450, the host monitors the SSD to determine whether operation meets the desired endurance level. That is, while the SSD is operating, the host can determine whether performance of the workload directed to the SSD may be compromised, whether software or applications accessing data from the SSD can support reduced export capacity, and / or when shaping of program data can be applied. This monitoring is continuous, as indicated by arrow 455. At block 460, based on the monitoring, the host switches to another power endurance mode (e.g., the host reduces the programming voltage window size, increases the overall TBW, and / or applies shaping) based on whether operation meets the desired power endurance level.

[0048] Go to Figure 5, a table 500 is provided that depicts the operation of the system according to one or more embodiments. Table 500 is an autonomous power endurance state transition table showing transitions between power endurance mode 0 (extreme power, BW, and low endurance level), power endurance mode 5 (medium power, BW, and medium endurance level), and power endurance mode 6 (medium power, medium BW, and high endurance level). Columns 502 and 503 describe transitions between one of the two modes configured by the host in this example.

[0049] Thus, the technical effects of the embodiments herein include optimizing device endurance (e.g., lifespan related to TBW terabyte ratings) to extend SSD operation and reduce data center expenses, which overcomes issues associated with conventional NVMe standards (i.e., these standards do not define endurance levels and compromise endurance with power). Thus, according to the embodiments herein, a host (e.g., a specific data center) can actually configure and tune an SSD based on device endurance along with power consumption (and performance) to allow for increased flexibility in optimizing performance and cost.

[0050] The flowcharts and block diagrams in the figures illustrate the architecture, functionality and operation of possible implementation schemes of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a portion of a module, segment or instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions marked in the box may not occur in the order marked in the figure. For example, depending on the functionality involved, the two boxes shown in succession can actually be executed substantially simultaneously, or the boxes can sometimes be executed in reverse order. It should also be noted that each box in the block diagram and / or flowchart illustration, and the combination of boxes in the block diagram and / or flowchart illustration can be implemented by a dedicated hardware-based system that performs a specified function or action, or implements a combination of dedicated hardware and computer instructions.

[0051] Although features and elements are described above in particular combinations, one of ordinary skill in the art will appreciate that each feature or element can be used alone or in any combination with other features and elements. In addition, the methods described herein can be implemented in a computer program, software, or firmware incorporated into a computer-readable medium for execution by a computer or processor. As used herein, a computer-readable medium should not itself be interpreted as a transient signal, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., a light pulse transmitted through a fiber optic cable), or an electrical signal transmitted through a wire.

[0052] Examples of computer-readable media include electronic, optical, magnetic, or any other storage devices capable of providing a processor-connected computer with data. Various embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits, by program instructions being executed by one or more processors, or by a combination of both. The embodiments described herein can be implemented in a computing device that includes hardware and software, such as a mobile device or server. A computing device includes a processor connected to one or more memory devices, such as volatile memory (e.g., random access memory (RAM)), and a non-volatile storage device (e.g., a disk drive, memory, or a combination of both). The processor is configured to execute program instructions stored in memory or on the non-volatile storage device to perform tasks. The aforementioned memory storage devices are examples of computer-readable storage media. A computing device includes a processor connected to one or more memory devices, such as volatile memory (e.g., random access memory (RAM)), and a non-volatile storage device (e.g., a disk drive, memory, or a combination of both). The processor is configured to execute program instructions stored in memory or on the non-volatile storage device to perform tasks. The aforementioned memory storage devices are examples of computer-readable storage media.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Similarly, the word "comprise" means to comprise but does not exclude the presence of other elements or steps. Also, as used herein, the word "can" is used to mean "is able to" but does not exclude other possible meanings.

[0054] Various units, circuits, or other components can be described as "configured to" perform a particular task or tasks. In such contexts, "configured to" is a broad recitation of structure generally meaning "having the circuitry, circuitry that is capable of, or circuitry that is operative to" perform the task or tasks. As such, the unit / circuit / component can be "configured to" perform the task even when the unit / circuit / component is not currently on. In general, the circuitry that forms the structure recited in a "configured to" clause is interconnected such that it performs the corresponding task(s). Those skilled in the art will recognize that, absent such interconnection, the unit / circuit / component merely would not perform its corresponding task(s).

[0055] As used herein, the term "based on" is used to describe one or more factors that affect a determination. This term is not exclusive, meaning that additional factors can also be involved. In other words, the determination can be based on the specified factor or factors and on other factors that are not specified. Consider the phrase "determine A based on B." This phrase specifies that B is a factor that is used in the determination of A. This phrase does not exclude the possibility that A can also be determined based on some other factor, e.g., C. This phrase also does not exclude the possibility that B and C are the same factor. The phrase "based on" is, therefore, synonymous with the phrase "based at least in part on."

[0056] Descriptions of various embodiments have been presented for illustrative purposes, but the descriptions are not intended to be exhaustive or limited to the disclosed embodiments. That is, although the present disclosure allows for various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. Without departing from the scope and spirit of the described embodiments, many modifications and variations will be apparent to those of ordinary skill in the art. Therefore, it should be understood that the drawings and the accompanying detailed descriptions are not intended to limit the present disclosure to the specific forms described, but rather, are intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure, including modifications, equivalents, and alternatives defined by the appended claims. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device comprising: multiple memory arrays; A power performance durability manager module configured to: storing a power endurance state descriptor data structure including a plurality of endurance levels associated with a plurality of power endurance modes; dynamically configuring the device to operate the plurality of memory arrays according to one of the plurality of power endurance modes based on a desired endurance level among the plurality of endurance levels; as well as Tuning the device to another power endurance mode of the plurality of power endurance modes corresponding to another desired endurance level of the plurality of endurance levels is determined based on a tradeoff between endurance operation and power consumption of the device.

2. The device of claim 1 , wherein the power-performance-endurance manager module is configured to receive instructions from a host in communication with the device, the instructions identifying the desired endurance level among the plurality of endurance levels for the power-performance-endurance manager module.

3. The apparatus of claim 1, wherein the desired endurance level comprises a scaled-down programming procedure that reduces a programming voltage window size or voltage step size to reduce cumulative stress on cells of the plurality of memory arrays and increase program-erase cycles.

4. The apparatus of claim 1, wherein the desired endurance level comprises a reduce export capacity procedure that reduces write amplification to increase overall terabytes written.

5. The apparatus of claim 1, wherein the desired endurance level comprises a program data shaping procedure that reduces a number of high voltage states based on internal compressibility of input data or based on allocation of additional data.

6. The apparatus of claim 1 , further comprising: A flash interface module is configured to interact with the plurality of memory arrays for read and write operations based on the one of the plurality of endurance levels.

7. The apparatus of claim 1 , further comprising: A scheduler configured to activate control paths for fetching physical region pages, issuing completions and interrupts, or Controls data transfer while activating direct memory access.

8. The apparatus of claim 1 , further comprising: An error correction engine is configured to correct data extracted from the plurality of memory arrays.

9. The apparatus of claim 1 , further comprising: A controller is configured to incorporate coupled dynamic random access memory for use by the device.

10. The device according to claim 1, Wherein the power performance endurance manager module is configured to implement autonomous power endurance mode transitions between the plurality of power endurance modes.

11. The device according to claim 1, Wherein the power performance endurance manager module is configured to operate one or more dies of the plurality of memory arrays according to the one of the plurality of power endurance modes based on the desired endurance level.

12. The apparatus of claim 1, wherein the desired endurance level comprises a reduced programming procedure, a reduced export capacity procedure, or a program data reshaping procedure.

13. A method comprising: storing, by a power performance endurance manager module of the solid-state drive, a power endurance state descriptor data structure comprising a plurality of endurance levels associated with a plurality of power endurance modes; dynamically configuring, by the power-performance-endurance manager module, the solid-state drive to operate a plurality of memory arrays of the solid-state drive according to one of the plurality of power-endurance modes based on a desired endurance level among the plurality of endurance levels; as well as Tuning the solid-state drive to another power endurance mode of the plurality of power endurance modes corresponding to another desired endurance level of the plurality of endurance levels is determined based on a tradeoff between endurance operation and power consumption of the solid-state drive.

14. The method according to claim 13, further comprising: Instructions are received from a host in communication with the solid-state drive, the instructions identifying the desired endurance level of the plurality of endurance levels for the power-performance endurance manager module.

15. The method of claim 13, wherein the desired endurance level comprises a scaled-down programming procedure that reduces a programming voltage window size or voltage step size to reduce cumulative stress on cells of the plurality of memory arrays and increase program-erase cycles.

16. The method of claim 13, wherein the desired durability level includes a reduce export capacity procedure that reduces write amplification to increase overall terabytes written.

17. The method of claim 13, wherein the desired endurance level includes a program data shaping procedure that reduces a number of high voltage states based on internal compressibility of input data or based on allocation of additional data.

18. The method of claim 13, further comprising: A flash interface module of the solid-state drive interacts with the plurality of memory arrays for read and write operations based on the one of the plurality of endurance levels.

19. The method of claim 13, further comprising: Data transfer is controlled by a scheduler of the solid-state drive while activating control paths for fetching physical region pages, issuing completions and interrupts, or activating direct memory access.

20. The method of claim 13, further comprising: Data extracted from the plurality of memory arrays is corrected by an error correction engine.

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