Hole precharging scheme using gate-induced drain leakage generation

Abstract

The present invention is entitled "Hole Precharge Scheme Using Gate Induced Drain Leakage Generation". A memory device is disclosed herein. The memory device includes: a memory string, the memory string including a first selection transistor, a memory cell transistor and a second selection transistor connected in series; a bit line, the bit line connected to one end of the first selection transistor; a source line, the source line connected to one end of the second selection transistor; a first selection line, the first selection line connected to the gate of the first selection transistor; a word line, the word line connected to the gate of the memory cell transistor; a second selection line, the second selection line connected to the gate of the second selection transistor; and a control circuit, the control circuit is configured to perform a precharge operation before a programming operation, the precharge operation including: applying a voltage to the second selection line connected to the gate of the second selection transistor to induce gate induced drain leakage from the second selection transistor.

Description

Technical Field

[0001] The present application relates to nonvolatile memory devices and the operation of nonvolatile memory devices. Background Art

[0002] This section provides background information related to technology related to the present disclosure and thus is not necessarily prior art.

[0003] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, nonvolatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0004] Charge storage materials (such as floating gates) or charge trapping materials may be used in such memory devices to store charge representing a data state. The charge trapping materials may be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is a bit cost scalable (BiCS) architecture, which includes a stack of alternating conductive and dielectric layers. Summary of the invention

[0005] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features and advantages.

[0006] An object of the present disclosure is to provide a memory device and a method of operating the memory device that addresses and overcomes the disadvantages described herein.

[0007] A memory device is disclosed herein. The memory device includes: a memory string including a first selection transistor, a memory cell transistor, and a second selection transistor connected in series; a bit line connected to one end of the first selection transistor; a source line connected to one end of the second selection transistor; a first selection line connected to a gate of the first selection transistor; a word line connected to the gate of the memory cell transistor; a second selection line connected to the gate of the second selection transistor; and a control circuit configured to perform a precharge operation before a programming operation, the precharge operation including: applying a voltage to a second selection line connected to a gate of the second selection transistor to cause gate-induced drain leakage from the second selection transistor.

[0008] In addition, a memory device is disclosed herein. The memory device includes: a memory string including a first selection transistor, a memory cell transistor, and a second selection transistor connected in series; a bit line connected to one end of the first selection transistor; a source line connected to one end of the second selection transistor; a first selection line connected to the gate of the first selection transistor; a word line connected to the gate of the memory cell transistor; a second selection line connected to the gate of the second selection transistor; and a control circuit configured to perform a precharge operation before a programming operation, the precharge operation including: applying a voltage to a source line connected to one end of the second selection transistor to cause gate-induced drain leakage from the second selection transistor.

[0009] In addition, a memory device is disclosed herein. The memory device includes: a memory string including a first selection transistor, a memory cell transistor, and a second selection transistor connected in series; a bit line connected to one end of the first selection transistor; a source line connected to one end of the second selection transistor; a first selection line connected to the gate of the first selection transistor; a word line connected to the gate of the memory cell transistor; a second selection line connected to the gate of the second selection transistor; and a control circuit configured to perform a precharge operation before a programming operation, the precharge operation including: applying a voltage to the first selection line connected to the gate of the first selection transistor to cause gate-induced drain leakage from the first selection transistor.

[0010] Further areas of applicability will become apparent from the description provided herein.The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a detailed description of exemplary embodiments, reference will now be made to the accompanying drawings, in which:

[0012] Figure 1A is a block diagram of an exemplary memory device;

[0013] Figure 1B is a block diagram of an exemplary control circuit including a programming circuit, a counting circuit, and a determination circuit;

[0014] Figure 2 depicts a block of memory cells in an exemplary two-dimensional configuration of the memory array of FIG. 1 ;

[0015] Figure 3A depicts a cross-sectional view of an exemplary floating gate memory cell in a NAND string;

[0016] Figure 3B Depicts a section of the 329 Figure 3A A cross-sectional view of the structure;

[0017] Figure 4A depicts a cross-sectional view of an exemplary charge trapping memory cell in a NAND string;

[0018] Figure 4B Depicts a section of the 429 Figure 4A A cross-sectional view of the structure;

[0019] Figure 5A depicts an exemplary block diagram of the sensing block SB1 of FIG. 1 ;

[0020] Figure 5B depicts another exemplary block diagram of the sensing block SB1 of FIG. 1 ;

[0021] Fig. 6A is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1 ;

[0022] Figure 6B Depicted Fig. 6A An exemplary cross-sectional view of a portion of one of the blocks;

[0023] Figure 6C Depicted Figure 6B A diagram of memory hole diameters in a stack of;

[0024] Fig.6D Depicted Figure 6B A close up view of the stacked region 622;

[0025] Fig. 7A Depicted Figure 6B A top view of an exemplary word line layer WLL0 of the stack;

[0026] Figure 7B Depicted Figure 6B A top view of an exemplary top dielectric layer DL19 of the stack;

[0027] Fig. 8A Depicted Fig. 7A Example NAND strings in sub-blocks SBa to SBd of FIG.

[0028] Figure 8B Another exemplary view of NAND strings in a sub-block is depicted;

[0029] Figure 8C depicts a top view of an exemplary wordline layer stack;

[0030] Fig. 9depicts the Vth distribution of memory cells in an exemplary one-pass programming operation with four data states;

[0031] Fig.10 depicts the Vth distribution of memory cells in an exemplary one-pass programming operation with eight data states;

[0032] Fig.11 depicts the Vth distribution of memory cells in an exemplary one-pass programming operation with sixteen data states;

[0033] Fig.12 is a flow chart of an exemplary programming operation in a memory device;

[0034] Fig.13A and Fig. 13B The Vth distribution of the memory cell is depicted;

[0035] Fig.14A and Fig. 14B An exemplary BiCS structure is depicted;

[0036] FIG. 15A to FIG. 15D Various graphs are provided illustrating implementations of hole pre-charging schemes generated using gate induced drain leakage according to embodiments described herein. DETAILED DESCRIPTION

[0037] In the following description, details are set forth to provide an understanding of the present disclosure. In some cases, certain circuits, structures, and techniques have not been described or shown in detail to avoid obscuring the present disclosure.

[0038] Generally speaking, the present disclosure relates to non-volatile memory devices of a type that is very suitable for many applications. The non-volatile memory devices and associated formation methods of the present disclosure will be described in conjunction with one or more example embodiments. However, the specific example embodiments disclosed are only for the purpose of clearly describing the concepts, features, advantages and purposes of the present invention to allow those skilled in the art to understand and practice the present disclosure. Specifically, example embodiments are provided so that the present disclosure will be comprehensive and the scope will be fully conveyed to those skilled in the art. Many specific details, such as examples of specific components, devices and methods, are set forth to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details do not need to be adopted, and the example embodiments can be embodied in a variety of different forms, and none of them should be construed as limiting the scope of the present disclosure. In some example embodiments, well-known processes, well-known device structures and well-known technologies are not described in detail.

[0039] Various terms are used to refer to specific system components. Different companies may refer to components by different names—this document does not intend to distinguish between components that differ in name but function the same. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended manner and thus should be understood to mean "including but not limited to..." In addition, the terms "couple" or "couples" are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, that connection may be made through a direct connection or through an indirect connection via other devices and connections.

[0040] Additionally, when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer of the substrate, or there can be intervening layers. Additionally, it should be understood that when a layer is referred to as being "below" another layer, it can be directly below the other layer, and there can be one or more intervening layers. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0041] As described, a non-volatile memory system is a type of memory that retains stored information without the need for an external power source. Non-volatile memory is widely used in a variety of electronic devices and stand-alone memory devices. For example, non-volatile memory can be found in laptop computers, digital audio players, digital cameras, smart phones, video games, scientific instruments, industrial robots, medical electronics, solid-state drives, USB drives, memory cards, etc. Non-volatile memory can be programmed / reprogrammed and erased electrically.

[0042] Examples of non-volatile memory systems include flash memory, such as NAND flash memory or NOR flash memory. The NAND flash memory structure typically arranges multiple memory cell transistors (e.g., floating gate transistors or charge trapping transistors) in series with two select gates (e.g., drain side select gate and source side select gate) and between the two select gates. The memory cell transistors and select gates in series may be referred to as a NAND string. In order to reduce the cost per bit, the size of the NAND flash memory may be reduced.

[0043] The programming operation of a group of memory cells of a memory device generally involves applying a series of programming voltages to the memory cells after providing the memory cells in an erased state. Each programming voltage is provided in a programming loop (also referred to as a programming-verification iteration). For example, the programming voltage may be applied to a word line that is connected to the control gate of the memory cell. In one method, incremental step pulse programming is performed, wherein the programming voltage is increased by a step size in each programming loop. A verification operation may be performed after each programming voltage to determine whether the memory cell has been programmed. When programming of a memory cell is completed, the memory cell may be locked to prevent further programming while continuing to program other memory cells in subsequent programming loops.

[0044] Each memory cell may be associated with a data state according to write data in a program command. Based on the data state of the memory cell, the memory cell will remain in the erased state or be programmed to a data state different from the erased state (programmed data state). For example, in a one-bit per cell memory device (single-level cell (SLC)), there are two data states, including an erased state and one higher data state. In a two-bit per cell memory device (multi-level cell (MLC)), there are four data states, including an erased state and three higher data states, referred to as A, B, and C data states (see Fig. 9 In a three-bit per cell memory device (triple-level cell (TLC)), there are eight data states, including the erased state and seven higher data states, referred to as the A, B, C, D, E, F, and G data states (see Fig.10 In a four-bit per cell memory device (quad-level cell (QLC)), there are sixteen data states, including the erased state and fifteen higher data states, referred to as the Er, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F data states (see Fig.11 ). Each memory cell can store a data state (e.g., a binary value) and is programmed to a threshold voltage state corresponding to the data state. Each state represents a different value and is assigned a voltage window that includes a range of possible threshold voltages.

[0045] When a program command is issued, the write data is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the cell will be programmed. Each programming data state is associated with a verification voltage, so that when a sensing operation determines that its threshold voltage (Vth) is higher than the associated verification voltage, the memory cell with a given data state is considered to have completed programming. The sensing operation can determine whether the memory cell has a Vth higher than the associated verification voltage by applying the associated verification voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, so that the Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, so that the Vth is higher than the control gate voltage.

[0046] The verification voltage used to determine that a memory cell has completed programming may be referred to as a final verification voltage or a lockout verification voltage. In some cases, an additional verification voltage may be used to determine that a memory cell is close to being programmed. The additional verification voltage may be referred to as an offset verification voltage and may be lower than the final verification voltage. When a memory cell is close to being programmed, the programming speed of the memory cell may be reduced, such as by raising the voltage of the corresponding bit line during one or more subsequent programming voltages. For example, in Fig. 9 In the embodiment, memory cells to be programmed to the A data state may be subjected to a verification test at VvAL (an offset verification voltage of the A data state) and VvA (a final verification voltage of the A data state).

[0047] The programming operation may include a precharge phase. During the precharge phase, the channel of the NAND string in the 3D stacked memory device may be prepared for programming. For example, the CPWELL precharge technique may be used to improve the reverse programming (ROP) erase upper tail by supplying holes into the channel. However, this technique cannot be implemented on the BiCS CMOS array (CUA) architecture. The embodiments described herein provide an alternative technique for improving the boost potential of the ROP of the BiCS CUA architecture. More specifically, the embodiments described herein relate to a precharge scheme generated using gate induced drain leakage (GIDL).

[0048] To help further explain the foregoing, we will now describe Figure 1A . Figure 1A1 is a block diagram of an exemplary memory device. The memory device 100 may include one or more memory dies 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and is addressable by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks SB1, SB2 ..., SBp (sense circuitry) and allows pages of memory cells to be read or programmed in parallel. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120, and between the controller and the one or more memory dies 108 via a line 118.

[0049] The memory structure may be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, the one or more memory cell arrays including a 3D array. The memory structure may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (but not in) a single substrate such as a wafer, without an intervening substrate. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of a memory cell array having an active area disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0050] Control circuit 110 cooperates with read / write circuit 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations. Storage area 113 may be provided, for example, for verifying parameters described herein.

[0051] An on-chip address decoder 114 provides an address interface between the address interface used by the host or memory controller and the hardware address used by decoders 124 and 132. A power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module may include drivers for the word lines, SGS and SGD transistors, and source lines. In one approach, the sense block may include a bit line driver. The SGS transistor is a select gate transistor at the source end of the NAND string, and the SGD transistor is a select gate transistor at the drain end of the NAND string.

[0052] In some implementations, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any one of the control circuit 110, the state machine 112, the decoder 114 / 132, the power control module 116, the sense blocks SB1, SB2...SBp, the read / write circuit 128, the controller 122, etc., or a combination thereof.

[0053] The control circuit may include a programming circuit configured to program memory cells of a word line of a block and verify the group of memory cells. The control circuit may also include a counting circuit configured to determine the number of memory cells verified to be in a data state. The control circuit may also include a determination circuit configured to determine whether the block is faulty based on the number.

[0054] For example, Figure 1B is a block diagram of an exemplary control circuit 150 including a programming circuit 151, a counting circuit 152, and a determination circuit 153. The programming circuit may include implementing, for example Fig.12 The counting circuit may include software, firmware and / or hardware that implements steps 1202 and 1204. Fig.12 The software, firmware and / or hardware of step 1206 of the embodiment of the present invention may include implementing, for example, Fig.12 The software, firmware and / or hardware of step 1208.

[0055] The off-chip controller 122 may include a processor 122c, a storage device (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, uncorrectable errors may exist in some cases. The technology provided herein reduces the possibility of uncorrectable errors.

[0056] The storage device includes code such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein.Alternatively or additionally, the processor may access code from the storage device 126a of the memory structure, such as a reserved area of ​​memory cells in one or more word lines.

[0057] For example, the controller 122 may use code to access memory structures, such as for programming operations, read operations, and erase operations. The code may include a boot code and a control code (e.g., a set of instructions). The boot code is software that initializes the controller and enables the controller to access the memory structure during the boot or boot process. The controller may use code to control one or more memory structures. When powered on, the processor 122c takes out the boot code from the ROM 122a or storage device 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes a driver that performs basic tasks, such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0058] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smart phone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid-state memory), and the one or more processor-readable storage devices store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0059] In addition to NAND flash memory, other types of non-volatile memory may be used.

[0060] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, a flash memory device may be configured in a NAND configuration or a NOR configuration.

[0061] The memory device may be formed of passive components and / or active components in any combination. By way of non-limiting example, passive semiconductor memory components include ReRAM device components, which in some embodiments include resistivity switching storage elements, such as antifuses or phase change materials, and optional steering elements, such as diodes or transistors. In addition, by way of non-limiting example, active semiconductor memory components include EEPROM and flash memory device components, which in some embodiments include components containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0062] Multiple memory elements may be configured so that they are connected in series or so that each element may be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND string is an example of a group of transistors connected in series that includes a memory cell and a SG transistor.

[0063] A NAND memory array can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0064] Semiconductor memory elements located in and / or over the substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0065] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the major surface of a substrate supporting the memory elements. The substrate may be a wafer on or in which the layers of the memory elements are formed, or it may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0066] The memory elements may be arranged in a single memory device level in an ordered array, such as in multiple rows and / or columns. However, the memory elements may be arranged in an unconventional configuration or a non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as a bit line and a word line.

[0067] The three-dimensional memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., x, y and z directions, where the z direction is substantially vertical and the x and y directions are substantially parallel to the major surface of the substrate).

[0068] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), each column having a plurality of memory elements. The columns may be arranged in a two-dimensional configuration, such as in an xy plane, to obtain a three-dimensional arrangement of memory elements, wherein the elements are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements may also constitute a three-dimensional memory array.

[0069] By way of non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings that span multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, with some NAND strings containing memory elements in a single memory level and other strings containing memory elements that span multiple memory levels. Three-dimensional memory arrays may also be designed in NOR configurations as well as ReRAM configurations.

[0070] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers of each memory device level that make up the array are typically formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between the memory device levels.

[0071] The two-dimensional arrays may then be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. In addition, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0072] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to implement functions such as programming and reading. The associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0073] Those skilled in the art will recognize that the present technology is not limited to the two-dimensional and three-dimensional exemplary structures described, but encompasses all related memory structures within the spirit and scope of the present technology as described herein and as understood by those skilled in the art.

[0074] Figure 2 Depicted are blocks of memory cells in an exemplary two-dimensional configuration of the memory array 126 of FIG. 1 . The memory array may include many blocks. Each exemplary block 200, 210 includes a plurality of NAND strings and corresponding bit lines, such as BL0, BL1 ... shared between blocks. Each NAND string is connected to a drain select gate (SGD) at one end, and the control gate of the drain select gate is connected via a common SGD line. The NAND string is connected to a source select gate at its other end, which in turn is connected to a common source line 220. Sixteen word lines, such as WL0 to WL15, extend between the source select gate and the drain select gate. In some cases, dummy word lines that do not contain user data may also be used in memory arrays adjacent to select gate transistors. Such dummy word lines can shield edge data word lines from certain edge effects.

[0075] One type of nonvolatile memory that can be provided in a memory array is floating gate memory. Figure 3A and Figure 3B Other types of nonvolatile memory may also be used. For example, a charge trap memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. See Figure 4A and Figure 4B . A triple layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split gate configuration, in which a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0076] In another approach, an NROM cell is used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0077] Figure 3A A cross-sectional view of an exemplary floating gate memory cell in a NAND string is depicted. The bit line or NAND string direction goes into the page, and the word line direction is from left to right. For example, word line 324 extends across the NAND string, which includes corresponding channel regions 306, 316, and 326. Memory cell 300 includes control gate 302, floating gate 304, tunnel oxide layer 305, and channel region 306. Memory cell 310 includes control gate 312, floating gate 314, tunnel oxide layer 315, and channel region 316. Memory cell 320 includes control gate 322, floating gate 321, tunnel oxide layer 325, and channel region 326. Each memory cell is in a different corresponding NAND string. An inter-polysilicon dielectric (IPD) layer 328 is also depicted. The control gate is part of the word line. Figure 3B A cross-sectional view taken along line 329 is provided in FIG.

[0078] The control gate is wrapped around the floating gate, thereby increasing the surface contact area between the control gate and the floating gate. This results in a higher IPD capacitance, which results in a higher coupling ratio, which makes programming and erasing easier. However, as NAND memory devices are scaled down, the spacing between adjacent cells becomes smaller, so there is almost no space for the control gate and IPD between two adjacent floating gates. As an alternative, such as Figure 4A and Figure 4B As shown, a flat or planar memory cell has been developed in which the control gate is flat or planar; that is, the control gate does not wrap over the floating gate, and the only contact of the control gate with the charge storage layer is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is made thinner. In addition, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the problem of ballistic electron transport, in which electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0079] Figure 3B Depicts a section of the 329 Figure 3A330 includes an SGS transistor 331, exemplary memory cells 300, 333, ... 334, and 335, and an SGD transistor 336. As an example of each memory cell, the memory cell 300 includes a control gate 302, an IPD layer 328, a floating gate 304, and a tunnel oxide layer 305, and Figure 3A The paths in the IPD layer in the SGS and SGD transistors allow the control gate layer and the floating gate layer to communicate. For example, the control gate layer and the floating gate layer may be polysilicon, and the tunnel oxide layer may be silicon oxide. The IPD layer may be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0080] The NAND string may be formed on a substrate including a p-type substrate region 355, an n-type well 356, and a p-type well 357. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch may be directly applied to the channel region of the substrate.

[0081] Figure 4A A cross-sectional view of an exemplary charge trapping memory cell in a NAND string is depicted. The view is in the word line direction of a memory cell including a planar control gate and a charge trapping region, as a 2D example of a memory cell in the memory cell array 126 of FIG. 1 . Charge trapping memory can be used in NOR and NAND flash memory devices. Compared to floating gate MOSFET technology that uses conductors such as doped polysilicon to store electrons, this technology uses insulators such as SiN films to store electrons. For example, a word line (WL) 424 extends across a NAND string that includes corresponding channel regions 406, 416, and 426. Portions of the word line provide control gates 402, 412, and 422. IPD layer 428, charge trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunnel layers 409, 407, and 408 are below the word line. Each charge trapping layer extends continuously in a corresponding NAND string.

[0082] Memory cell 400 includes control gate 402, charge trapping layer 404, polysilicon layer 405, and a portion of channel region 406. Memory cell 410 includes control gate 412, charge trapping layer 414, polysilicon layer 415, and a portion of channel region 416. Memory cell 420 includes control gate 422, charge trapping layer 421, polysilicon layer 425, and a portion of channel region 426.

[0083] Here a planar control gate is used, rather than a control gate wrapped around a floating gate. One advantage is that the charge trapping layer can be made thinner than the floating gate. In addition, the memory cells can be placed closer together.

[0084] 4B depicts a view taken along Route 429 Figure 4A . The view shows a NAND string 430 with a planar control gate and a charge trapping layer. The NAND string 430 includes a SGS transistor 431, exemplary memory cells 400, 433...434 and 435, and a SGD transistor 435.

[0085] The NAND string can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well 457. A channel voltage Vch can be applied directly to the channel region of the substrate. The memory cell 400 includes a control gate 402 and an IPD layer 428 above a charge trapping layer 404, a polysilicon layer 405, a tunnel layer 409, and a channel region 406.

[0086] For example, the control gate layer can be polysilicon and the tunnel layer can be silicon oxide. The IPD layer can be a stack of high-k dielectrics such as AlOx or HfOx, which helps increase the coupling ratio between the control gate layer and the charge trapping layer or charge storage layer. The charge trapping layer can be, for example, a mixture of silicon nitride and silicon oxide.

[0087] The SGD and SGS transistors have the same configuration as the memory cell, but have a longer channel length to ensure that current is cut off in the suppressed NAND string.

[0088] In this example, layers 404, 405, and 409 extend continuously in the NAND string.In another approach, portions of layers 404, 405, and 409 between control gates 402, 412, and 422 can be removed, exposing the top surface of channel 406.

[0089] Figure 5AAn exemplary block diagram of the sense block SB1 of FIG. 1 is depicted. In one approach, the sense block includes a plurality of sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sense blocks may be used to sense different subsets of bit lines. This allows the processing load associated with the sense circuits to be divided and processed by the corresponding processors in each sense block. For example, a sense circuit controller 560 in SB1 may communicate with the group of sense circuits and latches. The sense circuit controller may include a precharge circuit 561 that provides a voltage to each sense circuit for setting a precharge voltage. In one possible approach, for example, via a database 503 and a local bus such as Figure 5B LBUS1 or LBUS2 in the MCU independently provides voltage to each sensing circuit. In another possible method, for example, via Figure 5B The line 505 in the circuit provides a common voltage to each sensing circuit at the same time. The sensing circuit controller may also include a memory 562 and a processor 563. Figure 2 As described, the memory 562 may store code that can be executed by the processor to perform the functions described herein. These functions may include reading a latch associated with the sensing circuit, setting a bit value in the latch, and providing a voltage for setting a precharge level in a sensing node of the sensing circuit. More exemplary details of the sensing circuit controller and the sensing circuits 550a and 551a are provided below.

[0090] Figure 5B Another exemplary block diagram of the sensing block SB1 of FIG. 1 is depicted. The sensing circuit controller 560 is also Figure 5A5. The sensing circuit 550a includes a latch 550b including a trip latch 526, an offset verification latch 527, and a data state latch 528. The sensing circuit also includes a voltage clamp structure 521, such as a transistor, which sets a precharge voltage at a sensing node 522. A sensing node to bit line (BL) switch 523 selectively allows the sensing node to communicate with a bit line 525, for example, the sensing node is electrically connected to the bit line so that the sensing node voltage can be attenuated. The bit line 525 is connected to one or more memory cells, such as memory cell MC1. The voltage clamp structure 524 can set a voltage on the bit line, such as during a sensing operation or during a programming voltage. The local bus LBUS1 allows the sensing circuit controller to communicate with components in the sensing circuit, such as in some cases communicating with the latch 550b and the voltage clamp structure. To communicate with the sensing circuit 550a, the sensing circuit controller provides a voltage to transistor 504 via line 502 to connect LBUS1 with the data bus DBUS 503. The communication may include sending data to the sensing circuit and / or receiving data from the sensing circuit.

[0091] For example, the sense circuit controller may communicate with the different sense circuits in a time multiplexed manner, for example.In one approach, line 505 may be connected to a voltage clamping structure in each sense circuit.

[0092] The sensing circuit 551a includes a latch 551b, including a trip latch 546, an offset verification latch 547, and a data state latch 548. The voltage clamp structure 541 can be used to set a precharge voltage at the sensing node 542. The sensing node to bit line (BL) switch 543 selectively allows the sensing node to communicate with the bit line 545, and the voltage clamp structure 544 can set a voltage on the bit line. The bit line 545 is connected to one or more memory cells, such as memory cell MC2. The local bus LBUS2 allows the sensing circuit controller to communicate with components in the sensing circuit, such as in some cases communicating with the latch 551b and the voltage clamp structure. In order to communicate with the sensing circuit 551a, the sensing circuit controller provides a voltage to the transistor 506 via the line 501 to connect LBUS2 to DBUS.

[0093] Sense circuit 550a may be a first sense circuit including first trip latch 526 , and sense circuit 551a may be a second sense circuit including second trip latch 546 .

[0094] The sensing circuit 550a is an example of a first sensing circuit including a first sensing node 522, wherein the first sensing circuit is associated with the first memory cell MC1 and the first bit line 525. The sensing circuit 551a is an example of a second sensing circuit including a second sensing node 542, wherein the second sensing circuit is associated with the second memory cell MC2 and the second bit line 545.

[0095] Fig. 6A 1 is a perspective view of a group of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of FIG. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (storage elements), and a peripheral region 604 with circuits for use by the blocks. For example, the circuit may include a voltage driver 605 that can be connected to the control gate layer of the block. In one approach, the control gate layers at a common height in the block are driven together. The substrate 601 may also carry the circuit below the block, together with one or more lower metal layers, which are patterned in conductive paths to carry the signals of the circuit. The blocks are formed in the middle region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry the signals of the circuit. Each block includes a stacked region of memory cells, wherein the alternating layers of the stack represent word lines. In one possible approach, each block has an opposite layered side, and vertical contacts extend upward from the layered side to the upper metal layer to form a connection with the conductive path. Although four blocks are depicted as an example, two or more blocks extending in the x-direction and / or the y-direction may be used.

[0096] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends in one or more upper metal layers (the word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends in one or more upper metal layers (the bit line direction). The z-direction represents the height of the memory device.

[0097] Figure 6B Depicted Fig. 6A An exemplary cross-sectional view of a portion of one of the blocks of FIG. The block includes a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. In addition, a region of the stack including NAND strings NS1 and NS2 is depicted. Each NAND string covers a memory hole 618 or 619 that is filled with material that forms a memory cell adjacent to the word line. In FIG. Fig.6DThe stacked region 622 is shown in more detail in FIG.

[0098] The stack includes a substrate 611, an insulating film 612 on the substrate, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack. Metal-filled slits 617 and 620 may be provided periodically across the stack as interconnects extending through the stack, such as to connect the source line to a line above the stack. The slits may be used during the formation of the word lines and subsequently filled with metal. A portion of a bit line BL0 is also depicted. A conductive via 621 connects the drain terminal 615 to BL0.

[0099] Figure 6C Depicted Figure 6B A diagram of the diameter of the memory holes in a stack of. The vertical axis is Figure 6B The stack alignment is shown, and the width (wMH), e.g., diameter, of the memory hole 618 and the memory hole 619 is depicted. Fig. 6A The word line layers WLL0 to WLL10 of are repeated as examples and are at corresponding heights z0 to z10 in the stack. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth to diameter ratio of about 25 to 30 is common. The memory hole may have a circular cross-section. Due to the etching process, the width of the memory hole may vary along the length of the hole. Typically, the diameter of the memory hole tapers from its top to its bottom. That is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, there is a slight narrowing at the top of the hole near the select gate, so that the diameter of the memory hole widens slightly before tapering from its top to its bottom.

[0100] Due to the non-uniformity of the memory hole width, the programming speed including the programming slope and the erase speed of the memory cell may vary based on the position of the memory cell along the memory hole (e.g., based on the height of the memory cell in the stack). For memory holes of smaller diameter, the electric field across the tunnel oxide is relatively strong, so that the programming and erase speeds are relatively high. One method is to define a group of adjacent word lines with a similar diameter to the memory hole (e.g., within a defined diameter range) and apply an optimized verification scheme for each word line in the group. Different groups may have different optimized verification schemes.

[0101] Fig.6D Depicted Figure 6B622 of the stack. Memory cells are formed at different levels of the stack at the intersection of the word line layer and the memory hole. In this example, SGD transistors 680 and 681 are disposed above dummy memory cells 682 and 683 and data memory cells MC. Multiple layers may be deposited along the sidewalls (SW) of the memory hole 630 and / or within each word line layer (e.g., using atomic layer deposition). For example, each column (e.g., a column formed by the material within the memory hole) may include a charge trapping layer or film 663 (such as SiN or other nitride), a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layer may include a blocking oxide / block high-k material 660, a metal barrier layer 661, and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided in the memory hole. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form a pillar-shaped active area (AA) of the NAND string.

[0102] When programming a memory cell, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0103] Each of the memory holes may be filled with a plurality of annular layers, the annular layers including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are located between the core region and a word line in each of the memory holes.

[0104] The NAND string can be considered to have a floating channel because the length of the channel is not formed on the substrate. In addition, the NAND string is provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0105] Fig. 7A Depicted Figure 6B 00143] A top view of an exemplary word line layer WLL0 of a stack of. As mentioned, a 3D memory device may include a stack of alternating conductive layers and dielectric layers. The conductive layers provide control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, and the layer for the memory cells is the word line layer. In addition, memory holes are formed in the stack and filled with charge trapping material and channel material. Thus, a vertical NAND string is formed. The source line is connected to the NAND string below the stack and the bit line is connected to the NAND string above the stack.

[0106] The block BLK in the 3D memory device can be divided into sub-blocks, each of which includes a group of NAND strings with a common SGD control line. For example, refer to the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in the sub-blocks SBa, SBb, SBc, and SBd, respectively. The sub-blocks SBa, SBb, SBc, and SBd may also be referred to herein as strings of memory cells of word lines. As described, the strings of memory cells of word lines may include multiple memory cells belonging to the same sub-block and multiple memory cells that are also arranged in the same word line layer and / or configured to have their control gates biased by the same word line and / or using the same word line voltage.

[0107] In addition, the word line layer in the block can be divided into regions. Each region in the corresponding sub-block can extend between slits, which are periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. The processing may include replacing the sacrificial material of the word line layer with metal. Generally speaking, the distance between the slits should be relatively small to take into account the limitations of the distance that the etchant can travel laterally to remove the sacrificial material, and the metal can travel to fill the gap created by removing the sacrificial material. For example, the distance between the slits can allow for several rows of memory holes between adjacent slits. The layout of the memory holes and slits should also take into account the limitations on the number of bit lines that can extend across the region when each bit line is connected to a different memory cell. After processing the word line layer, the slits can optionally be filled with metal to provide interconnection through the stack.

[0108] This and other figures are not necessarily drawn to scale. In practice, the region may be longer in the x-direction relative to the y-direction than depicted to accommodate additional memory holes.

[0109] In this example, there are four rows of memory holes between adjacent slits. A row here is a group of memory holes aligned in the x-direction. In addition, the rows of memory holes are arranged in a staggered pattern to increase the density of the memory holes. The word line layer or word line is divided into regions WLL0 a, WLL0 b, WLL0 c, and WLL0 d, each connected by a connector 713. In one approach, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. The connector is in turn connected to the voltage driver of the word line layer. Region WLL0 a has exemplary memory holes 710 and 711 along line 712. Region WLL0 b has exemplary memory holes 714 and 715. Region WLL0 c has exemplary memory holes 716 and 717. Region WLL0 d has exemplary memory holes 718 and 719. The memory holes are also Figure 7BEach memory hole can be part of a corresponding NAND string. For example, memory holes 710, 714, 716, and 718 can be part of NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, respectively.

[0110] Each circle represents a cross section of a memory hole at a word line layer or SG layer. The exemplary circles shown with dashed lines represent memory cells provided by the material in the memory hole and the adjacent word line layer. For example, memory cells 720 and 721 are in WLL0 a, memory cells 724 and 725 are in WLL0 b, memory cells 726 and 727 are in WLL0 c, and memory cells 728 and 729 are in WLL0 d. These memory cells are at a common height in the stack.

[0111] Metal-filled slots 701, 702, 703, and 704 (e.g., metal interconnects) may be located between and adjacent to the edges of regions WLL0a to WLL0d. The metal-filled slots provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a wire above the stack, where the wire is connected to a voltage driver in a peripheral region of the memory device. See also Fig. 8A learn Fig. 7A More details of sub-blocks SBa to SBd.

[0112] Figure 7B Depicted Figure 6B 1. A top view of an exemplary top dielectric layer DL19 of a stack of . The dielectric layer is divided into regions DL19 a, DL19 b, DL19 c, and DL19 d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in one region of the word line layer to be programmed simultaneously, where each memory cell is in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to allow or prohibit programming during each programming voltage.

[0113] Region DL19a has exemplary memory holes 710 and 711 along line 712a that coincides with bit line BL0. Many bit lines extend over and connect to the memory holes, as indicated by the "X" symbol. BL0 connects to a group of memory holes that includes memory holes 711, 715, 717, and 719. Another exemplary bit line BL1 connects to a group of memory holes that includes memory holes 710, 714, 716, and 718. Also depicted are Fig. 7A The metal filled slots 701, 702, 703 and 704 in the stack as they extend vertically through the stack. The bit lines may be numbered in the order BL0 to BL23 across the DL19 layer in the x-direction.

[0114] Different subsets of the bit lines are connected to cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to cells in the first row of cells at the right hand edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to cells in an adjacent row of cells adjacent to the first row at the right hand edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to cells in the first row of cells at the left hand edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to cells in an adjacent row of cells adjacent to the first row at the left hand edge.

[0115] Fig. 8A Depicted Fig. 7A An exemplary NAND string in sub-blocks SBa to SBd. Figure 6B The conductive layers in the stack are depicted for reference on the left hand side. Each sub-block includes multiple NAND strings, of which one example NAND string is depicted. For example, SBa includes an example NAND string NS0_SBa, SBb includes an example NAND string NS0_SBb, SBc includes an example NAND string NS0_SBc, and SBd includes an example NAND string NS0_SBd.

[0116] In addition, NS0_SBa includes SGS transistors 800 and 801 , dummy memory cells 802 and 803 , data memory cells 804 , 805 , 806 , 807 , 808 , 809 , 810 , 811 , 812 , 813 and 814 , dummy memory cells 815 and 816 , and SGD transistors 817 and 818 .

[0117] NS0_SBb includes SGS transistors 820 and 821 , dummy memory cells 822 and 823 , data memory cells 824 , 825 , 826 , 827 , 828 , 829 , 830 , 831 , 832 , 833 , and 834 , dummy memory cells 835 and 836 , and SGD transistors 837 and 838 .

[0118] NS0_SBc includes SGS transistors 840 and 841 , dummy memory cells 842 and 843 , data memory cells 844 , 845 , 846 , 847 , 848 , 849 , 850 , 851 , 852 , 853 , and 854 , dummy memory cells 855 and 856 , and SGD transistors 857 and 858 .

[0119] NS0_SBd includes SGS transistors 860 and 861 , dummy memory cells 862 and 863 , data memory cells 864 , 865 , 866 , 867 , 868 , 869 , 870 , 871 , 872 , 873 , and 874 , dummy memory cells 875 and 876 , and SGD transistors 877 and 878 .

[0120] At a given height in the block, a group of memory cells in each sub-block is at a common height. For example, a group of memory cells (including memory cell 804) is formed in a plurality of memory cells along a tapered memory hole in a stack of alternating conductive layers and dielectric layers. A group of memory cells is at a specific height z0 in the stack. Another group of memory cells (including memory cell 824) connected to one word line (WLL0) is also at a specific height. In another approach, a group of memory cells (e.g., including memory cell 812) connected to another word line (e.g., WLL8) is at another height (z8) in the stack.

[0121] Figure 8B Another exemplary view of NAND strings in a sub-block is depicted. The NAND strings include NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, which have 48 word lines WL0 to WL47 in this example. Each sub-block includes a group of NAND strings that extend along the x-direction and have a common SGD line, such as SGD0, SGD1, SGD2, or SGD3. In this simplified example, there is only one SGD transistor and one SGS transistor in each NAND string. The NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd are in sub-blocks SBa, SBb, SBc, and SBd, respectively. In addition, an exemplary group of word lines G0, G1, and G2 is depicted.

[0122] Figure 8C Schematic diagrams of three types of interleaved string architectures 101, 103, 105 for BiCS memory (e.g., NAND) are generally shown. Referring to string architecture 101, strings are shown in rows 107-0 to 107-7 in architecture 101. Each row is shown as having four ends of a string. The string can be connected to an adjacent string at the end (not visible below this view). The first group of rows 107-0 to 107-3 is shown to be located on the left side of dummy row 108. The second group of rows 107-4 to 107-7 is shown to be located on the right side of dummy row 108. Dummy row 108 separates two groups of rows in eight interleaved rows. Source line 109 is positioned at the edge of the first group and away from dummy row 108. Source line 110 is positioned at the edge of the second group and away from dummy row 108 and source line 109.

[0123] The interleaved string architecture 103, 105 of the BiCS memory is similar to the interleaved string architecture of architecture 101, except that the former adds additional groups. Architecture 103 is twice the size of architecture 101 and includes sixteen rows of strings, where each group of four rows is separated by a dummy row. Architecture 105 is larger than both architecture 101 and architecture 103. Architecture 105 includes twenty rows of strings, where each group of four rows is separated by a dummy row 108.

[0124] These architectures 101, 103, 105 may include a chip below the array structure, for example, the control circuit is below the memory array which may include a group of memory strings. With a chip below the array structure, the strings may include direct strap contacts for the source lines for read and erase operations.

[0125] Fig.12 Waveforms for an exemplary programming operation are depicted. The horizontal axis depicts the programming loop number, and the vertical axis depicts the control gate or word line voltage. In general, a programming operation may involve applying a pulse train to a selected word line, where the pulse train includes a plurality of programming loops or program-verify (PV) iterations. The programming portion of a program-verify iteration includes a programming voltage, and the verify portion of a program-verify iteration includes one or more verify voltages.

[0126] For each programming voltage, a square wave is depicted for simplicity, but other shapes are possible, such as a multi-level shape or a ramp shape. In addition, incremental step pulse programming (ISPP) is used in this example, where the programming voltage is incremented in each consecutive programming cycle. This example uses ISPP in a single programming stage in which programming is completed. ISPP can also be used in each programming stage of a multi-stage operation.

[0127] The pulse train typically includes programming voltages that are gradually increased in amplitude using a fixed or variable step size in each programming-verification iteration. A new pulse train can be applied to each programming stage of a multi-stage programming operation, starting with an initial Vpgm level and ending at a final Vpgm level that does not exceed the maximum allowed level. In different programming stages, the initial Vpgm level may be the same or different. In different programming stages, the final Vpgm level may be the same or different. In different programming stages, the step size may be the same or different. In some cases, a smaller step size is used in the final programming stage to reduce the Vth distribution width.

[0128] The pulse train 900 includes a series of programming voltages 901, 902, 903, 904, 905, 906, 907, 908, 909, 910, 911, 912, 913, 914, and 915 applied to the word lines selected for programming, and an associated group of non-volatile memory cells. As an example, one, two, or three verification voltages are provided after each programming voltage based on the target data state being verified. 0V may be applied to the selected word line between the programming voltage and the verification voltage. For example, an A-state verification voltage (e.g., waveform or programming signal 916) of VvA may be applied after each of the first programming voltage 901, the second programming voltage 902, and the third programming voltage 903, respectively. An A-state verification voltage of VvA and a B-state verification voltage (e.g., programming signal 917) of VvB may be applied after each of the fourth programming voltage 904, the fifth programming voltage 905, and the sixth programming voltage 906, respectively. The A-state verification voltage of VvA, the B-state verification voltage of VvB, and the C-state verification voltage of VvC (e.g., programming signal 918) may be applied after each of the seventh programming voltage 907 and the eighth programming voltage 908, respectively. The B-state verification voltage of VvB and the C-state verification voltage of VvC (e.g., programming signal 919) may be applied after each of the ninth programming voltage 909, the tenth programming voltage 910, and the eleventh programming voltage 911, respectively. Finally, the C-state verification voltage of VvC (e.g., programming signal 1020) may be applied after each of the twelfth programming voltage 912, the thirteenth programming voltage 913, the fourteenth programming voltage 914, and the fifteenth programming voltage 915, respectively.

[0129] Fig.13A and Fig. 13B 2 shows the threshold voltage (Vth) distribution of memory cells in an exemplary two-phase programming operation. Specifically, the memory cell is initially in an erased state (bit 11), as shown in FIG. Fig.13A This is represented by the Vth distribution 1100 shown. Fig. 13B Depicted are the Vth distributions of memory cells after the first and second programming phases of an exemplary two-phase programming operation with four data states. Although two programming phases and four data states are shown, it should be understood that any number of programming phases (e.g., three or four programming phases) can be utilized and any number of data states are contemplated.

[0130] In this example, the first programming phase uses first verification voltages VvAf, VvBf, and VvCf, respectively, to bring the Vth of A-state cells, B-state cells, and C-state cells to Vth distributions 1002a, 1004a, and 1006a. The first programming phase can be coarse programming, using, for example, a relatively large step size, so that Vth distributions 1002a, 1004a, and 1006a are relatively wide. The second programming phase can use a smaller step size and make Vth distributions 1002a, 1004a, and 1006a transition to final Vth distributions 1002, 1004, and 1006 (e.g., narrower than Vth distributions 1002a, 1004a, and 1006a) using second verification voltages of VvA, VvB, and VvC, respectively. This two-stage programming operation can achieve a relatively narrow Vth distribution. Due to the bit ignore criteria, a small number of A-state cells, B-state cells, and C-state cells (eg, a plurality of memory cells less than a predetermined number) may have a Vth lower than VvA, VvB, or VvC, respectively.

[0131] In addition, the programming operation may also include a precharge phase. During the precharge phase, the channels of the NAND strings in the 3D stacked memory device may be prepared for programming. For example, the CPWELL precharge technique may be used to improve the reverse programming (ROP) erase tail by supplying holes into the channel. To illustrate, a typical architecture of a memory device using a NAND flash memory structure includes multiple NAND strings within a memory block. In some cases, the NAND strings within a memory block may share a common well (e.g., a p-well). As Fig.14A As shown, the BiCS cell next to the array (CNA) structure includes a p-well below a vertical memory hole or pillar. The memory hole extends vertically in the stack and includes the memory cell, such as in a vertical NAND string. Fig.14A As shown, by applying a positive voltage (eg, 2.2V) to the p-well, holes are pushed into the channel, helping to pre-charge the channel, thereby improving the boosting potential.

[0132] Fig. 14B An exemplary embodiment of a BiCS CMOS Under Array (CUA) structure is provided. Fig. 14B , the NAND string is connected to a common source line through its source side select transistor SGS1 (e.g., controlled by select line SGS1), and is connected to its associated bit line through its drain side select transistor SGD1 (e.g., controlled by select line SGD1). For illustrative purposes, Fig. 14BThe BiCS CMOS CUA structure in is shown as including select gates SGS0, SGS1, SGD0, and SGD1. However, according to the embodiments described herein, the BiCS CMOS CUA structure may be in any number of select gates.

[0133] like Fig. 14B As further shown in , the BiCS CUA structure does not include a p-well for supplying holes. Therefore, the CPWELL pre-charge technique cannot be implemented on the BiCS CUA structure.

[0134] Embodiments described herein provide an alternative technique for boost potential improvement of the ROP for a BiCS CUA architecture. More specifically, embodiments described herein relate to a precharge scheme using gate induced drain leakage (GIDL) generation. For example, a select gate transistor of a NAND string may be used to generate a hole current from the GIDL during a precharge cycle of a programming operation.

[0135] In some embodiments, such as Fig. 14B As shown, a negative bias (e.g., -Ve) may be applied to the gate of the select transistor SGS1 of the NAND string to generate GIDL during the precharge phase of the programming operation. In some embodiments, the SDS / WLDS of the NAND string is biased to ground. In addition, in some embodiments, and with continued reference to Fig. 14B , a larger positive voltage may be applied to the source line connected to the end of the select gate transistor SGS1 to generate GIDL. These precharge schemes achieve a gate-source voltage difference that can induce a GIDL current at the drain side of the SGS1 transistor. Again, in some embodiments, and with continued reference to Fig. 14B , a negative bias may be applied to the gate of the select gate transistor SGD1 of the NAND string to generate GIDL. This precharge scheme achieves a gate-source voltage difference that can induce a GIDL current at the drain side of the SGD1 transistor.

[0136] In some embodiments, the foregoing may be implemented by a controller, a control circuit, a processor, etc., as described in other parts of this document. For example, Figure 1A The control circuit 110 in the embodiment may be configured to perform a precharge operation before a programming operation, including applying a voltage to a selection line connected to the gate of the selection transistor SGS1 to generate GIDL. Figure 1A The control circuit 110 in the embodiment may be configured to perform a precharge operation including applying a voltage to a source line connected to one end of the selection transistor SGS1 to generate GIDL. In another example, Figure 1AThe control circuit 110 in may be configured to perform a precharge operation including applying a voltage to the gate of the selection transistor SGD1 to generate GIDL.

[0137] To explore this further, we will now describe FIG. 15A to FIG. 15D . Fig.15A , Fig. 15B , Fig. 15C and Fig.15D is a signal timing diagram of an exemplary implementation of the hole pre-charging scheme generated using GIDL for the BiCS CUA architecture described above. For example, Fig.15A FIG. 2 shows a hole precharge after a conventional CELSRC precharge (also referred to as “SGS1GIDL”). Fig.15A As shown, CELSRC precharge occurs from P5 to P7, while hole precharge occurs from P8 to P9 (by biasing the gate of SGS1 to -Ve). For example, hole precharge occurs after CELSRC precharge by turning the select line connected to the gate of select transistor SGS1 to a negative bias. In contrast, in Fig. 15B In this embodiment, CELSRC precharge does not occur, and hole precharge occurs from P4 to P9 (by biasing the gate of SGS1 to -Ve). In this embodiment, a longer time is provided for the hole GIDL current to be generated, thereby improving the boost potential. Fig.14A and Fig. 14B A similar scheme is implemented by selecting transistor SGD1 in FIG.

[0138] exist Fig. 15C In , CELSRC precharge occurs from P5 to P7, and hole precharge occurs from P8 to P9 (by applying PROGSRC_PCH2 at P8 to the source line connected to the source side of SGS1, where PROGSRC_PCH2>PROGSRC_PCH1). In contrast, in Fig.15D In , CELSRC precharge does not occur, and hole precharge occurs from P4 to P9 (by applying PROGSRC_PCH2 at P5 to the source line connected to the source side of SGS1). FIG. 15A to FIG. 15D Provided for illustration purposes only. In some implementations, hole precharge can occur at other times during the precharge phase of a programming operation.

[0139] As described, the GIDL current can be generated by applying a negative bias on the gate of the select transistor of the NAND string or by applying a larger positive source voltage to the source line connected to the source side of the select transistor of the NAND string. A higher GIDL current reduces the channel electron density after precharge and improves the boost potential under the channel. However, to reduce the GIDL requirement, a longer precharge time (such as Fig. 15B and Fig.15D shown).

[0140] The above specific embodiments of the present invention have been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments are selected to best explain the principles of the present invention and its practical application, so that other technical personnel in the field can best utilize the present invention in various embodiments and in various modifications suitable for the intended specific use. The scope of the present invention is intended to be limited by the appended claims.

Claims

1. A memory device, the memory device include: a memory string including a first selection transistor, a memory cell transistor, and a second selection transistor connected in series; a bit line connected to one end of the first selection transistor; a source line connected to one end of the second selection transistor; a first selection line connected to a gate of the first selection transistor; a word line connected to a gate of the memory cell transistor; a second selection line connected to a gate of the second selection transistor; and A control circuit, the control circuit being configured to perform a precharge operation before a programming operation, the precharge operation comprising: A negative voltage is applied to the second select line connected to the gate of the second select transistor to cause gate induced drain leakage from the second select transistor.

2. The memory device of claim 1 , wherein the precharge operation further comprises: include: A positive voltage is applied to the source line connected to one end of the second selection transistor.

3. The memory device of claim 1 , wherein the precharge operation further comprises: include: The word line connected to the gate of the memory cell transistor is biased to ground.

4. The memory device of claim 1 , wherein the precharge operation further comprises: include: A voltage is applied to the first select line connected to the gate of the first select transistor to cause gate induced drain leakage from the first select transistor. 5 . The memory device of claim 4 , wherein the voltage applied to the first selection line connected to the gate of the first selection transistor is negative.

6. A memory device, the memory device include: a memory string including a first selection transistor, a memory cell transistor, and a second selection transistor connected in series; a bit line connected to one end of the first selection transistor; a source line connected to one end of the second selection transistor; a first selection line connected to a gate of the first selection transistor; a word line connected to a gate of the memory cell transistor; a second selection line connected to a gate of the second selection transistor; and A control circuit, the control circuit being configured to perform a precharge operation before a programming operation, the precharge operation comprising: A positive voltage is applied to the source line connected to one end of the second selection transistor to cause gate induced drain leakage from the second selection transistor, wherein the positive voltage has a higher value than a voltage previously applied to the source line and a voltage applied to the second selection line connected to the gate of the second selection transistor.

7. The memory device of claim 6, wherein the precharge operation further include: A voltage is applied to the first select line connected to the gate of the first select transistor to cause gate induced drain leakage from the first select transistor. 8 . The memory device of claim 7 , wherein the voltage applied to the first selection line connected to the gate of the first selection transistor is negative.

9. The memory device of claim 6, wherein the precharge operation further include: The word line connected to the gate of the memory cell transistor is biased to ground.

10. A memory device, the memory device include: a memory string including a first selection transistor, a memory cell transistor, and a second selection transistor connected in series; a bit line connected to one end of the first selection transistor; a source line connected to one end of the second selection transistor; a first selection line connected to a gate of the first selection transistor; a word line connected to a gate of the memory cell transistor; a second selection line connected to a gate of the second selection transistor; and A control circuit, the control circuit being configured to perform a precharge operation before a programming operation, the precharge operation comprising: A negative voltage is applied to the first select line connected to the gate of the first select transistor to cause gate induced drain leakage from the first select transistor.

11. The memory device of claim 10, wherein the precharge operation further include: The word line connected to the gate of the memory cell transistor is biased to ground.

12. The memory device of claim 10 , wherein the precharge operation further comprises: include: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate induced drain leakage from the second select transistor, Wherein the voltage applied to the second selection line connected to the gate of the second selection transistor is negative.

13. The memory device of claim 10 , wherein the precharge operation further comprises: include: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate induced drain leakage from the second select transistor, wherein the precharge operation further comprises: A positive voltage is applied to the source line connected to one end of the second selection transistor.

Images