Identification method for photolithography process and semiconductor device

Abstract

The present invention provides an identification method and a semiconductor element used in a photolithography process. The method includes forming a mask layer on a semiconductor substrate, patterning the mask layer to form a dense line pattern in the element region, and forming a pseudo dense line pattern in the interface region between the element region and the peripheral region, wherein at least one connecting portion is provided between the first and third pseudo dense line patterns, and the second pseudo dense line pattern is discontinuous at the connecting portion and separated from the connecting portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether the landing position of the photoresist layer is correct is determined based on the distance from the edge of the photoresist layer to the closest pseudo dense line pattern and the width of the connecting portion.

Description

Technical Field

[0001] The invention relates to a semiconductor process technology, and in particular to an identification method and a semiconductor element used in a photolithography process. Background Art

[0002] Lithography is an important technology in the manufacturing process of semiconductor components. Everything related to the structure of metal oxide semiconductor components, such as the patterns of each layer of thin film and the area doped with impurities, is determined by the lithography step. Generally speaking, the lithography process includes photoresist coating, exposure step and development step. Among them, the exposure step is to make the light source irradiate the photoresist through the mask, so that the exposed area of ​​the photoresist produces photochemical changes. After the baking step and the development step, the mask pattern can be transferred to the photoresist to form a patterned photoresist layer.

[0003] As the integration of integrated circuits increases, the size (line width) of the entire semiconductor device also shrinks. Therefore, in order to cope with the miniaturization of device size, a self-aligned double patterning (SADP) process has been developed to overcome the limitations of the current photolithography process, so that the line width / line spacing (line / space) can be further reduced to the nanometer level, thereby achieving the purpose of device miniaturization.

[0004] However, during the SADP process, since the dense line mask formed on the semiconductor substrate usually has a consistent line width and line spacing, it is difficult to distinguish the different graphics produced by the SADP process (core-gap recognition). It is also not easy to distinguish the boundary between the cell region and the periphery region, which affects the landing position of the subsequent patterned photoresist layer.

[0005] In addition, the landing position (edge) of the patterned photoresist layer has been set in the device design stage, so a method is urgently needed to identify whether the landing position of the photoresist layer is incorrect online. Summary of the invention

[0006] The present invention is directed to an identification method for photolithography process, which can directly determine the boundary between a component area and a peripheral area and identify online whether the landing position of a photoresist layer is wrong.

[0007] The present invention is also directed to a semiconductor element, which is a semiconductor element with a specific structure manufactured by using the above identification method.

[0008] According to an embodiment of the present invention, a recognition method for a photolithography process includes forming a mask layer on a semiconductor substrate having a component region and a peripheral region, and then patterning the mask layer to form a plurality of dense line patterns in the component region, and forming a plurality of pseudo dense line patterns in the interface region between the component region and the peripheral region, wherein at least one connection portion is provided between the first pseudo dense line pattern and the third pseudo dense line pattern, and the second pseudo dense line pattern is discontinuous at the connection portion and separated from the connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether the landing position of the photoresist layer is correct is determined based on the distance from the edge of the photoresist layer to the closest pseudo dense line pattern and the width of the connection portion.

[0009] In the identification method according to an embodiment of the present invention, when the above-mentioned photoresist layer is set to cover the third fake dense line pattern, if the distance from the edge of the photoresist layer to the nearest fake dense line pattern is less than the distance between the third fake dense line pattern and the second fake dense line pattern, it is determined that the landing position of the photoresist layer is incorrect.

[0010] In the identification method according to an embodiment of the present invention, when the photoresist layer is set to cover the third pseudo dense line pattern, if a critical dimension scanning electron microscope (CD-SEM) is used but a measurement value cannot be obtained, it is determined that the landing position of the photoresist layer is incorrect.

[0011] In the identification method according to an embodiment of the present invention, when the above-mentioned photoresist layer is set to cover the second fake dense line pattern, if the distance from the edge of the photoresist layer to the nearest fake dense line pattern is less than the distance between the first fake dense line pattern and the second fake dense line pattern, it is determined that the landing position of the photoresist layer is incorrect.

[0012] In the identification method according to an embodiment of the present invention, when the photoresist layer is set to cover the second pseudo dense line pattern, if a critical dimension scanning electron microscope (CD-SEM) is used but a measurement value cannot be obtained, it is determined that the landing position of the photoresist layer is incorrect.

[0013] In the identification method according to the embodiment of the present invention, the method may further include estimating a critical dimension (CD) value of the photoresist layer according to a value of a distance from an edge of the photoresist layer to the closest pseudo dense line pattern.

[0014] In the identification method according to the embodiment of the present invention, the method may further include measuring the overlap amount according to the difference in the values ​​of the distances of opposite sides (from the edge of the photoresist layer to the closest pseudo dense line pattern).

[0015] In the identification method according to the embodiment of the present invention, the method of patterning the mask layer includes a self-aligned double patterning (SADP) process.

[0016] According to another embodiment of the present invention, a semiconductor element includes a semiconductor substrate having an element region and a peripheral region, a plurality of dense line structures and a truncated circuit. The dense line structure is formed in or on the semiconductor substrate, and the dense line structure is a structure obtained by performing an etching process or a deposition process using the dense line pattern in the above method as a mask, and the dense line structure and the dense line pattern are complementary patterns. The truncated circuit is arranged at the interface between the dense line structure and the peripheral region, and the truncated circuit is a structure obtained by performing the above etching process or the above deposition process using the photoresist layer and the pseudo dense line pattern in the above method as a mask. The truncated circuit and the first to third pseudo dense line patterns are complementary patterns, and the truncated circuit has at least one truncated portion complementary to at least one connecting portion in the pseudo dense line pattern.

[0017] In a semiconductor device according to another embodiment of the present invention, the dense line structure includes a buried word line (BWL), a bit line (BL) or a shallow trench isolation (STI) structure.

[0018] In a semiconductor device according to another embodiment of the present invention, a line width of the cutoff line is the same as a line width of the dense line structure.

[0019] In a semiconductor device according to another embodiment of the present invention, the cutoff line includes a plurality of extension portions adjacent to the cutoff portion and extending toward the peripheral region.

[0020] In a semiconductor device according to another embodiment of the present invention, the cutoff circuit is composed of a plurality of closed loops, and the cutoff portion is disposed between two closed loops.

[0021] In a semiconductor device according to another embodiment of the present invention, a line width of each of the closed loops is the same as a line width of the dense line structure.

[0022] Based on the above, the present invention uses a mask layer with a specific pattern to perform a photolithography process, which can not only directly determine the boundary between the component area and the peripheral area, but also can identify online whether the landing position of the photoresist layer is incorrect. In addition, the above identification method can also be applied to critical dimension (CD) detection and overlap detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0024] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A is a schematic top view of a manufacturing process of an identification method for a photolithography process according to a first embodiment of the present invention;

[0025] Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B yes Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A Schematic diagram of the cross section on the X-X' line segment;

[0026] Figure 1C , Figure 2C , Figure 3C , Figure 4C , Figure 5C and Figure 6C yes Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A Schematic diagram of the cross section on the Y-Y' line segment;

[0027] Fig. 7A is a top view schematically showing a semiconductor device according to a second embodiment of the present invention.

[0028] Figure 7B yes Fig. 7A Schematic diagram of the cross section on the line segment X-X';

[0029] Figure 7C yes Fig. 7A Schematic diagram of the cross section on the Y-Y' line segment;

[0030] Fig. 8A is a top view schematically showing a method for identifying a photolithography process according to a third embodiment of the present invention;

[0031] Figure 8B yes Fig. 8A Schematic diagram of the cross section on the line segment X-X';

[0032] Figure 8C yes Fig. 8A Schematic diagram of the cross section on the Y-Y' line segment;

[0033] Fig. 9is a top view schematically showing a semiconductor device according to a fourth embodiment of the present invention;

[0034] Fig. 10A is a top view of the first embodiment applied to critical dimension (CD) detection;

[0035] Fig. 10B It is a top view applied to overlap detection in the first embodiment.

[0036] Description of Figure Numbers

[0037] 10a: component area;

[0038] 10b: peripheral area;

[0039] 100: semiconductor substrate;

[0040] 102: mask layer;

[0041] 102a, 102b, 102c, 102d, 102e, 102e', 102f, 102g, 102h: material layer;

[0042] 104: Linear pattern;

[0043] 106: connect block;

[0044] 108: gap wall;

[0045] 110: oxide layer;

[0046] 112: dense line pattern;

[0047] 114, 1141, 1142, 1143: false dense line pattern;

[0048] 116: connecting portion;

[0049] 118: photoresist layer;

[0050] 118a: edge;

[0051] 700, 900: semiconductor components;

[0052] 702, 902: dense line structure;

[0053] 704, 904: cut off the line;

[0054] 706: channel;

[0055] 708, 906: truncation part. DETAILED DESCRIPTION

[0056] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A It is a schematic top view of a manufacturing process of an identification method for a photolithography process according to a first embodiment of the present invention. Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B yes Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A Schematic diagram of the cross section along the line segment XX'. Figure 1C , Figure 2C , Figure 3C , Figure 4C , Figure 5C and Figure 6C yes Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A and Fig. 6A Schematic diagram of the cross section along the Y-Y' line segment.

[0057] Please refer to Figure 1A , Figure 1B and Figure 1CA mask layer 102 is formed on a semiconductor substrate 100 having a device region 10a and a peripheral region 10b. The semiconductor substrate 100 may be formed of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP. In addition, in one embodiment, although not shown, a device isolation structure (such as STI), a doped region (such as a well region), etc. may be formed in the semiconductor substrate 100. The mask layer 102 may be composed of several material layers 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h with different etching selectivities. For example, adjacent material layers are different from each other, and non-adjacent materials may be the same or different. In one embodiment, the materials of the material layers 102a-h from bottom to top are, for example, PE-TEOS silicon oxide, diamond-like carbon (DLC), nitrogen-rich silicon oxynitride (N-SiON), silicon-rich silicon oxynitride (Si-SiON), DLC, oxygen-rich silicon oxynitride (O-SiON), spin-on carbon (SOC), and spin-on self-assembly (SOSA) materials; however, the present invention is not limited thereto, and the selection and arrangement of the aforementioned materials can be changed according to requirements, and some material layers can be omitted; or other material layers can be added to the aforementioned material layers 102a-h. Then, in order to pattern the mask layer 102, the material layers 102g and 102h can be patterned by a photolithography process, such as a self-aligned double patterning (SADP) process, to form a plurality of line patterns 104, and a connection block 106 is simultaneously formed between the first and second line patterns 104 adjacent to the interface of the device region 10a and the peripheral region 10b.

[0058] Next, please refer to Figure 2A , Figure 2B and Figure 2C Spacers 108 are formed on the sidewalls of the linear pattern 104 and the sidewalls of the connecting block 106. The forming method thereof is, for example, to conformally deposit the material of the spacers 108 on each of the linear pattern 104 and the connecting block 106, and then to etch back the material layer until the material layer 102f is exposed. The material of the spacers 108 is, for example, silicon oxide or other suitable materials, and the deposition method is, for example, chemical vapor deposition.

[0059] Then, please refer to Figure 3A , Figure 3B and Figure 3CAfter removing the linear pattern and the connecting blocks (104 and 106 in the previous figure), the spacer (108 in the previous figure) is used as an etching mask to transfer its pattern to the exposed material layer (102f in the previous figure), and then the patterned material layer is used as an etching mask to transfer its pattern to the underlying material layer (102e in the previous figure) to form a patterned material layer 102e' and expose the material layer 102d. The material layer above the patterned material layer 102e' can also be removed after this step. The above removal step is, for example, a dry etching process or a wet etching process.

[0060] Afterwards, please refer to Figure 4A , Figure 4B and Figure 4C , depositing an oxide layer 110 on the semiconductor substrate 100, and etching back the oxide layer 110 to expose the top of the patterned material layer 102e'. The oxide layer 110 may be deposited by, for example, chemical vapor deposition.

[0061] Next, please refer to Figure 5A , Figure 5B and Figure 5C After removing the patterned material layer (102e' in the previous figure), the oxide layer 110 is used as an etching mask to transfer its pattern to the exposed material layer (102d in the previous figure), thereby forming a patterned material layer 102d' and exposing the material layer 102c. The above-mentioned removal step is, for example, a dry etching process or a wet etching process.

[0062] The oxide layer 110 and the patterned material layer 102d' at this stage can be regarded as the mask layer after patterning, because the material layers 102a~c below maintain the same pattern in the device area 10a in the subsequent process, wherein the oxide layer 110 and the patterned material layer 102d' in the device area 10a constitute a plurality of dense line patterns 112, and a plurality of dummy dense line patterns 114 are distributed in the interface area between the device area 10a and the peripheral area 10b, and the dummy dense line patterns 114 are also distributed in the peripheral area 10b. Here, the so-called "dummy" refers to a structure that will be removed by the subsequent replacement process or a structure without function. At least one connecting portion 116 is provided between the first dummy dense line pattern 1141 and the third dummy dense line pattern 1143, and the second dummy dense line pattern 1142 is discontinuous in the connecting portion 116 and is separated from the connecting portion 116.

[0063] Then, please refer to Fig. 6A , Figure 6B and Figure 6C A photoresist layer 118 covering the peripheral region 10b is formed on the semiconductor substrate 100, and for the sake of clarity, the photoresist layer 118 is omitted. Fig. 6AThe X-X' and Y-Y' in the figure are indicated. Due to the existence of the connecting portion 116, the boundary between the component area 10a and the peripheral area 10b can be directly determined by visual inspection (such as OM or SEM image). Afterwards, based on the distance d1 from the edge 118a of the photoresist layer 118 to the closest pseudo dense line pattern 1142 and the width w of the connecting portion 116, it can be determined whether the landing position of the photoresist layer 118 is correct. Here, the "width" of the connecting portion 116 refers to the size of the connecting portion 116 parallel to the extension direction of the pseudo dense line pattern 114.

[0064] Specifically, when the photoresist layer 118 is set to cover the third pseudo dense line pattern 1143, if the distance d1 from the edge 118a of the photoresist layer 118 to the closest pseudo dense line pattern 1142 is less than the distance d2 between the third pseudo dense line pattern 1143 and the second pseudo dense line pattern 1142, it is determined that the landing position of the photoresist layer 118 is incorrect; a more precise setting is pre-set that the edge 118a of the photoresist layer 118 should land in the center of the third pseudo dense line pattern 1143, then once the distance d1 from the edge 118a of the photoresist layer 118 to the closest pseudo dense line pattern 1142 is not equal to the sum of the distance d2 and half the line width of the third pseudo dense line pattern 1143, it means that the landing position of the photoresist layer 118 is incorrect. However, the present invention is not limited to this, and the above setting may also have an allowable range.

[0065] In addition, if the edge 118a of the photoresist layer 118 is offset to the second pseudo dense line pattern 1142, the distance d1 may still meet the above-mentioned standard value. Therefore, it is necessary to perform a double check by measuring the width w of the connecting portion 116. Since the measurement is generally performed using an instrument such as a critical dimension scanning electron microscope (CD-SEM) for the set landing position, Fig. 6A The measurement landing position of the width w shown is set at a fixed distance from the edge 118a. Once the edge 118a shifts to the second pseudo dense line pattern 1142, the instrument will not be able to obtain the measurement value and will determine that the landing position of the photoresist layer 118 is incorrect.

[0066] In another embodiment, when the photoresist layer 118 is set to cover the second pseudo dense line pattern 1142, if the distance from the edge 118a of the photoresist layer 118 to the closest pseudo dense line pattern 1141 is less than the distance between the first pseudo dense line pattern 1141 and the second pseudo dense line pattern 1142, it is determined that the landing position of the photoresist layer 118 is incorrect. Even if the above determination is passed, the width w of the connecting portion 116 still needs to be measured using CD-SEM. If the measurement value cannot be obtained, it is determined that the landing position of the photoresist layer 118 is incorrect, and so on.

[0067] Fig. 7A is a top view schematically showing a semiconductor device according to a second embodiment of the present invention; Figure 7B yes Fig. 7A Schematic diagram of the cross section on the line segment X-X'; Figure 7C yes Fig. 7A Moreover, the second embodiment uses the same reference numerals as the first embodiment to indicate the same components, and the technical contents not described can refer to the above description, so they will not be repeated.

[0068] Please refer to Fig. 7A , Figure 7B and Figure 7C The semiconductor device 700 of the second embodiment includes a semiconductor substrate 100 having a device region 10a and a peripheral region 10b, a plurality of dense line structures 702 and a cutoff line 704. The semiconductor device 700 is a semiconductor device that utilizes Fig. 6A The photoresist layer 118, the dummy dense line pattern 114 and the dense line pattern 112 are used as masks to perform a series of etching processes to first form a channel 706 in the semiconductor substrate 100, and then remove the remaining material layers above the material layer 102a and fill them with conductive materials, so that the dense line structure 702 and Fig. 6A The dense line pattern 112 is a complementary pattern. The cut-off line 704 is arranged at the interface between the dense line structure 702 and the peripheral area 10b. The cut-off line 704 is formed by Fig. 6A The photoresist layer 118 and the pseudo dense line pattern 114 are used as a mask, so the cutoff line 704 and Fig. 6A The first to third pseudo dense line patterns 1141-1143 are complementary patterns, and the cutoff line 704 has the same Fig. 6A At least one truncated portion 708 is complementary to the connecting portion 116. Fig. 7A In the embodiment, the cutoff line 704 is composed of two closed loops, and the cutoff portion 708 is disposed between the two closed loops, and the line width of each closed loop may be the same as or different from the line width of the dense line structure 702. In the present embodiment, the dense line structure 702 is, for example, a buried word line (BWL); however, the present invention is not limited thereto, and the dense line structure 702 may also be a shallow trench isolation structure (STI) or a bit line (BL). If the dense line structure 702 is an STI, the trench 706 is filled with an insulating material; if the dense line structure 702 is a BL, the trench 706 may not be formed, but may be directly deposited on the semiconductor substrate 100.

[0069] Fig. 8A is a top view schematically showing a method for identifying a photolithography process according to a third embodiment of the present invention; Figure 8B yes Fig. 8A Schematic diagram of the cross section on the line segment X-X'; Figure 8C yes Fig. 8A Moreover, the process of the third embodiment can refer to the front-end process of the first embodiment (such as Figures 1A to 5C ), and the same figure numbers as those in the first embodiment are used to represent the same components. Technical contents not described can refer to the above description, so they will not be repeated here.

[0070] Please refer to Fig. 8A , Figure 8B and Figure 8C , the photoresist layer 118 is set to cover the second pseudo dense line pattern 1142, so when the distance d1 from the edge 118a of the photoresist layer 118 to the closest pseudo dense line pattern 1141 is less than the distance d3 between the first pseudo dense line pattern 1141 and the second pseudo dense line pattern 1142, it is determined that the landing position of the photoresist layer 118 is incorrect. Even if the above determination is passed, the width w of the connecting portion 116 still needs to be measured using CD-SEM. If the measurement value cannot be obtained, it is determined that the landing position of the photoresist layer 118 is incorrect, and so on.

[0071] When the landing position of the photoresist layer 118 is correct, Fig. 8A The photoresist layer 118, the dummy dense line pattern 114 and the dense line pattern 112 are used as masks to perform a series of processes as described in the second embodiment to form Fig. 9 A semiconductor device 900 is shown, which includes a dense line structure 902 and a cut-off line 904. Fig. 9 The difference between this embodiment and the second embodiment is that the cut-off line 904 is linear like the dense line structure 902, and further includes a plurality of extensions 908 adjacent to the cut-off portion 906 and extending toward the peripheral area 10b, wherein the line width of the cut-off line 904 and the line width of the dense line structure 902 may be the same or different. The rest of the contents not described may refer to the second embodiment and will not be described in detail.

[0072] In addition to determining whether the landing position of the photoresist layer is correct, the first embodiment can also be applied to critical dimension (CD) detection and overlap detection. Please refer to Fig. 10A and Fig. 10B .

[0073] Fig. 10A Displayed Fig. 6AThe zoomed-out image shows that the device area 10a is between the peripheral area 10b, and the interface between the device area 10a and the peripheral area 10b can be observed from the connection portion 116. The two distances d1a and d1b from the edge 118a of the opposite side of the photoresist layer 118 obtained by the photolithography process to the closest pseudo dense line pattern 114 can be used to estimate the CD value of the photoresist layer. When the two distances d1a and d1b are smaller than the set value, it means that the device area 10a will become smaller after this photolithography process, so the parameters of the subsequent photolithography process should be adjusted; if the two distances d1a and d1b are larger than the set value, it means that the device area 10a will become larger after this photolithography process, and the parameters of the subsequent photolithography process also need to be adjusted.

[0074] Fig. 10B Except for the landing position of the photoresist layer 118, Fig. 10A Similarly, there is an obvious difference between the distance d1a and the distance d1b. The overlap can be measured from the difference between the distances d1a and d1b on the opposite sides to verify whether the overlap between layers is correct.

[0075] In summary, the present invention uses a pseudo dense line pattern with at least one connecting portion to mark the interface between the component area and the peripheral area, which is conducive to directly determining the boundary between the component area and the peripheral area without additional optical proximity correction (OPC), and the distance from the edge of the photoresist layer to the closest pseudo dense line pattern and the width of the connecting portion can also identify online whether the landing position of the photoresist layer is incorrect. In addition, the above identification method can also be applied to CD detection and Overlap detection.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for identifying a photolithography process, characterized in that: include: forming a mask layer on a semiconductor substrate, wherein the semiconductor substrate has a device region and a peripheral region; Patterning the mask layer to form a plurality of dense line patterns in the device region and a plurality of pseudo dense line patterns in the interface region between the device region and the peripheral region, wherein at least one connecting portion is provided between a first pseudo dense line pattern and a third pseudo dense line pattern, and a second pseudo dense line pattern is discontinuous at the at least one connecting portion and is separated from the at least one connecting portion; forming a photoresist layer covering the peripheral area on the semiconductor substrate; as well as Whether the landing position of the photoresist layer is correct is determined according to the distance from the edge of the photoresist layer to the closest pseudo dense line pattern and the width of the at least one connecting portion.

2. According to the identification method for photolithography process according to claim 1, when the photoresist layer is set to cover the first pseudo dense line pattern, if the distance from the edge of the photoresist layer to the closest pseudo dense line pattern is less than the distance between the first pseudo dense line pattern and the second pseudo dense line pattern, it is determined that the landing position of the photoresist layer is incorrect.

3. The identification method for photolithography process according to claim 1, wherein when the photoresist layer is set to cover the first pseudo dense line pattern, if a critical dimension scanning electron microscope is used but a measurement value cannot be obtained, it is determined that the landing position of the photoresist layer is incorrect.

4. According to claim 1, the identification method for photolithography process, wherein the photoresist layer is set to cover the second pseudo dense line pattern, if the distance from the edge of the photoresist layer to the closest pseudo dense line pattern is smaller than the distance between the first pseudo dense line pattern and the second pseudo dense line pattern, it is determined that the landing position of the photoresist layer is incorrect.

5. The identification method for photolithography process according to claim 1, wherein when the photoresist layer is set to cover the second pseudo dense line pattern, if a critical dimension scanning electron microscope is used but a measurement value cannot be obtained, it is determined that the landing position of the photoresist layer is incorrect. 6 . The identification method for photolithography process according to claim 1 , further comprising estimating a critical dimension value of the photoresist layer according to a value of the distance between opposite sides. 7 . The identification method for a photolithography process according to claim 1 , further comprising measuring an overlap amount according to a difference in the distances of opposite sides. 8 . The identification method for photolithography process according to claim 1 , wherein the mask layer is formed by using a self-aligned double patterning process.

9. A semiconductor element, characterized in that: include: A semiconductor substrate having a device region and a peripheral region; A plurality of dense line structures are formed in or on the semiconductor substrate, wherein the plurality of dense line structures are structures obtained by performing an etching process or a deposition process using the plurality of dense line patterns in the method according to claim 1 as a mask, and the plurality of dense line structures and the plurality of dense line patterns are complementary patterns; as well as A cut-off line is arranged at the interface between the dense line structure and the peripheral area. The cut-off line is a structure obtained by performing the etching process or the deposition process using the photoresist layer and the plurality of pseudo dense line patterns in the method as claimed in claim 1 as masks, and the cut-off line and the first to third pseudo dense line patterns are complementary patterns, wherein the cut-off line has at least one cut-off portion complementary to at least one connecting portion in the pseudo dense line pattern. 10 . The semiconductor device as claimed in claim 9 , wherein the plurality of dense line structures comprise buried word lines, bit lines or shallow trench isolation structures. 11 . The semiconductor device according to claim 9 , wherein a line width of the cutoff line is the same as a line width of the plurality of dense line structures. 12 . The semiconductor device as claimed in claim 9 , wherein the cutoff circuit comprises a plurality of extension portions adjacent to the at least one cutoff portion and extending toward the peripheral region. 13 . The semiconductor device according to claim 9 , wherein the cutoff circuit is composed of a plurality of closed loops, and the cutoff portion is disposed between two of the closed loops. 14 . The semiconductor device according to claim 13 , wherein a line width of each of the closed loops is the same as a line width of the plurality of dense line structures.

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