Encapsulation method, encapsulation structure and encapsulation module

Abstract

The present application provides a packaging method, a packaging structure, and a packaging module to avoid generating voids around a chip. The packaging method includes: providing a substrate having an electrical connection layer; providing a bare die to be packaged, the bare die to be packaged having pads matching the electrical connection layer on the substrate; bonding the bare die to be packaged to the electrical connection layer of the substrate through the pads; repeating the steps of deposition and etching on the bare die to be packaged to form a curved sidewall layer on the sidewall of the bare die to be packaged; performing an injection molding operation to fill a plastic encapsulation material between the bare dies to be packaged on which the curved sidewall layer is formed. According to the above technical solution, after the curved sidewall layer is formed on the sidewall of the bare die to be packaged, it is beneficial for subsequent materials to be deposited on the curved sidewall layer, enabling the plastic to better fill around the bare die to be packaged and avoiding generating voids around the bare die to be packaged.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a packaging method, a packaging structure, and a packaging module. Background Art

[0002] Chip packaging is to first cut the chip and then package it. Wafer-level packaging is to move the packaging process forward, and package the chips on the wafer and then cut the individual chips. Wafer-level packaging can integrate wafer manufacturing, packaging, and testing, thereby simplifying the manufacturing process. Wafer-level packaging can also reduce the packaging size, thus saving materials, and the shortened manufacturing cycle time increases the production volume and reduces the manufacturing cost per unit. However, during the process of bonding the die to the substrate in wafer-level packaging, voids will be formed at the edge of the chip, which will affect the yield of the chip.

[0003] Therefore, how to avoid generating voids around the chip is a technical problem that needs to be solved. Summary of the Invention

[0004] The technical problem to be solved by the present application is to provide a packaging method, a packaging structure, and a packaging module to avoid generating voids around the chip.

[0005] To solve the above problems, the present application provides a packaging method. The packaging method includes: providing a substrate having an electrical connection layer; providing a die to be packaged having pads matching the electrical connection layer on the substrate; bonding the die to be packaged to the electrical connection layer of the substrate through the pads; repeating the steps of deposition and etching on the die to be packaged to form a curved sidewall layer on the sidewall of the die to be packaged; performing an injection molding operation to fill a molding compound between the dies to be packaged with the curved sidewall layer formed.

[0006] In some embodiments, after repeating the steps of deposition and etching on the die to be packaged to form a curved sidewall layer on the sidewall of the die to be packaged, it further includes: depositing a protective layer on the top of the die to be packaged, and the ratio of the thickness of the protective layer to the thickness of the die to be packaged ranges from 10 -7 ~10 -5 .

[0007] In some embodiments, the substrate has a first dielectric layer, and the electrical connection layer is formed in the first dielectric layer; the die to be packaged has a second dielectric layer, and the pads are formed in the second dielectric layer; the bonding of the die to be packaged to the electrical connection layer of the substrate through the pads includes: fitting the surface of the second dielectric layer of the die to be packaged to the surface of the first dielectric layer of the substrate, and the pads cover the electrical connection layer; performing a high-temperature annealing operation to bond the pads to the electrical connection layer.

[0008] In some embodiments, performing a high-temperature annealing operation to bond the pad to the electrical connection layer includes: performing a first high-temperature annealing operation at a first temperature to melt-bond the first dielectric layer and the second dielectric layer; performing a second high-temperature annealing operation at a second temperature to melt-bond the pad to the electrical connection layer; wherein the second temperature is greater than the first temperature.

[0009] In some embodiments, performing an injection molding operation to fill a molding compound between the die to be encapsulated with a curved sidewall layer includes: repeating the steps of injection molding and etching a preset number of times on the die to be encapsulated to fill the molding compound between the die to be encapsulated with a curved sidewall layer and the molding compound covers the die to be encapsulated.

[0010] In some embodiments, the encapsulation method further includes: performing a planarization operation to remove part of the molding compound, and the remaining molding compound is flush with the top of the die to be encapsulated.

[0011] In some embodiments, the encapsulation method further includes: cutting the molding compound and the substrate to form a plurality of encapsulation modules, and each encapsulation module includes a die to be encapsulated.

[0012] In some embodiments, repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewall of the die to be encapsulated includes: depositing an insulating material layer on the die to be encapsulated, the insulating material layer covering the sidewall and the top surface of the die to be encapsulated, and the top surface of the substrate between the dies to be encapsulated; partially etching the deposited insulating material layer to remove the insulating material layer on the top surfaces of the die to be encapsulated and the substrate.

[0013] The present application also provides an encapsulation structure. The encapsulation structure includes: a substrate having an electrical connection layer; a plurality of dies to be encapsulated having pads matching the electrical connection layer on the substrate, and the plurality of dies to be encapsulated are bonded to the electrical connection layer of the substrate through the pads; a curved sidewall layer formed on the sidewalls of the dies to be encapsulated; and an encapsulation layer filled between the dies to be encapsulated.

[0014] In some embodiments, the encapsulation structure further includes: a protective layer located on the top of the die to be encapsulated, and the ratio of the thickness of the protective layer to the thickness of the die to be encapsulated ranges from 10 -7 ~10 -5 。

[0015] In some embodiments, the substrate has a first dielectric layer, and the electrical connection layer is formed in the first dielectric layer; the die to be encapsulated has a second dielectric layer, and the pad is formed in the second dielectric layer.

[0016] In some embodiments, the thickness of the curved sidewall layer increases in the direction from the top to the bottom of the die to be encapsulated.

[0017] In some embodiments, the ratio of the spacing between the dies to be encapsulated to the thickness of the die to be encapsulated ranges from 10 -3 to 10 -2 .

[0018] In some embodiments, the material of the protective layer is one of silicon nitride, silicon oxide, or silicon oxynitride.

[0019] The present application also provides a packaging module. The packaging module includes: a first chip having an electrical connection layer; a second chip having pads matching the electrical connection layer on the first chip, and the second chip is bonded to the electrical connection layer of the first chip through the pads; the second chip includes a die, a curved sidewall layer formed on the sidewall of the die, and a protective layer formed on the top of the die; and a packaging layer covering the sidewall of the curved sidewall layer.

[0020] In some embodiments, the packaging module further includes: a stack stacked on the second chip and interconnected with the electrical connection layer in the first chip.

[0021] In the above technical solution, after forming the curved sidewall layer on the sidewall of the die to be encapsulated, it is beneficial for subsequent materials to be deposited on the curved sidewall layer, enabling the plastic to better fill around the die to be encapsulated and avoiding voids around the die to be encapsulated. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of a packaging method according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of a substrate and a die to be encapsulated according to an embodiment of the present application;

[0024] Figure 3 is a schematic diagram of a substrate and a die to be encapsulated according to another embodiment of the present application;

[0025] Figure 4 is a schematic diagram of a second high-temperature annealing operation according to an embodiment of the present application;

[0026] Figure 5 is a schematic diagram of a second high-temperature annealing operation according to an embodiment of the present application;

[0027] Figure 6 is a schematic diagram of depositing an insulating material layer according to an embodiment of the present application;

[0028] Figure 7Schematic diagram of partially etching an insulating material layer according to an embodiment of the present application;

[0029] Figure 8 Schematic diagram of depositing a protective layer according to an embodiment of the present application;

[0030] Figure 9 Schematic diagram of performing an injection molding operation according to an embodiment of the present application;

[0031] Figure 10 Schematic diagram of a packaging structure according to an embodiment of the present application;

[0032] Figure 11 Schematic diagram of a packaging module according to an embodiment of the present application. Detailed implementation manners

[0033] The following will make a detailed description of the detailed implementation manners of the packaging method, packaging structure, and packaging module provided by the present application with reference to the accompanying drawings.

[0034] Figure 1 Schematic diagram of a packaging method according to an embodiment of the present application. The packaging method includes: Step S101, providing a substrate having an electrical connection layer; Step S102, providing a bare die to be packaged, the bare die to be packaged having pads matching the electrical connection layer on the substrate; Step S103, bonding the bare die to be packaged to the electrical connection layer of the substrate through the pads; Step S104, repeating the steps of deposition and etching on the bare die to be packaged to form a curved sidewall layer on the sidewall of the bare die to be packaged; Step S105, performing an injection molding operation to fill a molding compound between the bare dies to be packaged on which the curved sidewall layer is formed.

[0035] Next, please continue to refer to Figure 1 , Step S101, providing a substrate having an electrical connection layer. Step S102, providing a bare die to be packaged, the bare die to be packaged having pads matching the electrical connection layer on the substrate. The number of the pads is more than one. Figure 2 Schematic diagram of a substrate and a bare die to be packaged according to an embodiment of the present application. Next, please refer to Figure 2 , The substrate 1 has an electrical connection layer 2, and the bare die 3 to be packaged has pads 4 matching the electrical connection layer 2 on the substrate 1. In this embodiment, the pads are copper pads.

[0036] Next, please continue to refer to Figure 1 , Step S103, bonding the bare die to be packaged to the electrical connection layer of the substrate through the pads. Figure 3 Schematic diagram of a substrate and a bare die to be packaged according to another embodiment of the present application. Next, please refer to Figure 3, in this embodiment, the substrate 1 has a first dielectric layer 5, and the electrical connection layer 2 is formed in the first dielectric layer 5; the die 3 to be encapsulated has a second dielectric layer 6, and the pad 4 is formed in the second dielectric layer 6. Bonding the die 3 to be encapsulated to the electrical connection layer 2 of the substrate 1 through the pad 4 includes: fitting the surface of the second dielectric layer 6 of the die 3 to be encapsulated to the surface of the first dielectric layer 2 of the substrate 1, and the pad 4 covering the electrical connection layer 2; performing a high-temperature annealing operation to bond the pad 4 to the electrical connection layer 2.

[0037] In this embodiment, performing a high-temperature annealing operation to bond the pad to the electrical connection layer includes: performing a first high-temperature annealing operation at a first temperature to melt-bond the first dielectric layer and the second dielectric layer; performing a second high-temperature annealing operation at a second temperature to melt-bond the pad to the electrical connection layer; wherein, the second temperature is greater than the first temperature. Figure 4 is a schematic diagram of the first high-temperature annealing operation of an embodiment of the present application. Please refer to the following Figure 4 , performing a first high-temperature annealing operation at a first temperature to melt-bond the first dielectric layer 5 on the substrate 1 to the second dielectric layer 6 on the die 3 to be encapsulated. Figure 5 is a schematic diagram of the second high-temperature annealing operation of an embodiment of the present application. Please refer to the following Figure 5 , performing a second high-temperature annealing operation at a second temperature to melt-bond the pad 4 on the die 3 to be encapsulated to the electrical connection layer 2 on the substrate 1. In some embodiments, benzocyclobutene is used as an adhesive to bond the die to be encapsulated to the electrical connection layer of the substrate through the pad.

[0038] Please continue to refer to the following Figure 1 , step S104, repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewall of the die to be encapsulated. In some embodiments, repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewall of the die to be encapsulated includes: depositing an insulating material layer on the die to be encapsulated, the insulating material layer covering the sidewalls and the top surface of the die to be encapsulated, and the top surface of the substrate between the dies to be encapsulated; partially etching the deposited insulating material layer to remove the insulating material layer on the top surfaces of the die to be encapsulated and the substrate. Figure 6 is a schematic diagram of depositing an insulating material layer of an embodiment of the present application. Please refer to the following Figure 6 , in this embodiment, an insulating material layer 7 is deposited on the die 3 to be encapsulated, and the insulating material layer 7 covers the sidewalls and the top surface of the die 3 to be encapsulated, and the top surface of the first dielectric layer 5 on the substrate 1 between the dies 3 to be encapsulated. Figure 7It is a schematic diagram of partially etching an insulating material layer according to an embodiment of the present application. Please refer to the following Figure 7 , partially etch the deposited insulating material layer to remove the insulating material layer on the top surface of the first dielectric layer 5 on the die 3 to be encapsulated and the substrate 1, and form a curved sidewall layer 8 on the sidewall of the die 3 to be encapsulated.

[0039] Figure 8 It is a schematic diagram of depositing a protective layer according to an embodiment of the present application. Please refer to the following Figure 8 , in this embodiment, after repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer 8 on the sidewall of the die to be encapsulated, it further includes: depositing a protective layer 9 on the top of the die to be encapsulated, and the ratio of the thickness of the protective layer 9 to the thickness of the die to be encapsulated ranges from 10 -7 ~10 -5 . The front of the die 3 where the device layer is formed faces the front of the substrate 1, and a protective layer 9 is deposited on the back of the die 3 to be encapsulated. In some embodiments, the material of the protective layer is one of silicon nitride, silicon oxide, or silicon oxynitride. In this embodiment, the material of the protective layer is silicon oxide, the thickness of the die to be encapsulated is 100 mm to 300 mm, and the thickness of the protective layer is 100 Å to 2000 Å to resist repeated etching during the manufacturing process.

[0040] Please continue to refer to the following Figure 1 , step S105, perform an injection molding operation to fill a molding compound between the dies to be encapsulated with the curved sidewall layer formed. Figure 9 It is a schematic diagram of performing an injection molding operation according to an embodiment of the present application. Please refer to the following Figure 9 , the performing of the injection molding operation to fill a molding compound between the dies to be encapsulated with the curved sidewall layer formed includes: repeating the steps of injection molding and etching on the die 3 to be encapsulated a preset number of times to fill a molding compound between the dies 3 to be encapsulated with the curved sidewall layer formed and the molding compound covers the die 3 to be encapsulated. In some other embodiments, the encapsulation method further includes: performing a planarization operation to remove part of the molding compound, and the remaining molding compound is flush with the top of the die to be encapsulated to form an encapsulation layer 10. In some embodiments, the encapsulation method further includes: cutting the molding compound and the substrate to form a plurality of encapsulation modules, and each encapsulation module includes a die to be encapsulated. Please continue to refer to the following Figure 9, in some embodiments, the substrate 1 has a first dielectric layer 5, and the electrical connection layer 2 is formed in the first dielectric layer 5; the die 3 to be encapsulated has a second dielectric layer 6, and the pad 4 is formed in the second dielectric layer 6. In some embodiments, in the direction from the top to the bottom of the die to be encapsulated, the thickness of the curved sidewall layer 8 increases. In some embodiments, the ratio range of the spacing between the dies to be encapsulated to the thickness of the die to be encapsulated is 10 -3 ~10 -2 .

[0041] In the above technical solution, after the curved sidewall layer 8 is formed on the sidewall of the die 3 to be encapsulated, it is beneficial for the plastic 10 to be deposited on the curved sidewall layer 8 during the subsequent injection molding operation, so that the plastic 10 can better fill around the die 3 to be encapsulated, avoiding the generation of voids around the die to be encapsulated. After repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewall of the die to be encapsulated, a protective layer 9 is deposited on the top of the die to be encapsulated to resist repeated etching during the manufacturing process. Then, the encapsulation material and the substrate are cut to obtain a plurality of encapsulated modules. It reduces the formation of voids at the edge of the chip during the process of bonding the die to the substrate, thereby improving the yield of the chip.

[0042] The present application also provides an encapsulation structure. Figure 10 is a schematic diagram of an encapsulation structure according to an embodiment of the present application. The encapsulation structure includes: a substrate 1, the substrate 1 having an electrical connection layer 2; a plurality of dies 3 to be encapsulated, the plurality of dies 3 to be encapsulated having pads 4 matching the electrical connection layer on the substrate, and the plurality of dies 3 to be encapsulated are bonded to the electrical connection layer 2 of the substrate through the pads 4; a curved sidewall layer formed on the sidewalls of the dies to be encapsulated; an encapsulation layer 10 filled between the dies 3 to be encapsulated.

[0043] Figure 1 is a schematic diagram of an encapsulation method according to an embodiment of the present application. The above encapsulation structure is obtained through the encapsulation method. The encapsulation method includes: step S101, providing a substrate, the substrate having an electrical connection layer; step S102, providing a die to be encapsulated, the die to be encapsulated having a pad matching the electrical connection layer on the substrate; step S103, bonding the die to be encapsulated to the electrical connection layer of the substrate through the pad; step S104, repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewall of the die to be encapsulated; step S105, performing an injection molding operation to fill the encapsulation material between the dies to be encapsulated on which the curved sidewall layer is formed.

[0044] Please continue to refer to the following Figure 1, Step S101, provide a substrate having an electrical connection layer. Step S102, provide a die to be encapsulated having pads matching the electrical connection layer on the substrate. The number of the pads is more than one. Figure 2 is a schematic diagram of the substrate and the die to be encapsulated according to an embodiment of the present application. Please refer to the following Figure 2 , the substrate 1 has an electrical connection layer 2, and the die 3 to be encapsulated has pads 4 matching the electrical connection layer 2 on the substrate 1. In this embodiment, the pads are copper pads.

[0045] Please continue to refer to the following Figure 1 , Step S103, bond the die to be encapsulated to the electrical connection layer of the substrate through the pads. Figure 3 is a schematic diagram of the substrate and the die to be encapsulated according to another embodiment of the present application. Please refer to the following Figure 3 , in this embodiment, the substrate 1 has a first dielectric layer 5, and the electrical connection layer 2 is formed in the first dielectric layer 5; the die 3 to be encapsulated has a second dielectric layer 6, and the pads 4 are formed in the second dielectric layer 6. Bonding the die 3 to be encapsulated to the electrical connection layer 2 of the substrate 1 through the pads 4 includes: fitting the surface of the second dielectric layer 6 of the die 3 to be encapsulated to the surface of the first dielectric layer 2 of the substrate 1, and the pads 4 cover the electrical connection layer 2; performing a high-temperature annealing operation to bond the pads 4 to the electrical connection layer 2.

[0046] In this embodiment, performing a high-temperature annealing operation to bond the pads to the electrical connection layer includes: performing a first high-temperature annealing operation at a first temperature to melt-bond the first dielectric layer and the second dielectric layer; performing a second high-temperature annealing operation at a second temperature to melt-bond the pads to the electrical connection layer; wherein, the second temperature is greater than the first temperature. Figure 4 is a schematic diagram of the first high-temperature annealing operation according to an embodiment of the present application. Please refer to the following Figure 4 , perform a first high-temperature annealing operation at a first temperature to melt-bond the first dielectric layer 5 on the substrate 1 to the second dielectric layer 6 on the die 3 to be encapsulated. Figure 5 is a schematic diagram of the second high-temperature annealing operation according to an embodiment of the present application. Please refer to the following Figure 5 , perform a second high-temperature annealing operation at a second temperature to melt-bond the pads 4 on the die 3 to be encapsulated to the electrical connection layer 2 on the substrate 1. In some embodiments, benzocyclobutene is used as an adhesive to bond the die to be encapsulated to the electrical connection layer of the substrate through the pads.

[0047] Please continue to refer to the following Figure 1, Step S104, repeat the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewalls of the die to be encapsulated. In some embodiments, repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewalls of the die to be encapsulated includes: depositing an insulating material layer on the die to be encapsulated, the insulating material layer covering the sidewalls and the top surface of the die to be encapsulated, and the top surface of the substrate between the dies to be encapsulated; partially etching the deposited insulating material layer to remove the insulating material layer on the top surfaces of the die to be encapsulated and the substrate. Figure 6 is a schematic diagram of depositing an insulating material layer according to an embodiment of the present application. Please refer to the following Figure 6 , in this embodiment, an insulating material layer 7 is deposited on the die 3 to be encapsulated, and the insulating material layer 7 covers the sidewalls and the top surface of the die 3 to be encapsulated, and the top surface of the first dielectric layer 5 on the substrate 1 between the dies 3 to be encapsulated. Figure 7 is a schematic diagram of partially etching the insulating material layer according to an embodiment of the present application. Please refer to the following Figure 7 , partially etch the deposited insulating material layer to remove the insulating material layer on the top surfaces of the die 3 to be encapsulated and the first dielectric layer 5 on the substrate 1, and form a curved sidewall layer 8 on the sidewalls of the die 3 to be encapsulated.

[0048] Figure 8 is a schematic diagram of depositing a protective layer according to an embodiment of the present application. Please refer to the following Figure 8 , in this embodiment, after the step of repeating deposition and etching on the die to be encapsulated to form a curved sidewall layer 8 on the sidewalls of the die to be encapsulated, it further includes: depositing a protective layer 9 on the top of the die to be encapsulated, and the ratio of the thickness of the protective layer 9 to the thickness of the die to be encapsulated ranges from 10 -7 ~10 -5 . The front side of the die 3 to be encapsulated where the device layer is formed faces the front side of the substrate 1, and a protective layer 9 is deposited on the back of the die 3 to be encapsulated. In some embodiments, the material of the protective layer is one of silicon nitride, silicon oxide, or silicon oxynitride. In this embodiment, the material of the protective layer is silicon oxide, the thickness of the die to be encapsulated is 100 mm to 300 mm, and the thickness of the protective layer is 100 Å to 2000 Å to resist repeated etching during the manufacturing process.

[0049] Please continue to refer to the following Figure 1 , Step S105, perform an injection molding operation to fill the encapsulation material between the dies to be encapsulated with the curved sidewall layer formed. Figure 9 is a schematic diagram of performing an injection molding operation according to an embodiment of the present application. Please refer to the following Figure 9, performing the injection molding operation to fill the encapsulation material between the bare dies formed with the curved sidewall layer, including: repeating the steps of injection molding and etching a preset number of times on the bare die 3 to fill the encapsulation material between the bare dies formed with the curved sidewall layer and the encapsulation material covering the bare die 3. In some other embodiments, the encapsulation method further includes: performing a planarization operation to remove part of the encapsulation material, and the remaining encapsulation material is flush with the top of the bare die to form the encapsulation layer 10. In some embodiments, the encapsulation method further includes: cutting the encapsulation material and the substrate to form a plurality of encapsulation modules, and each encapsulation module includes a bare die to be encapsulated. Please continue to refer to Figure 9 , in some embodiments, the substrate 1 has a first dielectric layer 5, and the electrical connection layer 2 is formed in the first dielectric layer 5; the bare die 3 to be encapsulated has a second dielectric layer 6, and the pad 4 is formed in the second dielectric layer 6. In some embodiments, in the direction from the top to the bottom of the bare die to be encapsulated, the thickness of the curved sidewall layer 8 increases. In some embodiments, the ratio range of the spacing between each of the bare dies to be encapsulated to the thickness of the bare die to be encapsulated is 10 -3 ~10 -2 .

[0050] In the above technical solution, after the curved sidewall layer 8 is formed on the sidewall of the bare die 3 to be encapsulated, it is beneficial for the plastic 10 to be deposited on the curved sidewall layer 8 during the subsequent injection molding operation, so that the plastic 10 can better fill around the bare die 3 to be encapsulated, and avoid generating voids around the bare die to be encapsulated. After repeating the steps of deposition and etching on the bare die to be encapsulated to form the curved sidewall layer on the sidewall of the bare die to be encapsulated, a protective layer 9 is deposited on the top of the bare die to be encapsulated to resist repeated etching during the manufacturing process. Then, the encapsulation material and the substrate are cut to obtain a plurality of encapsulation modules. It reduces the formation of voids at the edge of the chip during the process of bonding the bare die to the substrate, thereby improving the yield of the chip.

[0051] The present application also provides an encapsulation module. Figure 11 is a schematic diagram of an encapsulation module according to an embodiment of the present application. The encapsulation module includes: a first chip 11, the chip having an electrical connection layer 2; a second chip 12, the second chip 12 having pads 4 matching the electrical connection layer 2 on the first chip 11, and the second chip 12 is bonded to the electrical connection layer 2 of the first chip 11 through the pads 4; the second chip 12 includes a bare die 3, a curved sidewall layer 8 formed on the sidewall of the bare die, and a protective layer 9 formed on the top of the bare die; an encapsulation layer 10 covering the sidewall of the curved sidewall layer. In some embodiments, the encapsulation module further includes: a stack body (not shown), stacked on the second chip and interconnected with the electrical connection layer 2 in the first chip.

[0052] In some embodiments, the ratio of the thickness of the protective layer to the thickness of the die to be encapsulated ranges from 10 -7 to 10 -5 . The front side of the die layer formed on the die to be encapsulated faces the front side of the substrate, and a protective layer is deposited on the back side of the die to be encapsulated. In some embodiments, the material of the protective layer is one of silicon nitride, silicon oxide, or silicon oxynitride. In this embodiment, the material of the protective layer is silicon oxide, the thickness of the die to be encapsulated is 100 mm to 300 mm, and the thickness of the protective layer is 100 Å to 2000 Å to resist repeated etching during the manufacturing process.

[0053] In some embodiments, the step of forming the curved sidewall layer on the sidewall of the die includes: depositing an insulating material layer on the die to be encapsulated, the insulating material layer covering the sidewalls and the top surface of the die to be encapsulated, and the top surface of the substrate between the dies to be encapsulated; partially etching the deposited insulating material layer to remove the insulating material layer on the top surfaces of the die to be encapsulated and the substrate. Figure 6 is a schematic diagram of depositing an insulating material layer according to an embodiment of the present application. Please refer to the following Figure 6 . In this embodiment, an insulating material layer 7 is deposited on the die 3 to be encapsulated, and the insulating material layer 7 covers the sidewalls and the top surface of the die 3 to be encapsulated, and the top surface of the first dielectric layer 5 on the substrate 1 between the dies 3 to be encapsulated. Figure 7 is a schematic diagram of partially etching the insulating material layer according to an embodiment of the present application. Please refer to the following Figure 7 . Partially etch the deposited insulating material layer to remove the insulating material layer on the top surfaces of the die 3 to be encapsulated and the first dielectric layer 5 on the substrate 1, and form a curved sidewall layer 8 on the sidewall of the die 3 to be encapsulated.

[0054] In the above technical solution, after forming the curved sidewall layer 8 on the sidewall of the die 3 to be encapsulated, it is beneficial for subsequent materials to be deposited on the curved sidewall layer 8, and the curved sidewall layer avoids generating voids around the die to be encapsulated. After repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewall of the die to be encapsulated, a protective layer 9 is deposited on the top of the die to be encapsulated to resist repeated etching during the manufacturing process. Then, the encapsulation material and the substrate are cut to obtain a plurality of encapsulated modules. The formation of voids at the edge of the chip during the process of bonding the die to the substrate is reduced, thereby improving the yield of the chip.

[0055] The above are only the preferred embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. An encapsulation method, characterized in that, it includes: providing a substrate having an electrical connection layer; providing a die to be encapsulated having pads matching the electrical connection layer on the substrate; bonding the die to be encapsulated to the electrical connection layer of the substrate through the pads; repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewall of the die to be encapsulated; performing an injection molding operation to fill a molding compound between the dies to be encapsulated with the curved sidewall layer formed.

2. The encapsulation method according to claim 1, characterized in that, After repeating the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewalls of the die to be encapsulated, the method further includes: depositing a protective layer on the top of the die to be encapsulated, and the ratio of the thickness of the protective layer to the thickness of the die to be encapsulated ranges from 10 -7 to 10 -5 .

3. The encapsulation method according to claim 1, characterized in that, the substrate has a first dielectric layer, and the electrical connection layer is formed in the first dielectric layer; the die to be encapsulated has a second dielectric layer, and the pads are formed in the second dielectric layer; the bonding of the die to be encapsulated to the electrical connection layer of the substrate through the pads includes: fitting the surface of the second dielectric layer of the die to be encapsulated to the surface of the first dielectric layer of the substrate, and the pads covering the electrical connection layer; performing a high-temperature annealing operation to bond the pads to the electrical connection layer.

4. The encapsulation method according to claim 3, characterized in that, performing a high-temperature annealing operation to bond the pads to the electrical connection layer includes: performing a first high-temperature annealing operation at a first temperature to melt-bond the first dielectric layer and the second dielectric layer; performing a second high-temperature annealing operation at a second temperature to melt-bond the pads to the electrical connection layer; wherein, the second temperature is greater than the first temperature.

5. The encapsulation method according to claim 1, characterized in that, the performing of the injection molding operation to fill a molding compound between the dies to be encapsulated with the curved sidewall layer formed includes: repeating the steps of injection molding and etching on the die to be encapsulated a preset number of times to fill a molding compound between the dies to be encapsulated with the curved sidewall layer formed and the molding compound covering the die to be encapsulated.

6. The encapsulation method according to claim 5, characterized in that, it further includes: performing a planarization operation to remove part of the molding compound, and the remaining molding compound is flush with the top of the die to be encapsulated.

7. The encapsulation method according to claim 1, characterized in that, the method further includes: cutting the molding compound and the substrate to form a plurality of encapsulation modules, and each encapsulation module includes a die to be encapsulated.

8. The encapsulation method according to claim 1, characterized in that, the repeating of the steps of deposition and etching on the die to be encapsulated to form a curved sidewall layer on the sidewall of the die to be encapsulated includes: depositing an insulating material layer on the die to be encapsulated, the insulating material layer covering the sidewall and the top surface of the die to be encapsulated, and the top surface of the substrate between the dies to be encapsulated; partially etching the deposited insulating material layer to remove the insulating material layer on the top surfaces of the die to be encapsulated and the substrate.

Images