Display substrate and display device

Abstract

A display substrate and display device, comprising a display area and a peripheral area at least partially surrounding the display area, and including a base substrate; the display area including a plurality of pixel units arranged in an array on the base substrate and a plurality of signal lines electrically connected to the plurality of pixel units; the peripheral area including at least one first electrode pattern electrically connected to at least one of the plurality of signal lines, and a second electrode pattern, wherein the at least one first electrode pattern and the second electrode pattern at least partially overlap in a direction perpendicular to the surface of the base substrate and are insulated from each other; the peripheral area also including a gate scan drive circuit configured to provide gate scan signals to the plurality of pixel units, wherein the at least one first electrode pattern and the second electrode pattern are located between the gate scan drive circuit and the display area in a direction parallel to the surface of the base substrate. The display substrate can compensate for the transmission load of the signal lines, thereby improving signal transmission.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display devices have the advantages of thin thickness, light weight, wide viewing angle, active light emission, continuously adjustable light color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, high luminous efficiency and flexible display. Therefore, they are increasingly widely used in display fields such as mobile phones, tablets, and digital cameras. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which has a display area and a peripheral area at least partially surrounding the display area, and includes: a base substrate; wherein the display area includes a plurality of pixel units arranged in an array on the base substrate and a plurality of signal lines electrically connected to the plurality of pixel units respectively, the peripheral area includes at least one first electrode pattern electrically connected to at least one of the plurality of signal lines, and includes a second electrode pattern, the at least one first electrode pattern and the second electrode pattern at least partially overlap and are insulated from each other in a direction perpendicular to the board surface of the base substrate, the peripheral area also includes a gate scan drive circuit, the gate scan drive circuit is configured to provide a gate scan signal to the plurality of pixel units, and in a direction parallel to the board surface of the base substrate, the at least one first electrode pattern and the second electrode pattern are located between the gate scan drive circuit and the display area.

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, the orthographic projection of the at least one first electrode pattern on the base substrate is located within the orthographic projection of the second electrode pattern on the base substrate.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second electrode pattern is located on a side of the at least one first electrode pattern away from the base substrate.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least one of the multiple pixel units includes a pixel driving circuit located on the base substrate, the pixel driving circuit includes a thin film transistor and a storage capacitor; the thin film transistor includes an active layer, a gate, a source and a drain, the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode in a direction perpendicular to the plate surface of the base substrate; the source and the drain are located on the side of the active layer away from the base substrate, the first electrode pattern, the gate and the first capacitor electrode are arranged on the same layer, and the second electrode pattern and the second capacitor electrode are arranged on the same layer.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the plurality of signal lines are arranged in the same layer as the source and drain of the thin film transistor, and the at least one first electrode pattern is electrically connected to at least one of the plurality of signal lines through a via structure.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second electrode pattern is configured to receive a first voltage signal from a first voltage source.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the peripheral area also includes a power wiring pattern, the power wiring pattern is electrically connected to the first voltage source, and the second electrode pattern is electrically connected to the power wiring pattern to receive the first voltage signal through the power wiring pattern.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the power wiring pattern is provided in the same layer as the source and drain of the thin film transistor, and the second electrode pattern is electrically connected to the power wiring pattern through a via structure.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a direction parallel to the surface of the base substrate, at least a portion of the second electrode pattern is electrically connected between the power wiring pattern and the multiple pixel units, and the power wiring pattern provides the first voltage signal to at least a portion of the multiple pixel units through the second electrode pattern.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the at least one first electrode pattern includes a plurality of first electrode patterns, and the plurality of first electrode patterns are arranged at intervals; the peripheral area also includes a spacing pattern located between two adjacent first electrode patterns and insulated from the first electrode patterns.

[0013] For example, in the display substrate provided by at least one embodiment of the present disclosure, the spacing pattern is configured to receive a second voltage signal from a second voltage source different from the first voltage source.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, the spacing pattern is electrically connected to the second electrode pattern to receive the first voltage signal from the first voltage source.

[0015] For example, in the display substrate provided by at least one embodiment of the present disclosure, the spacing pattern is provided in the same layer as the active layer of the thin film transistor.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second electrode pattern is continuously arranged along the edge of the display area, and at least partially overlaps with the multiple first electrode patterns in a direction perpendicular to the plate surface of the base substrate and is insulated from each other.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, an extension direction of at least a portion of the edge of the display area intersects with and is not perpendicular to an extension direction of the plurality of signal lines.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes a first insulating layer located between the first electrode pattern and the second electrode pattern, and a material of the first insulating layer includes silicon nitride or silicon oxynitride.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the multiple pixel units include a first column of pixel units and a second column of pixel units, the number of pixel units in the first column of pixel units is less than the number of pixel units in the second column of pixel units, and the signal line electrically connected to the first column of pixel units is electrically connected to a first electrode pattern.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the signal line electrically connected to the second column of pixel units is electrically connected to another first electrode pattern, and the compensation capacitance formed by the one first electrode pattern electrically connected to the second electrode pattern and the signal line electrically connected to the first column of pixel units is greater than the compensation capacitance formed by the second electrode pattern and the other first electrode pattern electrically connected to the signal line electrically connected to the second column of pixel units.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first electrode pattern and the second electrode pattern have different lengths in the column direction, or the first electrode pattern and the second electrode pattern have different lengths in the row direction.

[0022] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of signal lines are scan lines or data lines.

[0023] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first end or the second end of at least one of the multiple signal lines is electrically connected to a first electrode pattern, or the first end of at least one of the multiple signal lines is electrically connected to a first electrode pattern, and the second end of at least one of the multiple signal lines is electrically connected to another first electrode pattern.

[0024] At least one embodiment of the present disclosure further provides a display device, comprising the display substrate described in any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0026] Figure 1A A schematic plan view of a display substrate provided in some embodiments of the present disclosure;

[0027] Figure 1B A schematic plan view of another display substrate provided for some embodiments of the present disclosure;

[0028] Figure 2A Some embodiments of the present disclosure provide a Figure 1A A schematic diagram of a compensation method for a display substrate is shown;

[0029] Figure 2B Another embodiment of the present disclosure provides Figure 1A A schematic diagram of a compensation method for a display substrate is shown;

[0030] Figure 2C Another embodiment of the present disclosure provides Figure 1A A schematic diagram of a compensation method for a display substrate is shown;

[0031] Figure 3 A schematic diagram of a partial structure of a display substrate provided in some embodiments of the present disclosure;

[0032] Figure 4 A schematic diagram of a partial planar structure of a peripheral area of ​​a display substrate provided in some embodiments of the present disclosure;

[0033] Figure 5A A schematic diagram of a partial cross-sectional structure of a peripheral area of ​​a display substrate provided in some embodiments of the present disclosure;

[0034] Figure 5BA schematic diagram of a partial cross-sectional structure of a peripheral area of ​​another display substrate provided in some embodiments of the present disclosure;

[0035] Figure 6 A schematic diagram of a partial cross-sectional structure of a display area and a partial cross-sectional structure of a peripheral area of ​​a display substrate provided in some embodiments of the present disclosure;

[0036] Figure 7 An equivalent circuit diagram of a pixel driving circuit in a display substrate provided in some embodiments of the present disclosure;

[0037] Figures 8A-8E A schematic diagram of various layers of a pixel driving circuit in a display substrate provided in some embodiments of the present disclosure;

[0038] Figure 9 A schematic block diagram of a display device provided in some embodiments of the present disclosure; and

[0039] Figure 10 A schematic block diagram of another display device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] At present, with the continuous popularization of electronic display products, users' requirements for the functions and appearance of electronic display products are further improved. In order to meet the different actual needs of users, the appearance or display area of ​​electronic display products sometimes needs to be designed into an irregular or special shape. However, since the display area has an irregular or special shape, the number of pixel units included in different rows in the display area may be different, or the number of pixel units included in different columns in the display area may also be different. For example, taking the different numbers of pixel units included in different columns in the display area as an example, due to the different numbers of pixel units in different columns, the transmission loads on the multiple signal lines used to provide pixel units located in different columns with, for example, data signals or other required electrical signals may be different, resulting in inconsistent signal transmission effects (such as transmission speeds) of the multiple signal lines, which in turn leads to reduced brightness uniformity and consistency of the provided display image, and may even cause display anomalies.

[0043] At least one embodiment of the present disclosure provides a display substrate having a display area and a peripheral area at least partially surrounding the display area, and comprising a base substrate. The display area includes a plurality of pixel units arranged in an array on the base substrate and a plurality of signal lines electrically connected to the plurality of pixel units; the peripheral area includes at least one first electrode pattern electrically connected to at least one of the plurality of signal lines, and a second electrode pattern, wherein the at least one first electrode pattern and the second electrode pattern at least partially overlap in a direction perpendicular to the surface of the base substrate and are insulated from each other; the peripheral area also includes a gate scan drive circuit, the gate scan drive circuit being configured to provide a gate scan signal to the plurality of pixel units, and the at least one first electrode pattern and the second electrode pattern being located between the gate scan drive circuit and the display area in a direction parallel to the surface of the base substrate.

[0044] The display substrate provided by the above-mentioned embodiments of the present disclosure forms a capacitor between the first electrode pattern and the second electrode pattern by causing the first electrode pattern and the second electrode pattern to at least partially overlap in a direction perpendicular to the board surface of the base substrate and to be insulated from each other, thereby compensating for the transmission load on the signal line electrically connected to the first electrode pattern, thereby improving the consistency of the signal transmission effect of multiple signal lines, thereby improving the brightness uniformity and consistency of the display screen, thereby reducing or avoiding display anomalies or poor phenomena in the display screen, and improving the display effect of the screen.

[0045] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements described.

[0046] Figure 1A A schematic plan view of a display substrate provided in some embodiments of the present disclosure. Figure 1AAs shown, the display substrate 10 has a display area 101 and a peripheral area 102 that at least partially surrounds (e.g., completely surrounds) the display area 101. For example, the display area 101 of the display substrate 10 can be circular in shape, and the peripheral area 102 surrounds the display area 101 and has a contour that is approximately circular. Thus, the display substrate 10 has a substantially circular shape to meet users' actual needs for display substrates of different shapes.

[0047] It should be noted that the embodiment of the present disclosure does not limit the specific shape of the display substrate. For example, Figure 1B A schematic plan view of another display substrate provided in some embodiments of the present disclosure. Figure 1B As shown, the display substrate 20 has a display area 201 and a peripheral area 202 that at least partially surrounds (e.g., completely surrounds) the display area 201. For example, the display area 201 of the display substrate 20 can be in the shape of a square with rounded corners, while the peripheral area 202 surrounds the display area 201 and has the same contour as the display area 201, thereby making the display substrate 20 have a square shape with rounded corners. In other embodiments of the present disclosure, the display substrate can also have a regular shape such as an ellipse, sector, triangle, diamond, pentagon, or other suitable irregular shape, and the embodiments of the present disclosure are not limited thereto.

[0048] In the following, the embodiments of the present disclosure are Figure 1A The shape of the display substrate 10 shown is taken as an example to illustrate the display substrate provided by the embodiment of the present disclosure, but this does not constitute a limitation to the embodiment of the present disclosure.

[0049] Figure 2A Some embodiments of the present disclosure provide a Figure 1A A schematic diagram of a compensation method for a display substrate is shown; Figure 3 A schematic diagram of a partial structure of a display substrate provided in some embodiments of the present disclosure, for example Figure 3 Can correspond Figure 2A The region REG1 is shown in FIG.

[0050] For example, Figure 1A 、 Figure 2A and Figure 3As shown, the display substrate 10 includes a base substrate 100. The display area 101 includes a plurality of pixel units 110 arranged in an array on the base substrate 100 and a plurality of signal lines 120 electrically connected to the plurality of pixel units 110. The peripheral area 102 includes at least one first electrode pattern 130 electrically connected to at least one of the plurality of signal lines 120, and a second electrode pattern 140. The first electrode pattern 130 and the second electrode pattern 140 at least partially overlap in a direction perpendicular to the surface of the base substrate 100 and are insulated from each other to form a capacitor. The capacitance formed between the first electrode pattern 130 and the second electrode pattern 140 can compensate for the transmission load on the signal line 120 electrically connected to the first electrode pattern 130 (for example, the transmission load on the signal line 120 can refer to the transmission resistance of the signal line 120, or the capacitance formed between the signal line 120 and other wiring), thereby improving the consistency of the transmission load on the plurality of signal lines 120 in the display area 101. In this way, the signal transmission effect of the multiple signal lines 120 in the display area 101 can be improved, so that the brightness uniformity and consistency of the provided display screen can be improved, thereby reducing or avoiding display anomalies or poor phenomena on the display screen and improving the display effect of the screen.

[0051] In some embodiments of the present disclosure, the signal line 120 can be a scan line, for example, for providing a gate scan signal to the pixel unit 110, or it can be a data line, for example, for providing a data signal to the pixel unit 110, or it can be a signal line for providing other electrical signals required to realize screen display to the pixel unit 110.

[0052] For example, in the case where the signal line 120 is a scanning line, the transmission load on the scanning line electrically connected to the first electrode pattern 130 is compensated by the capacitance formed between the first electrode pattern 130 and the second electrode pattern 140, thereby improving the transmission effect of, for example, a gate scanning signal transmitted on the scanning line, and improving the consistency of the transmission effect of the gate scanning signals on multiple scanning lines in the display area 101.

[0053] For example, in the case where the signal line 120 is a data line, the transmission load on the data line electrically connected to the first electrode pattern 130 is compensated by the capacitance formed between the first electrode pattern 130 and the second electrode pattern 140, thereby improving the transmission effect of, for example, a data signal transmitted on the data line, and enhancing the consistency of the transmission effect of the data signals on multiple data lines in the display area 101.

[0054] The following embodiments of the present disclosure are described by taking the signal line 120 as a data line as an example, but it should be noted that the embodiments of the present disclosure include but are not limited to this.

[0055] For example, Figure 1A 、 Figure 2A and Figure 3 As shown, the peripheral region 102 further includes a gate scan driver circuit (Gate on array, GOA) 150, which is configured to provide gate scan signals to the plurality of pixel units 110. The gate scan driver circuit 150 is fabricated directly on the base substrate 100, for example, using a semiconductor process. In a direction parallel to the surface of the base substrate 100, the first electrode pattern 130 and the second electrode pattern 140 are located between the gate scan driver circuit 150 and the display region 101. This improves the space utilization of the peripheral region 102 and reduces the space required by the first electrode pattern 130 and the second electrode pattern 140 on the display substrate 10, thereby facilitating a narrow-frame design for the display substrate 10.

[0056] For example, the gate scan driver circuit 150 may include a plurality of cascaded shift register units, for example, the output end of each shift register unit is electrically connected to a row of pixel units 110 in the display area 101 via a gate line, so as to provide a gate scan signal to the plurality of pixel units 110 in a row. For example, the plurality of pixel units 110 may be arranged in an array in the display area 101, and the gate scan driver circuit 150 is configured to provide, for example, a row-by-row shifted gate scan signal to the plurality of rows of pixel units 110 arranged in the array in the display area 101.

[0057] For example, the shift register unit in the above-mentioned gate scan driving circuit 150 can be a 4T1C structure, that is, it includes at least four transistors and one capacitor to respectively realize functions such as signal input, signal output, and register reset, or it can also include more transistors and / or capacitors, for example, adding sub-circuits for realizing pull-up node control, pull-down node control, noise reduction and other functions, etc., to achieve more stable input, output and reset, and the embodiments of the present disclosure are not limited to this.

[0058] For example, if the signal line 120 is a data line, the first electrode pattern 130 can be electrically connected between the corresponding data line and a data driver circuit. The data driver circuit is used to provide corresponding data signals to multiple columns of pixel units 110 in the display area 101, thereby enabling the transmission of data signals via the signal line 120 and the first electrode pattern 130. For example, the first electrode pattern 130 also at least partially functions to transmit the data signal. For example, the data driver circuit can use a reference gamma voltage to convert digital image data input from the timing controller into data signals based on multiple data control signals from the timing controller. For example, the data driver circuit can be implemented as a semiconductor chip, mounted on a flexible printed circuit board, and coupled to the data lines on the display substrate through bonding.

[0059] Figure 4A schematic diagram of a partial planar structure of a peripheral area of ​​a display substrate provided in some embodiments of the present disclosure, for example Figure 4 correspond Figure 3 The region REG2 is shown in FIG. Figure 5A A schematic diagram of a partial cross-sectional structure of a peripheral area of ​​a display substrate provided in some embodiments of the present disclosure, for example Figure 5A The display substrate 10 may be Figure 3 Schematic diagram of the partial cross-sectional structure of the AA' line shown in FIG. Figure 5B A schematic diagram of a partial cross-sectional structure of a peripheral area of ​​another display substrate provided in some embodiments of the present disclosure, for example Figure 5B The display substrate 10 may be Figure 3 Schematic diagram of the partial cross-sectional structure of the BB' line shown in FIG.

[0060] For example, combined with Figure 3-5B As shown, the orthographic projection of the first electrode pattern 130 on the substrate 100 is located within the orthographic projection of the second electrode pattern 140 on the substrate 100. That is, in a direction R1 perpendicular to the surface of the substrate 100, the second electrode pattern 140 completely covers the first electrode pattern 130. This increases the overlap area between the first and second electrode patterns 130, 140 in the direction R1 perpendicular to the surface of the substrate 100, thereby increasing the capacitance of the compensation capacitor formed between the first and second electrode patterns 130, 140. This allows for a stable capacitance to be formed between the first and second electrode patterns 130, 140. This further enhances the compensation effect on the transmission load of the signal lines 120, thereby improving the stability and consistency of the signal transmission effect of the multiple signal lines 120 in the display area 101.

[0061] It should be noted that in some embodiments of the present disclosure, in order to improve the electrical connection between the first electrode pattern 130 and the signal line 120, a connector for achieving electrical connection between the first electrode pattern 130 and the signal line 120 may be provided between the first electrode pattern 130 and the signal line 120. For example, the connector may be located on the same layer as the first electrode pattern 130 or the signal line 120, or may be located on a layer different from the first electrode pattern 130 and the signal line 120, and the embodiments of the present disclosure are not limited in this regard.

[0062] For example, in Figure 3 In some of the embodiments shown, the first electrode pattern 130 extends in a straight line and is in the shape of an elongated strip; in some other embodiments of the present disclosure, the first electrode pattern 130 may also extend in a curved line, a broken line, or other suitable contours, and the shape of the first electrode pattern 130 may also be, for example, an elliptical, square, serrated, or other suitable regular or irregular shapes according to actual needs, and the embodiments of the present disclosure are not limited to this.

[0063] For example, combined with Figure 3-5B As shown, the second electrode pattern 140 is located on the side of the first electrode pattern 130 away from the base substrate 100, so that the second electrode pattern 140 can play an electric field shielding role, which can weaken or avoid the interference of other structures or devices in the display substrate 10 located on the side of the second electrode pattern 140 away from the base substrate 100 on the electrical signal transmitted on the first electrode pattern 130, thereby improving the stability of the electrical signal transmitted on the signal line 120 electrically connected to the first electrode pattern 130.

[0064] Figure 6 Schematic diagram of a partial cross-sectional structure of a display area and a partial cross-sectional structure of a peripheral area of ​​a display substrate provided in some embodiments of the present disclosure, for example Figure 6 The cross-sectional structure of the display substrate 10 shown may include Figure 5A The cross-sectional structure of the peripheral region 102 of the display substrate 10 is shown as follows: Figure 5B The partial cross-sectional structure of the peripheral area 102 of the display substrate 10 is shown, and also includes the partial cross-sectional structure of the display area 101 of the display substrate 10 , for example, the partial cross-sectional structure of the pixel driving circuit of a pixel unit 110 in the display area 101 .

[0065] For example, combined with Figure 3-Figure 6 As shown, at least one of the plurality of pixel units 110 (e.g., each pixel unit 110) includes a pixel driving circuit located on a base substrate 100, and the pixel driving circuit includes a thin film transistor 160 and a storage capacitor 170. The thin film transistor 160 includes an active layer 161, a gate 162, a source 163, and a drain 164. The storage capacitor 170 includes a first capacitor electrode 171 and a second capacitor electrode 172 that is opposite to the first capacitor electrode 171 in a direction R1 perpendicular to the plate surface of the base substrate 100. The source 163 and the drain 164 are located on a side of the active layer 161 away from the base substrate 100.

[0066] For example, the first electrode pattern 130, the gate electrode 162, and the first capacitor electrode 171 are arranged on the same layer, and the second electrode pattern 140 and the second capacitor electrode 172 are arranged on the same layer. Thus, by forming the first electrode pattern 130, the gate electrode 162, and the first capacitor electrode 171 on the same layer during the manufacturing process (for example, using the same material layer through a patterning process), and forming the second electrode pattern 140 and the second capacitor electrode 172 on the same layer during the manufacturing process, the manufacturing process of the display substrate 10 can be simplified, the manufacturing cost of the display substrate 10 can be reduced, and thus it is conducive to the mass production and application of the display substrate 10.

[0067] It should be noted that, in the embodiments of the present disclosure, “same-layer arrangement” means that two functional layers or structural layers are in the same layer and are formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed by the same material layer, and the required patterns and structures can be formed by the same composition process. For example, the material layer can be formed first and then formed by the material layer through a composition process.

[0068] For example, the display substrate 10 further includes a first insulating layer 1101 located between the first electrode pattern 130 and the second electrode pattern 140. The material of the first insulating layer 1101 may include, for example, silicon nitride or silicon oxynitride, or may also include other insulating materials with a higher dielectric constant. Thus, by using an insulating material with a higher dielectric constant (such as silicon nitride or silicon oxynitride) as the first insulating layer 1101 between the first electrode pattern 130 and the second electrode pattern 140, a compensation capacitor with a larger capacitance can be formed between the first electrode pattern 130 and the second electrode pattern 140, thereby reducing the size of the first electrode pattern 130 and the second electrode pattern 140. As a result, the space required to be occupied by the first electrode pattern 130 and the second electrode pattern 140 in a plane parallel to the base substrate 100 can be further reduced, which is conducive to achieving a narrow frame design for the display substrate 10.

[0069] For example, the first insulating layer 1101 is located between the first electrode pattern 130 and the second electrode pattern 140, that is, between the first capacitor electrode 171 and the second capacitor electrode 172. Therefore, the first insulating layer 1101 can not only increase the capacitance of the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140, but also increase the capacitance of, for example, the storage capacitor formed between the first capacitor electrode 171 and the second capacitor electrode 172, thereby improving the overall performance of the display substrate 10 and improving the stability of the display substrate 10.

[0070] For example, the display substrate 10 further includes a buffer layer 1104 , a second insulating layer 1102 and a third insulating layer 1103 . The buffer layer 1104 is located on the base substrate 100, the active layer 161 is located on the side of the buffer layer 1104 away from the base substrate 100, the second insulating layer 1102 is located on the side of the active layer 161 away from the base substrate 100, the first electrode pattern 130, the gate 162 and the first capacitor electrode 171 are located on the side of the second insulating layer 1102 away from the base substrate 100, the first insulating layer 1101 is located on the side of the first electrode pattern 130, the gate 162 and the first capacitor electrode 171 away from the base substrate 100, the second electrode pattern 140 and the second capacitor electrode 172 are located on the side of the first insulating layer 1101 away from the base substrate 100, the third insulating layer 1103 is located on the side of the second electrode pattern 140 and the second capacitor electrode 172 away from the base substrate 100, and the source 163 and the drain 164 are located on the side of the third insulating layer 1103 away from the base substrate 100.

[0071] For example, Figure 6 As shown, multiple signal lines 120 can be arranged in the same layer as the source 163 and the drain 164 of the thin film transistor 160, and the first electrode pattern 130 can be electrically connected to the signal line 120 through, for example, a via structure that penetrates the first insulating layer 1101 and the third insulating layer 1103, thereby compensating for the transmission load of the signal line 120.

[0072] For example, the display substrate further includes a protective layer (not shown) located on the side of the source 163 and the drain 164 away from the base substrate 100, and a light-emitting element (not shown) arranged on the side of the protective layer away from the base substrate 100, and the source 163 or the drain 164 is electrically connected to the light-emitting element arranged on the protective layer through a via located in the protective layer.

[0073] For example, the material of the active layer 161 may include polycrystalline silicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate 162 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (e.g., a three-layer metal stack of titanium, aluminum, and titanium (Al / Ti / Al)). The material of the source 163 and the drain 164 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure may be a multi-metal layer stack (e.g., a three-layer metal stack of titanium, aluminum, and titanium (Al / Ti / Al)). The embodiments of the present disclosure do not specifically limit the materials of each structural or functional layer.

[0074] For example, the buffer layer 1104 can prevent harmful substances in the base substrate 100 from invading the interior of the display substrate 10, and can also increase the adhesion of the film layer in the display substrate 10 on the base substrate 100. For example, the material of the buffer layer 1104 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the material of one or more of the first insulating layer 1101, the second insulating layer 1102, the third insulating layer 1103, and the protective layer may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The materials of the first insulating layer 1101, the second insulating layer 1102, the third insulating layer 1103, the buffer layer 1104, and the protective layer may be the same as or different from each other, and the embodiments of the present disclosure are not limited to this.

[0075] It should be noted that Figure 6 , the thin film transistor 160 is shown as an example of a top-gate thin film transistor, while in some other embodiments of the present disclosure, the thin film transistor 160 may also be a bottom-gate thin film transistor or other suitable types of thin film transistors, and the embodiments of the present disclosure are not limited to this.

[0076] It should be noted that the detailed description of the pixel driving circuit of the display substrate 10 can be referred to in the following Figure 7 and Figures 8A-8E The content of the specific example of a pixel driving circuit shown is not repeated here.

[0077] In some embodiments of the present disclosure, Figure 3-Figure 6 As shown, the display substrate 10 further includes a first voltage source 181, and the second electrode pattern 140 is configured to receive a first voltage signal from the first voltage source 181, thereby ensuring that the second electrode pattern 140 has a stable voltage. This improves the stability of the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140, and further reduces or prevents interference with the electrical signal transmitted on the first electrode pattern 130 by other structures or devices on the display substrate 10 located on a side of the second electrode pattern 140 away from the base substrate 100. For example, the first voltage signal can be a high-level voltage signal or a low-level voltage signal, and the embodiments of the present disclosure are not limited thereto.

[0078] For example, Figure 3-Figure 6 As shown, the peripheral region 102 further includes a power trace pattern 182. The power trace pattern 182 is electrically connected to the first voltage source 181, and the second electrode pattern 140 is electrically connected to the power trace pattern 182 to receive a first voltage signal through the power trace pattern 182. This improves the layout structure of the display substrate 10, thereby facilitating a narrow-frame design for the display substrate 10 and simplifying the manufacturing process of the display substrate 10.

[0079] For example, in some examples, in a direction parallel to the surface of the base substrate 100, the power trace pattern 182 may be located between the first voltage source 181 and the second electrode pattern 140, or may be located on a side of the first voltage source 181 and the second electrode pattern 140 away from the display area 101; or, in some examples, in a direction perpendicular to the surface of the base substrate 100, the power trace pattern 182 may also at least partially overlap with the second electrode pattern 140, and the embodiments of the present disclosure are not limited to this.

[0080] For example, the power wiring pattern 182 can be set in the same layer as the source 163 and the drain 164 of the thin film transistor 160, and the second electrode pattern 140 is electrically connected to the power wiring pattern 182 through, for example, a via structure passing through the third insulating layer 1103, thereby optimizing the layout structure within the peripheral area 102 of the display substrate 10.

[0081] For example, in a direction parallel to the surface of the base substrate 100, at least a portion (e.g., all of the portion) of the second electrode pattern 140 is electrically connected between the power trace pattern 182 and the plurality of pixel units 110, and the power trace pattern 182 provides a first voltage signal to at least a portion of the plurality of pixel units 110 through the second electrode pattern 140. Thus, while the second electrode pattern 140 and the first electrode pattern 130 form a compensation capacitor to compensate for the transmission load on the signal line 120 electrically connected to the first electrode pattern 130, the second electrode pattern 140 can also be used to transmit a power voltage signal (i.e., the first voltage signal) for display, thereby further optimizing the layout structure of the display substrate 10, helping the display substrate 10 achieve a narrow-frame design, and also improving the stability of the display substrate 10.

[0082] For example, Figure 3 As shown, the second electrode pattern 140 can be electrically connected to a plurality of first power lines 183 in the display area 101, so as to transmit the first voltage signal provided by the first voltage source 181 to the pixel unit 110 through the first power lines 183. For example, the first power lines 183 can be provided in the same layer as the source 163 and the drain 164 of the thin film transistor 160, and the second electrode pattern 140 is electrically connected to the first power lines 183 through, for example, a via structure penetrating the third insulating layer 1103.

[0083] For example, Figure 3-Figure 6As shown, the peripheral region 102 of the display substrate 10 includes a plurality of first electrode patterns 130, which are spaced apart. For example, in a direction parallel to the surface of the base substrate 100, the peripheral region 102 further includes a spacer pattern 190 located between two adjacent first electrode patterns 130 and insulated from the first electrode patterns 130. The spacer pattern 190 can reduce or prevent signal interference between adjacent first electrode patterns 130, thereby improving the stability of the electrical signals transmitted by the first electrode patterns 130.

[0084] In some embodiments of the present disclosure, the spacing pattern 190 can be configured to receive a second voltage signal from a second voltage source different from the first voltage source, thereby enabling the spacing pattern 190 and the adjacent first electrode pattern 130 to form a capacitor in a plane parallel to the board surface of the base substrate 100, thereby further enhancing the compensation effect for the transmission load on the signal line 120 electrically connected to the first electrode pattern 130, and further enhancing the stability and consistency of the signal transmission effect of multiple signal lines 120 in the display area 101.

[0085] In some embodiments of the present disclosure, the spacing pattern 190 may also be electrically connected to the second electrode pattern 140 to receive a first voltage signal from the first voltage source 181. This allows the spacing pattern 190 and the adjacent first electrode pattern 130 to form a capacitor in a plane parallel to the surface of the base substrate 100, thereby further optimizing the layout structure within the peripheral area 102 of the display substrate 10, thereby helping the display substrate 10 to achieve a narrow-border design.

[0086] For example, Figure 3 As shown, the spacer pattern 190 can be electrically connected to the second electrode pattern 140 via the first power line 183. The spacer pattern 190 can be provided in the same layer as the active layer 161 of the thin film transistor 160, and can be electrically connected to the first power line 183 via a via structure that penetrates at least the first insulating layer 1101, the second insulating layer 1102, and the third insulating layer 1103, and can further be electrically connected to the second electrode pattern 140. Thus, by forming the spacer pattern 190 and the active layer 161 of the thin film transistor 160 in the same layer during the manufacturing process (e.g., using the same material layer through a patterning process), the manufacturing process of the display substrate 10 can be further simplified, reducing the manufacturing cost of the display substrate 10, thereby facilitating mass production and application of the display substrate 10.

[0087] In an embodiment of the present disclosure, the spacing pattern 190 extends in a straight line and is in the shape of an elongated strip; while in some other embodiments of the present disclosure, the spacing pattern 190 may also extend in a curved line, a broken line or other suitable contour, and the shape of the spacing pattern 190 may also be, for example, an elliptical, square, serrated or other suitable regular or irregular shape according to actual needs, and the embodiments of the present disclosure are not limited to this.

[0088] For example, Figure 3-Figure 6 Taking the elongated strip-shaped spacing pattern 190 as an example, in the extension direction of the spacing pattern 190, the spacing pattern 190 includes a first end and a second end opposite each other, with the first end being closer to the display area 101 than the second end. The first end of the spacing pattern 190 can be electrically connected to the first power line 183, and further electrically connected to the second electrode pattern 140, for example, via a via structure that penetrates at least the first insulating layer 1101, the second insulating layer 1102, and the third insulating layer 1103, thereby receiving the first voltage signal. The second end of the spacing pattern 190 can be suspended, eliminating the need for a corresponding via structure, thereby reducing the number of vias required in the display substrate 10 and further simplifying the manufacturing process of the display substrate 10. Alternatively, in some other examples of the present disclosure, the first and second ends of the spacing pattern 190 can both be electrically connected to the first power line 183 or the second electrode pattern 140 via a via structure to simultaneously receive the first voltage signal, thereby improving the stability of the first voltage signal transmitted on the spacing pattern 190. The embodiments of the present disclosure are not limited to this.

[0089] In some embodiments of the present disclosure, since the peripheral area 102 provided with the spacing pattern 190 at least partially surrounds the display area 101 and is arranged along the edge of the display area 101, by providing the spacing pattern 190 on the same layer as the active layer 161 of the thin film transistor 160, excessive etching of the active layer near the edge of the display area 101 during the preparation process of the display substrate 10 can be weakened or avoided, thereby improving the etching uniformity at the boundary position of the display area 101 and achieving a better etching effect.

[0090] For example, Figure 3-Figure 6As shown, the second electrode patterns 140 can be continuously arranged along the edge of the display area 101, and at least partially overlap with the multiple first electrode patterns 130 in a direction R1 perpendicular to the surface of the base substrate 100, and are arranged insulated from each other. This can improve the consistency and stability of the first voltage signal transmitted by the second electrode patterns 140, thereby improving the consistency and stability of the multiple compensation capacitors formed between the second electrode patterns 140 and the multiple first electrode patterns 130, further improving the signal transmission performance of the signal lines 120 electrically connected to the first electrode patterns 130. Furthermore, the continuously arranged second electrode patterns 140 help simplify the manufacturing process of the display substrate 10, reduce the manufacturing cost of the display substrate 10, and thus facilitate the mass production and application of the display substrate 10.

[0091] For example, Figure 2A Taking the specific example of the display substrate 10 shown as an example, the second electrode pattern 140 can be continuously arranged along the edge of the display area 101 and in a stepped shape, that is, the electrode patterns at the upper and lower steps adjacent to each other are connected to each other to form a whole second electrode pattern 140, thereby reducing the voltage drop when the first voltage signal is transmitted through the second electrode pattern 140, thereby further improving the brightness uniformity and consistency of the display screen.

[0092] For example, Figure 2A As shown, the multiple pixel units 110 include a first column of pixel units 111 and a second column of pixel units 112. The number of pixel units 110 in the first column of pixel units 111 is less than the number of pixel units 110 in the second column of pixel units 112. The signal line 120 electrically connected to the first column of pixel units 111 is electrically connected to a first electrode pattern 130. Thus, the transmission load of the signal line 120 electrically connected to the first column of pixel units 111 is compensated by the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140, thereby improving the signal transmission effect on the signal line 120, so that the signal transmission effect on the signal line 120 is basically consistent with the signal transmission effect of other signal lines 120 (for example, the signal line 120 electrically connected to the second column of pixel units 112).

[0093] For example, the signal line 120 electrically connected to the second column of pixel cells 112 may also be electrically connected to another first electrode pattern 130. The compensation capacitance formed by the second electrode pattern 140 and the first electrode pattern 130 electrically connected to the signal line 120 electrically connected to the first column of pixel cells 111 is greater than the compensation capacitance formed by the second electrode pattern 140 and the other first electrode pattern 130 electrically connected to the signal line 120 electrically connected to the second column of pixel cells 112. Thus, by using different compensation capacitances to compensate for the transmission load of the signal line 120 electrically connected to the first column of pixel cells 111 and the transmission load of the signal line 120 electrically connected to the second column of pixel cells 112, respectively, the consistency and stability of the signal transmission performance of the signal line 120 electrically connected to the first column of pixel cells 111 and the signal transmission performance of the signal line 120 electrically connected to the second column of pixel cells 112 can be improved. This improves the consistency and stability of the signal transmission performance of the multiple signal lines 120 within the display area 101, thereby improving the display quality of the provided display image and reducing or avoiding display anomalies or poor display effects.

[0094] For example, the multiple pixel units 110 also include a third column of pixel units 113, and load compensation can be provided for the signal lines 120 electrically connected to the first column of pixel units 111 and the second column of pixel units 112 based on the transmission load of the signal lines 120 electrically connected to the third column of pixel units 113, so that the loads of the compensated signal lines 120 electrically connected to the first column of pixel units 111 and the second column of pixel units 112 are respectively substantially the same as the load of the signal lines 120 electrically connected to the third column of pixel units 113, thereby making the loads of the signal lines 120 electrically connected to each column of pixel units 110 in the display substrate 10 substantially consistent, thereby improving the consistency of the signal transmission effects of each signal line 120 in the display area 101 and improving the display effect of the display screen.

[0095] For example, the lengths of the first electrode pattern 130 and the second electrode pattern 140 in the column direction can be different, or the lengths of the first electrode pattern 130 and the second electrode pattern 140 in the row direction can be different. For example, the lengths of the first electrode pattern 130 and the second electrode pattern 140 in the column direction or the row direction can be designed to provide different load compensations. For example, taking the example of providing data signals to each column of pixel cells 110 in the display area 101 via signal lines 120, for a column including fewer pixel cells 110, a greater load compensation amount needs to be provided to the signal lines 120 electrically connected to the column of pixel cells 110. Therefore, the first electrode pattern 130 and the second electrode pattern 140 need to have a greater length in the column direction or the row direction. That is, the fewer the number of pixel cells 110 in a column, the greater the load compensation amount needs to be provided to the signal lines 120 electrically connected to the column of pixel cells 110. This allows the first electrode pattern 130 and the second electrode pattern 140 to be flexibly arranged within the peripheral area 102, thereby further optimizing the layout structure within the peripheral area 102 of the display substrate 10.

[0096] For example, when compensating the transmission load on the signal line 120 electrically connected to the first electrode pattern 130 by the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140, the compensation amount can be as follows: Figure 2A or Figure 2B As shown in FIG, the first end or the second end of the signal line 120 is electrically connected to a first electrode pattern 130, or as shown in FIG. Figure 2C As shown in FIG, the first end of the signal line 120 is electrically connected to one first electrode pattern 130 and the second end is electrically connected to another first electrode pattern 130, that is, the two ends of the signal line 120 are electrically connected to the two first electrode patterns 130, respectively, to increase the load compensation amount. The embodiments of the present disclosure are not limited to this.

[0097] In some embodiments of the present disclosure, the extension direction of at least part of the edge of the display area 101 of the display substrate 10 intersects with and is not perpendicular to the extension direction of the signal line 120. For example, it can be designed according to the user's actual requirements for the shape of the display substrate 10 to provide a display substrate 10 with different shapes or contours, rather than being limited to a single square display substrate with right angles.

[0098] For example, the display substrate provided in the embodiment of the present disclosure, such as the display substrate 10 or the display substrate 20 , may be an organic light emitting diode display substrate.

[0099] For example, the display substrate provided in the embodiment of the present disclosure may also be a quantum dot light-emitting diode display substrate, an electronic paper display substrate, or other substrates with display functions or other types of display substrates, and the embodiment of the present disclosure does not limit this.

[0100] Figure 7 This is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided in some embodiments of the present disclosure. Figures 8A-8E This is a schematic diagram of various layers of a pixel driving circuit in a display substrate provided in some embodiments of the present disclosure. For example, Figure 6 The storage capacitor 170 shown in FIG. 1 may be Figure 7 and Figure 8A The storage capacitor Cst in the pixel driving circuit 7120 shown in FIG. Figure 6 The thin film transistor 160 shown in FIG. Figure 7 and Figure 8A At least one of the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 in the pixel driving circuit 7120 shown in FIG. Figure 7 and Figure 8A The specific structure of the pixel driving circuit 7120 shown in FIG is only an exemplary description, and the embodiments of the present disclosure include but are not limited to this.

[0101] In some embodiments, as Figure 7 As shown, the pixel driving circuit 7120 includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, a plurality of signal lines (for example, including the signal line 120 in the above embodiment) connected to the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, and a storage capacitor Cst. The plurality of signal lines include a gate line GL, a light emitting control line EM, an initialization line RL, a data line DL and a first power line VDD (for example, the first power line 183 in the above embodiment). The gate line GL may include a first gate line GLn and a second gate line GLn-1. For example, the first gate line GLn may be used to transmit a gate scan signal, and the second gate line GLn-1 may be used to transmit a reset signal. The light emitting control line EM may be used to transmit a light emitting control signal. Thus, the pixel driving circuit 7120 is a 7T1C pixel driving circuit.

[0102] For example, taking the signal line 120 in the above embodiment as the data line DL as an example, the transmission load of the data line DL electrically connected to the first electrode pattern 130 is compensated by the compensation capacitor Ccp formed between the first electrode pattern 130 and the second electrode pattern 140, thereby improving the compensation effect of the data signal transmitted on the data line DL.

[0103] For example, the first power line VDD can be directly electrically connected to the power wiring pattern 182 in the above embodiment to receive the first voltage signal provided by the first voltage source 181, or can be electrically connected to the power wiring pattern 182 by being electrically connected to the second wiring pattern 140 in the above embodiment.

[0104] It should be noted that the embodiments of the present disclosure include but are not limited to this. The pixel driving circuit 7120 may also adopt other types of circuit structures, such as a 7T2C structure or a 9T2C structure, etc., and the embodiments of the present disclosure are not limited to this.

[0105] For example, Figure 7 As shown, the first gate G1 of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4. The first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5. The first drain D1 of the first thin film transistor T1 is electrically connected to the third source S3 of the third thin film transistor T3 and the sixth source S6 of the sixth thin film transistor T6.

[0106] For example, Figure 7 As shown, the second gate G2 of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive a gate scan signal, the second source S2 of the second thin film transistor T2 is configured to be electrically connected to the data line DL to receive a data signal, and the second drain D2 of the second thin film transistor T2 is electrically connected to the first source S1 of the first thin film transistor T1.

[0107] For example, Figure 7 As shown, the third gate G3 of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, the third source S3 of the third thin film transistor T3 is electrically connected to the first drain electrode D1 of the first thin film transistor T1, and the third drain D3 of the third thin film transistor T3 is electrically connected to the first gate G1 of the first thin film transistor T1.

[0108] For example, Figure 7 As shown, the fourth gate G4 of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, the fourth source S4 of the fourth thin film transistor T4 is configured to be electrically connected to the initialization line RL to receive an initialization signal, and the fourth drain D4 of the fourth thin film transistor T4 is electrically connected to the first gate G1 of the first thin film transistor T1.

[0109] For example, Figure 7 As shown, the fifth gate G5 of the fifth thin film transistor T5 is configured to be electrically connected to the light emitting control line EM to receive the light emitting control signal, the fifth source S5 of the fifth thin film transistor T5 is configured to be electrically connected to the first power line VDD to receive the first power signal, and the fifth drain D5 of the fifth thin film transistor T5 is electrically connected to the first source S1 of the first thin film transistor T1.

[0110] For example, Figure 7As shown, the sixth gate G6 of the sixth thin film transistor T6 is configured to be electrically connected to the light emitting control line EM to receive a light emitting control signal, the sixth source S6 of the sixth thin film transistor T6 is electrically connected to the first drain D1 of the first thin film transistor T1, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (e.g., anode) of the light emitting element.

[0111] For example, Figure 7 As shown, the seventh gate electrode G7 of the seventh thin-film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, the seventh source electrode S7 of the seventh thin-film transistor T7 is electrically connected to the first display electrode (e.g., the anode) of the light-emitting element, and the seventh drain electrode D7 of the seventh thin-film transistor T7 is configured to be electrically connected to the initialization line RL to receive an initialization signal. For example, the seventh drain electrode D7 of the seventh thin-film transistor T7 can be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin-film transistor T4.

[0112] For example, Figure 7 As shown, the storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2 (e.g., the first capacitor electrode 171 and the second capacitor electrode 172 in the above embodiment). The second capacitor electrode CE2 is electrically connected to the first power line VDD, and the first capacitor electrode CE1 is electrically connected to the first gate electrode G1 of the first thin film transistor T1 and the third drain electrode D3 of the third thin film transistor T3.

[0113] For example, Figure 7 As shown, the second display electrode (eg, cathode) of the light emitting element is electrically connected to the second power line VSS.

[0114] It should be noted that one of the first power line VDD and the second power line VSS is a power line providing a high voltage, and the other is a power line providing a low voltage. Figure 7 In the illustrated embodiment, a first power line VDD (e.g., the first power line 183 electrically connected to the first voltage source 181) provides a constant first voltage (i.e., the first voltage signal), which is a positive voltage; and a second power line VSS provides a constant second voltage, which can be a negative voltage, etc. For example, in some examples, the second voltage can be a ground voltage.

[0115] It should be noted that, in some embodiments, the reset signal and the initialization signal may be the same signal.

[0116] It should be noted that, according to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present disclosure are described using P-type transistors (e.g., P-type MOS transistors) as an example. That is, in the description of the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors. However, the transistors in the embodiments of the present disclosure are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (e.g., N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs.

[0117] It should be noted that the transistors used in the embodiments of the present disclosure may be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The thin-film transistors may include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors. The source and drain of the transistor may be structurally symmetrical, so the source and drain may be physically identical. The source and drain of all or some of the transistors in the embodiments of the present disclosure may be interchangeable as needed.

[0118] For example, Figure 8A Schematic diagram of the stacking position relationship of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer of the pixel driving circuit 7120.

[0119] Figure 8B 7120 shows the semiconductor layer of the pixel driving circuit. Figure 8B As shown, the semiconductor layer can be formed by patterning a semiconductor material. The semiconductor layer can be used to form the active layers of the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7. Each active layer may include a source region, a drain region, and a channel region between the source and drain regions. For example, the semiconductor layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source and drain regions can be regions doped with n-type impurities or p-type impurities.

[0120] For example, the active layer 161 and the spacing pattern 190 in the above embodiment may be located in the above semiconductor layer.

[0121] In the display substrate provided in some embodiments of the present disclosure, a gate insulating layer (such as the second insulating layer 1102 in the above embodiment, Figures 8A-8E ), which is not shown in the figure, is used to protect the above-mentioned semiconductor layer.

[0122] Figure 8C 71 shows the first conductive layer of the pixel driving circuit 7120. For example, Figure 8C As shown, the first conductive layer of the pixel driving circuit 7120 is arranged on the gate insulating layer so as to Figure 8B The semiconductor layer shown is insulated. The first conductive layer may include a first capacitor electrode CE1 of the storage capacitor Cst, a first gate line GLn, a second gate line GLn-1, a light emitting control line EM, and gates of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7. Figure 8C As shown, the gates of the second thin-film transistor T2, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7 are the portions where the first gate line GLn and the second gate line GLn-1 overlap with the semiconductor layer. The third thin-film transistor T3 may be a dual-gate thin-film transistor, one gate of which may be the portion where the first gate line GLn overlaps with the semiconductor layer, and the other gate of which may be a protrusion from the first gate line GLn. The gate of the first thin-film transistor T1 may be the first capacitor electrode CE1. The fourth thin-film transistor T4 may be a dual-gate thin-film transistor, with both gates being the portions where the second gate line GLn-1 overlaps with the semiconductor layer.

[0123] For example, the first electrode pattern 130 , the gate electrode 162 and the first capacitor electrode 171 in the above embodiment may be located in the above-mentioned first conductive layer.

[0124] In the display substrate provided in some embodiments of the present disclosure, a first interlayer insulating layer (such as the first insulating layer 1101 in the above embodiment, Figures 8A-8E (not shown) for protecting the first conductive layer.

[0125] Figure 8D 71 shows the second conductive layer of the pixel driving circuit 7120. For example, Figure 8D As shown, the second conductive layer of the pixel driving circuit 7120 includes a second capacitor electrode CE2 of the storage capacitor Cst and an initialization line RL. The second capacitor electrode CE2 at least partially overlaps with the first capacitor electrode CE1 to form the storage capacitor Cst.

[0126] For example, the second electrode pattern 140 and the second capacitor electrode 172 in the above embodiment may be located in the above second conductive layer.

[0127] In some embodiments, the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792. The orthographic projection of the first light shielding portion 791 on the base substrate 710 covers the active layer of the second thin-film transistor T2, the drain electrode of the third thin-film transistor T3, and the drain electrode of the fourth thin-film transistor T4, thereby preventing external light from affecting the active layers of the second thin-film transistor T2, the third thin-film transistor T3, and the fourth thin-film transistor T4. The orthographic projection of the second light shielding portion 792 on the base substrate 710 covers the active layer between the two gate electrodes of the third thin-film transistor T3, thereby preventing external light from affecting the active layer of the third thin-film transistor T3. The first light shielding portion 791 may be integrally formed with the second light shielding portion 792 of the adjacent pixel driving circuit and electrically connected to the first power line VDD via a via extending through the second interlayer insulating layer.

[0128] In the display substrate provided in some embodiments of the present disclosure, a second interlayer insulating layer (such as the third insulating layer 1103 in the above embodiment, Figures 8A-8E (not shown) for protecting the second conductive layer.

[0129] Figure 8E 71 shows the third conductive layer of the pixel driving circuit 7120. For example, Figure 8E As shown, the third conductive layer of the pixel driving circuit 7120 includes a data line DL (eg, the signal line 120 in the above embodiment) and a first power line VDD (eg, the first power line 183 in the above embodiment). Figure 8A and Figure 8E As shown, the data line DL is connected to the source region of the second thin-film transistor T2 in the semiconductor layer through at least one via in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power line VDD is connected to the source region of the corresponding fifth thin-film transistor T5 in the semiconductor layer through at least one via in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power line VDD is connected to the second capacitor electrode CE2 in the second conductive layer through at least one via in the second interlayer insulating layer.

[0130] For example, the power wiring pattern 182 , the signal line 120 , the first power line 183 , the source 163 and the drain 164 in the above embodiment may be located in the above third conductive layer.

[0131] For example, the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3. One end of the first connection portion CP1 is connected to the drain region of the corresponding third thin-film transistor T3 in the semiconductor layer through at least one via in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The other end of the first connection portion CP1 is connected to the gate of the first thin-film transistor T1 in the first conductive layer through at least one via in the first interlayer insulating layer and the second interlayer insulating layer. One end of the second connection portion CP2 is connected to the initialization line RL through a via in the second interlayer insulating layer. The other end of the second connection portion CP2 is connected to the source region of the seventh thin-film transistor T7 and the source region of the fourth thin-film transistor T4 in the semiconductor layer through at least one via in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The third connection portion CP3 is connected to the drain region of the sixth thin-film transistor T6 in the semiconductor layer through at least one via in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.

[0132] In the display substrate provided in some embodiments of the present disclosure, a protective layer ( Figures 8A-8E The first display electrode (eg, anode) of the light-emitting element in the pixel unit may be disposed on the protective layer.

[0133] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate described in any embodiment of the present disclosure.

[0134] Figure 9 This is a schematic block diagram of a display device provided in some embodiments of the present disclosure. Figure 9 As shown, the display device 40 includes a display substrate 401 . The display substrate 401 may be the display substrate provided by any embodiment of the present disclosure, for example, the display substrate 10 or the display substrate 20 described above.

[0135] Figure 10 A schematic block diagram of another display device provided in some embodiments of the present disclosure. Figure 10 As shown, the display device 50 includes a display substrate 501 . The display substrate 501 may be the display substrate provided by any embodiment of the present disclosure, for example, the display substrate 10 or the display substrate 20 described above.

[0136] For example, Figure 10As shown, the display device 50 further includes a data driver 510, a gate driver 520, a timing controller 530, and a voltage source 540. For example, the gate driver 520 may include the gate scan driver circuit 150 in the embodiment described above regarding the display substrate 10, that is, it may be directly manufactured on the substrate through a semiconductor process; the voltage source 540 may include the first voltage source 181 in the embodiment described above regarding the display substrate 10, and may be implemented as a power management circuit, for example.

[0137] For example, in one embodiment, a plurality of pixel units P (such as the pixel units 110 in the embodiment of the display substrate 10 described above) are arranged in an array in the display area of ​​the display substrate 501. Each pixel unit P receives a data signal provided by a data driver 510 via a data line DL and receives a voltage signal provided by a voltage source 540 via a power line VDD. For example, in the case where the signal line in the embodiment of the present disclosure is a data line, the data line DL may include, for example, the signal line 120 in the embodiment of the display substrate 10 described above. For example, the power line VDD may include, for example, the first power line 183 in the embodiment of the display substrate 10 described above.

[0138] For example, the data driver 510 converts the digital image data RGB input from the timing controller 530 into a data signal based on the data control signal DCS provided by the timing controller 530. For example, the data driver 510 converts the data signal into an analog voltage signal based on the data control signal DCS provided by the timing controller 530, and performs processing such as operational amplification on the analog voltage signal before providing the corresponding data signal to each pixel unit P via the data line DL. For example, the data driver 510 can be implemented as a semiconductor chip.

[0139] For example, the gate driver 520 is electrically connected to each pixel unit P through a scan line SL to provide a scan signal to each pixel unit P. For example, the gate driver 520 provides a gate signal based on a plurality of scan control signals GCS provided by the timing controller 530. For example, the gate driver 520 can be implemented as a semiconductor chip, or can be integrated into the display device 50 to form a GOA circuit, such as the gate scan driver circuit 150 in the embodiment of the display substrate 10 described above.

[0140] For example, the timing controller 530 is used to process image data RGB input from outside the display device 50, provide the processed image data RGB to the data driver 510, and provide a data control signal DCS and a scan control signal GCS to the data driver 510 and the gate driver 520 to control the data driver 510 and the gate driver 520.

[0141] For example, the timing controller 530 processes externally input image data RGB to match the size and resolution of the display device 50, and then provides the processed image data RGB to the data driver 510. The timing controller 530 generates a scan control signal GCS and a data control signal DCS using synchronization signals SYNC (e.g., a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device 50. The timing controller 530 provides the generated data control signal DCS and scan control signal GCS to the data driver 510 and the gate driver 520, respectively, for controlling the data driver 510 and the gate driver 520.

[0142] The structure, function, and technical effects of the display device 40 and the display device 50 provided in the embodiments of the present disclosure can refer to the corresponding description of the display substrate 10 or the display substrate 20 provided in the above-mentioned embodiments of the present disclosure, and will not be repeated here.

[0143] For example, the display devices 40 and 50 provided in the embodiments of the present disclosure may be organic light-emitting diode display devices. Alternatively, the display devices 40 and 50 provided in the embodiments of the present disclosure may also be devices with display functions such as quantum dot light-emitting diode display devices, electronic paper display devices, or other types of display devices, and the embodiments of the present disclosure are not limited thereto.

[0144] For example, the display device 40 and the display device 50 provided in the embodiments of the present disclosure can be any product or component with a display function, such as a display substrate, a display panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited to this.

[0145] There are a few points to note:

[0146] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0147] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or first substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or intervening elements may be present.

[0148] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0149] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate having a display area and a peripheral area at least partially surrounding the display area, and comprising: substrate; The display area includes a plurality of pixel units arrayed on the substrate and a plurality of signal lines electrically connected to the plurality of pixel units respectively. The peripheral region includes at least one first electrode pattern electrically connected to at least one of the plurality of signal lines, and includes a second electrode pattern, The at least one first electrode pattern and the second electrode pattern at least partially overlap in a direction perpendicular to the plate surface of the base substrate and are spaced apart and insulated from each other. The peripheral area further includes a gate scanning driving circuit, wherein the gate scanning driving circuit is configured to provide a gate scanning signal to the plurality of pixel units. In a direction parallel to the surface of the base substrate, the at least one first electrode pattern and the second electrode pattern are located between the gate scanning driving circuit and the display area; The at least one first electrode pattern includes a plurality of first electrode patterns, and the plurality of first electrode patterns are arranged at intervals; The peripheral region further includes a spacing pattern located between two adjacent first electrode patterns and insulated from the first electrode patterns.

2. The display substrate according to claim 1, wherein An orthographic projection of the at least one first electrode pattern on the base substrate is located within an orthographic projection of the second electrode pattern on the base substrate.

3. The display substrate according to claim 1 or 2, wherein: The second electrode pattern is located on a side of the at least one first electrode pattern away from the base substrate.

4. The display substrate according to claim 3, wherein: At least one of the plurality of pixel units includes a pixel driving circuit located on the substrate, wherein the pixel driving circuit includes a thin film transistor and a storage capacitor; The thin film transistor includes an active layer, a gate, a source electrode and a drain electrode, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode in a direction perpendicular to the plate surface of the substrate; The source electrode and the drain electrode are located on a side of the active layer away from the substrate. The first electrode pattern, the gate, and the first capacitor electrode are arranged in the same layer, and the second electrode pattern and the second capacitor electrode are arranged in the same layer.

5. The display substrate according to claim 4, wherein: The plurality of signal lines are arranged in the same layer as the source and the drain of the thin film transistor, and the at least one first electrode pattern is electrically connected to at least one of the plurality of signal lines through a via structure.

6. The display substrate according to claim 4, wherein: The second electrode pattern is configured to receive a first voltage signal from a first voltage source.

7. The display substrate according to claim 6, wherein: The peripheral area also includes a power supply wiring pattern, The power wiring pattern is electrically connected to the first voltage source, and the second electrode pattern is electrically connected to the power wiring pattern to receive the first voltage signal through the power wiring pattern.

8. The display substrate according to claim 7, wherein: The power supply wiring pattern is arranged on the same layer as the source and drain of the thin film transistor. The second electrode pattern is electrically connected to the power wiring pattern through a via structure.

9. The display substrate according to claim 7, wherein: In a direction parallel to the surface of the base substrate, at least a portion of the second electrode pattern is electrically connected between the power wiring pattern and the plurality of pixel units. The power wiring pattern provides the first voltage signal to at least part of the plurality of pixel units through the second electrode pattern.

10. The display substrate according to claim 6, wherein: The spaced pattern is configured to receive a second voltage signal from a second voltage source different from the first voltage source.

11. The display substrate according to claim 1, wherein: The spacing pattern is electrically connected to the second electrode pattern to receive a first voltage signal from a first voltage source.

12. The display substrate according to claim 4, wherein: The spacing pattern is arranged in the same layer as the active layer of the thin film transistor.

13. The display substrate according to claim 1, wherein The second electrode patterns are continuously arranged along the edge of the display area, and at least partially overlap with the plurality of first electrode patterns in a direction perpendicular to the plate surface of the base substrate and are arranged insulated from each other.

14. The display substrate according to claim 1 or 2, wherein: An extension direction of at least a portion of the edge of the display area intersects with an extension direction of the plurality of signal lines and is not perpendicular to the extension direction.

15. The display substrate according to claim 1 or 2, wherein: The display substrate further includes a first insulating layer located between the first electrode pattern and the second electrode pattern. The material of the first insulating layer includes silicon nitride or silicon oxynitride.

16. The display substrate according to claim 1 or 2, wherein: The plurality of pixel units include a first column of pixel units and a second column of pixel units, the number of pixel units in the first column of pixel units is less than the number of pixel units in the second column of pixel units, and the signal line electrically connected to the first column of pixel units is electrically connected to a first electrode pattern.

17. The display substrate according to claim 16, wherein: The signal line electrically connected to the second column of pixel units is electrically connected to another first electrode pattern, The compensation capacitance formed by the second electrode pattern and the one first electrode pattern electrically connected to the signal line electrically connected to the first column of pixel units is greater than the compensation capacitance formed by the second electrode pattern and the other first electrode pattern electrically connected to the signal line electrically connected to the second column of pixel units.

18. The display substrate according to claim 1 or 2, wherein: The first electrode pattern and the second electrode pattern have different lengths in the column direction, or The first electrode pattern and the second electrode pattern have different lengths in the row direction.

19. The display substrate according to claim 1 or 2, wherein: The plurality of signal lines are scan lines or data lines.

20. The display substrate according to claim 1 or 2, wherein: A first end or a second end of at least one of the plurality of signal lines is electrically connected to a first electrode pattern, or A first end of at least one of the plurality of signal lines is electrically connected to one first electrode pattern, and a second end of at least one of the plurality of signal lines is electrically connected to another first electrode pattern.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

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