A fully pipelined multi-cycle A / D conversion sampling method

Abstract

The present invention provides a full-pipeline multi-cycle A / D conversion sampling method, which includes the following steps: S1: Start the processor; S2: Assign 0 to i and 0 to s, where i is the i-th analog input signal to be collected currently, and s is the A / D conversion state to be executed; S3: Start the tasks in this cycle; S4: Determine the value of s. If s is equal to 0, then execute S5. If s is equal to 1, then execute s7. If s is equal to 2, then execute s9; S5: Select the address of i; S6: After s is incremented by 1, execute S11; S7: Start to convert the i-th analog input signal; S8: After s is incremented by 1, execute S11; S9: Select the address corresponding to the i value in the next cycle in parallel and determine whether the start conversion in the previous cycle is completed; S10: Decrement s by 1; S11: Perform other tasks in this cycle; S12: After this cycle ends, return to S3 for the next cycle. This method fully improves the operating efficiency of the processor and effectively reduces the ineffective waiting time during the A / D conversion sampling process.

Description

Technical Field

[0001] The present invention belongs to the field of airborne computers, and particularly relates to an all-pipelined multi-cycle A / D conversion sampling method. Background Art

[0002] The basic circuit model for an airborne embedded computer to perform analog-to-digital conversion on external multi-channel analog input signals is as Figure 3 shown. Among them, a multiplexer is used to select and connect a certain channel of analog signal to the subsequent A / D conversion circuit. Inside the A / D conversion circuit, after sampling and holding the signal, the analog-to-digital conversion is performed. The processor can obtain digital quantity information through the bus interface circuit of the A / D conversion circuit. Based on this hardware structure, the classical A / D conversion sampling method is as Figure 4 shown in the process. The characteristic of this process is that when performing the A / D conversion sampling task in this cycle, the digital quantity information of all complete analog signals is obtained within this cycle. The biggest drawback of this method is that it requires a large amount of waiting time. The multiplexer needs time to select data, the establishment after signal selection requires waiting time, sampling and holding requires waiting time, and A / D conversion requires waiting time. The multiple concentrated accumulations of these times will seriously restrict the performance of the real-time characteristics of the embedded computer and will affect the timely execution of other tasks in the current cycle. Summary of the Invention

[0003] In order to solve the above problems, the present invention provides an all-pipelined multi-cycle A / D conversion sampling method, which fully improves the operating efficiency of the processor and effectively reduces the ineffective waiting time-consuming during the A / D conversion sampling process.

[0004] The object of the present invention is to provide an all-pipelined multi-cycle A / D conversion sampling method, characterized in that the method comprises the following steps:

[0005] S1: Start the processor;

[0006] S2: Assign 0 to i and 0 to s, where i is the i-th channel of analog input signal to be collected currently, and s is the A / D conversion state to be executed;

[0007] S3: Start the task in this cycle;

[0008] S4: Determine the value of s. If s is equal to 0, then execute S5. If s is equal to 1, then execute s7. If s is equal to 2, then execute s9;

[0009] S5: Select the i address;

[0010] S6: Increment s by 1 and then execute S11;

[0011] S7: Start to convert the i-th channel of analog input signal;

[0012] S8: Increment s by 1, and then execute S11;

[0013] S9: Perform address strobe for the i value corresponding to the next cycle in parallel and determine whether the start conversion of the previous cycle is completed;

[0014] S10: Decrement s by 1;

[0015] S11: Perform other tasks in this cycle;

[0016] S12: After this cycle ends, return to S3 for the next cycle.

[0017] The full-pipeline multi-cycle A / D conversion sampling method provided by the present invention further has the following feature that the i address strobe is to strobe the i-th analog input signal by a command multiplexer.

[0018] The full-pipeline multi-cycle A / D conversion sampling method provided by the present invention further has the following feature that the steps of S9 are as follows:

[0019] S9.1: Determine whether i is less than N - 1. If so, perform S9.2; if not, assign 0 to i and then perform S9.3:

[0020] S9.2: Increment i by 1;

[0021] S9.3: Perform i address strobe;

[0022] S9.4: Determine whether the conversion is completed. If completed, perform S9.5; if not completed, repeat S9.4;

[0023] S9.5: Read the conversion result.

[0024] The full-pipeline multi-cycle A / D conversion sampling method provided by the present invention further has the following feature that the steps of determining whether the conversion is completed in S9.4 are as follows:

[0025] S9.4.1: Start and enter the "conversion completed" discrimination process;

[0026] S9.4.2: Assign 0 to c, where c is used for loop counting;

[0027] S9.4.3: Determine whether the value of c is less than M. If less than M, perform S9.4.5 next; otherwise, perform S9.4.4 next, where M is the counting threshold value;

[0028] S9.4.4: Perform fault handling and then perform S9.4.7 next;

[0029] S9.4.5: Determine whether the "A / D conversion completion signal indication" is in the completed state. If it is completed, execute S9.4.7 in the next step; otherwise, execute S9.4.6 in the next step:

[0030] S9.4.6: Increment i by 1, that is, add 1 to the value of i, and then execute S9.4.3 in the next step;

[0031] S9.4.7: Assign 0 to c;

[0032] S9.4.8: Exit, and the "conversion completion" discrimination process is completed.

[0033] Compared with the prior art, the beneficial effects of the present invention are:

[0034] The present invention provides a full-pipeline multi-cycle A / D conversion sampling method, which fully improves the operating efficiency of the processor and effectively reduces the ineffective waiting time during the A / D conversion sampling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 Flowchart of the full-pipeline multi-cycle A / D conversion sampling method provided by the embodiment of the present invention;

[0037] Figure 2 Flowchart of the conversion completion step in the method provided by the embodiment of the present invention;

[0038] Figure 3 Basic model of the A / D conversion sampling circuit;

[0039] Figure 4 Single-cycle full-data A / D conversion sampling method in the prior art. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] In order to make the technical means, creative features, achieved purposes, and effects of the present invention easy to understand, the following embodiments will specifically describe the full-pipeline multi-cycle A / D conversion sampling method provided by the present invention in conjunction with the drawings.

[0041] In the description of the embodiments of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0042] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise stated, the meaning of "a plurality" is two or more.

[0043] The terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] As Figure 1 shown, the present invention provides a full-pipeline multi-cycle A / D conversion sampling method, and the method includes the following steps:

[0045] S1: Start the processor;

[0046] S2: Assign 0 to i and 0 to s, where i is the i-th analog input signal to be collected currently, and s is the A / D conversion state to be executed;

[0047] S3: Start the tasks in this cycle;

[0048] S4: Determine the value of s. If s equals 0, then execute S5; if s equals 1, then execute S7; if s equals 2, then execute S9;

[0049] S5: Select the address of i;

[0050] S6: Increment s by 1 and then execute S11;

[0051] S7: Start converting the i-th analog input signal;

[0052] S8: Increment s by 1 and then execute S11;

[0053] S9: Simultaneously perform address strobe for the i value corresponding to the next cycle and determine whether the start conversion of the previous cycle is completed;

[0054] S10: Decrement s by 1;

[0055] S11: Perform other tasks for this cycle;

[0056] S12: After this cycle ends, return to S3 for the next cycle.

[0057] In some embodiments, the i address strobe is that the command multiplexer strobes the i-th analog input signal.

[0058] In some embodiments, the steps of S9 are as follows:

[0059] S9.1: Determine whether i is less than N - 1. If so, perform S9.2. If not, assign 0 to i and then perform S9.3:

[0060] S9.2: Increment i by 1;

[0061] S9.3: Perform i address strobe;

[0062] S9.4: Determine whether the conversion is completed. If completed, perform S9.5. If not completed, repeat S9.4;

[0063] S9.5: Read the conversion result.

[0064] In some embodiments, as Figure 2 shown, the steps of determining whether the conversion is completed in S9.4 are as follows:

[0065] S9.4.1: Start and enter the "conversion completed" discrimination process;

[0066] S9.4.2: Assign 0 to c, where c is used for loop counting;

[0067] S9.4.3: Determine whether the value of c is less than M. If less than M, perform S9.4.5 next. Otherwise, perform S9.4.4 next, where M is the counting threshold value;

[0068] S9.4.4: Perform fault handling and perform S9.4.7 next;

[0069] S9.4.5: Determine whether the "A / D conversion completed signal indication" is in the completed state. If completed, perform S9.4.7 next. Otherwise, perform S9.4.6 next:

[0070] S9.4.6: Increment i by 1, that is, add 1 to the value of i, and perform S9.4.3 next;

[0071] S9.4.7: Assign 0 to c;

[0072] S9.4.8: Exit, the "conversion completed" discrimination process is completed.

[0073] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention. The above is only the preferred implementation manner of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as within the protection scope of the present invention.

Claims

1. A full-pipeline multi-cycle A / D conversion sampling method, characterized in that, The method includes the following steps: S1: Start the processor; S2: Assign 0 to i and 0 to s, where i is the i-th analog input signal to be collected currently, and s is the A / D conversion status to be executed; S3: Start the tasks in this cycle; S4: Determine the value of s. If s equals 0, then execute S5; if s equals 1, then execute S7; if s equals 2, then execute S9; S5: Select the address of i; S6: Increment s by 1 and then execute S11; S7: Start to convert the i-th analog input signal; S8: Increment s by 1 and then execute S11; S9: Simultaneously select the address of the i value corresponding to the next cycle and determine whether the start conversion of the previous cycle is completed; S10: Decrement s by 1; S11: Perform other tasks in this cycle; S12: After this cycle ends, return to S3 for the next cycle, The steps of S9 are as follows: S9.1: Determine whether i is less than N - 1. If so, then execute S9.2; if not, then assign 0 to i and then execute S9.3; S9.2: Increment i by 1; S9.3: Select the address of i; S9.4: Determine whether the conversion is completed. If completed, then execute S9.5; if not completed, then repeat S9.4; S9.5: Read the conversion result, The steps of determining whether the conversion is completed in S9.4 are as follows: S9.4.1: Start and enter the "conversion completed" discrimination process; S9.4.2: Assign 0 to c, and c is used for loop counting; S9.4.3: Determine whether the value of c is less than M. If less than M, then execute S9.4.5 next; otherwise, execute S9.4.4 next, where M is the counting threshold value; S9.4.4: Fault handling, and execute S9.4.7 next; S9.4.5: Whether the "A / D conversion completed signal indication" is in the completed state. If completed, then execute S9.4.7 next; otherwise, execute S9.4.6 next; S9.4.6: Increment i by 1, that is, add 1 to the value of i, and execute S9.4.3 next; S9.4.7: Assign 0 to c; S9.4.8: Exit, and the "conversion completed" discrimination process is completed.

2. The all-pipelined multi-cycle A / D conversion sampling method according to claim 1, wherein The selection of the address of i is to select the i-th analog input signal by the command multiplexer.

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