true / false vector index register

Abstract

Disclosed herein are vector index registers for storing or loading indices of true and / or false results of compare operations in a vector processor. Each of the vector index registers stores a plurality of addresses for accessing a plurality of locations in an operand vector.

Description

[0001] Related applications

[0002] This application claims priority to U.S. patent application serial number 16 / 417,495, filed on May 20, 2019, entitled “TRUE / FALSEVECTOR INDEX REGISTERS,” the entire disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] In general, at least some embodiments disclosed herein relate to vector processors. Additionally, at least some embodiments disclosed herein relate to registers in a vector processor that store addresses for storing vectors. Background Art

[0004] A vector processor can be or include a central processing unit (CPU) that implements an instruction set containing instructions that operate on arrays of data, often called vectors. This differs from a scalar processor, where instructions operate on individual data items. Compared to scalar processors, vector processors can significantly improve performance on certain workloads, particularly numerical simulations and similar tasks. Vector processors appeared in the early 1970s, and a large portion of supercomputing designs were from the 1970s to the 1990s. The rapid decline in the price / performance ratio of more conventional microprocessor designs, such as scalar processor designs, led to a reduction in the development and manufacture of vector processors.

[0005] Generally speaking, conventional CPUs (e.g., scalar-based CPUs) can manipulate only a few pieces of data at a time. For example, such CPUs may have an instruction that essentially adds A to B and stores the result in C. The data for A, B, and C is typically referenced by passing the address to the memory location holding the data. Decoding this address and fetching the data from memory takes some time, during which the CPU can remain idle, waiting for the requested data to appear.

[0006] To reduce the amount of time these steps take, more modern CPUs use a technique called instruction pipelining, where instructions are passed through several subunits in sequence. The first subunit reads and decodes the address, the next subunit retrieves the value at that address, and the next subunit performs the mathematical operations itself. With pipelining, the CPU begins decoding the next instruction before the first one even leaves the CPU, similar to an assembly line. In this way, the address decoder and the other mentioned components are used simultaneously and continuously. Thanks to pipelining, all instructions take the same amount of time to complete.

[0007] Vector processors improve pipelining. Rather than just pipeline instructions, these processors also pipeline data. Therefore, instead of having to continually decode instructions and then fetch the data needed to complete them, vector processors fetch a single instruction from memory. This reduces decode time and power consumption (e.g., a vector processor decodes once instead of multiple times).

[0008] Vector processors, as well as other types of processors, such as conventional scalar processors, contain index registers for modifying operand addresses during the execution of a program or operation. Indexing is commonly used and is beneficial for performing vector or array operations. The contents of an index register can be added to or subtracted from an immediate address to form the effective address of the actual data or operand. Instructions often test the index register, and if the test fails, the instruction can reset the start of a loop. Some instruction sets allow for the use of multiple index registers.

[0009] Generally, it is known to use scalar registers for indexing. In other words, it is known to use scalar index registers. However, using scalar registers for indexing has many limitations. Furthermore, some of these limitations may limit the performance of processors that use index registers. For example, to access multiple locations in an operand vector, the scalar index register must be incremented, and each increment requires a separate load by the processor to access the operand vector. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure will be more fully understood through the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0011] Figure 1 An exemplary portion of an exemplary computing device 100 is shown, in accordance with some embodiments of the present disclosure.

[0012] Figure 2 An exemplary portion of an exemplary computing device 200 is shown, in accordance with some embodiments of the present disclosure.

[0013] Figure 3 An exemplary system 300 including a vector index register 302 is shown, in accordance with some embodiments of the present disclosure.

[0014] Figure 4 An exemplary system 400 including vector index registers 402a, 402b, and 402c is shown, in accordance with some embodiments of the present disclosure.

[0015] Figure 5 An exemplary system 500 including a vector index register 502 and a vector priority register 503 is shown, in accordance with some embodiments of the present disclosure.

[0016] Figure 6 Exemplary operations of a method 600 for accessing elements of an operand vector are shown, according to some embodiments of the present disclosure.

[0017] Figure 7 Exemplary operations of a method 700 for compressing elements of an operand vector are shown, in accordance with some embodiments of the present disclosure.

[0018] Figure 8 An exemplary system 800 including a vector index register 802 for compressing elements of an input operand vector stored in an input OVR 804 is shown, in accordance with some embodiments of the present disclosure.

[0019] Figure 9 Exemplary operations of a method 900 for expanding elements of an operand vector, such as compressing elements of the operand vector, are shown, in accordance with some embodiments of the present disclosure.

[0020] Figure 10 Exemplary operations of method 1000 are shown in relation to operations on a plurality of compressed vectors, in accordance with some embodiments of the present disclosure.

[0021] Figure 11 Exemplary operations of method 1100 are shown for constructing index vectors to store in vector index registers (VIR_TRUE and VIR_FALSE) for TRUE and FALSE results (eg, “0” and “1” results) of comparisons in accordance with some embodiments of the present disclosure.

[0022] Figure 12 An exemplary system 1200 for constructing index vectors to store in VIR_TRUE 1202a and VIR_FALSE 1202b is shown in accordance with some embodiments of the present disclosure.

[0023] Figure 13 Exemplary operations of method 1300 are shown for constructing a combined index vector to store in a combined vector index register (VIR_combined) of TRUE and FALSE results of comparisons, in accordance with some embodiments of the present disclosure.

[0024] Figure 14 An exemplary system 1400 for constructing a combined index vector for storage in VIR_combined 1402 is shown in accordance with some embodiments of the present disclosure.

[0025] Figure 15 An exemplary system 1500 including VIR_TRUE 1502a and VIR_FALSE 1502b is shown in accordance with some embodiments of the present disclosure.

[0026] Figure 16 Exemplary operations of method 1600 for compressing elements of an operand vector according to VIR_TRUE are shown, in accordance with some embodiments of the present disclosure.

[0027] Figure 17 An exemplary system 1700 including VIR_TRUE 1702a for compressing elements of an input operand vector stored in an input OVR 1704 is shown, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] In general, at least some embodiments disclosed herein relate to vector processors. Furthermore, at least some embodiments disclosed herein relate to registers in a vector processor that store addresses for accessing vectors. Furthermore, at least some of the embodiments disclosed herein are vector index registers in a vector processor that each store a plurality of addresses for accessing a plurality of locations in a vector.

[0029] It is known to use a scalar index register in a vector processor to reference multiple positions of a vector by changing the value stored in the scalar index register during a vector operation. However, by using a vector index register to index multiple positions of one or more operand vectors, the scalar index register can be replaced and at least the continuous changing of the value in the scalar index register during the vector operation can be avoided. This is just one example of a technical solution to the technical problem described herein.

[0030] A scalar or single-entry register can store index i, which allows operations on vector registers to begin with element i, or operations can begin with element zero. Subsequent portions of the operation access element 0+1 or i+1 on each increment. As a side note, using a single-entry register to store index i can be used for vector-first operations and indexing, which is also disclosed to some extent herein.

[0031] However, indexing with scalar registers or single-entry vectors has many limitations. Furthermore, some of these limitations can limit the performance of vector processors that use index registers. For example, to access multiple locations in an operand vector, a scalar or single-entry index register needs to be incremented, and each increment requires a separate load by the vector processor to access the operand vector.

[0032] By using a vector index register to index multiple positions of one or more operand vectors, a scalar index register can be replaced and at least continuous changing of the scalar index register during vector operations can be avoided.

[0033] Generally speaking, the embodiments disclosed herein provide specific technical solutions at least for the technical problems mentioned in the background technology section and other parts of this application, as well as other technical problems that are not described herein but are recognized by those skilled in the art.

[0034] In some embodiments, a vector index register (VIR) can store address components for vector operations using selective indexing. This is somewhat similar to vector priority processing or indexing. For example, using selective indexing, the VIR can store address parts i_1, i_2, ..., i_n. This allows operations on vector registers to traverse elements i_1, i_2, ..., i_n of the input vector, rather than i, i+1, i+2, ..., i+n of the input vector. For example, using selective indexing, the VIR can store non-sequential address parts i_1, i_3, ..., i_8. This allows operations on vector registers to traverse non-sequential elements of the input vector.

[0035] VIRs have many uses. For example, VIRs can be used to more efficiently implement vector compression or expansion functions. For example, when a vector comparison operation generates an index vector for selected elements, the selected components can be loaded into the VIR, which can be used for addressing in the generation of the compressed vector. The elements in the VIR (or elements in VMX(i)) are address components used to access non-contiguous elements in vector V(i). Instead of accessing V(i) via a single-entry index vector, where i=i+1 for each iteration, the vector processor can access V(VMX(i)) sequentially, where i=i+1 for each iteration. Furthermore, in this way, the components are only loaded once from the VIR for use by the vector processor. If a single-entry index vector is used, such as a vector priority register, the elements in the input vector are addressed by a counter that starts with the value in the single-entry index vector. To use a single-entry index register, each address is loaded sequentially from the index register. Similarly, with VIRs, each address or address component stored in the VIR is only loaded once simultaneously. This provides a significant performance improvement for vector processors using VIRs.

[0036] In some embodiments, a counter (e.g., a counter register) can drive the VIR. Furthermore, a multiplexer, such as an N:1 multiplexer (i.e., a multiple-input, single-output multiplexer), can be used to selectively switch between the output of the counter to generate an output to access a certain location of the operand register for each vector iteration; or an index from the VIR to access a certain location of the operand register for each iteration of the counter.

[0037] The above and other features disclosed herein are useful in conditional operations. For example, instead of generating a vector mask register for a conditional operation on a vector, one of the circuits disclosed herein can generate one or more index vectors. Then, using the index vectors, branches of the vector mask register can be evaluated separately via corresponding VIRs. VIRs speed up processing by the vector processor because there is no need to generate or iterate over the vector mask, and there is no need to load the mask components separately for each iteration.

[0038] This functionality may also be useful for vector expansion operations and / or merging the results of vector operations into vector registers. For example, a VIR may be used to operate on an index into B(VMX(i))=A(i), where "B(VMX(i)" is the expanded compressed vector A. Additionally, a VIR may be used to operate on an index into B(VMX(i))=A(i)+a, where "B(VMX(i)" is the expanded compressed vector A and the scalar value "a" is added to the expanded vector A. Additionally, a VIR may be used to operate on an index into B(VMX(i))=function(A(VMX(i)),C(VMX(i)), where the processor operates on vectors A and C with respect to the elements selected by the VIR labeled "VMX". This is an example of conditional processing and may also be used for nested conditional processing.

[0039] The index value or addressing component (e.g., [2,4,5,8]) stored in the VIR used to access elements within the operand vector register (OVR) can be converted to a memory address (e.g., a base address plus increments for each memory cell). Thus, the output described herein, such as the output from the multiplexer described herein, can be converted to a memory address to directly access a vector in main memory in a manner similar to accessing the operand vector register (OVR).

[0040] Figure 1An exemplary portion of an exemplary computing device 100 according to some embodiments of the present disclosure is shown. As shown, the device 100 can be communicatively coupled to one or more networks 112. The device 100 includes a vector processor 102 according to some embodiments of the present disclosure. The device 100 also includes at least a bus 104, a main memory 106, a data storage system 108, and a network interface 110. The bus 104 communicatively couples the vector processor 102, the main memory 106, the data storage system 108, and the network interface 110. The device 100 includes a computer system that includes at least the vector processor 102, the main memory 106 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and the data storage system 108, which communicate with each other via the bus 104 (which may include multiple buses).

[0041] in other words, Figure 1 1 is a block diagram of an exemplary apparatus 100 having a computer system in which embodiments of the present disclosure may operate. In some embodiments, the computer system may include a set of instructions that, when executed, cause the machine to perform any one or more of the methodologies discussed herein. In such embodiments, the machine may be connected (e.g., via a network interface 110) to other machines in a LAN, an intranet, an extranet, and / or the Internet (e.g., network 112). The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment (e.g., the peer-to-peer network described herein), or as a server or a client machine in a cloud computing infrastructure or environment.

[0042] The vector processor 102 represents one or more vector processors according to some embodiments of the present disclosure. The vector processor 102 may include a microprocessor, a central processing unit, etc. More particularly, the vector processor 102 may include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets, as long as the processor uses: vector instructions, vector registers, vector priority, and multi-channel configuration. The vector processor 102 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a graphics processing unit (GPU), a network processor, etc. The vector processor 102 may be configured to execute instructions for performing the operations and steps discussed herein. The vector processor 102 may further include a network interface device, such as a network interface 110, to communicate via one or more communication networks (e.g., network 112).

[0043] The data storage system 108 may include a machine-readable storage medium (also referred to as a computer-readable medium) on which one or more sets of instructions or software are stored, and may embody at least some aspects of one or more methods or functions described herein. The data storage system 108 may include non-volatile storage. Instructions may also reside, in whole or in part, within the main memory 106 and / or the vector processor 102 during execution by the computer system, with the main memory 106 and the vector processor 102 also constituting machine-readable storage media. Although the memory, vector processor, and data storage components are each illustrated as a single component in the exemplary embodiment, each component should be understood to include a single component or multiple components that can store instructions and perform their corresponding operations. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions to be executed by a machine and causing the machine to perform any one or more of the methods disclosed herein. Thus, the term "machine-readable storage medium" should be understood to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0044] Figure 2 FIG2 shows an exemplary portion of an exemplary computing device 200 according to some embodiments of the present disclosure. As shown, the computing device 200 includes a vector processor 102 and a bus 104 and a main memory 106 (e.g., see FIG2 ). Figure 1 ). The computing device 200 may also be or include the computing device 100.

[0045] like Figure 2As shown in FIG, the vector processor 102 includes vector registers 202, scalar registers 204, a bus 206, an arithmetic logic unit 208 (ALU 208), and a vector load-store unit 210. Other embodiments of the computing device 200 may include the scalar registers 204 external to the vector processor 102 or in a unit of the vector processor that is separate from the unit in the vector processor having the vector registers 202. The bus 206 communicatively couples the vector registers 202, the scalar registers 204, the arithmetic logic unit (ALU) 208, and the vector load-store unit 210, and such components can communicate with each other via the bus 206 (which may include multiple buses). The vector registers 202 include multiple vector registers. Furthermore, the ALU 208 includes multiple ALUs—for example, arithmetic logic unit (ALU) 0, ALU 1, and ALU N.

[0046] The vector processor 102 includes at least one vector index register.The vector processor 102 may be or include one or more central processing units (CPUs) that implement instructions that operate on one-dimensional arrays of data called vectors.

[0047] The vector registers 202 in the vector processor 102 may include operand vector registers (i.e., input vector registers), result vector registers (i.e., output vector registers), and vector index registers for accessing elements in the operand vector registers and / or the result vector registers. The values ​​in the accessed elements of the operand vector registers and / or the result vector registers may be used as inputs to an ALU, such as one or more of the ALUs 208.

[0048] Generally speaking, the vector processor 102 may include index registers, which may include scalar index registers and vector index registers, such as Figure 3 、 4 and the vector index register shown in 5.

[0049] The scalar registers 204 of the vector processor 102 may include scalar index registers, operand scalar registers (i.e., input scalar registers), and result scalar registers (i.e., output scalar registers). At least some of the scalar registers may provide index and control values ​​for many different types of scalar and vector operations. In addition, the scalar registers may also provide numerical values ​​used by vector instructions. For example, a vector provided by a vector register may be multiplied by a scalar provided by a scalar register.

[0050] At least some of the scalar registers 204 and the vector registers 202 may be connected to corresponding ALUs in the ALUs 208. One of the ALUs 208 may include combinational digital electronic circuits that perform arithmetic and bitwise operations on integer binary numbers. In the vector processor 102, if the output vector register provides feedback during operation, one of the ALUs 208 may be connected to an input vector register and, in some instances, to an output vector register. In such instances, the output vector register serves as both an input vector and an output vector.

[0051] In addition, scalar registers 204 may include programmable scalar registers. Programmable scalar registers may be used so that a vector provided by a vector register (e.g., one of vector registers 202) may be subjected to a scalar operation provided by and programmed into one of the programmable scalar registers. For example, an operation may include multiplying a vector by a scalar value (e.g., vector A(i) x scalar p).

[0052] The depicted bus 206 may be configured to communicatively couple the vector load-store unit 210, the vector registers 202, the scalar registers 204, and the arithmetic logic unit 208. The bus 206 may include a 2:1 multiplexer, a 3:1 multiplexer, or an N:1 multiplexer configured to receive input from a vector index register and output an address or address component to access an operand vector. (See, e.g., Figure 3 、 4 and 5).

[0053] The vector load-store unit 210 contains circuitry for executing load and store instructions, generating addresses for load and store vector operations, and loading data from memory or storing it back to memory from registers of the vector processor 102. The vector load-store unit 210 can perform many of the operations described herein, including Figure 6-10 Many operations of methods 600, 700, 900 and 1000 are included.

[0054] Each computing device described herein may be a machine capable of executing a set of instructions (sequential or otherwise) that specify actions for the machine to take. Figure 1 and 2 Each illustrated computing device shows a single machine, but the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods or operations discussed herein. Furthermore, each illustrated computing device can each include at least one bus and / or motherboard, one or more controllers (e.g., one or more CPUs), main memory that can include temporary data storage, at least one type of network interface, a storage system that can include permanent data storage, and / or any combination thereof.

[0055] In discussion Figure 3 、 4 Before describing the systems 300, 400, and 500 depicted in Figures 3 and 5, it is important to understand that elements in a vector register can be addressed using at least an index from a vector index register (VIR) or another type of register such as a counter register. Generally, when a counter register is used, the counter increments itself by 1 for each iteration or step in a DO or FOR loop to generate the address for the next iteration or step. The VIR does not have to be driven by a counter, but it can be useful to have a counter drive the VIR. A common counter can either drive the VIR or provide a separate input to a receive multiplexer that outputs address components for accessing the operand vector in a vector operation.

[0056] For example, a VIR can store a vector VMX, where VMX(i), and i=0, 1, ..., n-1. A simple example of an application using a VIR is a compression operation, such as B(i)=A(VMX(i)). In addition, when another vector register stores a vector A, its elements are A(i), where i=0, 1, 2, ..., n. In normal mode (for example, when the counter output is selected for use by the multiplexer), the processor can perform A+a, where "a" is a scaler from the counter via the multiplexer. The result is stored in the output vector register B, where B(i)=A(i)+a, and where i=0, 1, ..., n-1. In a mode using a VIR (for example, an alternative selection control of the multiplexer), the processor can perform A(VMX)+a by using the address generated from the VIR output. Therefore, the output vector register has B, where B(i)=A(VMX(i))+a, and where i=0, 1, ..., n-1. Furthermore, for example, a vector processor may be configured to operate on two vectors, such as B(i)=Function(A(VMX(i)), C(VMX(i)), where "Function" is implemented via the ALU.

[0057] Figure 3 An exemplary system 300 including a vector index register 302 is shown, in accordance with some embodiments of the present disclosure.

[0058] System 300 may be a vector processor 102 (e.g., see Figure 1 or 2) or more vector processors. System 300 includes a vector index register 302 (VIR 302), a counter register 304, a 2:1 multiplexer 306, and a select register 308 connected to the multiplexer. VIR 302 can be Figure 2The counter register 304 and the select register 308 may be registers in the scalar register 204. The 2:1 multiplexer 306 may be Figure 2 The bus 206 shown in or Figure 1 A portion of bus 104 is shown in FIG.

[0059] System 300 may be part of a vector processor comprising one of a plurality of arithmetic logic units (ALUs). The vector processor may further comprise one of a plurality of operand vector registers (OVRs). The OVR may be configured to store elements of an operand vector to be used as input to a vector operation of the ALU.

[0060] The VIR 302 may be configured to store multiple address components corresponding to multiple locations in the OVR. Each address component may be added to the effective address for accessing the corresponding location in the OVR. Each location in the OVR may contain an element of an operand vector to be operated on by the ALU.

[0061] In some embodiments, an exemplary OVR may be 64 bits in length. If an operand is smaller than 64 bits (e.g., a 32-bit integer), the operand may be right-aligned. In this example, the indexing techniques described herein apply similarly. For example, an OVR may include padding within its elements to accommodate different data types.

[0062] As shown, counter register 304 is part of system 300. Counter register 304 may also be part of a vector processor with system 300. Counter register 304 may be configured to store a count 310. Count 310 may be added to the effective address used to access the OVR, or the count may be used by the vector processor to iterate over multiple address components stored in VIR 302.

[0063] As shown, a 2:1 multiplexer 306 is part of the system 300. The 2:1 multiplexer 306 may also be part of a vector processor having the system 300. The 2:1 multiplexer 306 may be configured to receive as inputs a count 310 from the counter register 304 and an output 312 from the VIR 302. The output 312 from the VIR 302 may include one of a plurality of address components of the VIR corresponding to the count 310. The 2:1 multiplexer 306 may also be configured to receive as a select input a mode value 314. The mode value 314 may be or include a value for selecting the count 310 or a value for selecting the output 312 from the VIR 302. The 2:1 multiplexer 306 may also be configured to select the count 310 or the output 312 from the VIR 302 based on the received mode value 314. The 2:1 multiplexer 306 may also be configured to receive as inputs a mode value 314 from the counter register 304. The mode value 314 may be or include a value for selecting the count 310 or a value for selecting the output 312 from the VIR 302. The 2:1 multiplexer 306 may also be configured to select the count 310 or the output 312 from the VIR 302 based on the received mode value 314. The 2:1 multiplexer 306 may also be configured to receive as inputs a mode value 314 from the VIR 302. Figure 1 The select output 316 is communicated to a requester of the OVR accessing the ALU. The requester may be a vector load-store unit of a vector processor (e.g., see Figure 2 ) or a vector load-store unit of another vector processor.

[0064] When the requester is a vector load-store unit, it can be configured to generate effective addresses for load and store operations of the vector processor. The vector load-store unit can also be configured to, for each address component of the VIR, add the address component of the VIR to the effective address for accessing the corresponding location in the OVR.

[0065] Figure 4 An exemplary system 400 including vector index registers 402a, 402b, and 402c is shown, in accordance with some embodiments of the present disclosure.

[0066] System 400 may be a vector processor 102 (e.g., see Figure 1 or 2) or more vector processors. System 400 includes a plurality of vector index registers, including vector index registers 402a, 402b, and 402c (VIRs 402a, 402b, and 402c). System 400 also includes a counter register 404, an N:1 multiplexer 406, and a select register 408 connected to the multiplexer. VIRs 402a, 402b, and 402c may be Figure 2The vector registers of the vector registers 202 shown in FIG. The counter register 404 and the select register 408 may be registers in the scalar register 204. The N:1 multiplexer 406 may be Figure 2 The bus 206 shown in or Figure 1 . As shown, N:1 multiplexer 406 is a multiplexer that can receive at least four inputs. However, in some embodiments, multiplexer 406 can receive more than four inputs. N:1 multiplexer 406 outputs one output, which can be an address component used to access an operand vector register (OVR).

[0067] System 400 may be part of a vector processor comprising an ALU in an ALU. The vector processor may also comprise an OVR in an OVR. The OVR may be configured to store elements of an operand vector to be used as input to a vector operation of the ALU.

[0068] For example, VIRs 402a, 402b, and 402c can each be configured to store multiple address components corresponding to multiple locations in an OVR or three separate OVRs. In an example with multiple OVRs, each OVR can have a separate multiplexer. Furthermore, in an example with multiple OVRs, each OVR can have a separate addressing system, such as system 300. Each address component of multiple VIRs (e.g., VIRs 402a, 402b, and 402c) can be added to the effective address used to access the corresponding location in the OVR or multiple OVRs. Each location in the OVR can contain an element of an operand vector to be operated on by the ALU.

[0069] As shown, counter register 404 is part of system 400. Counter register 404 may also be part of a vector processor with system 400. Counter register 404 may be configured to store a count 410. Count 410 may be added to an effective address used to access one or more OVRs, or the count may be used by the vector processor to iterate over multiple address components stored in multiple VIRs (e.g., VIRs 402a, 402b, and 402c).

[0070] As shown, an N:1 multiplexer 406 is part of system 400. N:1 multiplexer 406 can also be part of a vector processor having system 400. N:1 multiplexer 406 can be configured to receive a count 410 from counter register 404 and outputs (e.g., outputs 412a, 412b, and 412c) from a plurality of VIRs (e.g., VIRs 402a, 402b, and 402c) as inputs. Outputs 412a, 412b, and 412c from VIRs 402a, 402b, and 402c can each contain one of a plurality of address components corresponding to the corresponding VIR of count 410. N:1 multiplexer 406 can also be configured to receive a mode value 414 as a select input. For example, the mode value 414 may be or include a value for selecting the count 410 or a value for selecting the outputs 412a, 412b, and 412c from the VIRs 402a, 402b, and 402c. The N:1 multiplexer 406 may also be configured to select the count 410 or the outputs 412a, 412b, and 412c from the VIRs 402a, 402b, and 402c based on the received mode value 414. The N:1 multiplexer 406 may also be configured to receive the count 410 and the outputs 412a, 412b, and 412c from the VIRs 402a, 402b, and 402c via the bus (e.g., Figure 1 The select output 416 may be communicated to a requestor that accesses an ALU or an OVR or multiple OVRs. The requestor may be a vector load-store unit of a vector processor (e.g., see Figure 2 ) or a vector load-store unit of another vector processor. When the requester is a vector load-store unit, it can be configured to generate effective addresses for load and store operations of the vector processor. The vector load-store unit can also be configured to, for each address component of the VIR, add the address component to the effective address for accessing the corresponding location in the OVR.

[0071] In some embodiments, a vector processor having multiple VIRs may include a counter configured to store a count, and the count may be added to the effective address used to access the OVR, or the count may be used to iterate over each corresponding address component of a plurality of address components stored in the VIR. In such instances, the processor may also include an N:1 multiplexer configured to receive as inputs the count from the counter and the corresponding output from the VIR. Each output from a given VIR among the VIRs may include one of the plurality of address components of the given VIR corresponding to the count. The multiplexer may also be configured to receive a mode value as a select input. The mode value may be a value for selecting the count or a value for selecting one of the corresponding outputs from the VIR. The multiplexer may also be configured to select the count or one of the corresponding outputs from the VIR based on the received mode value. The multiplexer may also be configured to communicate the selected count or the selected output from the corresponding output of the VIR to a requester (e.g., a vector load-store unit of a vector processor) accessing the OVR of the ALU.

[0072] Figure 5 An exemplary system 500 including a vector index register 502 is shown, in accordance with some embodiments of the present disclosure.

[0073] System 500 may be a vector processor 102 (e.g., see Figure 1 or 2) or more vector processors. System 500 includes a vector index register 502 (VIR 502), a counter register 504, a 3:1 multiplexer 506, and a select register 508 connected to the multiplexer. System 500 also includes a vector priority register 503 connected to the multiplexer 506. VIR 502 can be Figure 2 The counter register 504, the select register 508 and the vector priority register 503 (VFR 503) may be registers in the scalar register 204. The 3:1 multiplexer 506 may be Figure 2 The bus 206 shown in or Figure 1 A portion of bus 104 is shown in FIG.

[0074] System 500 may be part of a vector processor comprising one of a plurality of arithmetic logic units (ALUs). The vector processor may further comprise an operand vector register (OVR) of a plurality of operand vector registers. The OVR may be configured to store elements of an operand vector to be used as inputs to vector operations of the ALU. VIR 502 may be configured to store a plurality of address components corresponding to a plurality of locations in the OVR. Each address component may be added to an effective address for accessing a corresponding location in the OVR. Each location in the OVR may contain an element of an operand vector to be operated on by the ALU.

[0075] The VFR 503 may be configured to store a single address component 511. The single address component 511 is an address component that directs initial access of the OVR at an initial location of the OVR based on the single address component 511 so that the initial location accessed is not the first location of the OVR. For example, if the VFR 503 stores a scalar "3," then during a vector operation of the OVR, the fourth location of the OVR is initially accessed. This replaces starting access to the OVR at the first location of the OVR (e.g., OVR(0)).

[0076] As shown, counter register 504 is part of system 500. Counter register 504 may also be part of a vector processor with system 500. Counter register 504 may be configured to store a count 510. Count 510 may be added to the effective address used to access the OVR, or the count may be used by the vector processor to iterate over multiple address components stored in VIR 502. Additionally, count 510 may be used by the vector processor to increment a single address component 511 of VFR 503, or as shown, it may be added to single address component 511, and the sum of count 510 and single address component 511 is a vector priority address component 513.

[0077] As shown, a 3:1 multiplexer 506 is part of system 500. The 3:1 multiplexer 506 may also be part of a vector processor with system 500. The 3:1 multiplexer 506 may be configured to receive as inputs a count 510 from counter register 504, an output 512 from VIR 502, and a vector-first address component 513 of the sum of the outputs of VFR 503 and counter 504. The output 512 from VIR 502 may include one of the multiple address components of the VIR corresponding to the count 510. The 3:1 multiplexer 506 may also be configured to receive a mode value 514 as a select input. The mode value 514 may be or include a value for selecting the count 510, a value for selecting the output 512 from VIR 502, or a value for selecting the vector-first address component 513 of the sum of the outputs of VFR 503 and counter 504. The 3:1 multiplexer 506 may also be configured to select the count 510 or the output 512 from the VIR 502 or the vector priority address component 513 based on the received mode value 514. The 3:1 multiplexer 506 may also be configured to receive the vector priority address component 513 via a bus (e.g., Figure 1 2) output and communicates a select output 516, which is one of the selected count or the selected output from the VIR or the vector priority address component 513. The select output 516 can be communicated to a requester of the OVR accessing the ALU. The requester can be a vector load-store unit of a vector processor (e.g., see Figure 2 ) or a vector load-store unit of another vector processor. When the requester is a vector load-store unit, it can be configured to generate effective addresses for load and store operations of the vector processor. The vector load-store unit can also be configured to, for each address component of the VIR, add the address component of the VIR to the effective address for accessing the corresponding location in the OVR.

[0078] In some embodiments, a vector processor having at least one VIR may further include at least one VFR and at least one corresponding counter connected to the VIR and the VFR. The counter may be configured to store a count. The count may be added to the effective address used to access the OVR. The count may be used to increment a vector priority address component, or the count may be used to iterate over multiple address components stored in the VIR. The vector processor may further include a 3:1 multiplexer configured to receive as inputs a count from the counter, an output from the VFR, and an output from the VIR. The output from the VIR may include one of the multiple address components of the VIR corresponding to the count, and the vector priority address component may also correspond to the count. The multiplexer may be configured to receive a mode value as a select input. The mode value may be a value for selecting the count, a value for selecting the output from the VFR, or a value for selecting the output from the VIR. The multiplexer can be configured to select a count, an output from the VFR, or an output from the VIR based on a received mode value, and to communicate the selected count, the selected output from the VFR, or the selected output from the VIR to a requester of the OVR accessing the ALU (e.g., a vector load-store unit such as a vector processor).

[0079] Not present Figure 3-5 As shown in FIG, the system may include a corresponding vector length register for each VIR in the VIR. Each corresponding vector length register may be configured to store the length of the vector stored in the corresponding VIR. For example, the system 300 may include a vector length register (VLR) configured to store the length of the vector stored in the VIR. The VLR may be useful in some operations that utilize the VIR to perform address generation in vector operations.

[0080] In some embodiments, the result of the sum of the output of the counter and the output of the alternative address candidate can be multiplexed with the output of the VIR and / or the counter (see, for example, Figure 5 503, which is the sum of the output of counter 504 and the single address component 511 stored in VFR 503). Alternatively, an alternate address candidate (e.g., an address component stored in VFR 503) can be used to set the initial value of the counter. In an alternative embodiment, the counter set by the alternate address candidate is a separate counter from the counter driving the VIR.

[0081] In some embodiments, a vector processor having one of the systems 300, 400, or 500 may further include a vector load-store unit configured to generate effective addresses for load and store operations of the vector processor. The vector load-store unit may also be configured to, for each address component of the VIR, add the address component of the VIR to the effective address for accessing the corresponding location in the OVR. Some vector operations may use the effective address and value in the VLR to improve the performance of the operation.

[0082] In some embodiments, a vector load-store unit connected to one of the systems 300, 400, or 500 is configured to load an operand vector stored in an OVR and load a scalar stored in a scalar register. This vector load-store unit can also be configured to compare the elements of the loaded operand vector with the loaded scalar and store the positions of the elements of the loaded operand vector in the VIR based on the comparison. For example, the vector load-store unit can also be configured to store the positions of elements that match the scalar, store the positions of elements that are greater than the scalar, or store the positions of elements that are greater than or equal to the scalar. In addition, for example, the vector load-store unit can be configured to store the positions of even elements and not the positions of odd elements, or vice versa.

[0083] A vector load-store unit coupled to one of the systems 300, 400, or 500 may also be configured to load storage locations of elements of the load operand vector from the VIR. Furthermore, the vector load-store unit may be configured to iterate vector operations on the elements of the load operand vector according to the load locations stored in the VIR.

[0084] In some embodiments, the vector operation is a pack operation configured to store elements of the load operand vector into the output OVR corresponding to load locations stored in the VIR.

[0085] In some embodiments, the vector load-store unit may be configured to load a storage element from the output OVR and then iterate a second vector operation on the storage element from the output OVR according to the load position stored in the VIR. The second vector operation may be an expand operation configured to store an element from the output OVR into the second output OVR at a position in the second output OVR according to the load position stored in the VIR. The expand operation may be further configured to store a scalar into the second output OVR at another position in the second output OVR.

[0086] In some embodiments, the vector load-store unit may be configured to iterate a second compression operation on elements of the second load operand vector according to the load locations stored in the second VIR. In such embodiments, the vector load-store unit may be configured to store the elements of the second load operand vector into a second output OVR corresponding to the load locations stored in the second VIR. Furthermore, the vector load-store unit may be configured to perform one or more vector operations using elements from the first output OVR and the second output OVR.

[0087] In some embodiments, the vector load-store unit may be configured to perform one or more vector operations using elements from the first output OVR and / or the second output OVR and elements of a third operand vector stored in a third OVR that is accessed sequentially and not generated by indexing of the VVRs. The results of the operations may be stored sequentially in a fourth OVR.

[0088] As mentioned, the systems 300, 400, and 500 may be part of one or more vector processors. The systems 300, 400, and 500 may also be subsystems of a larger system of one or more vector processors.

[0089] For example, systems 300, 400, and 500 may be included in another system or connected to another system that has one or more vector processors. This system may not also be part of a vector processor.

[0090] Also disclosed herein is a system that can include one of a plurality of ALUs. The system can also include one of a plurality of operand vector registers (OVRs). The OVR can be configured to store elements of an operand vector to be used as inputs for vector operations of the ALU. The system can also include one of a plurality of vector index registers (VIRs). The VIR can be configured to store a plurality of address components corresponding to a plurality of locations in the OVR. Each address component can be added to an effective address for accessing a corresponding location in the OVR. Furthermore, each location in the OVR can contain an element of an operand vector to be operated on by the ALU.

[0091] The system may further comprise a counter (or counter register). The counter may be configured to store a count. The count may be added to at least an effective address for accessing the OVR or for iterating over a plurality of address components stored in the VIR.

[0092] The system may further include an N:1 multiplexer. In other words, the system may include a multiplexer having multiple inputs and one output. The N:1 multiplexer may be configured to receive at least a count from a counter and an output from a VIR as inputs. The output from the VIR may include one of a plurality of address components of the VIR corresponding to the count. The N:1 multiplexer may also be configured to receive a mode value as a select input, the mode value being at least a value for selecting the count or a value for selecting the output from the VIR. The N:1 multiplexer may also be configured to select at least the count or the output from the VIR based on the received mode value. The N:1 multiplexer may also be configured to output the selection and communicate it to a vector load-store unit of the OVR accessing the ALU.

[0093] In some embodiments, the count may also be used to increment an address component of a scalar index register used to access the OVR. In such instances, the N:1 multiplexer may be further configured to receive as inputs at least the count from the counter, the output from the VIR, and the output from the scalar index register. The N:1 multiplexer may also be further configured to receive as a select input a mode value, the mode value being at least a value for selecting the count, a value for selecting the output from the VIR, or a value for selecting the output from the scalar index register. The N:1 multiplexer may also be further configured to select at least the count, the output from the VIR, or the output from the scalar index register based on the received mode value.

[0094] In some embodiments, the scalar index register may be a vector priority register (VFR). The VFR may be configured to store a vector first address component. The vector first address component may be an address component that directs an initial access of the OVR at an initial location of the OVR based on the vector first address component so that the initial location accessed is not the first location of the OVR. Based on the value stored in the VFR, the VFR may be used to initially access the OVR at any location in the OVR.

[0095] In some embodiments, the count can also be used to iterate over multiple address components stored in a second VIR in a plurality of VIRs. In such instances, the N:1 multiplexer can be configured to receive at least the count from the counter, the output from the VIR, and the output from the second VIR as inputs. Furthermore, the N:1 multiplexer can be configured to receive a mode value as a selection input, the mode value being at least a value for selecting the count, a value for selecting the output from the VIR, or a value for selecting the output from the second VIR. Furthermore, the N:1 multiplexer can be configured to select at least the count, the output from the VIR, or the output from the second VIR based on the received mode value.

[0096] Figure 6-10 In some embodiments, a vector load-store unit, such as vector load-store unit 210, may perform or facilitate operations alone or in combination with other parts of a vector processor. Figure 6-10 In some embodiments, the storing, loading, determining, incrementing, and changing of values ​​described herein may be performed by a vector load-store unit of a vector processor according to instructions stored in the vector load-store unit. In some other embodiments, other portions of the vector processor may perform or facilitate Figure 6-10 The operations shown in and other operations described herein.

[0097] In general, the systems described herein can implement a number of functions, including vector compression and expansion functions. For example, in a list of address components stored in a VIR, such as VMX, the elements of a given vector A can be compressed into a new vector by reading element A (VMX(i)) from vector A and storing it in an output vector B(i). Thus, vector A is compressed to B by B(i) = A(VMX(i)), where i = 0, 1, ... n. Similarly, expansion can be performed in the reverse direction (e.g., B(VMX(i)) = A(i)). Furthermore, one or more VIRs can allow the vector processor to directly perform sparse operations with or without compression and / or expansion. For example, VIR can implement indexing in B(i)=function(A(VMX(i)),C(VMX(i)), which can be a sparse operation with compression. In addition, VIR can implement indexing in B(VMX(i))=function(A(VMX(i)),C(VMX(i)), which can be a sparse operation without compression. In addition, VIR can implement indexing in B(VMX(i))=function(A(i),C(i)), which can be an operation on a compressed vector with expansion.

[0098] Figure 6 Exemplary operations of a method 600 for accessing elements of an operand vector for one or more vector operations are shown, in accordance with some embodiments of the present disclosure.

[0099] exist Figure 6 In the embodiment of the present invention, method 600 begins with step 602, in which elements of an operand vector to be used as inputs to a vector operation of one of a plurality of arithmetic logic units (ALUs) in a vector processor are stored in an operand vector register (OVR) of a plurality of operand vector registers (OVRs) in the vector processor. The elements of the operand vector may be stored in the OVR at any time before the operand vector is used as input to the vector operation of the ALU. For example, step 602 may be performed after step 618.

[0100] At step 604 , the method 600 continues by storing a plurality of address components corresponding to a plurality of locations in the OVR in a vector index register (VIR) of a plurality of vector index registers (VIRs) in the vector processor.

[0101] At step 606, the method 600 continues to iterate over the plurality of address components stored in the VIR according to a count (e.g., a count stored in a counter register) to provide an output. Subsequently, the vector load-store unit adds the output from the VIR to the effective address for accessing the OVR. The output from the VIR may include one of the plurality of address components of the VIR corresponding to the count. A single iteration over the plurality of address components stored in the VIR according to the count may be performed each time the vector load-store unit requests the output from the VIR to add the output of the VIR to the effective address for accessing the OVR. This may be repeated until the VIR has iterated over the operation on the OVR.

[0102] At step 608 , the method 600 continues by receiving, by the N:1 multiplexer of the vector processor, at least the count from the counter and the output from the VIR, wherein the output from the VIR may include one of a plurality of address components of the VIR corresponding to the count.

[0103] At step 610 , the method 600 continues with receiving, by the N:1 multiplexer, a select input comprising a mode value, the mode value being at least a value for selecting a count or a value for selecting an output from the VIR.

[0104] At step 612, the method 600 continues with the N:1 multiplexer selecting at least the count or the output from the VIR based on the received mode value.

[0105] At step 614, the selection is communicated to the vector load-store unit of the vector processor accessing the OVR of the ALU.

[0106] At step 616 , the method 600 continues by adding the count stored in the counter to the effective address used to access the OVR.

[0107] The method 600 continues by adding the address component of the VIR to the effective address used to access the corresponding location in the OVR at step 618. Each location of the OVR may contain an element of an operand vector to be operated on by the ALU.

[0108] At step 620 , method 600 continues by the vector load-store unit accessing the OVR of the ALU based on the effective address generated at step 616 or 618 .

[0109] Figure 71 shows exemplary operations of a method 700 for compressing elements of an operand vector according to some embodiments of the present disclosure. Figure 7 In the embodiment of the present invention, the method 700 begins with step 702 where the vector load-store unit loads an input operand vector stored in the input OVR.

[0110] At step 704 , the method 700 continues by loading the count stored in the counter register by the vector load-store unit.

[0111] At step 706 , the method 700 continues by the vector load-store unit loading the storage locations of the elements of the input operand vector from the VIR load according to the count.

[0112] At step 708, method 700 continues by performing a vector compression operation on the elements of the load input operand vector according to the load location from the VIR. Step 708 includes step 710, which includes method 700 continuing by storing the elements of the load input operand vector into the output OVR corresponding to the load location from the VIR.

[0113] At step 712, method 700 continues by comparing the count with a value representing the vector length of the VIR (i.e., VL) so that the vector compression operation can be iterated for the input OVR at each location stored in the VIR. When the count is equal to the vector length of the VIR, method 700 ends. When the count is less than the vector length of the VIR, method 700 continues to increment the count at 714 and then returns to step 704 (loading the count stored in the counter register), followed by steps 706 (loading the storage location of the elements of the loaded input operand vector from the VIR according to the count by the vector load-store unit) and 708 (running the vector compression operation on the elements of the loaded input operand vector according to the load location from the VIR). In this manner, the vector compression operation is iterated for the input OVR at each location stored in the VIR.

[0114] Figure 8 An exemplary system 800 is shown including a vector index register 802 (VIR 802) for compressing elements of an input operand vector stored in an input OVR 804, in accordance with some embodiments of the present disclosure. Exemplary system 800 is one example of a system in which at least method 700 may be implemented.

[0115] exist Figure 8, VIR 802 stores a list of positions of input OVR 804 (e.g., "2" as the first element of input OVR and "4" as the second element of input OVR). In this illustrated example, the vector processor is shown running two cycles or two iterations of a vector compression operation. During the first iteration, counter 806 outputs a count of "0," which is the value stored in the counter during the first cycle. During the first cycle, VIR 802 is shown outputting "2." Multiplexer 808 selects between the address component ("0") specified by counter 806 in normal mode operation or the address component ("2") specified by VIR 802 in VIR operating mode (or compression operating mode in this specific example). When multiplexer 808 selects VIR (or compression mode) in the first cycle, the output "2" from VIR 802 is the address component used to access input OVR 804. Therefore, the output for element "C" at position "2" of the input OVR accesses input OVR 804. Output OVR 810 is directly addressed by the count stored in counter 806. Since the count in counter 806 is "0" in the first cycle, output ORV 810 stores "C" as its first element. In the next iteration or cycle, output ORV 810 stores "E" as the second element in position "1" of output OVR. In this example with two cycles, input OVR 804 having elements {A, B, C, D, E} is compressed into output OVR 810 having elements {C, E}.

[0116] In addition, reference Figure 8 , if the address signals of the input / output vector are inverted, {C,E} can be expanded to a second output OVR with elements {x,x,C,x,E}, where x is the existing value before the compression operation or a scalar value selected from a scalar register (see, for example, Figure 9 , which is an exemplary method of extending a compressed vector with a scalar value from a scalar register).

[0117] Furthermore, if the value from the VFR is added to the count of the counter, the sum of the two can be used so that the first iteration of the operation on the input OVR is performed at another position of the input OVR than the first position of the input OVR (e.g., the first position of the input OVR 804 is marked as "0"). For example, see Figure 5 Alternatively, the VFR can be used to provide input to the count register so that the initial value of the count register at the start of a vector operation is the value stored in the VFR. Such an option allows vector priority processing.

[0118] Figure 9Exemplary operations of a method 900 for expanding elements of an operand vector, such as compressing elements of the operand vector, are shown, in accordance with some embodiments of the present disclosure.

[0119] like Figure 9 As shown in , method 900 may begin with method 700, which ends with outputting a compressed operand vector stored in an output OVR. Next, method 900 continues at step 902 by loading a storage element from the output OVR by a vector load-store unit. The storage element is an element of the compressed vector.

[0120] At step 904, method 900 continues by iterating a second vector operation on the stored elements from the output OVR according to the load location stored in the VIR. The second operation is a vector extend operation. In other words, the second vector operation, which is a vector extend operation, extends the compressed vector stored in the output OVR.

[0121] At step 906 , the method 900 continues by storing the element from the output OVR into the second output OVR at the location of the second output OVR according to the load location stored in the VIR according to the expand operation.

[0122] At step 908, method 900 continues by storing the scalar value in the second output OVR at the other location of the second output OVR according to the expand operation. The final output of the expand operation after step 908 is an expanded vector having elements from the compressed vector and one or more instances of the scalar value at the other location of the expanded vector. The location of the elements from the compressed vector in the expanded vector corresponds to the load location or address component stored in the VIR.

[0123] Figure 10 Exemplary operations of method 1000 are shown in relation to operations on a plurality of compressed vectors, in accordance with some embodiments of the present disclosure.

[0124] like Figure 10 As shown in , method 1000 may begin with method 700, which ends with outputting the compressed operand vector stored in the OVR. In addition, similar operations as method 700 are performed on the second operand vector. For example, at step 1002, method 1000 continues to iterate the second compression operation on the elements of the second load operand vector according to the load location stored in the second VIR.

[0125] At step 1004 , method 1000 continues by storing elements of the second load operand vector into a second output OVR corresponding to the load locations stored in the second VIR.

[0126] At step 1006, the method 1000 continues by performing one or more vector operations using elements from the first output OVR and the second output OVR. The one or more vector operations use elements from two compressed vectors, which are elements from the first output OVR and the second output OVR.

[0127] As mentioned herein, at least some embodiments disclosed herein are vector index registers in a vector processor that each store a plurality of addresses for accessing a plurality of locations in a vector. Additionally, at least some embodiments disclosed herein are vector index registers for TRUE and / or FALSE results of one or more comparisons (e.g., numeric comparisons), each storing a plurality of addresses for accessing a plurality of locations in an operand vector.

[0128] Furthermore, as mentioned herein, it is known to use a scalar index register in a vector processor to reference multiple locations of a vector by changing the value stored in the scalar index register during a vector operation. However, by using a vector index register (VIR), such as a VIR for a TRUE result or a VIR for a FALSE result, to index multiple locations of one or more operand vectors, the scalar index register can be replaced, and at least the continuous changing of the value in the scalar index register during a vector operation using TRUE and / or FALSE results can be avoided.

[0129] As mentioned herein, there are a number of limitations associated with using scalar registers or single-entry vectors to index vectors. Furthermore, some of these limitations may limit the performance of vector processors that use scalar index registers. By using vector index registers, such as a VIR for a TRUE result or a VIR for a FALSE result, to index multiple locations of one or more operand vectors used in vector comparison operations or other types of operations, scalar index registers can be replaced and, at least, the need for continuous changes to the scalar index register during vector operations can be avoided.

[0130] In some embodiments, when calculating a vector of TRUE and FALSE elements (e.g., the contents of a vector mask Vm), the system or circuit can generate an index vector to supplement or replace the vector. The index vector can be used for a TRUE result or a FALSE result, or a combination thereof, and these types of index vectors can be stored in the corresponding vector index registers VIR_TRUE, VIR_FALSE, and VIR_COMBINED. VIR_COMBINED is a single VIR containing a TRUE portion and a FALSE portion.

[0131] VIR_TRUE, VIR_FALSE, and / or VIR_COMBINED may contain a vector mask (Vm) or an element in a corresponding OVR. Vm is a vector that stores the TRUE and FALSE results of vector comparisons (e.g., numeric comparisons of vectors). Vm can be used for conditional operations and compression and expansion operations. A vector register of Vm can be replaced by VIR_TRUE, VIR_FALSE, and / or VIR_COMBINED. Furthermore, when a vector processor performs vector operations, VIR_TRUE, VIR_FALSE, and / or VIR_COMBINED can improve the performance of the vector processor replacing Vm.

[0132] For example, a counter can be used to track the number of TRUE elements in the Vm calculation, starting with zero. When the i-th TRUE element is identified as the result of the j-th element of Vm, the index j is saved to the i-th element of the vector VmxT (and stored in VIR_TRUE). Similarly, a counter can be used to track FALSE results and the index of the FALSE result is saved in the vector VmxF (and stored in VIR_FALSE). The sum of the vector lengths of VmxT and VmxF is equal to the vector length of Vm. The vector processor can use Vi as a vector, where the i-th element generates VmxT and VmxF with the value I, where VmxT = compress(Vi, Vm) and VmxF = compress(Vi,!Vm).

[0133] Compressed index or address vectors VmxT and / or VmxF stored or loaded in VIR_TRUE or VIR_FALSE can be used for conditional operations and / or for compression and expansion operations (e.g., the compression and expansion operations described herein). Since vectors or address vectors with compressed indices can be accessed, such operations can be performed directly on the vectors without generating compressed vectors on intermediate vector registers such as registers used to iterate Vm.

[0134] As mentioned in this article, there are many uses for VIRs such as VIR_TRUE or VIR_FALSE. For example, VIR_TRUE or VIR_FALSE can be used to more efficiently implement vector compression or expansion functions.

[0135] Figure 11 Exemplary operations of method 1100 are shown for constructing index vectors to store in vector index registers (VIR_TRUE and VIR_FALSE) for TRUE and FALSE results (eg, “1” or “0” results) of comparisons in accordance with some embodiments of the present disclosure.

[0136] The method 1100 begins at step 1102 by loading an operand vector stored in an operand vector register (OVR) by a vector load-store unit of a vector processor.

[0137] At step 1104 , the method 1100 continues by loading the scalar stored in the scalar register of the vector processor by the vector load-store unit.

[0138] At step 1106, method 1100 continues with the vector processor comparing the elements of the load operand vector with the load scalar based on the count stored in the counter. The counter can be another scalar register and be part of the vector processor. Furthermore, in some embodiments, method 1100 can continue with the vector processor comparing the elements of the load operand vector with another operand vector based on the count stored in the counter. In some embodiments, to perform the comparison, the elements of the load operand vector are accessed by the vector processor based on a first count in a first counter, while the elements of the other load operand vector are accessed by the vector processor based on a second count in a second counter. The comparison can be a numerical comparison.

[0139] At step 1108, method 1100 continues by identifying whether the comparison result of step 1106 is TRUE or FALSE (e.g., "1" or "0"). If the comparison result of step 1106 is TRUE, method 1100 continues at step 1110a by storing the location of the element of the load operand vector in the vector index register (VIR_TRUE) of the TRUE result of the comparison according to the count (e.g., via the TRUE count stored in the TRUE counter according to the count - see, for example, Figure 12 1216a). If the comparison result of step 1106 is FALSE, then method 1100 continues at step 1110b by storing the location of the element of the load operand vector in the vector index register (VIR_FALSE) of the FALSE result of the comparison according to the count (e.g., via the FALSE count stored in the FALSE counter according to the count - see, for example, Figure 12 FALSE counter 1216b) depicted in FIG.

[0140] At step 1112, method 1100 continues to identify whether the count is equal to the vector length (VL) of the operand vector stored in the OVR. In some embodiments, method 1100 may continue to identify whether the VL of the OVR is equal to the sum of the VL of VIR_TRUE and the VL of VIR_FALSE, which may be another way to identify whether the count is equal to the VL of the operand vector stored in the OVR. These exemplary alternative ways of identifying whether the count is equal to the VL of the OVR may indicate that all elements of the OVR are compared. If the count is less than the VL, the method continues to increment the count at step 1114. By incrementing the count until the count equals the VL, the vector processor may continue to store the positions of the elements of the load operand vector according to the count until the positions of the elements of the load operand vector are stored in VIR_TRUE or VIR_FALSE. In other words, method 1100 continues to store the positions of the elements of the load operand vector according to the count until the positions of the elements of the load operand vector are stored in VIR_TRUE or VIR_FALSE.

[0141] At step 1112, if count equals VL, then method 1100 has completed building the index vector for storage in VIR_TRUE and VIR_FALSE. Count cannot be greater than VL because the operation of building the index vector is complete when count equals VL. When a new index vector is to be built, count is reset, and the VL register storing the scalar value of VL may also be reset. The vector processor may initially determine the vector length of the OVR and then store the length in the VL register before proceeding with method 1100.

[0142] After completing the construction of the index vectors stored in VIR_TRUE and VIR_FALSE, method 1100 continues by loading the storage locations of the elements of the load operand vector from at least one of VIR_TRUE or VIR_FALSE, or a combination thereof, by the vector load-store unit at step 1116. Furthermore, at step 1118, method 1100 continues by iterating one or more vector operations on the elements of the load operand vector based on the load locations.

[0143] Figure 12 An exemplary system 1200 is shown for constructing index vectors for storage in VIR_TRUE 1202a and VIR_FALSE 1202b according to some embodiments of the present disclosure. System 1200 can implement many operations and aspects of method 1100, and system 1200 can be part of one or more vector processors.

[0144] The system 1200 includes VIR_TRUE 1202a and VIR_FALSE 1202b, such as the VIR_TRUE and VIR_FALSE described in the description of the method 1100. The system also includes OVR 1204, such as the OVR described in the description of the method 1100.

[0145] System 1200 also includes a scalar register (SR) 1206, such as the scalar register described in the description of method 1100. In some embodiments, the scalar register may be replaced with another OVR that is addressed in the same manner as OVR 1204.

[0146] The system also includes a counter 1208 , which may be implemented in part by a counter register and may be the counter described in the description of method 1100 .

[0147] System 1200 also includes a comparator 1210 that can compare the value stored in SR 1206 with the value stored in the element of OVR 1204. Comparator 1210 can perform the following operations:<SR、OVR(i)=SR、OVR(i)> SR, OVR(i) ≤ SR, or OVR(i) ≥ SR. Comparator 1210 compares two numbers each time or each cycle. At each iteration i (which also represents the address or address component i), counter 1208 provides the address i used to access OVR 1204 for comparison with the scalar value from SR 1206 by comparator 1210. In short, the output of OVR 1204 at that iteration, or address i, is compared with the value from scalar register 1206. Comparator 1210 generates a single output, which is either TRUE or FALSE (e.g., "1" or "0").

[0148] Comparator 1210 can be configured to perform the comparison at step 1106 of method 1100. In other words, comparator 1210 can be configured to compare the elements of the load operand vector with the load scalar based on the count stored in the counter register. Comparator 1210 can also be configured to identify a TRUE or FALSE result at step 1108. In other words, comparator 1210 can be configured to identify whether the comparison result of step 1106 is TRUE or FALSE. Comparator 1210 can be configured to output a TRUE or FALSE result, for example, "1" to indicate a TRUE result or "0" to indicate a FALSE result. The output of comparator 1210 is input into the corresponding write enable of each of VIR_TRUE 1202a and VIR_FALSE 1202b.

[0149] The output from comparator 1210 can be directly communicated to the write enable 1212a of VIR_TRUE 1202a. The output from comparator 1210 can be indirectly communicated to the write enable 1212b of VIR_FALSE 1202b via inverter 1214. Inverter 1214 is configured to invert the output of comparator 1210 before it reaches the write enable 1212b of VIR_FALSE 1202b. For example, if the output of comparator 1210 is TRUE (e.g., "1"), when it is input to inverter 1214, the inverter inverts the value to FALSE (e.g., "0") and outputs FALSE.

[0150] System 1200 also includes a separate TRUE counter 1216a for VIR_TRUE 1202a and a separate FALSE counter 1216b for VIR_FALSE 1202b. The output of comparator 1210 drives two counters, counters 1216a and 1216b. Counters 1216a and 1216b are separate from counter 1208, which provides an address for OVR 1204. The output of TRUE counter 1216a serves as the address for accessing VIR_TRUE 1202a. The output of FALSE counter 1216b serves as the address for accessing VIR_FALSE 1202b.

[0151] For example, when the output of comparator 1210 is TRUE, the output triggers write enable 1212a to write the current position from OVR 1204 to VIR_TRUE 1202a. When the output of comparator 1210 is FALSE, the output triggers write enable 1212b to write the current position from OVR 1204 to VIR_FALSE 1202b. This functionality is provided by a circuit including an inverter 1214 and two write enables 1212a and 1212b.

[0152] The output of counter 1208 serves as the address or address component to be written to VIR_TRUE 1202a at the address specified by TRUE counter 1216a. This occurs when the output of comparator 1210 is TRUE. For each trigger of the TRUE output from comparator 1210, the value stored in TRUE counter 1216a is incremented by one. The output of counter 1208 serves as the address or address component to be written to VIR_FALSE 1202b at the address specified by FALSE counter 1216b. This occurs when the output of comparator 1210 is FALSE. For each trigger of the FALSE output from comparator 1210, the value stored in FALSE counter 1216b is incremented by one. This overall function of selecting where the address of the OVR component is stored is provided by the circuitry comprising comparator 1210, write enables 1212a and 1212b, inverter 1214, and TRUE and FALSE counters 1216a and 1216b.

[0153] VIR_TRUE 1202a and VIR_FALSE 1202b are each output registers of system 1200. VIR_TRUE 1202a has three inputs. The first input comes from write enable 1212a. For example, a TRUE input from this first input allows writes to VIR_TRUE 1202a, while a FALSE input does not allow writes to the register. The second input comes from TRUE counter 1216a, which is used to access the address of VIR_TRUE 1202a. The third input comes from counter 1208 and contains the data to be written to VIR_TRUE 1202a at the register address provided by TRUE counter 1216a (or the second input).

[0154] The system 1200 may be part of a vector processor including a vector load-store unit. The vector load-store unit may load data stored in registers of the system 1200 into main memory and store data from main memory into the system's registers, and vice versa (load data stored in memory into registers of the system 1200 and store data from the system's registers into memory).

[0155] System 1200 is also shown as including a scalar register for vector length, namely vector length register 1224 (VLR 1224). VLR 1224 is configured to store the vector length (VL) of OVR 1204. The vector processor can load the VL from VLR 1224 into memory to identify whether the count from counter 1208 is equal to the VL of the operand vector stored in OVR 1204. This is for example implemented Figure 111202a or VIR_FALSE 1202b. In other words, the system 1200 may continue to store the positions of the elements of the OVR 1204 according to the count until the position of the element of the load operand vector is stored in VIR_TRUE 1202a or VIR_FALSE 1202b. This is one way that the system 1200 may implement the operations of the method 1100. If the count is less than VL, the count in the counter 1208 continues to be incremented at each clock cycle or upon another trigger or iteration (e.g., see step 1114). By incrementing the count until the count equals VL, the vector processor may continue to store the positions of the elements of the OVR 1204 according to the count until the position of the element of the OVR is stored in VIR_TRUE 1202a or VIR_FALSE 1202b.

[0156] If the count is equal to VL, then the vector processor using system 1200 has completed the construction of the index vector for storage in VIR_TRUE 1202a and VIR_FALSE 1202b. The count cannot be greater than VL because the operation of constructing the index vector is completed when the count is equal to VL. When a new index vector is to be constructed, the count is reset in counter 1208, and VL is determined and stored in VLR 1224. The vector processor can initially determine the vector length of the OVR (e.g., OVR 1204) and then store it in VLR 1224 before proceeding with method 1100.

[0157] After completing the construction of the index vectors stored in VIR_TRUE 1202a and VIR_FALSE 1202b, the vector processor may continue to load the storage locations of the elements of OVR 1204 from at least one of VIR_TRUE or VIR_FALSE, or a combination thereof, using a vector load-store unit of the processor. Furthermore, the vector processor may continue to iterate one or more vector operations on the elements of OVR 1204 based on the loaded locations in VIR_TRUE 1202a and / or VIR_FALSE 1202b.

[0158] An alternative to System 1200 is Figure 14 , where VIR_TRUE and VIR_FALSE are essentially combined into one vector index register, where the TRUE addresses of the OVR are stored top to bottom in the register, and the FALSE addresses of the OVR are stored bottom to top. In this alternative, the counter used to address the TRUE portion of the combined VIR starts at address "zero" and increments by one for each TRUE input to the combined register. The FALSE counter starts at "N-1" for the address accessing the combined VIR, and decrements by one for each FALSE input to the combined register. Figure 14The multiplexer shown in can be used to select the counter for the TRUE input or the counter for the FALSE input. For each cycle, the VIR is enabled once for writing because the input is for the TRUE part of the VIR (e.g., address 0, 1, 2, ..., count + 1, where the count starts with "0") or the FALSE part (e.g., address N-1, N-2, N-3, ..., VIR_length-count + 1, where the count starts with "0"); and therefore, the index is generated from top to bottom or bottom to top.

[0159] Figure 13 Exemplary operations of method 1300 are shown for constructing a combination index vector to store in a combination vector index register (VIR_combined) for TRUE and FALSE results (eg, "1" or "0" results) of comparisons in accordance with some embodiments of the present disclosure.

[0160] The method 1300 begins with step 1302 where a vector load-store unit of a vector processor loads an operand vector stored in an OVR.

[0161] At step 1304 , the method 1300 continues by loading the scalar stored in the scalar register of the vector processor by the vector load-store unit.

[0162] At step 1306, method 1300 continues with the vector processor comparing the elements of the load operand vector with the load scalar based on the count stored in the counter. The counter can be another scalar register and be part of the vector processor. Furthermore, in some embodiments, method 1300 can continue with the vector processor comparing the elements of the load operand vector with another operand vector based on the count stored in the counter. In some embodiments, to perform the comparison, the elements of the load operand vector are accessed by the vector processor based on a first count in a first counter, while the elements of the other load operand vector are accessed by the vector processor based on a second count in a second counter. The comparison can be a numerical comparison.

[0163] At step 1308, method 1300 continues by identifying whether the comparison result of step 1306 is TRUE or FALSE (e.g., "1" or "0"). If the comparison result of step 1306 is TRUE, method 1300 continues at step 1310a by storing the location of the element of the load operand vector at the top unfilled location in VIR_combined according to the count (e.g., via the TRUE count stored in the TRUE counter according to the count - see, for example, Figure 141416a depicted in FIG. 141). If the comparison result of step 1306 is FALSE, then method 1300 continues at step 1310b by storing the location of the element of the load operand vector at the bottom most unfilled location in VIR_combined according to the count (e.g., via the FALSE count stored in the FALSE counter according to the count—e.g., see FIG. Figure 14 FALSE counter 1416b) depicted in FIG.

[0164] At step 1312, method 1300 continues to identify whether count equals the vector length (VL) of the operand vector stored in OVR. In some embodiments, method 1300 may continue to identify whether the VL of OVR equals the sum of the TRUE portion of VIR_COMBINED and the FALSE portion of VIR_COMBINED. This may be another way to identify whether count equals the VL of the operand vector stored in OVR. These exemplary alternative ways of identifying whether count equals the VL of OVR may indicate that all elements of OVR are compared. If count is less than VL, the method continues to increment count at step 1314. By incrementing count until count equals VL, the vector processor may continue to store the positions of elements of the load operand vector according to count until the positions of the elements of the load operand vector are stored in VIR_combined. In other words, method 1300 continues to store the positions of elements of the load operand vector according to count until the positions of the elements of the load operand vector are stored in VIR_combined.

[0165] At step 1312, if count is equal to VL, then method 1300 has completed building the index vector for storage in VIR_combined. Count cannot be greater than VL because the operation of building the index vector is complete when count is equal to VL. When a new index vector is to be built, count is reset, and the VL register storing the scalar value of VL may also be reset. The vector processor may initially determine the vector length of the OVR and then store the length in the VL register before proceeding with method 1300.

[0166] After completing the construction of the index vector stored in VIR_combined, method 1300 continues by loading the storage locations of the elements of the load operand vector from VIR_combined by the vector load-store unit at step 1316. Furthermore, at step 1318, method 1300 continues to iterate one or more vector operations on the elements of the load operand vector based on the load locations.

[0167] Figure 14An exemplary system 1400 for constructing a combined index vector for storage in VIR_combined 1402 is shown in accordance with some embodiments of the present disclosure.

[0168] The system 1400 includes a VIR_combined 1402, such as the VIR_combined 1402 described in the description of the method 1300. The system also includes an OVR 1404, such as the OVR described in the description of the method 1300.

[0169] System 1400 also includes a scalar register (SR) 1406, such as the scalar register described in the description of method 1300. In some embodiments, the scalar register may be replaced with another OVR that is addressed in the same manner as OVR 1404.

[0170] The system also includes a counter 1408 , which may be implemented in part by a counter register and may be the counter described in the description of method 1300 .

[0171] System 1400 also includes a comparator 1410 that can compare the value stored in SR 1406 with the value stored in the element of OVR 1404. Comparator 1410 can perform the following operations:<SR、OVR(i)=SR、OVR(i)> SR, OVR(i) ≤ SR, or OVR(i) ≥ SR. Comparator 1410 compares two numbers each time or each cycle. At each iteration i (which also represents the address or address component i), counter 1408 provides the address i used to access OVR 1404 for comparison with the scalar value from SR 1406 by comparator 1410. In short, the output of OVR 1404 at that iteration, or address i, is compared with the value from scalar register 1406. Comparator 1410 generates a single output, which is either TRUE or FALSE.

[0172] Comparator 1410 can be configured to perform the comparison at step 1306 of method 1300. In other words, comparator 1410 can be configured to compare the elements of the load operand vector with the load scalar based on the count stored in the counter register. Comparator 1410 can also be configured to identify a TRUE or FALSE result at step 1308. In other words, comparator 1410 can be configured to identify whether the comparison result of step 1306 is TRUE or FALSE. Comparator 1410 can be configured to output a TRUE or FALSE result, for example, "1" to indicate a TRUE result or "0" to indicate a FALSE result. The output of comparator 1410 is input into a corresponding write enable of the TRUE and FALSE portions of VIR_COMBINED 1402.

[0173] System 1400 also includes a separate TRUE counter 1416a for addressing the TRUE portion of VIR_COMBINED 1402 and a separate FALSE counter 1416b for addressing the FALSE portion of VIR_COMBINED. The output of comparator 1410 drives two counters, counters 1416a and 1416b. Counters 1416a and 1416b are separate from counter 1408, which provides the address for OVR 1404. The output of counter TRUE 1416a is used as the address for accessing VIR_COMBINED 1402 from top to bottom. The output of counter FALSE 1416b is also used as the address for accessing VIR_COMBINED 1402, but from bottom to top. Further explanation of how the counters address VIR_COMBINED 1402 is discussed below.

[0174] The output of counter 1408 serves as the address or address component to be written into the TRUE portion at the address specified by TRUE counter 1416a. This occurs when the output of comparator 1410 is TRUE. For each TRUE output from comparator 1410, the value stored in TRUE counter 1416a increments by one. The output of counter 1408 serves as the address or address component to be written into the FALSE portion at the address specified by FALSE counter 1416b. This occurs when the output of comparator 1410 is FALSE. For each FALSE output from comparator 1410, the value stored in FALSE counter 1416b increments by one. The overall function of selecting where to store the address of the OVR component is provided by the circuitry comprising comparator 1410, TRUE and FALSE counters 1416a and 1416b, and multiplexer 1420. The output from comparator 1410 controls multiplexer 1420 via select register 1422.

[0175] The multiplexer 1420 controls which counter output of the VIR_COMBINED 1402 the receive counters 1416a and 1416b provide. The control is performed via the selection of counter 1416a or 1416b, and the selection is controlled via the mode value stored in the selection register 1422. The selection register 1422 receives the mode value from the output of the comparator 1410. For each cycle, the VIR_COMBINED 1402 is enabled once for writing because the input is targeted at the TRUE part of the VIR (e.g., addresses 0, 1, 2, …, count + 1, where the count starts with “0”) or the FALSE part of the VIR (e.g., addresses N - 1, N - 2, N - 3, …, VIR_length – count + 1, where the count starts with “0”); and thus, the index is generated top - down or bottom - up. In Figure 14 the illustrated example, the TRUE counter 1416a starts with “0” and increments by “1” with each cycle. In this example, the FALSE counter 1416b starts with a scalar value representing the length of the VIR_COMBINED 1402 (i.e., N - 1) and decrements by “1” with each cycle. For example, in Figure 14 the comparison performed by the comparator 1410 is SR < OVR(i), and thus, the value “2” at address “0” of the OVR 1404 is TRUE, so the address “0” of the OVR is stored at address “0” of the VIR_COMBINED 1402 (or the top of the VIR). Also, the value “5” at address “1” of the OVR 1404 is FALSE, so the address “1” of the OVR is stored at address “N - 1” of the VIR_COMBINED 1402 (or the bottom of the VIR). Also, the value “3” at address “2” of the OVR 1404 is TRUE, so the address “2” of the OVR is stored at address “1” of the VIR_COMBINED 1402 (or the top - most position of the unfilled VIR). Also, the value “6” at address “3” of the OVR 1404 is FALSE, so the address “3” of the OVR is stored at address “N - 2” of the VIR_COMBINED 1042 (or the bottom - most position of the unfilled VIR).

[0176] The TRUE part and the FALSE part are each part of the output register of the system 1400. The VIR_COMBINED1402 has at least two inputs. The first input comes from counter 1416a or 1416b for accessing the address of the VIR_COMBINED 1402. The second input comes from counter 1408, and this input contains the data written to the VIR_COMBINED 1402 at the address of the register provided by counter 1416a or 1416b.

[0177] System 1400 may be part of a vector processor that includes a vector load-store unit. The vector load-store unit may load data stored in registers of system 1400 into main memory and store data from main memory into the system's registers, and vice versa (load data stored in memory into registers of system 1400 and store data from the system's registers into memory).

[0178] System 1400 is also shown as containing a scalar register for vector length, namely vector length register 1424 (VLR 1424). VLR 1424 is configured to store the vector length (VL) of OVR 1404. The vector processor can load the VL from VLR 1424 into memory to identify whether the count from counter 1408 is equal to the VL of the operand vector stored in OVR 1404. This is for example implemented Figure 13 1402. This is one way in which the system 1400 can implement the operations of method 1300 by continuing to store the positions of elements of OVR 1404 according to the count until the positions of the elements of OVR are stored in the TRUE portion or the FALSE portion of VIR_COMBINED 1402. This is one way in which the system 1400 can implement the operations of method 1300. If the count is less than VL, the count in counter 1408 continues to be incremented on each clock cycle or upon another trigger or iteration (e.g., see step 1314). By incrementing the count until the count equals VL, the vector processor can continue to store the positions of elements of OVR 1404 according to the count until the positions of the elements of OVR are stored in the TRUE portion or the FALSE portion of VIR_COMBINED 1402. In other words, the system 1400 can continue to store the positions of elements of OVR 1404 according to the count until the positions of the elements of the load operand vector are stored in the TRUE portion or the FALSE portion of VIR_COMBINED 1402. This is one way in which the system 1400 can implement the operations of method 1300.

[0179] If the count is equal to VL, then the vector processor using system 1400 has completed the construction of the index vector for storage in the TRUE portion or the FALSE portion of VIR_COMBINED 1402. The count cannot be greater than VL because the operation of constructing the index vector is completed when the count is equal to VL. When a new index vector is to be constructed, the count is reset in counter 1408 and VL is determined and stored in VLR 1424. The vector processor can initially determine the vector length of the OVR (e.g., OVR 1404) and then store it in VLR 1424 before proceeding with method 1300.

[0180] After completing the construction of the index vector stored in VIR_COMBINED 1402, the vector processor can continue to load the storage location of the elements of OVR 1404 from VIR_COMBINED by the vector load-store unit of the processor. In addition, the vector processor can also continue to iterate one or more vector operations on the elements of OVR 1404 based on the loaded location in VIR_COMBINED 1402.

[0181] Figure 15 An exemplary system 1500 is shown that includes VIR_TRUE 1502a and VIR_FALSE 1502b, according to some embodiments of the present disclosure. For purposes of this disclosure, it should be understood that a system similar to system 1500 can include multiple VIR_TRUEs and multiple VIR_FALSEs. For example, an embodiment similar to system 1500 having two VIR_TRUEs and two VIR_FALSEs can include a 5:1 multiplexer having four inputs for receiving two VIR_TRUEs and two VIR_FALSEs and one input for receiving input from a counter (e.g., a counter similar to counter 1504). In some embodiments, in such a system, the amount of VIR_TRUEs is equal to the amount of VIR_FALSEs.

[0182] System 1500 may be a vector processor 102 (e.g., see Figure 1 or 2) or more vector processors. System 1500 includes vector index registers VIR_TRUE 1502a and VIR_FALSE 1502b, a counter register 1504, a 2:1 multiplexer 1506, and a select register 1508 connected to the multiplexer. VIR_TRUE 1502a and VIR_FALSE 1502b can be Figure 2 The counter register 1504 and the select register 1508 may be registers in the scalar register 204. The 2:1 multiplexer 1506 may be Figure 2 The bus 206 shown in or Figure 1 A portion of bus 104 is shown in FIG.

[0183] VIR_TRUE 1502a is a vector index register for TRUE results of comparisons and is configured to store multiple address components corresponding to multiple locations in the OVR that produce a TRUE result when used in a comparison. For example, see VIR_TRUE 1202a, which can be part of system 1500.

[0184] VIR_FALSE 1502b is a vector index register for FALSE results of comparisons and is configured to store multiple address components corresponding to multiple locations in the OVR that produce a FALSE result when used in a comparison. For example, see VIR_FALSE 1202b, which can be part of system 1500.

[0185] Each address component can be added to the effective address for accessing the corresponding location in the OVR. Each location in the OVR can contain an element of an operand vector to be operated on by an ALU. For example, system 1500 can be part of a vector processor that includes one of a plurality of arithmetic logic units (ALUs). The vector processor can also include an operand vector register (OVR) in a plurality of operand vector registers. The OVR can be configured to store elements of an operand vector to be used as input to an ALU vector operation.

[0186] As shown, counter register 1504 is part of system 1500. Counter register 1504 may also be part of a vector processor with system 1500. Counter register 1504 may be configured to store a count 1510. Count 1510 may be an effective address that may be added to access an OVR, or the count may be used by the vector processor to iterate over multiple address components stored in VIR 1502.

[0187] As shown, a 3:1 multiplexer 1506 is part of system 1500. 3:1 multiplexer 1506 may also be part of a vector processor with system 1500. 3:1 multiplexer 1506 may be configured to receive as inputs a count 1510 from counter register 1504 and outputs 1512a and 1512b from VIRs 1502a and 1502b, respectively. Outputs 1512a and 1512b from VIRs 1502a and 1502b may include one of a plurality of address components of the VIR corresponding to count 1510. 3:1 multiplexer 1506 may also be configured to receive a mode value 1514 as a select input. Mode value 1514 may be or include a value for selecting count 1510 or a value for selecting one of outputs 1512a or 1512b from VIRs 1502a and 1502b. The 3:1 multiplexer 1506 may also be configured to select the count 1510 or one of the outputs 1512a or 1512b from the VIRs 1502a and 1502b based on the received mode value 1514. The 3:1 multiplexer 1506 may also be configured to receive the count 1510 via a bus (e.g., Figure 11 or 2) output and communicates a select output 1516, which is one of the selected count or the selected output from the VIR. The select output 1516 may be communicated to a requester of the OVR accessing the ALU. The requester may be a vector load-store unit of a vector processor (e.g., see Figure 2 ) or a vector load-store unit of another vector processor.

[0188] Figure 16 1502a) or VIR_COMBINED 1402).

[0189] exist Figure 16In step 1602, method 1600 begins with a vector load-store unit loading an input operand vector stored in an input OVR. At step 1604, method 1600 continues with the vector load-store unit loading a count stored in a counter register. At step 1606, method 1600 continues with the vector load-store unit loading the storage locations of the elements of the loaded input operand vector from VIR_TRUE based on the count. At step 1608, method 1600 continues with performing a vector compression operation on the elements of the loaded input operand vector based on the load locations from VIR_TRUE. Step 1608 includes step 1610, which includes method 1600 continuing to store the elements of the loaded input operand vector into the output OVR corresponding to the load locations from VIR_TRUE. At step 1612, method 1600 continues with comparing the count to a value representing the vector length (i.e., VL) of VIR_TRUE, so that the vector compression operation can be iterated for each input OVR location stored in VIR_TRUE. When the count is equal to the vector length of VIR_TRUE, then method 1600 ends. When the count is less than the vector length of VIR_TRUE, then method 1600 continues to increment the count at 1614 and then returns to step 1604 (loading the count stored in the counter register), followed by steps 1606 (loading the storage location of the element of the load input operand vector from VIR_TRUE according to the count by the vector load-store unit) and 1608 (running the vector compression operation on the element of the load input operand vector according to the load location from VIR_TRUE). In this manner, the vector compression operation is iterated for each input OVR location stored in VIR_TRUE.

[0190] Figure 17 An exemplary system 1700 is shown that includes VIR_TRUE 1702a (which may be similar to VIR_TRUE 1202a or 1502a) for compressing elements of an input operand vector stored in an input OVR 1704, according to some embodiments of the present disclosure. Alternatively, the exemplary system 1700 may be configured to compress elements of the operand vector based on VIR_FALSE 1702b (which may be similar to VIR_FALSE 1202b or 1502b), according to some embodiments of the present disclosure. Furthermore, the exemplary system 1700 may be configured to compress elements of the operand vector based on the TRUE or FALSE portion of VIR_COMBINED (e.g., see VIR_COMBINED 1402), according to some embodiments of the present disclosure.

[0191] Exemplary system 1700 is one example of a system in which at least method 1600 may be implemented.

[0192] exist Figure 17, VIR_TRUE 1702a stores a list of the locations of input OVR 1704 (e.g., "2" as the first element of input OVR and "4" as the second element of input OVR). In this illustrated example, the vector processor is shown running two cycles or two iterations of the vector compression operation. At the first iteration, counter 1706 outputs a count of "0", which is the value stored in the counter at the first cycle. In the first cycle, VIR_TRUE 1702a is shown as outputting "2". Multiplexer 1708 selects between the address component ("0") specified by counter 1706 in normal mode operation or the address component ("2") specified by VIR_TRUE 1702a in VIR_TRUE operating mode (or compression operating mode based on the contents of VIR_TRUE 1702a in this specific example). When multiplexer 1708 selects VIR_TRUE (or VIR_TRUE compression mode) in the first cycle, output "2" from VIR_TRUE 1702a is the address component used to access input OVR 1704. Thus, the output for element "C" at position "2" of input OVR accesses input OVR 1704. Output OVR 1710 is directly addressed by the count stored in counter 1706. Since the count in counter 1706 is "0" in the first cycle, output ORV 1710 stores "C" as its first element. In the next iteration, or cycle, output ORV 1710 stores "E" as the second element at position "1" of output OVR. In this example, which has two cycles, input OVR 1704 having elements {A, B, C, D, E} is compressed into output OVR 1710 having elements {C, E}.

[0193] In addition, reference Figure 17 , if the address signals of the input / output vector are inverted, {C,E} can be expanded to a second output OVR with elements {x,x,C,x,E}, where x is the existing value before the compression operation or a scalar value selected from a scalar register (see, for example, Figure 9 , which is an exemplary method of extending a compressed vector with a scalar value from a scalar register).

[0194] Furthermore, if the value from the VFR is added to the count of the counter, the sum of the two can be used so that the first iteration of the operation on the input OVR is performed at another position of the input OVR than the first position of the input OVR (e.g., the first position of the input OVR 1704 is marked as "0"). For example, see Figure 5Alternatively, VIR_TRUE 1702 can be used to provide an input to the count register so that the initial value of the count register at the start of a vector operation is the value stored in VIR_TRUE 1702a. Such an option allows for vector priority processing. It should be understood that VIR_FALSE 1702b can be used instead of VIR_TRUE 1702a for different types of operations. For example, a compression operation can be based on an index in VIR_FALSE 1702b instead of VIR_TRUE 1702a. In addition, VIR_COMBINED can replace VIR_FALSE 1702b and VIR_FALSE 1702b in system 1700.

[0195] Methods 600, 700, 900, 1000, 1100, 1300, and 1600 include only some of the many operations that may be performed by the vector processors and systems described herein.

[0196] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations that produces a desired result. These operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common purposes, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0197] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and converts them into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0198] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. The computer program may be stored on a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0199] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to carry out the methods. The structures of various such systems will appear as set forth in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0200] The present disclosure may be provided in part as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0201] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A method for a vector processor, comprising: The vector load-store unit of the vector processor loads the operand vector stored in the operand vector register OVR; The vector load-store unit loads a scalar stored in a scalar register; Determine the vector length of the load operand vector; Load the count stored in the counter register; Perform the following operations until the count equals the vector length of the load operand vector: comparing, by the vector processor, elements of the load operand vector with the load scalar according to the count; responsive to the element of the load operand vector matching the load scalar, storing a position of the element of the load operand vector in a vector index register VIR_TRUE of a TRUE result of the comparison according to the count, wherein the VIR_TRUE is a top portion of a combined vector index register VIR_combined, and storing the position of the element of the load operand vector in the VIR_TRUE comprises storing the position of the element of the load operand vector at a topmost unfilled position in the VIR_combined; responsive to the element of the load operand vector not matching the load scalar, storing a position of the element of the load operand vector in a vector index register VIR_FALSE of a FALSE result of the comparison according to the count, wherein the VIR_FALSE is a bottom portion of the VIR_combined, and storing the position of the element of the load operand vector in the VIR_FALSE comprises storing the position of the element of the load operand vector at a bottommost unfilled position in the VIR_combined; and The count is incremented.

2. The method according to claim 1, further comprising: loading, by the vector load-store unit, a storage location of the element of the load operand vector from at least one of the VIR_TRUE or the VIR_FALSE or a combination thereof; and One or more vector operations are iterated on the elements of the load operand vector according to the position of the load.

3. The method according to claim 1, further comprising: loading, by the vector load-store unit, the storage location of the element of the load operand vector from the VIR_combined; and One or more vector operations are iterated on the elements of the load operand vector according to the position of the load.

4. The method according to claim 1, further comprising: Load the input operand vector stored in the input OVR; loading a second count from a second counter register; loading the storage locations of the elements of the loaded input operand vector from said VIR_TRUE according to said second count; and As part of a vector operation, the elements of the loaded input operand vector are stored in output OVR corresponding to locations loaded from the VIR_TRUE.

5. The method of claim 4, wherein the vector operation is a pack operation, and wherein the method further comprises storing the elements of the loaded input operand vector into an output OVR corresponding to a load location stored in the VIR_TRUE.

6. The method according to claim 5, further comprising: Loading stored elements from the output OVR; iterating a second vector operation on the stored elements from the output OVR according to the load location stored in the VIR_TRUE, wherein the second vector operation is an expand operation; and According to the expansion operation, the element from the output OVR is stored into the second output OVR at a position of the second output OVR according to the load position stored in the VIR_TRUE. 7 . The method of claim 6 , further comprising storing a scalar into the second output OVR at another location of the second output OVR according to the expansion operation.

8. The method according to claim 7, further comprising: iterating a second compression operation on elements of the load operand vector according to the load position stored in the VIR_FALSE; storing the element of the load operand vector into a second output OVR corresponding to the load location stored in the VIR_FALSE; and One or more vector operations are performed using the elements from the output OVR and the second output OVR.

9. The method according to claim 7, further comprising: iterating a second compression operation on the elements of the second load operand vector according to the load position stored in the second VIR_TRUE; storing the elements of the second load operand vector into a second output OVR corresponding to the load locations stored in the second VIR_TRUE; and One or more vector operations are performed using the elements from the output OVR and the second output OVR.

10. A computing system comprising: a vector processor configured to compare elements of a load operand vector to a load scalar according to a count stored in a counter register of the vector processor; An operand vector register OVR of the vector processor is configured to store an operand vector; a scalar register of the vector processor configured to store a scalar; and A vector load-store unit of the vector processor is configured to: Loading the operand vector stored in the OVR; Loading the scalar stored in the scalar register; Determine the vector length of the load operand vector; loading the count stored in the counter register; Perform the following operations until the count equals the vector length of the load operand vector: comparing elements of the load operand vector to the load scalar according to the count; responsive to the element of the load operand vector matching the load scalar, storing a position of the element of the load operand vector in a vector index register VIR_TRUE of the vector processor of a TRUE result of a compare of the vector processor according to the count, wherein the VIR_TRUE is a top portion of a combined vector index register VIR_combined, and storing the position of the element of the load operand vector in the VIR_TRUE comprises storing the position of the element of the load operand vector at a topmost unfilled position in the VIR_combined; responsive to the element of the load operand vector not matching the load scalar, storing a position of the element of the load operand vector in a vector index register VIR_FALSE of the vector processor of a FALSE result of the vector processor compare according to the count, wherein the VIR_FALSE is a bottom portion of the VIR_combined, and storing the position of the element of the load operand vector in the VIR_FALSE comprises storing the position of the element of the load operand vector at a bottommost unfilled position in the VIR_combined; and The count is incremented.

11. The system of claim 10 , wherein the vector load-store unit is configured to load a storage location of the element of the load operand vector from at least one of the VIR_TRUE or the VIR_FALSE or a combination thereof, and wherein the vector processor is configured to iterate one or more vector operations on the elements of the load operand vector according to the loaded location.

12. The system of claim 10 , wherein the vector load-store unit is configured to load storage locations of the elements of the load operand vector from the VIR_combined, and wherein the vector processor is configured to iterate one or more vector operations on the elements of the load operand vector according to the loaded locations.

13. The system of claim 10 , wherein the vector load-store unit is configured to: Loading an input operand vector stored in an input OVR of the vector processor; loading a second count from a second counter register of the vector processor; loading the storage locations of the elements of the loaded input operand vector from the VIR_TRUE according to the second count; and As part of a vector operation, the elements of the loaded input operand vector are stored in output OVR corresponding to locations loaded from the VIR_TRUE.

14. The system of claim 13 , wherein the vector operation is a pack operation, and wherein the vector load-store unit is configured to store the elements of the loaded input operand vector into an output OVR corresponding to a load location stored in the VIR_TRUE.

15. The system of claim 14 , wherein the vector load-store unit is configured to load stored elements from the output OVR, wherein the vector processor is configured to iterate a second vector operation on the stored elements from the output OVR according to the load location stored in the VIR_TRUE, wherein the second vector operation is an expand operation, and wherein the vector load-store unit is further configured to store the elements from the output OVR into a second output OVR of the vector processor at a location of the second output OVR according to the load location stored in the VIR_TRUE according to the expand operation. 16 . The system of claim 15 , wherein the vector load-store unit is configured to store a scalar into the second output OVR at another location of the second output OVR according to the expand operation.

17. The system of claim 16 , wherein the vector processor is configured to iterate a second compression operation on elements of the load operand vector according to the load location stored in the VIR_FALSE, wherein the vector load-store unit is configured to store the elements of the load operand vector into a second output OVR corresponding to the load location stored in the VIR_FALSE, and Wherein the vector processor is further configured to perform one or more vector operations using the elements from the output OVR and the second output OVR.

18. A vector processor comprising: an arithmetic logic unit ALU among the plurality of arithmetic logic units; an operand vector register OVR of the plurality of operand vector registers configured to store elements of an operand vector to be used as inputs to vector operations of the ALU; a vector index register for TRUE results of comparison VIR_TRUE configured to store a plurality of address components corresponding to a plurality of locations in the OVR that produce a TRUE result when used for comparison; and a vector index register VIR_FALSE for FALSE results of comparison configured to store a plurality of address components corresponding to a plurality of locations in the OVR that produce a FALSE result when used for the comparison, Each address component is addable to an effective address for accessing a corresponding location in the OVR, and each location of the OVR comprises an element of the operand vector to be operated on by the ALU, wherein the vector processor is configured to: loading the operand vector stored in the operand vector register; Loads a scalar stored in a scalar register; Determine the vector length of the load operand vector; Load the count stored in the counter register; Perform the following operations until the count equals the vector length of the load operand vector: comparing elements of the load operand vector to the load scalar according to the count; responsive to the element of the load operand vector matching the load scalar, storing a position of the element of the load operand vector in the VIR_TRUE according to the count, wherein the VIR_TRUE is a top portion of a combined vector index register VIR_combined, and storing the position of the element of the load operand vector in the VIR_TRUE comprises storing the position of the element of the load operand vector at a topmost unfilled position in the VIR_combined; and responsive to the element of the load operand vector not matching the load scalar, storing the position of the element of the load operand vector in the VIR_FALSE according to the count, wherein the VIR_FALSE is a bottom portion of the VIR_combined, and storing the position of the element of the load operand vector in the VIR_FALSE comprises storing the position of the element of the load operand vector at a bottom-most unfilled position in the VIR_combined; and The count is incremented.

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