Method and apparatus for shared cross-flow event detection

Abstract

Shared events are identified across spike neural network data streams with significant random content. The data streams first undergo cross-correlation. If two data streams are completely uncorrelated, the rate of occurrence of cross-stream spike pairs is approximately uniform across all event time intervals, "r_ind". Any shared event forms a gradient, where r_ind increases to a rate "r_shr" for any TBE ≤ the time of discrimination. The search for the actual TOD can be performed using a predicted TOD. An exponential decay test is performed on TOD_c, where the rate of exponential decay is set to the predicted r_ind. A range of equal exponential decay values ​​when r_ind_c = actual r_ind represents equal probability. Values ​​for TOD_c and r_ind are generated until regions with equal probabilities are found to receive combinations of statistically equal numbers of cross-stream events. It is then known that TOD_a ≤ TOD_c.

Description

[0001] This patent claims the benefit of the following U.S. patent applications whose filing dates are incorporated herein by reference in their entirety:

[0002] The invention is "Method and Apparatus for Shared Cross-Stream Event Detection", filed on June 2, 2019, with David Carl Barton as the inventor and application number 62 / 856,142.

[0003] This patent is incorporated herein by reference in its entirety from the following patent applications:

[0004] The inventor is David Carl Patton, and the U.S. patent application filed on March 17, 2019, with application number 62 / 819,590, entitled "Method and Apparatus for CrossCorrelation"; and

[0005] The PCT international application filed on March 15, 2020, with David Carl Patton as the inventor and application number PCT / US2020 / 022869, is entitled "Method and apparatus for cross-related applications". Technical Field

[0006] This invention generally relates to detecting shared events occurring across multiple data streams, and more specifically, to detecting shared events across data streams with significantly random content. Background Technology

[0007] The importance of achieving synchronization (or cross-correlation) between signal (or data) streams is well-known in many technical fields, including (but not limited to) signal processing and computer networks. For example, in signal processing, cross-correlation is commonly used to determine the relative delay between signal streams in various applications. After two signal streams have undergone cross-correlation, a measure of their degree of synchronization can be useful.

[0008] Therefore, there is a need for a better measure of the correlation between signal streams. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention:

[0010] Figure 1 Describe an example application scenario of the multi-stream cross correlator in the field of spike neural networks.

[0011] Figure 2 It is aimed at Figure 1 Functional block diagram of the internal structure of each CCU instance.

[0012] Figure 3 Describe a functional implementation of learning delay, wherein the learning delay utilizes information present in its FOR. d Each pair of spikes at the input is used as a reference frame to analyze any spikes that appear at other inputs during the learning delay.

[0013] Figure 4 An example pseudocode implementation scheme for learning delay based on the Python programming language is described.

[0014] Figures 5 to 7 Describe an example implementation of learning delay.

[0015] Figure 8 yes Figure 2 The functional block diagram of the CCU, except that a conflict resolution block is added to the memoryless version that causes latency.

[0016] Figure 9 An example of implementing a delay by combining an exponential decay curve with threshold detection is described.

[0017] Figure 10 Presentation for implementation integration Figure 8 The circuit system for generating delay functionality is discussed for function block 0220.

[0018] Figure 11 Describing and Figure 8 The same CCU is shown, except that the "Learning Rate All" (or LRA) function block 0223 is added.

[0019] Figure 12 Depicting in the known actual MEA ALL In the case of a spike in instance distribution.

[0020] Figure 13 Described in MEA ALL Guessing the value (called MEA) guess The distribution of peaks when the value is too high.

[0021] Figure 14 Described in MEA ALL Guessing the value (called MEA) guess The distribution of peaks when the value is too low.

[0022] Figure 15 Describe an equality test method that finds the MEA instead of solving for the point that produces half of the total range of Equation 1 (e.g., P = 0.5).

[0023] Figure 16 The complete circuit implementation scheme for learning rate based on the equality test method is presented.

[0024] Figure 17 and 18 Presented in Figure 6 and 7 The same circuit implementation for the learning delay shown in the figure, except for the addition of r ALL Except for the input hardware.

[0025] Figure 19 Presentation Figure 10 The same circuit implementation for generating delay shown in the figure, except for the addition of r ALL Except for the input hardware.

[0026] Figure 20 Describe a block diagram showing how the TOD unit will be used in conjunction with the output of the cross-correlated unit (or CCU).

[0027] Figure 21 The fragments of two spike flows that may appear after the correlation are presented.

[0028] Figure 22 Describing and Figure 21 The same spike flow, except for instances highlighting the arbitrary inter-spike delay between the two types.

[0029] Figure 23 For the purpose of emphasizing the central problem of the invention (determining the "discrimination time" or TOD), only the two CSSP TBEs are illustrated.

[0030] Figure 24 Depicting how to merge into Figure 20 In the design, it is possible to perform actions on spike streams. Figure 26 The simulation of two examples of TOD unit implementation schemes.

[0031] Figure 25A The aim is to illustrate the behavior of CS spike convection with only random content.

[0032] Figure 25B The purpose is to illustrate the additional rate added to r_ind (if a shared spike exists) for time intervals of TOD or smaller.

[0033] Figure 26 Presenting targeting Figure 20 The learning of each implementation instance partition in the TOD unit is specifically suited to hardware.

[0034] Figure 27A-B presents a functional view of the implementation using TOD_c and r_ind_c.

[0035] Figure 28A -B is used for Figure 20 The implementation plan of instance pseudocode for each of the learning TOD units.

[0036] Figure 29 Depicting based on Figure 26 Example circuit-level implementation of hardware partitioning.

[0037] Figure 30A -B corresponds to respectively Figure 27A -B, only Figure 30A -B describes instances where the time range after TOD_c is divided into four or two, except for those instances.

[0038] Figure 31 Presentation Figure 30A Example circuit-level implementations of -B's multi-scale (quarter and half) and multi-sample (Q4 / Q3 and Q2 / Q1) methods.

[0039] Figure 32A -C is used for Figure 20 The implementation scheme of multi-scale, multi-sample pseudocode for learning each instance in the TOD unit. Detailed Implementation

[0040] Various embodiments of the invention will now be described in detail with reference to the accompanying drawings, which illustrate examples of the invention. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0041] Please refer to Section 7 (“Selected Terminology List”) which defines the selected terms used below.

[0042] Catalog of Implementation Methods

[0043] 1 Overview

[0044] 2. Examples and Implementations

[0045] 3. Partitioning Implementation Example

[0046] 3.1 Overview

[0047] 3.2 Widespread

[0048] 3.3 Circuit Implementation Scheme

[0049] 4. Pseudocode Implementation Plan

[0050] 5. Multi-scale, multi-sample

[0051] 5.1 Overview

[0052] 5.2 Examples and Implementations

[0053] 5.3 Example Electricity Implementation Plan

[0054] 5.4 Pseudocode Implementation Plan

[0055] 6 Other variations

[0056] 7. Select a glossary

[0057] 8. Computing devices

[0058] 9 Appendix

[0059] 1 Overview

[0060] This patent is directly based on the following U.S. provisional application: “Method and apparatus for detecting shared cross-flow events” (hereinafter referred to as '142 application), filed on June 2, 2019, by David Carl Patton, application number 62 / 856,142.

[0061] The '142 application itself is based on the following U.S. provisional application:

[0062] The invention is “Method and apparatus for cross-related applications” (hereinafter referred to as '590 application) filed on March 17, 2019, with David Carl Patton as the inventor and application number 62 / 819,590.

[0063] The full text of application '590 is included as an appendix in application '142. Essentially, the full text of application '590 is also included as an appendix in this document. As stated above, the full text of application '590 is incorporated herein by reference.

[0064] Application 590 presents a method and apparatus for cross-correlation between data streams having significant random content (e.g., that may appear in a spike neural network).

[0065] Because application '590 includes figures numbered 1 to 19, therefore this patent... Figures 1 to 19 This is explained in the appendix (i.e., section 9) included in this document.

[0066] The figure number in application '142 and the discussion of the shared cross-flow event detection in this patent are in Figure 20 Start here.

[0067] The description presented herein focuses on the application of the invention to spike neural networks. However, as explained in the glossary below, the term "spike" as used herein can refer to a broader range of signal discontinuities. To emphasize the broad range of the term "spike," it may be replaced throughout this document with the terms "event" or "performance."

[0068] Figure 21 The two spike streams 2001 and 2002 are presented as fragments, since they may have emerged after being correlated with the invention of application '590. Thus, apart from certain pairs of spikes that have been identified as correlated across the two streams, the spikes of streams 2001 and 2002 can be expected to be randomly distributed (or, as one might say, predominantly random). In individual consideration, randomness occurs both relative to each spike stream itself and when examining spikes across two or more streams.

[0069] As can be seen, for the purposes of discussion, each peak of flow 2001 has been assigned a label from a1 to j1, and each peak of flow 2002 has been assigned a label from a2 to f2.

[0070] Figure 22 Describing and Figure 21 The same spike flow, except for instances highlighting the arbitrary inter-spike delay between the two types.

[0071] Figure 22 Two intra-flow (IS) spike pairs are highlighted within flow 2001:

[0072] • The IS peak pair consisting of peaks a1 and b1, and

[0073] • The IS peak pair consisting of peaks b1 and c1.

[0074] Figure 22 The two cross-flow (CS) spike pairs of flows 2001 and 2002 are also highlighted:

[0075] • The CS peak pair consisting of peaks a2 and b1, and

[0076] • CS peak pair of peaks b2 and d1.

[0077] The time interval between two consecutive spikes that occur in the same or separate flow is called the time between events (TBE) of the spike pair. (In '590 application, the TBE of the IS spike pair is called the inter-spike gap or ISG.) In this patent, the TBE of the CS spike pair will be discussed in detail. The CS spike pair may also be referred to herein as a CSSP, and the IS spike pair may also be referred to herein as an ISSP. A continuous CSSP generated by selecting two spike flows can be called a CS spike pair flow (or CSSP flow).

[0078] Figure 22 Highlight the following two TBEs for the IS spike pair:

[0079] • TBE 2210 of peaks a1 and b1, and

[0080] • TBE 2211 for peaks b1 and c1.

[0081] Figure 22 The following two TBEs of CSSP are also highlighted:

[0082] • TBE 2220 between peaks a2 and b1, and

[0083] • TBE 2221 between peaks b2 and d1.

[0084] Unless otherwise restricted, the time range of TBE can be virtually any value from arbitrarily close to 0 to arbitrarily close to infinity.

[0085] As discussed above, within each flow of an ISSP or CSSP, the time interval can be expected to be arbitrary, except for those CS spike pairs whose correlation has been identified. The arbitrary distribution of ISSP or CSSP flows is typically a Poisson distribution. Although arbitrary, each flow of an ISSP or CSSP can be expected to have a relatively constant average time interval. This average time interval can also be expressed as the average rate of spike pair occurrence, or r_avg.

[0086] As mentioned, in addition to random content, the stream of CSSPs can also have non-random content, and this invention is aimed at detecting non-random CSSPs. When non-random CSSPs occur, the spikes that form them can be expected to have a fixed time relationship (subject to limitations present in any real-world signaling system, such as jitter).

[0087] Although they have a fixed temporal relationship, these spikes can generally be expected to appear at different times (due to reasons other than jitter, and inherent to the operation of systems such as spike neural networks). Additionally, it is possible that one or two spikes, as part of a non-random CSSP, will not reliably represent themselves in their respective spike streams (even though these spikes are expected to have a fixed temporal relationship with each other when they appear). Since non-random CS spike pairs represent multiple spikes shared in the representation of a given fundamental event, they can be called "shared" CS spike pairs. The representational spikes in a shared CS spike pair can be called "shared" CS spikes (or simply shared spikes).

[0088] Compared to shared CS spike pairs, random CS spike pairs represent spike pairs where the occurrence of one spike is independent of the occurrence of the other spike. Thus, the spikes in random CS spike pairs can be referred to as "independent" CS spikes (or simply independent spikes for short). The average occurrence rate of these independent spikes can be expressed as r_ind (rather than r_avg).

[0089] After applying the related invention of the '590 application, it can be expected that shared CS spike pairs have a time separation (or TBE) close to zero. This invention seeks to determine the maximum time distance, herein referred to as the "discrimination time" (or TOD). CS spike pairs with a TBE equal to or less than TOD are classified as consisting of shared spikes, while CS spike pairs with a TBE greater than TOD are considered independent.

[0090] Once the correlation is found, the determination of TOD is based on an understanding of how independent and shared spikes interact. This will be illustrated by Figures 25A-25B for illustration. Figures 25A-25B Each presents a type of graph depicting the relationship between the rate (vertical axis) of a specific CS spike stream and the time separation (horizontal axis, labeled "TBE"). The specific numbers on the TBE axis are for illustrative purposes only.

[0091] Figure 25A is intended to illustrate the behavior of a CS spike stream with only random content. It depicts the fact that across all time separations, it can be expected that the CSSP exhibits an approximately uniform average occurrence rate, i.e., r_ind (as discussed above).

[0092] However, in comparison,[[]] Figure 25B is intended to illustrate the additional rate of shared spikes (if any) added to r_ind for time separations up to and including TOD 2510. This combined rate labeled 2530 in Figure 25B is referred to as the shared rate or r_shr. Thus, TOD such as 2510 can be determined by finding the time separation with the following characteristics:

[0093] · For all larger TBEs, the rate of the CSSP is lower (e.g., in Figure 25B it drops to r_ind 2521); and

[0094] · For all equal or smaller time separations (relative to TOD), the rate of the TBE is higher (e.g., it increases to r_shr 2530).

[0095] Figure 25B also depicts the fact that even within the range of time separation < TOD, there is still a background random rate of CSSP occurrence (in Figure 25BThe indicator is 2520). This background rate is added to the rate of the shared CSSP, resulting in a combined level of r_shr. The background rate indicator r_ind can be expected to produce a certain number of false alarms.

[0096] Figure 23 For the purpose of emphasizing the central problem of the invention (determining the "discrimination time" or TOD), only two CSSP TBEs are illustrated. For the purpose of illustration, TBE 2221 is considered to be >TOD, and therefore spikes b2 and d1 are considered non-shared. TBE 2222 is considered sufficiently small such that c2 and e1 are considered shared spikes.

[0097] 2 Examples and Implementations

[0098] To present example implementations, introducing additional nomenclature will be useful. Specifically, distinguishing between the two types of TODs is useful:

[0099] • TOD_a: The actual TBE time interval, after which the CSSP rate decreases from r_shr to r_ind.

[0100] • TOD_c: For implementations seeking to determine TOD_a, TOD_c represents the currently estimated value.

[0101] Although embodiments of the present invention cannot directly detect TOD_a, they can detect the gradient separating TOD_c and TOD_a, thereby searching for increasingly accurate estimates of TOD_a.

[0102] Similarly, it is useful to distinguish between the two types of r_ind:

[0103] ·r_ind_a: The actual rate of CSSP for time intervals greater than TOD_a.

[0104] • r_ind_c: For the implementation seeking to determine r_ind_a, r_ind_c represents the current estimated value based on CSSP>TOD_c.

[0105] Similarly, although embodiments of the present invention cannot directly detect r_ind_a, they can detect the gradient separating r_ind_c and r_ind_a, and thereby search for a value representing a more accurate estimate of r_ind_c.

[0106] Figure 27A -B presents a functional view of the implementation using TOD_c and r_ind_c. Specifically, Figure 27A Each of the elements in -B describes one of the two key operational modes:

[0107] · Figure 27A: Depicts the case where TOD_a < TOD_c, which is referred to as the "first mode" or "mode one". For the shown example, TOD_a is illustrated at 0.05 seconds and TOD_c is at 0.10 seconds.

[0108] · Figure 27B : Depicts the case where TOD_a > TOD_c, which is referred to as the "second mode" or "mode two". For the shown example, TOD_a is illustrated at 0.51 seconds and TOD_c is at 0.10 seconds.

[0109] As can be seen, Figure 27A Consists of the following two main sub - parts:

[0110] · Chart 2700: Depicts an exponential decay curve 2710 in the form of e -rt . The horizontal axis represents the time distance between the first and second spikes of the CSSP (i.e., TBE). Assume the exponential decay rate ("r") is equal to the actual average rate of independent (or randomly spaced) CSSPs (r_ind_a). Then, each value along the vertical TBE_P axis represents the following probability. Specifically, if the first spike of an independent CSSP has just occurred, then for each time along the horizontal TBE axis, its TBE_P value represents the probability that the second spike will occur, either at time TBE or at any time thereafter. Thus, for example, when the first spike is at TBE time = 0 seconds, the probability that the second spike will occur at 0 seconds or at any time thereafter is 1 or 100% (according to the TBE_P axis).

[0111] · Chart 2701: Depicts a chart of substantially the same type as previously discussed for Figure 25B , except that Figure 27A the TOD_a of

[0112] Chart 2700 is also based on the use of two threshold detectors:

[0113] · The first threshold detector is set to the threshold th_c, which, when projected onto the time axis (i.e., projected onto the TBE axis) through the exponential decay 2710, identifies TOD_c. Thus, this threshold detector identifies TOD_c for the time range to infinity. In Figure 27A , the example value is th_c = 0.74, and the corresponding TOD_c = 0.10 seconds.

[0114] · The second threshold detector is set to th_c / 2. In Figure 27A , for the purpose of the example, th_c / 2 = 0.37. The second threshold detector determines the median expected arrival (MEA) time when projected onto the time axis, for the time range from TOD_c to infinity. In Figure 27AIn the example, the MEA time is 0.33 seconds. Therefore, th_c / 2 can be used as follows to divide the time range from TOD_c to infinity into two equal parts:

[0115] ○ The first half, called H2, where: TOD_c < H2 ≤ MEA. For Figure 27A , the example range is: 0.10 seconds < H2 ≤ 0.33 seconds.

[0116] ○ The second half, called H1, where: MEA < H1 ≤ ∞. For Figure 27A , the example range is: 0.33 seconds < H2 ≤ ∞ seconds.

[0117] Although the example of dividing into two equal parts is used, for the first introduction of the division of the time range from TOD_c to infinity, other division units (such as dividing the range into four equal parts) can be used. Therefore, each division unit can also be called a "region". Figure 27A Two regions are shown, where each region is half of the time range.

[0118] Dividing into two equal parts can be used to converge r_ind_c to r_ind_a as follows:

[0119] · For each independent CS spike pair, the second spike (called spike_2) is considered a negative proxy for r_ind_a.

[0120] · Regardless of which half spike_2 occurs in, adjust r_ind_c to increase the likelihood that future spikes will occur in the other half. For example, Figure 27A depicts an example spike_2 at 0.51 seconds within H1. Therefore, gradually decrease r_ind_c (according to the learning rate required), as this will tend to shift spikes towards H2 in the future. Generally, the rules for adjusting r_ind_c are as follows:

[0121] ○ If the second spike in the CS spike pair appears within H1:

[0122] Gradually decrease r_ind_c so that subsequent spikes will have a greater tendency to occur within H2.

[0123] ○ If the second spike in the CS spike pair appears within H2:

[0124] Gradually increase r_ind_c so that subsequent spikes will have a greater tendency to occur within H1.

[0125] · Temporarily ignoring the influence of TOD_a (i.e., assuming a time range within which r_ind_a is searched and having a uniform rate r_ind_a), it can be understood how this method will statistically result in the convergence of r_ind_c to r_ind_a:

[0126] ○ If, over time, H1 receives more of the second spikes in the CS spike pairs than H2, then it is known that r_ind_c is too high (i.e., it is known that r_ind_c > r_ind_a) by some unknown amount. Thus, the search space gradient indicates that r_ind_a is somewhat lower than r_ind_c, and r_ind_c should be decreased to reduce the difference.

[0127] ○ If, over time, H2 receives more of the second spikes in the CS spike pairs than H1, then it is known that r_ind_c is too low (i.e., it is known that r_ind_c < r_ind_a) by some unknown amount. Thus, the search space gradient indicates that r_ind_a is somewhat higher than r_ind_c, and r_ind_c should be increased to reduce the difference.

[0128] · The incremental amount by which r_ind_c is decreased or increased determines the learning rate, and this amount is referred to as R_LR.

[0129] Following these rules, if the optimization process starts with r_ind_c just below r_ind_a, then more spikes will occur in H2 than in H1, resulting in a net increase in r_ind_c. Increasing r_ind_c will decrease the time-axis projection of th_c (i.e., will cause TOD_c to decrease). For purposes of explanation, it will be assumed that the decrease in TOD_c is not sufficient to cause it to exit mode one (i.e., will not cause TOD_c to be equal to or less than TOD_a). For r_ind_c starting above r_ind_a, the adjustment of r_ind_c (i.e., its decrease) will not cause an exit from mode one (since it increases the amount by which TOD_c exceeds TOD_a).

[0130] Thus, for this first operating mode, without an additional mechanism (and an additional mechanism will be discussed below), a balanced state can be reached where only r_ind_c equals r_ind_a, and TOD_a is less than TOD_c. In such a case, an equal number of spikes still occur in H2 and H1, which means a net dynamic balance.

[0131] Figure 27B Depict the second main operating mode, where TOD_a is greater than TOD_c. As Figure 27A , Figure 27B is composed of an upper subgraph and a lower subgraph. Figure 27B The upper subgraph of Figure 27A is the same as the upper subgraph of Figure 27B (and thus both are labeled 2700). Figure 27A The lower subgraph of Figure 27A (labeled 2702) differs from the lower subgraph of Figure 27B (labeled 2701) only in that TOD_a exceeds TOD_c.

[0132] In Mode 2, it can be observed that because r_shr always extends into region H2 by at least some amount (assuming TOD_a > TOD_c), and r_shr will always extend into region H1 by a smaller amount (if any), the net peak occurrence rate of H2 will always be higher than that of H1. This observation can be used to adjust TOD_c toward TOD_a as follows:

[0133] If the second peak in a CS peak pair appears within H2: assume it is a result of TOD_a extending by at least some unknown amount beyond TOD_c. The imbalance rate (between H2 and H1) is reduced by gradually increasing TOD_c toward TOD_a (by gradually decreasing th_c). While this assumption may not be entirely correct when dealing with individual peak pairs, statistically, for a large number of peak pairs, the second peak in H2 will necessarily be more numerous than in H1 (provided TOD_a extends by at least some amount beyond TOD_c).

[0134] If the second peak in the CS peak pair appears within H1: assume it is a result of the balancing rate between H2 and H1, and therefore gradually decreases TOD_c (by gradually increasing th_c). While this decrease will slow the approach of TOD_c towards TOD_a (if TOD_c is actually less than TOD_a), it is necessary for the TOD learning device to eventually achieve the first operating mode (i.e., to achieve TOD_c equal to or greater than TOD_a). In the first mode, once r_ind_c equals r_ind_a, not only will the change in r_ind_c be balanced, but the change in TOD_c will also be balanced, thus giving TOD_c a net dynamic balance.

[0135] The learning rate is determined by the increment by which TOD_c decreases or increases (through the adjustment of th_c), and this amount is called TH_LR.

[0136] It should be noted that in Mode 2, the greater tendency for peaks to appear in H2 compared to H1 will also lead to an increase in r_ind_c (because if the TOD learning device is actually in Mode 1, then the increase is necessary, and it is assumed that the device does not know whether it is actually in Mode 1 or Mode 2). As mentioned above, this rate increase tends to decrease TOD_c, and thus acts to counteract the increase in TOD_c.

[0137] However, eventually, r_ind_c will be increased to a sufficiently high rate such that each increment of the rate (through R_LR) will decrease TOD_c by a smaller amount than the increase in TOD_c (caused by the decrease in th_c per unit TH_LR). Furthermore, as TOD_c approaches TOD_a, the frequency of rate increases will decrease (because the average rate across H2 decreases towards the average rate across H1). Eventually, TOD_c will equal or exceed TOD_a, leading to a first operating mode where an equal number of spikes (on average) appear in either H2 or H1. Therefore, in the first operating mode, the increment of th_c reaches equilibrium and has no effect on the position of TOD_c.

[0138] As mentioned above, this has been combined with... Figure 27A As mentioned, under the equilibrium conditions in the first mode, it is understood that without further mechanisms, TOD_c can remain greater than, but not necessarily equal to, TOD_a. This problem can be addressed by adding an additional mechanism to reduce TOD_c. Specifically, th_c can always be increased by a small increment each time a peak pair is detected, regardless of whether it is in the H2 or H1 half. To prevent the constant (or region-independent) increase of th_c from significantly affecting the accuracy of the results (which are the values ​​of TOD_c, which are accurate estimates of TOD_a), the value utilized can be a small fraction of TH_LR. For example, a value of TH_LR / 10 or smaller can be used.

[0139] 3-partition example

[0140] 3.1 Overview

[0141] Figure 20 Corresponding to application 590 Figure 1 The main difference is that the TOD (Transit-Oriented Development) units 2021 and 2022 are used instead of the TOD units. Figure 1 The "soma" 0121. Each learning TOD unit has the same internal structure, the only difference being its connection to the spike streams 2001 and 2002. Each learning TOD unit is designed to learn TOD from CS spike pairs, where the first spike in each considered pair appears at the "Other" input and the second spike appears at the "Me" input. As can be seen, this causes learning TOD units 2021 and 2022 to operate as follows:

[0142] • The TOD learning unit 2021 learns TOD from the CS spike pair, where the first spike comes from stream 2002 (via CCU2012) and the second spike comes from stream 2001 (via CCU2010).

[0143] • The TOD learning unit 2022 learns TOD from the CS spike pair, where the first spike comes from stream 2001 (via CCU2010) and the second spike comes from stream 2002 (via CCU2012).

[0144] Therefore, in combination, the learning TOD units 2021 and 2022 can identify either direction of the crossflow spike pair that occurs across flows 2001 and 2002, and the output of one or the other learning TOD unit drives the "shared event" output of the "OR" gate 2015.

[0145] Regarding the learning to identify CS spike pairs, the two operations for learning TOD units can be referenced. Figure 24 and 26 To understand.

[0146] 3.2 Widespread

[0147] Figure 26 This section presents example partitions of implementation schemes for each of the Learning TOD Units 2021 and 2022, with a particular focus on hardware. While partitions are organized around hardware-centric implementation schemes, specific technology implementation schemes of choice are also discussed. Figure 26 It has also become relatively widespread.

[0148] As can be seen, for each learning TOD unit, its "Me", "Other" and "Other Shared" inputs are directed to a state machine 2610 called the "Pair Detector".

[0149] The purpose of detector 2610 is to detect each occurrence of a pair of consecutive spikes, wherein (among other potential requirements) the first spike occurs at another input, and the subsequent consecutive spikes occur at the Me input. Detector 2610 can be designed to start in state #0 upon power-on or reset.

[0150] The detector 2610 provides a directed edge indication from state #0 to state #1. When a spike is received at another input, it transitions to state #1 and outputs a pulse at its "Start or Restart" (SR) output. The SR pulse triggers the exponential decay block 2620. The decay block 2620 generates an exponentially decayed value at its "P" (or "probability") output. (See above regarding...) Figures 27A-27B As discussed, exponential decay (if its rate of r_ind_c is a good approximation of r_ind_a) represents the probability value of starting at 1 and decaying toward 0. If the exponential decay block 2620 is already experiencing exponential decay, then the decay process restarts (at 1) when another SR trigger pulse arrives. According to an example method of the implementation, the value at the "P" output can be represented by a voltage.

[0151] As the decay process continues, comparators 2640 and 2641 evaluate the value of "P" using reference standards 2630 and 2631, respectively. Specifically, reference standard 2630 provides a signal (typically a voltage) representing th_c, while 2631 outputs th_c divided by 2. When P falls below th_c, comparator 2640 asserts its output line. Therefore, in terms of time, comparator 2640 asserts its output only after TOD_c has elapsed. Similarly, when P falls below th_c / 2, comparator 2641 asserts its output line. Therefore, in terms of time, comparator 2641 asserts its output only after MEA time (from TOD_c to infinity in the time domain) has elapsed.

[0152] If a spike is received at the "Me" input while the device is already in state #1, then detector 2610 transitions from state #1 to state #2. This transition to state #2 causes state machine 2610 to output a pulse at its Event Pair Detection (EPD) output. The EPD is applied to AND gates 2650-2652 that decode the comparator output:

[0153] As can be seen, when P does not drop below th_c during the EPD time, the AND gate 2652 asserts its output (becoming the shared event output of the learning TOD unit).

[0154] The AND gate 2651 identifies whether P is in ( ) by determining that P is less than th_c but not less than th_c / 2. Figure 27A -B)H2.

[0155] The AND gate 2650 identifies whether P is within H1 by determining that P is below th_c / 2.

[0156] If the transition from state #1 to state #2 causes the first learning TOD unit to assert its shared event output (according to...) Figure 20 The output will be displayed as an "Other Shared" (OS) input at the second learning TOD unit. The assertion of the OS input forces the pair detector 2610 of the second learning TOD unit into state #0 (if it is not already in state #0). Returning to state #0 ensures that the same peak of the shared CS peak pair identified by the first learning TOD unit cannot be used as the first peak of another peak pair at the second learning TOD unit.

[0157] As discussed previously, regarding Figure 27A -B, the inferred rate (r_ind_c) of independent CS spike pairs approximates the actual rate (r_ind_a) of these spike pairs by adjusting the rate based on whether the second spike in the CS spike pair is in region H2 or H1. This adjusted learning rate is described by the variable R_LR. Figure 26As can be seen, the exponential decay unit 2620 is shown to have two rate adjustment inputs: one labeled +R_LR (where a pulse at this input increases the decay rate by R_LR), and the other labeled -R_LR (where a pulse decreases the decay rate by R_LR). It can be seen that a spike determined to be in H2 (via AND 2651) results in a pulse at the +R_LR input, while a spike determined to be in H1 (via AND 2650) results in a pulse at the -R_LR input.

[0158] Similarly, Figure 27A -B has already discussed adjusting th_c toward th_a (or, respectively, TOD_c toward TOD_a) based on whether the second peak in the CS peak pair is in region H2 or H1. The learning rate for such adjustments has been described by the variable TH_LR. Figure 26 As can be seen, reference standard 2630 is shown with two level-adjusting inputs: one labeled +TH_LR (where the pulse at this input decreases TOD_c by increasing th_c), and the other labeled -TH_LR (where the pulse at this input increases TOD_c by decreasing th_c). It can be seen that a spike determined to be in H1 causes a pulse at the +TH_LR input, while a spike determined to be in H2 causes a pulse at the -TH_LR input. Adjusting the output of 2630 automatically results in an adjustment at the output of 2631, because 2631 operates by dividing the current signal output of 2630 by 2.

[0159] Figure 24 Depicting and displaying Figure 26 Two examples of learning TOD unit implementation schemes (if merged into) Figure 20 The design simulates how peak flows 2001 and 2002 can be performed. The simulation is for peaks a1-i1 in flow 2001 and peaks a2-d2 in flow 2002. During the process of these peaks, a total of 8 CS peak pairs are identified, all of which are independent except for the peak pair c2 and e1 (which can also be expressed as (c2, e1)). Since this independent peak pair ends at flow 2001 (i.e., its second element is in flow 2001), it is identified by the learned TOD unit 2021.

[0160] To reduce the graphics space, Figure 24 Use the following abbreviations:

[0161] • Learn TOD Unit 2021 as “LU1” and learn TOD Unit 2022 as “LU2”.

[0162] • “pr” and “sp” mean “pair” (meaning peak pair) and “peak”, respectively. Therefore, for example, “pr1” means the first pair of peaks identified in a peak convection, and “sp1” means the first peak of a pair that has been identified.

[0163] • “ipair” means that an independent crossover pair has been identified, and “spair” means that a shared crossover pair has been found.

[0164] • NOP means "no operation" performed due to spikes.

[0165] • SKIP means skipping over a spike regardless of whether it is a spike pair.

[0166] The peak-by-peak simulation of the operations of LU1 and LU2 (both assumed to start in state #0) can be described as follows:

[0167] •a1 (see also note box 2410):

[0168] ○LU1: Applied to its Me input, performs NOP, where state machine 2610 simply loops back to state #0.

[0169] ○LU2: Applied to other inputs, causing its state machine 2610 to transition from state #0 to state #1, while simultaneously asserting the "SR" or "start or restart" signal. Therefore, LU2 has identified the first spike in the potential first spike pair to be identified. The assertion of SR initiates the timing operation.

[0170] •a2 (see also note box 2411):

[0171] ○LU1: Applied to other inputs, causing its state machine 2610 to transition from state #0 to state #1, while simultaneously asserting the "SR" or "start or restart" signal. Therefore, LU1 has identified the first spike in the potential first spike pair to be identified. The assertion of SR initiates the timing operation.

[0172] ○LU2: Causes its state machine 2610 to transition from state #1 to state #2, while simultaneously asserting the "EPD" or "Event Pair Detection" signal. For the purposes of this example, assume that the time interval between spikes a1 and a2 is greater than TOD_c. Therefore, independent crossflow pairs have been identified by LU2 (indicated by comment box 2430).

[0173] •b1 (see also note box 2412):

[0174] ○LU1: Causes its state machine 2610 to transition from state #1 to state #2, while asserting the "EPD" or "Event Pair Detection" signal. For the purposes of this example, assume that the time separation between spikes a2 and b1 is greater than TOD_c. Therefore, independent crossflow pairs have been identified by LU1 (indicated by comment box 2431).

[0175] ○LU2: Applied to other inputs, causing its state machine 2610 to transition from state #2 to state #1, while simultaneously asserting the "SR" or "start or restart" signal. Therefore, LU2 has identified the first spike in the potential second spike pair to be identified. The assertion of SR initiates timing operations.

[0176] • c1 (see also note box 2413):

[0177] ○LU1: Causes its state machine 2610 to perform NOP, in which it reflexively transitions from state #2 back to state #2 and asserts that there is no output signal.

[0178] ○LU2: When spike b1 is applied to other inputs, it causes a complete repetition of the operation described above. The only difference is that the timing operation starts from the time of spike c1 instead of b1.

[0179] •b2 (see also note box 2414):

[0180] ○LU1: Applied to other inputs, causing its state machine 2610 to transition from state #2 to state #1, while simultaneously asserting the "SR" or "start or restart" signal. Therefore, LU1 has identified the first spike in the potential second spike pair to be identified. The assertion of SR initiates timing operations.

[0181] ○LU2: Causes its state machine 2610 to transition from state #1 to state #2, while simultaneously asserting the “EPD” or “Event Pair Detection” signal. For the purposes of this example, assume that the time separation of spikes c1 and b2 is greater than TOD_c. Therefore, another independent crossflow pair has been identified by LU2 (indicated by comment box 2432).

[0182] ·d1 (see also note box 2415):

[0183] ○LU1: Causes its state machine 2610 to transition from state #1 to state #2, while asserting the "EPD" or "Event Pair Detection" signal. For the purposes of this example, assume that the time interval between spikes b2 and d1 is greater than TOD_c. Therefore, independent crossflow pairs have been identified by LU1 (indicated by comment box 2433).

[0184] ○ LU2: Applied to other input, causing its state machine 2610 to transition from state #2 to state #1, while asserting the "SR" or "Start or Restart" signal. Thus, LU2 has identified the first spike in the potential third spike pair to be identified. The assertion of SR starts the timing operation.

[0185] · c2 (see also annotation box 2416):

[0186] ○ LU1: Applied to other input, causing its state machine 2610 to transition from state #2 to state #1, while asserting the "SR" or "Start or Restart" signal. Thus, LU1 has identified the first spike in the potential third spike pair to be identified. The assertion of SR starts the timing operation.

[0187] ○ LU2: Causes its state machine 2610 to transition from state #1 to state #2, while asserting the "EPD" or "Event Pair Detection" signal. For purposes of illustration, assume that the time separation between spike d1 and c2 > TOD_c. Thus, another independent cross-stream pair (indicated by annotation box 2434) has been identified by LU2.

[0188] · e1 (see also annotation box 2417):

[0189] ○ LU1: Causes its state machine 2610 to transition from state #1 to state #2, while asserting the "EPD" or "Event Pair Detection" signal. For purposes of illustration, assume that the time separation between spike c2 and e1 < TOD_c. Thus, the first shared cross-stream pair (indicated by annotation box 2435) has been identified by LU1. Soon after asserting EPD, the "Shared Event" output of LU1 is asynchronously asserted and applied to the "Other Shared" (OS) input of LU2.

[0190] ○ LU2: Instead of transitioning from state #2 to state #1 and identifying the first spike in the potential fourth spike pair to be identified, the OS input of LU2 is asserted. The assertion of OS causes the state machine of LU2 to transition from state #2 to state #0. This prevents spike e1 from becoming part of another CS spike pair because e1 is already part of a shared CS spike pair. Thus, LU2 skips over spike e1 and does not consider it.

[0191] · f1, g1, and h1 (see also annotation box 2418):

[0192] ○ LU1: Applied to its Me input, f1, g1, and h1 cause LU1 to perform a NOP, where its state machine 2610 simply loops back to state #2. (Similar to LU1's operation on spike a1.)

[0193] ○LU2: Applied to other inputs, f1 causes its state machine 2610 to transition from state #0 to state #1, while asserting either the "SR" or "start or restart" signal. After each of g1 and h1, it simply loops back to state #1, reasserting the SR signal each time. Thus, LU2 identifies the first spike in the potential fourth spike pair to be identified three times. Each assertion of SR initiates or restarts a timing operation, with the last timing operation initiated at h1.

[0194] ·d2 (see also note box 2419): When spikes a2, b2 or c2 are received, the operations performed by LU1 and LU2 are substantially the same as those described above.

[0195] • i1 (see also note box 2420): When spikes b1, c1 or d1 are received, the operations performed by LU1 and LU2 are substantially the same as those described above.

[0196] 3.3 Circuit Implementation Scheme

[0197] Figure 29 Depicting based on Figure 26 Example circuit-level implementation of hardware partitioning. Figure 26 and 29 The correspondence between them is as follows:

[0198] · Figure 26 The external input interface 2600 (outside the learning TOD unit) corresponds to Figure 29 2900.

[0199] · Figure 26 The external output interface 2601 corresponds to Figure 29 2901.

[0200] · Figure 26 The state machine 2610 corresponds to Figure 29 The outline of state machine 2910 is as follows. Like state machine 2610, 2910 has three inputs (Me, others, and others shared) and two outputs (SR and EPD). A detailed explanation of state machine 2910 is provided below.

[0201] Unit 2920 corresponds to exponential decay unit 2620. As can be seen, the exponential decay in 2920 is achieved by an RC combination of variable resistor 2924 and capacitor 2923. The inputs used to increase or decrease the decay rate of 2620 (+R_LR and -R_LR, respectively) are implemented in 2920 by decreasing or increasing the resistance of 2924, respectively. An assertion at the SR input of 2920 causes switch 2921 to recharge capacitor 2923 with a unit voltage source 2922.

[0202] • Reference standard 2630 corresponds to a variable voltage source 2930 with a maximum output of 1 volt. The inputs used to increase or decrease the threshold generated by 2630 (+TH_LR and -TH_LR, respectively) are implemented in 2930 by increasing or decreasing the voltage of 2924, respectively. To ensure that TOD_c converges toward TOD_a, when TOD_c is exactly > TOD_a (meaning that balance can be achieved only based on an appropriate value of r_ind_c), the EPD output of 2910 provides a region-independent signal to 2930. As discussed above, with respect to a generalized hardware implementation, the adjustment of th_c by each EPD pulse can be made much smaller (e.g., an order of magnitude or less) than the region-independent adjustment.

[0203] • Divide th_c by 2 using 2631 Figure 29 This is implemented very simply by a voltage divider 2931. 2931 is simply two resistors of equal resistance connected between th_c and ground.

[0204] · Figure 26 The comparators 2640 and 2641 correspond to respectively Figure 29 The operational amplifier comparators 2940 and 2941.

[0205] · Figure 26 The AND gates 2650-2652 correspond to respectively Figure 29 The "AND" gate 2950-2952.

[0206] The detailed explanation of the operations of state machine 2910 is as follows:

[0207] The state is maintained by two flip-flops: a set-reset flip-flop 2911 and a negative edge-triggered flip-flop 2912. Both flip-flops are reset when powered on (i.e., Q is low).

[0208] ○ Each of the single-shot 2913 and 2914 generates a short pulse at its output EPD and SR respectively when the positive edge of its trigger input is reached.

[0209] In most cases, it can be expected that the learning TOD unit will receive independent CS spike pairs. In this case, state machine 2910 spends most of its time on Figure 26 This is represented as a cycle between states #1 and #2. These states are maintained by the SR trigger 2911.

[0210] ○ When the trigger 2912 is in the reset state, Enable AND 2915 so that it is only a pass-through for the spike at the Me input of external interface 2900 to the setting input of set-reset trigger 2911. Similarly, the low state of the Q output of 2912 disables AND 2917 and 2918 as potential pass-throughs for signals at Me and other external inputs, respectively. As will be briefly explained below, trigger 2912 is only used when a shared CS spike pair is present.

[0211] When processing a mixture of independent CS spike pairs that may be mixed with intra-stream (IS) spike pairs, trigger 2911 may operate as follows:

[0212] ■ Each spike at other inputs simply re-triggers single 2914, thereby causing a restart of exponential decay by asserting the SR output of 2910.

[0213] ■ When a Me spike occurs, the sr flip-flop 2911 is set, causing the single-shot 2913 to assert the EPD output of 2910, and thus measuring the time delay between the two spikes of the CS spike pair. After the Me spike has set the sr flip-flop 2911, a further Me spike is a NOP: since the sr flip-flop 2911 remains set, the single-shot 2913 does not generate an additional EPD pulse.

[0214] ○ For the first learning TOD unit, its state machine 2910 is affected when its peer (or second) learning TOD unit detects a shared CS spike pair. The following explanation will focus on the state machine of the first learning TOD unit:

[0215] ■ Other shared (OS) inputs of the first learning TOD unit are asserted when there is a Me spike for the second learning TOD unit and another spike for the first learning TOD unit. For the first learning TOD unit, simultaneous assertion of other OS inputs causes AND gate 2919 to generate a high level at the trigger input of flip-flop 2912 (via OR 2916).

[0216] ■ For the first learning TOD unit, once the assertion of other inputs and OS is revoked, the negative edge-triggered flip-flop 2912 changes state, thereby causing Q to generate a logic 1 (or a high signal) and causing This generates a logic 0 (or a low signal). At this time, the flip-flop 2912 is said to be in a logic 1 state.

[0217] ■ The logic 1 state of flip-flop 2912 means that if the next spike of the first learned TOD unit is at the input of Me, it will not pair with any other spike that is immediately preceding it. The logic 0 state disables the AND gate 2915. Therefore, the logic 1 state of the flip-flop 2912 prevents the first learning TOD unit from attempting to pair spikes that have already been identified as shared CS spike pairs.

[0218] ■ The logic 1 output of flip-flop 2912 causes the Q output to enable AND gates 2917 and 2918. These ensure that flip-flop 2912 will transition back to logic 0 when the next spike is revoked, regardless of whether the next spike is at Me or another input.

[0219] 4. Pseudocode Implementation Plan

[0220] As an alternative to the hardware-centric approach in Chapter 3, learning TOD units can also be implemented in software (or through any appropriate combination of software and hardware, determined by the constraints of the specific application environment).

[0221] Figure 28A The -B option presents a pseudocode program for a software-centric approach, called Leam_TOD_H2H1. The pseudocode is based on the Python programming language.

[0222] Figure 28A Each execution instance of the pseudocode for -B corresponds to Figure 20 Learn the TOD unit 2021 or 2022.

[0223] Figure 28A Lines 5-13 introduce some global variables, while lines 15-26 introduce local internal variables for each instance of Learn_TOD_H2H1.

[0224] Figure 28A Lines 28-34 address the case of spikes in other inputs applied to the learning of the TOD unit.

[0225] if( Figure 28A If the "elif" test in line 36 is positive, then we know that a new CS spike pair has just been identified, where the current spike applies to the Me input, and the spike immediately preceding it applies to the other inputs of the learning TOD unit. All the remaining pseudocode handles the case where the test in line 36 is positive.

[0226] Line 38 determines the time interval between the peaks of the current CS peak pair.

[0227] Line 39 converts this into a probability by applying exponential decay to the unit value (and assuming that r_ind_c is an accurate estimate of r_ind_a).

[0228] Line 43 sets the indicator that the previous event was applied to its Me input for the next call to this instance of Learn_TOD_H2H1.

[0229] Although CS spike pairs have been identified, since the current spike applies to the Me input, it is still necessary to ensure that earlier spikes that did not reveal the current CS spike are part of a shared CS spike pair. This is because, under a shared event model, it at most represents a single spike per stream. This is achieved through... Figure 28B The variable "lastEventWasShared" is tested at line 1 to ensure this. If the test shows this variable is true, the process jumps directly to... Figure 28B Line 50. Since only a portion of the previously identified shared CS spike pair was found to be present in the previous spike, line 50 sets the value of lastEventWasShared so that the current spike might be paired in subsequent calls. However, if lastEventWasShared tests false (a more likely outcome), then lines 4-46 become the potential execution topic. Lines 4-46 are the subject of the rest of the explanation for Learn_TOD_H2H1.

[0230] Line 4 introduces the regional independence trend toward reducing TOD_c for the case where TOD_c is exactly > TOD_a, and the region-based adjustment can be stabilized by simply adjusting r_ind_c to be sufficiently close to r_ind_a.

[0231] Line 8 tests whether this latest CS spike pair can actually reflect the possibility of shared underlying events. In this case, lines 10 and 14 are executed:

[0232] · Line 10 indicates the relationship with Figure 26 Assertions for the "Shared Events" output of the relevant external interface 2601.

[0233] Since the current spike has been found to be part of a shared CS spike pair, line 14 ensures that the current spike will not be found to be part of a subsequent spike pair.

[0234] If row 8 evaluates negatively, then we know that an independent CS spike pair has been found. The task then becomes ( Figure 28B (Lines 17-44) Adjust the tasks of th_c and r_ind_c appropriately based on the current TBE, where the current TBE is used as a negative proxy for TOD_a. Specifically, the current TBE is used as a negative proxy for values ​​for which TOD_a is not.

[0235] Since no part of the shared CS spike pair was found in the current spike, line 20 allows the current spike to be part of a subsequent spike pair.

[0236] Execute line 23 Figure 26Function 2631: Divide the time range from TOD_c to infinity at MEA time. Specifically, divide the time range from TOD_c to infinity into two halves, where H2 is the first half (i.e., before MEA time) and H1 is the second half.

[0237] The test applicable to H2 or H1 is performed by line 30, where:

[0238] If the TBE of the current CS spike pair is found in H2, then execute lines 33-36. As a negative proxy of TOD_a, perform adjustments to th_c and r_ind_c so that future CS spike pairs are more likely to occur within the time frame of H1.

[0239] If the TBE of the current CS spike pair is found in H1, then execute lines 41-44. As a negative proxy of TOD_a, perform adjustments to th_c and r_ind_c so that future CS spike pairs are more likely to occur within the time frame of H2.

[0240] Regardless of whether the CS spikes just processed are shared or independent, line 46 ensures that th_c always remains within the appropriate probability range.

[0241] 5. Multi-scale, multi-sample

[0242] 5.1 Overview

[0243] The search space formed by TOD_c and r_ind_c is convex and has no local minimum; therefore, the procedure presented in this paper will converge toward the solution (i.e., TOD_c = TOD_a, and r_ind_c = r_ind_a). However, as mentioned above regarding Mode 2, a temporary situation may occur where optimization of one variable is detrimental to optimization of the other. For example, as discussed above regarding Mode 2, the primary objective is to increase TOD_c to be close to TOD_a (i.e., to make TOD_c = TOD_a, where the current state is TOD_a > TOD_c). However, precisely, since TOD_a > TOD_c, region H2 will have a higher peak rate than H1, which leads to an increase in r_ind_c. For a given value of th_c, increasing r_ind_c will often make TOD_c smaller (i.e., increase the difference between TOD_c and TOD_a).

[0244] Furthermore, choosing a poor initial value for r_ind_c, TOD_c, or both can increase the convergence time.

[0245] Therefore, considering practical efficiency (which depends on real-world applications and their constraints), the multi-scale and multi-sample techniques in this chapter may be very useful.

[0246] 5.2 Examples and Implementations

[0247] Other time scales besides dividing the time range from TOD_c to infinity by 2 are possible. For example, Figure 30A -B describes an instance where the time range after TOD_c is divided into four.

[0248] Figure 30A Corresponding to in the following sense Figure 27A : Figure 30A It also describes a pattern called Pattern One (or First Pattern), where TOD_c > TOD_a. Similarly, Figure 30B Corresponding to in the following sense Figure 27B : Figure 30B It is also described as a pattern called Pattern Two (or Second Pattern), where TOD_a > TOD_c.

[0249] Along the probability axis (TBE_P), identify two additional split points ( Figure 27A -B extra)(in Figure 30A (in each of -B):

[0250] • The midpoint of the range from th_c / 2 to th_c: (3 / 4)th_c, when projected onto the time axis, positions this upper half of the MEA. This value of the MEA can be divided into MEA_H2 because it divides the time range of H2. Figure 30A In the -B instance, (3 / 4)th_c = 0.555 and MEA_H2 = 0.20 seconds.

[0251] The midpoint of the range from 0 to th_c / 2: (1 / 4)th_c, when projected onto the time axis, locates this lower half of the MEA. This value of the MEA can be divided into MEA_H1 because it divides the time range of H1. Figure 30A In the -B instance, (1 / 4)th_c = 0.185 and MEA_H2 = 0.565 seconds.

[0252] The essentially same logic described above for adjusting th_c toward th_a and r_ind_c toward r_ind_a using H2 and H1 can be applied to one or both of the following two pairs: Q4 and Q3 (also called Q4 / Q3), or Q2 and Q1 (also called Q2 / Q1). As indicated in the parentheses of H1 and H2, in Figure 30A The top of each of the -B values ​​indicates that the independent CS spike pairs within H2 result in an increase (hence the "+" sign). This increase applies to both rate and TOD_c. Conversely, the independent CS spike pairs within H1 result in a decrease (hence the "-" sign). This decrease applies to both rate and TOD_c.

[0253] As indicated in the parentheses of Q4 and Q3, in Figure 30A The top of each of the terms in -B, independent CS spike pairs within Q4 result in an increase (hence the "+"), while independent CS spike pairs within Q3 result in a decrease (hence the "-"). The same annotation applies to the parentheses of Q2 and Q1, in... Figure 30A -The top of each of -B: Independent CS spike pairs within Q2 result in an increase, while independent CS spike pairs within Q1 result in a decrease.

[0254] If both Q4 / Q3 and Q2 / Q1 are used simultaneously, this can be considered an example of a multi-sample method. This is because the subsequent TOD_c time range is actually sampled at two different locations.

[0255] If both Q4 / Q3 and Q2 / Q1 are used simultaneously, and H2 / H1 is also used concurrently, then this can be called an instance of a multi-scale method (and it is still multi-sample for the reasons just explained above). This is because the post-TOD_c time range is actually used on two different time scales: a quarter-scale and a second half-scale. Interestingly, note that this particular multi-scale and multi-sample method simplifies to using only Q4 and Q1. This can be verified by examining... Figure 30A -The plus or minus sign in the parentheses at the top of each of the terms in B makes it easy to understand:

[0256] • When H2 and Q3 overlap, H2 and Q3 cancel each other out, leaving only Q4.

[0257] • When H1 and Q2 overlap, H1 and Q2 cancel each other out, leaving only Q1.

[0258] 5.3 Example Electric Implementation Plan

[0259] Figure 31 Example circuit-level implementations of the multi-scale (quarter and half) and multi-sample (Q4 / Q3 and Q2 / Q1) methods discussed above are presented. Figure 31 The circuit follows the same rules as described above. Figure 26 and 29 The hardware partitioning discussed is similar. Figure 29 and 31 The correspondence between them is as follows:

[0260] · Figure 29 External input interfaces 2900 and 2901 in Figure 31 The middle remains unchanged.

[0261] · Figure 29 State machine 2910 in Figure 31 It remains unchanged (although it remains unchanged in) Figure 31 (Only outlines are shown in the image).

[0262] · Figure 29 The exponential decay unit 2920 in Figure 31 The middle remains unchanged.

[0263] · Figure 29 The variable voltage source 2930 in Figure 31 The middle remains unchanged.

[0264] · Figure 29 The operational amplifier comparators 2940 and 2941 in Figure 31 The remainder remains unchanged. To test (3 / 4)th_c and (1 / 4)th_c, Figure 31 Operational amplifier comparators 3120 and 3121 were added respectively.

[0265] · Figure 29 The "AND" gate 2950-2952 in Figure 31 The middle remains unchanged. Figure 31 New AND gates 3130-3133 have been added for decoding Q1-Q4 respectively.

[0266] OR gates 3140 and 3141 implement the multi-scale and multi-sample method discussed above. 3140 decodes for an increase in (r_ind_c, TOD_c, or both), while 3141 decodes for a decrease in (r_ind_c, TOD_c, or both). The fact that this multi-scale and multi-sample method simplifies to only Q4 indicating an increase and Q1 indicating a decrease is also described.

[0267] 5.4 Pseudocode Implementation Plan

[0268] Figure 32A -C describes an alternative to the hardware-centric approach described in Chapter 5.3 for multi-scale, multi-sample methods used to learn TOD units.

[0269] Figure 32A The -C option presents a pseudo-code program called Learn_TOD_MSMS. This pseudo-code is based on the Python programming language.

[0270] Figure 32A Each execution instance of the -C pseudocode corresponds to Figure 20 Learn the TOD unit 2021 or 2022.

[0271] The learning TOD unit can also be implemented through any suitable combination of software and hardware, as determined by the constraints of the specific application environment. The trade-offs are similar to those discussed in Section 4 of the previous article (“Pseudocode Implementation”) concerning the pseudocode program Learn_TOD_H2H1.

[0272] Figure 28A-B presents Learn_TOD_H2H1. All pseudocode for Learn_TOD_H2H1 is contained within Learn_TOD_MSMS. The only functional difference between Learn_TOD_H2H1 and Learn_TOD_MSMS is as follows: Figure 28B The code in lines 30-43 has been expanded. Figure 28B The same functionality in lines 30-43 is retained, but additional functionality has been added. Therefore, Figure 28B Rows 30-43 correspond to the following portion of Figure 32: Figure 32B Line 26 to Figure 32C Line 20. The following is... Figure 28A -B and Figure 32A A more detailed comparison of -C.

[0273] Figure 28B Lines 30-35 address the case where TBE is within H2. The logic for the second peak in the CS peak pair being within this region is to increase both the lower bound of H2 (i.e., see line 32) and the rate r_ind_c (i.e., see line 34). Figure 32B Implementation of Sections 26-32 Figure 28B The same logic applies to lines 30-35.

[0274] Similarly, Figure 28B Lines 37-43 address the case where TBE is within H1. The logic for the second peak in the CS peak pair being within this region is to decrease both the lower bound of H2 (i.e., see line 39) and the rate r_ind_c (i.e., see line 42). Figure 32C Implementation of Sections 1-8 Figure 28B The same logic applies to lines 37-43.

[0275] However, in order to implement the additional quarter scale, Figure 32B Lines 34-44 add the ability to handle a quarter of Q4 / Q3 when the test shows TBE is within H2. Line 36 tests whether the second spike in the CS spike pair is within Q4 or Q3. If the spike is within Q4, then perform the same procedure as described above for H2. Figure 32B The same increment logic as lines 28-30 ( Figure 32B (Lines 38-39). Similarly, if the spike is within Q3, then perform the same action as described above for H1 ( Figure 32C The same decrease logic as lines 3-6) Figure 32B of lines 42-43).

[0276] To handle a quarter of Q2 / Q1, when the TBE is tested and found to be within H1, add... Figure 32CLines 10-20. Line 12 tests whether the second spike in the CS spike pair is within Q2 or Q1. If the spike is within Q2, then perform the same procedure as described above for H2. Figure 32B The same increment logic as lines 28-30 ( Figure 32C (Lines 14-15). Similarly, if the spike is within Q1, then perform the same action as described above for H1 ( Figure 32C The same decrease logic as lines 3-6) Figure 32C of lines 18-19).

[0277] As discussed above in Chapter 5.3 (Example Implementation Scheme), it is interesting to note that all multi-scale, multi-sample logic ( Figure 32B Line 23 to Figure 32C The combination of line 20) leads to simplification, where only the following logic is needed:

[0278] • If TBE is within Q4 (via Figure 32B If tests 26 and 36 are performed, then the increase logic described above for Q4 will be executed. Figure 32B (Lines 38-39)

[0279] • If TBE is within Q1 (via Figure 32C If we perform tests 1 and 16, then the reduction logic described above for Q1 will be executed. Figure 32C (Lines 18-19).

[0280] 6 Other variations

[0281] Section 5.2 (“Example Implementation”) discusses using Q4 / Q3 and Q2 / Q1 as instance multi-sample methods (on a one-quarter scale of the range). While Section 5.2 discusses using both Q4 / Q3 and Q2 / Q1, it is worth noting that this is unnecessary on an individual peak (or “peak-by-peak”) basis. For example, for an individual peak n, it may be the case that only Q4 / Q3 is effective. For a peak that occurs i times after peak n (i.e., for a later peak n+i), it may be the case that only Q2 / Q1 is effective.

[0282] Furthermore, for the same number of peaks, Q4 / Q3 and Q2 / Q1 need not each be valid individually. For example, as part of the sampling process, it might be that Q4 / Q3 is valid for a set of x peaks, and Q2 / Q1 is valid for a set of y peaks, where the number of members in the x set is not equal to the number of members in the y set (symbolically, |x|≠|y|).

[0283] for Figure 30A -B, each scale (half or a quarter of the range) is displayed with the following two properties:

[0284] 1. The region occupies the entire range of the TBE_P axis, from 0 to th_c.

[0285] 2. The regions are placed at regular intervals so that an integer number of regions can occupy the entire range of the TBE_P axis, from 0 to th_c.

[0286] Neither of these two properties is necessary.

[0287] For example, regarding the first property listed above, the case might be that only Q4 / Q3 is used (or "covered") on a scale of one-quarter of the range. In the context of the previous discussion where Q4 / Q3 is described as valid for a set of x peaks and Q2 / Q1 is described as valid for a set of y peaks, this can be considered equivalent to the case where y = {} and x ≠ {} (i.e., only Q4 / Q3 is valid, and it is valid for its set of x peaks).

[0288] The drawback of covering only a portion of the TBE_P axis with a specific scale (also known as "partial coverage") is the potential for non-convergence (at least without additional gradient detection on other scales) of values ​​for (TOD_a, r_ind_a, or both). Furthermore, this is particularly problematic for designs that learn TOD units (e.g.,...). Figure 20 Each of the added scopes (2021 and 2022) introduces additional complexity and may also add complexity to the implementation (or physical implementation) scheme.

[0289] The advantages of partial covering include: within its operating range, it can be used to improve convergence speed, increase near-convergence stability, or both. Outside its operating range, partial covering is unlikely to significantly slow down convergence and will not reduce convergence stability.

[0290] As an example of the second property listed above, each of Q1-Q4 is described as (in Figure 30A -B covers one-quarter of the TBE_P axis, from 0 to th_c. This is not necessary for partial coverage. If Q4 / Q3 are used for partial coverage, then they can each be placed relative to the TBE_P axis as follows (for example):

[0291] Q4: Instead of positioning it in the range of (0.75)th_c to (1.00)th_c, position it in the range of (0.59)th_c to (0.84)th_c.

[0292] Q3: Instead of positioning it in the range of (0.50)th_c to (0.75)th_c, position it in the range of (0.34)th_c to (0.59)th_c.

[0293] Please note that the use of a quarter-scale in the example is arbitrary. Without loss of generality, the same technique can be applied to any other fraction. Furthermore, using 0.59 as the dividing point between Q4 and Q3 is also arbitrary. Without loss of generality, the same technique can be applied to locate other dividing points between quarters or other fractions of the range.

[0294] As part of the search for TOD_a and r_ind_a, the regions used do not necessarily need to be contiguous. For example, refer to... Figure 30A -B, It is worth noting that a fully functional implementation can be achieved using only Q4 and Q1. (Section 5.2 states that when using the following multi-scale and multi-sample methods, using only Q4 and Q1 results in simplified net results: H2 / H1, and Q4 / Q3 and Q2 / Q1.) A potential disadvantage of not using Q3 or Q2 is that their time-domain spikes do not contribute to convergence toward TOD_a and r_ind_a. A potential advantage of not using Q3 or Q2 is greater stability during this convergence process.

[0295] Furthermore, as part of the search for TOD_a and r_ind_a, it is unnecessary to utilize an even number of regions. For example, refer to... Figure 30A -B, a fully functional implementation can be achieved using the following three regions: Q4, Q3, and H1. A key requirement is probability symmetry. For this example, the TBE_P axis portion of each of Q4, Q3, and H1 is represented as follows: P(Q4), P(Q3), and P(H1). A key requirement is that the net probability of the increasing (or "+") region is equal to the net probability of the decreasing (or "-") region. (As discussed above in Section 5.2 "Example Implementation," the increasing region immediately increases r_ind_c and TOD_c after each peak within its range, while the decreasing region immediately decreases r_ind_c and TOD_c after each peak within its range.) In this example, it is known that P(Q4) + P(Q3) = P(H1). Therefore, according to... Figure 30A The only necessary change among the three regions described in -B is to change Q3 into an increasing region like Q4.

[0296] Learning TOD units can produce useful outputs beyond whether a shared event was detected. For example, a hypothesized discrimination threshold (i.e., th_c) can be a useful signal. Figure 29 and 31 The example hardware implementation is reflected in the settings of the variable voltage source (2930) (in analog or digital form). Similarly, the average occurrence rate of independent cross-current spike pairs (independent CSSPs) can also be a useful output. Figure 29 and 31The example hardware implementation is reflected in the setting of the variable resistor (2924).

[0297] 7. Select a glossary

[0298] Adder amplifier: At any given moment, the output is the sum of the voltages present at its inputs.

[0299] Event: Any kind of discrete discontinuity when considering the time-domain behavior of a signal.

[0300] Single-fire: It has an input trigger and one output. Upon receiving the trigger signal, a pulse is immediately generated at its output.

[0301] Region: The range of values ​​along the probability (i.e., TBE_P) or time (i.e., TBE) axis. For example, the probability range from 0 to th_c or the time range from infinity to TOD_c can be divided such that each region occupies one-half or one-quarter of its total range.

[0302] Spike: As used herein, a spike can refer to any event in a signal that, when considered in the time domain, can be viewed as at least one discrete and discontinuous transition between two different levels. As an example, as used herein, a spike can refer to a sharp point that appears in a region of a neural network. As another example, in the field of digital logic, a spike can refer to an abrupt transition (also known as an “edge”) of a signal from a first level to a second level.

[0303] Subtraction amplifier: At any given time, the output is the voltage obtained by subtracting the voltage at the second input from the voltage at the first input.

[0304] TBE: In this article, it is sometimes used to refer to the second peak in a CS peak pair (because TBE is the time distance between the peaks in a pair).

[0305] Dual-fiber: Features input triggering and two outputs. Upon receiving a trigger signal, it immediately generates pulses sequentially at each of its two outputs.

[0306] 8 computing devices

[0307] The inventive methods, procedures, or techniques described herein can be implemented using any suitable computing hardware, electronic hardware, or a combination of both, as is commonly known to those skilled in the art. Suitable computing hardware may include the use of one or more general-purpose computers or processors. Hardware implementation techniques may include the use of various types of integrated circuits, including digital, analog, or a combination of both (e.g., mixed-signal). Digital hardware may include programmable memory (volatile or non-volatile).

[0308] Such hardware (whether in the form of integrated circuits or otherwise) is typically based on the use of transistors (field-effect, bipolar, or both), although it may contain other types of components (including capacitors, resistors, or inductors). A variety of component technologies can be used, including optical, microelectromechanical, magnetic, or any combination thereof.

[0309] Any computing hardware has the properties of consuming energy, requiring a certain amount of time to change its state, and occupying a certain amount of physical space.

[0310] Programmable memory is typically implemented as an integrated circuit and is subject to the same physical limitations described above for computing hardware. Programmable memory is designed to contain means that utilize any kind of physical effect or property to store information, at least in a non-transitory manner and for a duration commensurate with the application. Types of physical effects used to implement such storage include, but are not limited to: maintaining a specific state through feedback signals, charge storage, changes in the optical properties of materials, magnetic changes, or chemical changes (reversible or irreversible).

[0311] Unless otherwise specifically indicated, the terms computing hardware, programmable memory, computer-readable media, system and subsystem do not include a person or mental steps that a person might take.

[0312] For any of the methods, procedures, or techniques described above, insofar as they are implemented to program a computer or other data processing system, they may also be described as a computer program product. A computer program product may be embodied on any suitable computer-readable medium or programmable memory. The types of information described herein (e.g., data and / or instructions) (which are on a computer-readable medium and / or programmable memory) may be stored on a computer-readable code means embodied herein. A computer-readable code means may represent a portion of memory in which defined information units (e.g., bits) may be stored, retrieved, or both.

[0313] 9 Appendix

[0314] This appendix is ​​essentially the full text of the following U.S. patent applications, which are incorporated herein by reference in their entirety:

[0315] The invention is "Method and apparatus for cross-related applications" filed on March 17, 2019, with David Carl Patton as the inventor and application number 62 / 819,590.

[0316] Application No. 62 / 819,590 is also substantially identical to the following PCT international application, which is also incorporated herein by reference in its entirety:

[0317] "Method and Apparatus for Cross-Correlation", filed on March 15, 2020, with inventor David Carl Barton and application number 62 / 819,590.

[0318] 9.1 Introduction

[0319] Cross-correlation is known to have many important applications. Among these applications, it is expected that cross-correlation will continue to be important in the field of spiking neural networks, where relative spike timing can be critical for proper operation.

[0320] Figure 1 Depict an example application scenario in the field of spiking neural networks. The input on the left is three spike trains: S1, S2, and S3. Each spike train is expected to contain significant random (or stochastic) content.

[0321] Regarding the random content, the temporal size of the inter-spike gap (or ISG) follows a random distribution (usually Poisson), and each ISG_i is in the range:

[0322] 0 seconds < i < ∞ seconds

[0323] For the entire time range of i, we refer to the average spike rate of the spike train as r ALL (since a rate of all spikes can occur).

[0324] This content is random both with respect to the stream in which it occurs and relative to other streams. However, non-random events that manifest themselves across two or more of the input streams are also expected to occur. (In the following explanations, we will generally refer to non-random events simply as "events".)

[0325] Each of the streams S1, S2, and S3 is coupled to the F.O.R. inputs: 0110, 0112, and 0114 of a cross-correlation unit (or CCU). Each CCU has an output labeled "FOR d ". As can be seen, each FOR d output is connected to the input of a "soma" 0121. At its most basic functional level, the soma can be designed to act as a coincidence detector that generates an output spike whenever spikes occur simultaneously at each of its inputs.

[0326] In the following discussion, three input streams are chosen for ease of explanation. It will be readily understood that the system (such as Figure 1 's system) can be applied to any large number of inputs without any change in the operating principle. At least two input streams are required. Generally speaking, for example Figure 1 's system can be regarded as a biologically inspired model of a neuron. Although biologically inspired, from an engineering design (and non-biological) perspective, Figure 1This can be understood as representing a multi-stream cross correlator or "MCC".

[0327] When an event occurs, in two or more input streams of the MCC, its performance in each input stream is expected to have a fixed temporal relationship with its performance in the other spike streams. While the multi-stream performance of the event is expected to have a fixed temporal relationship with each other, it is also expected that such performance will not occur simultaneously.

[0328] It is expected that any other spike (i.e., any non-event spike) has an arbitrary relationship with respect to all other non-event spikes, both within the input stream in which the spike occurs and with respect to other input streams. We also refer to any such non-event spike as an "arbitrary spike".

[0329] The task of each of CCUs 0110, 0112, and 0114 is to determine a delay or time offset such that as many event manifestations as possible across multiple streams appear simultaneously at the output of the CCU (and therefore simultaneously at the input of the Soma 0121).

[0330] More specifically, it can be observed that each CCU in Figure 01 has two inputs:

[0331] FOR, and

[0332] ·other.

[0333] "FOR" (which may be written as "FOR") means "frame of reference". (Unless the context indicates otherwise, any use of the term "FOR" or "FOR" in this document refers to "frame of reference" and not to the preposition "for".) The spiked stream of the FOR input presented to the CCU appears in the CCU's FOR after a certain modification. d At the output. The CCU may modify its FOR by inserting a delay relative to the spikes appearing at its FOR input. d Output stream. The “other” inputs of each CCU are intended to be a combination of spikes appearing at the FORd outputs of other CCUs (i.e., other CCUs connected to the same SMART).

[0334] As can be seen, the other inputs of each CCU are determined as follows. First, the output spikes of all CCUs are concatenated together through an OR gate 0120 to form a single combined spike stream. The output of this OR gate is marked "ANY" because a spike is expected to appear at its output, provided it appears at the FOR gate of any CCU. d That's all you need to do at the output location.

[0335] Each of CCUs 0110, 0112, and 0114 has AND gates 0111, 0113, and 0115, respectively. As can be seen, each AND gate filters out (i.e., removes) the spike stream received by the other inputs of its CCU. Specifically, it removes any spikes caused by the CCUs of the AND gates.

[0336] 9.2 Cross-related units

[0337] 9.2.1 Overview

[0338] Compared to conventional correlation and cross-correlation techniques, the MCC of this invention relies on the presence of a large number (e.g., hundreds or thousands) of arbitrary spikes.

[0339] MCC operates by making each CCU operate substantially independently of the other CCUs. An exception to independent operation is the fact that each CCU receives (at its other inputs) FOR signals from other CCUs. d The union of outputs (more precisely, for example, the union of the spike streams presented to other CCUs for the input).

[0340] Figure 2 It is aimed at Figure 1 Functional block diagram of the internal structure of each CCU instance.

[0341] As can be seen, the CCU consists of two main units:

[0342] • Generates a delay (block 0225), and

[0343] • Learning delay (block 0226).

[0344] It generates a delayed input spike stream (at its FOR input) and at its output (called FOR). d The delayed version of this input stream is generated at (). The delayed FOR input is coupled to the CCU's FOR input (labeled 0211), and the delayed FOR... d FOR of output coupled to CCU d Output (marked as 0212).

[0345] The learning delay accepts other spike streams from the CCU (other input 0210 from the CCU), and also accepts (in the learning delay FOR) d The input field generates a delay FOR. d Output. Learning delayed use exists in its FOR. d Each pair of spikes at the input is used as a reference frame to analyze any spikes that appear at other inputs during the learning delay.

[0346] If the resulting delay is incorporated into sufficient memory, then it is reproducible (in its FOR). d The output is the same spike stream as the spike stream at its FOR input, except for the possibility of delay. We can call this a lossless version that produces delay.

[0347] Depending on the application, the memory that generates delay can be implemented using analog or digital devices. For digital implementations, delay generation can include, for example, a FIFO (First-In-First-Out) queue or buffer implemented using semiconductor random access memory (RAM). For analog implementations, delay generation can include any suitable signal or waveguide, such as a cable or free-space wave propagation cavity.

[0348] However, in general, lossless versions that produce latency may require an unlimited (or unrestricted) amount of memory.

[0349] Another important aspect of the invention is to utilize the random nature of the spike stream of the FOR input presented to the CCU to generate FOR at the output that produces the delay. d The lossy version. In fact, just one spike (once) of memory can be enough to reduce latency in the CCU's FOR. d A useful correlated spike stream is generated at the output. When using storage with only one spike, the generated delay can be considered as a kind of "timer". The timer is started when the spike appears at its FOR input. At the end of the delay period, the timer is the FOR that generated the delay. d The output produces a spike. The use of a single-spiking memory is discussed below in Section 9.2.3 (“Generating Delay”).

[0350] 9.2.2 Learning Delay

[0351] 9.2.2.1 Functional Description

[0352] As described above, delayed use of learning exists in its FOR d Each pair of spikes at the input is used as a reference frame to analyze any spikes that appear at other inputs during the learning delay. Figure 3 Describe this type of instance.

[0353] As can be seen, Figure 3 Contains two axes:

[0354] • Horizontal time axis, where: 0.00 seconds ≤ t ≤ 0.60 seconds.

[0355] • The vertical axis used to assign weights to each other spike (explained further below), where: 0.00 ≤ weight ≤ 1.00.

[0356] Let's learn about delayed FOR d The input calls a consecutive pair of spikes, which serve as a framework for evaluating other spikes n and n+1. A vertical line (besides representing the weight axis) is drawn at time t = 0.00 to depict spike n (this spike is also labeled 0310). Conversely, spike n+1 (this spike is also labeled 0311) is drawn at t = 0.60. The magnitudes of spikes n and n+1 along the vertical axis are unrelated and are selected solely for graphical purposes.

[0357] The weight axis is related to curves 0320 and 0321. As can be seen, 0320 is of the form e. -rt The exponential decay curve is given by r, where r is the rate, t is time, and r (for example purposes) equals 3. Conversely, 0321 is of the form e -r(m-t) The curves are exponentially increasing, where r and t are the same as in 0320, and m (the "maximum" time) is equal to 0.60 seconds. For reasons explained below, curves 0320 and 0321 are also referred to as "Post" and "Pre," respectively.

[0358] Appeared in FOR d Each other peak between peak n and n+1 is assigned both Post and Pre values. Peaks whose Post value is greater than their Pre value are characterized as "later" (or subsequent) peak n being stronger than "preceding" (or preceding) peak n+1. Conversely, peaks whose Pre value is greater than their Post value are characterized as "preceding" (or preceding) peak n+1 being stronger than "later" (or subsequent) peak n.

[0359] Figure 3 Describe two instances of other spikes with the following values:

[0360] Other peaks 1:

[0361] ○t = 0.065 seconds.

[0362] ○Post value = 0.723

[0363] ○Pre value = 0.05

[0364] Other peaks 2:

[0365] ○t = 0.44 seconds.

[0366] ○Post value = 0.112

[0367] ○Pre value = 0.446

[0368] As can be seen, each other spike is given two weights, depending on where it intersects with the Post and Pre weighted curves.

[0369] Crossing can occur in a pair of FOR d Multiple other peaks between peak n and n+1 can be identified and corrected for a net trend that tends towards "back" or "forward" as follows:

[0370] • Sum all Post values ​​to obtain the sum (which we also call "postAcc"), and

[0371] • Sum all the Pre values ​​to get the sum (we also call it "preAcc").

[0372] If postAcc > preAcc, then:

[0373] Other spike flows are generally considered to appear in FOR d Behind the peak. This also means FOR d The flow generally occurs earlier.

[0374] ○ Learning delay (e.g., Figure 2 The learning delay block (0226) may attempt to correct the advance by issuing a command (e.g., a pulse) at its "more d" output.

[0375] ○ In response to the "more d" command, a delay is generated (e.g., see Generation Delay Block 0225) to make its FOR input and FOR d The delay between outputs increases by a specific increment.

[0376] If preAcc > postAcc, then:

[0377] Other spike flows are generally considered to appear in FOR d In front of the peak. This also means FOR d The flow is generally lagging.

[0378] ○ The learning delay may attempt to correct the hysteresis by issuing a command (e.g., a pulse) at its "less d" output.

[0379] ○ In response, a delay can be generated to make its FOR input and FOR d The delay between outputs reduces a specific increment.

[0380] The increment by which the learning latency is changed (in response to a "more d" or "less d" command) can be chosen based on the specific application and its speed and accuracy requirements. Generally, smaller increments (also known as slower learning rates) increase the time it takes for the CCU to discover the latency value necessary to achieve optimal synchronization of its events with its other streams. However, smaller increments have the advantage of producing a more accurate determination of the necessary latency value.

[0381] Although exponential curves that are both decreasing and increasing have been shown, various functions are suitable for Post and Pre weighting purposes. The main criteria for a suitable function include:

[0382] • The Pre function is the symmetrical opposite of the Post function.

[0383] • The Post and Pre functions that reach their maximum values ​​at peak times n and n+1, respectively.

[0384] • The Post and Pre functions, which monotonically decrease from their maximum values.

[0385] 9.2.2.2 Sequential Operation and Pseudo-coding Implementation Scheme

[0386] The operation explained in the previous subsections regarding learning delay is discussed in a manner consistent with the following spike obtained at a given time:

[0387] ·FOR d The input spikes n and n+1, and

[0388] • In n and n+1, F.OR d The time interval between spikes refers to any spikes present at other inputs during the learning delay.

[0389] During actual operation, the CCU (and its associated MCC) are expected to operate on a peak-by-peak basis. For example, based on the FOR that exists at the learning delay, which we can call peak n. d Each spike at the input can be expected to delay the execution of two main operations:

[0390] If an n-1 peak exists, the aim is to complete the cross-correlation analysis starting with the peak n-1. In other words, the cross-correlation analysis is performed with the peak n-1 and n as reference frames.

[0391] • Immediately after the arrival of peak n+1, a new cross-correlation analysis, which will be completed in the future, will commence. In other words, a new cross-correlation analysis will begin, in which peaks n and n+1 will be used as reference frames.

[0392] Depending on the specific application, learning delays can be implemented as computer programs, as electrical hardware, or as a hybrid of both methods.

[0393] Figure 4This document describes an example pseudocode implementation of a learning delay based on the Python programming language. Bold text closely corresponds to Python syntax and semantics. Comments are inserted according to Python syntax. Line numbers have been added to the left to aid explanation. The main deviation from Python syntax and semantics is the right-hand side of the assignment operator, on lines 5 through 17. Furthermore, the document informally handles the passing and passing of parameters or other data into and out of the program.

[0394] Figure 4 The program is called "Learn_Delay_PC", where the "PC" suffix indicates pseudocode. Line 1.

[0395] Whenever a spike occurs at FOR d Learn_Delay_PC can be called at other input points.

[0396] Several important values ​​and variables are assigned on lines 5 to 17, but these important values ​​and variables will be presented on lines 22 to 44 as part of the pseudocode for discussing the use of these variables.

[0397] Line 22 updates the Pre accumulator "preAcc" by causing its contents to undergo exponential decay relative to the amount of time (i.e., T-TLO), because the last other spike causes a call to Learn_Delay_PC (where in Figure 4 T and TLO are defined at lines 8-9. As will be explained further below, this exponential decay of preAcc is combined with the addition of a unit value to preAcc whenever another spike occurs.

[0398] At each additional peak, add a unit value to preAcc, causing preAcc to undergo exponential decay (until the next FOR). d Peak time) is mathematically equivalent to the above regarding Figure 3 The preAcc accumulation method discussed: immediately after each other peak appears, e... -r(m-t) The value is added to preAcc (where m is the maximum value of t), and preAcc has no decay.

[0399] Causing preAcc to undergo exponential decay might seem like an unnecessary indirect method of accumulating Pre values. However, as will be discussed in the next subsection, with e -rt Comparison, e -r(m-t) It is a relatively complex function implemented with the aid of electronic hardware.

[0400] Following the update to preAcc, execution of the current spike is of type FOR. d Or some other test. Line 25. FOR dSpikes are considered to "belong" to the currently executing learning delay unit because they originate from production delay units belonging to the same CCU. Therefore, the IS_MINE variable falsely indicates that other spikes have been received, causing execution to proceed through lines 26 to 33. Otherwise, the current spike is of type FOR. d And execute lines 35 to 45.

[0401] Assuming IS_MINE is false, perform the following steps:

[0402] • To indicate that the current spike is of another type, add a unit value to preAcc. Line 26.

[0403] The value added to postAcc is only from the last FOR. d Exponential decay in unit values ​​since the peak. Line 30.

[0404] • Update the time of the last other spike to prepare for the next call to Learn_Delay_PC. Line 32.

[0405] Assuming IS_MINE is true, perform the following steps:

[0406] • As a completion of the previous FOR d The current cross-correlation analysis, which begins with the spike, first performs a test to determine if any other spikes have appeared. (Line 35)

[0407] • Assuming at least one other spike has occurred, compare the value of preAcc with the value of postAcc. (Line 38)

[0408] If preAcc > postAcc, then overall, FOR d Peaks are considered to be lagging relative to other peaks. The delay from which the delay is generated is reduced, represented by the variable D. The amount by which the learning rate is reduced is indicated by "-D_LR" in line 38.

[0409] ○ If postAcc > preAcc, then overall, the FORd spike is considered to be ahead of other spikes. Increase the delay from which the delay is generated, represented by the variable D. The amount of increase controlling the learning rate is represented by "D_LR" in line 38.

[0410] • Perform an actionable check to ensure that D remains within acceptable limits. Line 40.

[0411] • As part of initiating a new cross-correlation analysis, perform the following steps:

[0412] ○ Reset preAcc and postAcc to zero. Line 42.

[0413] ○The last FOR d The peak time is updated to the current time. Line 44.

[0414] 9.2.2.3 Electricity Implementation Plan

[0415] Figures 5 to 7 Describe an example implementation of learning delay.

[0416] Figure 5 Describe the top-level control and interface of the learning delay module. Figure 6 The focus is on circuit systems related to the accumulation of postAcc values, and Figure 7 The focus is on the circuit system related to the accumulation of preAcc.

[0417] Figure 5 Outline 0510 indicates the external interface for learning delay, where each connection corresponds to the previously combined... Figure 2 The input or output of the learning delay function block 0221 discussed.

[0418] Outline 0520 indicates the learning delay and Figure 6 postAcc circuit system and Figure 7 The internal interface of the preAcc circuit system.

[0419] External interface 0510 will be discussed below.

[0420] Presented to FOR d Each spike in the input triggers "DualShot" 0530. First, DualShot's out1 completes the current reference frame by causing a readout of comparator amplifier 0540. Second, out2 resets the postAcc and preAcc circuitry, allowing accumulation to begin across the next reference frame.

[0421] Out1 triggers a read of comparator 0540 by enabling AND gates 0541 and 0542. If the output of comparator 0540 is logic 0 when the AND gates are enabled, then AND gate 0542 presents a trigger signal to single-electrode 0532. Single-electrode 0532, when triggered, generates a pulse at the "less d" output (of interface 0510). Conversely, if the output of comparator 0540 is logic 1, then AND gate 0541 presents a trigger signal to single-electrode 0531. Single-electrode 0531, when triggered, generates a pulse at the "more d" output (of interface 0510).

[0422] Comparator 0540 compares two signals: the signal representing preAcc (referred to as "preAcc"), and the signal representing postAcc (referred to as "postAcc"). From Figure 6The circuit system generates the postAcc signal, and at the same time, by Figure 7 The circuit system accumulates the preAcc signal. Each of the preAcc and postAcc signals is analog, having a voltage level representing its accumulated value. If the preAcc signal has a higher voltage than postAcc, then comparator 0540 outputs a signal representing logic 0. As discussed above, logic 0 (when read from out1 of dual-output 0530) causes a pulse from the "lesser d" output. Conversely, if postAcc > preAcc, then comparator 0540 outputs logic 1. As discussed above, logic 1 (when read from out1 of dual-output 0530) causes a pulse from the "more d" output.

[0423] The last connection to be discussed regarding external interface 0510 is other inputs. (FOR) d With the same input, spikes elsewhere also trigger a double trigger. In this case, it's a double trigger 0533. As will be discussed further below, the out1 of the double trigger 0533 causes the current voltage level of each of the postAcc and preAcc accumulators to be sampled (and other actions). Next, out2 causes the postAcc and preAcc accumulators to be charged to the new voltage level respectively.

[0424] about Figure 6 Capacitor 0650 maintains the voltage of the postAcc signal (or node). (Regarding the above...) Figure 3 The Post n function 0320 discussed is determined by the combination of capacitor 0640 and resistor 0641. Figure 6 In this context, the Post n function can be obtained at the decay variable node.

[0425] As discussed above, as part of initiating a new reference frame, the dual-electrode 0530 (at its out2 output) asserts a "Reset (FOR)" signal. Regarding Figure 6 As can be seen, the reset (FOR) signal causes the following capacitors to reset:

[0426] • The accumulated value of postAcc is reset to zero by switch 0660, which couples the postAcc node to ground.

[0427] • Switches S1 and S2 of switching unit 0643 reset the Post n function 0320 to a new exponential decay period. Specifically, during the duration of the reset (FOR) pulse:

[0428] ○S1 couples capacitor 0640 to a unit voltage source 0642, and

[0429] ○S2 ensures that the decay variable node maintains the correct initial value for restarting exponential decay when capacitor 0640 is recharged.

[0430] • At the appropriate time, capacitor 0632 is used to hold a sample of the voltage at the decaying variable node. It is reset by switch 0662, which couples capacitor 0632 to ground.

[0431] • At the appropriate time, capacitor 0622 is used to hold a sample of the voltage at the postAcc node. It is reset by switch 0661, which couples capacitor 0622 to ground.

[0432] Once the reset (FOR) signal ends, the combination of capacitor 0640 and resistor 0641 begins its exponential decay, where the Post n function can be obtained at the decay variable node.

[0433] If the postAcc node is reset (via FOR) d If another spike appears after the first spike, then a double shot (0533) is triggered. (Regarding...) Figure 6 Therefore, the assertion of the "sampling (other)" signal causes the following:

[0434] • The current voltage is sampled at the decay variable node by closing switch 0631.

[0435] • Sample the current voltage at the postAcc node by closing switch 0621.

[0436] Following the assertion of the "Sampling (Other)" signal, the following occurs:

[0437] • Switch 0631 is open, and the sampled voltage of the decay variable node is held by capacitor 0632.

[0438] • Switch 0621 is open, and the sampled voltage of the postAcc node is maintained by capacitor 0622.

[0439] • The voltage held by capacitors 0632 and 0622 is summed by adder amplifier 0610.

[0440] Next, both transmitters use 0533 to assert the "Charging Acc (Other)" signal, which closes the connection. Figure 6 Switch 0611 is activated. This causes comparator 0612 to compare the voltage at the postAcc node with the output of adder amplifier 0611. The voltage from the adder amplifier will be greater than the voltage at the postAcc node by the amount sampled at the decay variable node. Therefore, comparator 0612 will cause switch 0613 to close and remain closed until the postAcc node has been charged to a voltage substantially equal to the output voltage of the adder amplifier.

[0441] As you may understand, the following is the net effect of the sequential assertions for the "Sampling (Other)" and "Charging Acc (Other)" signals. At each other spike, the voltage increase at the postAcc node is equal to the amount by which the voltage at the decay variable node is at that time.

[0442] about Figure 7 Capacitor 0720 maintains the voltage of the preAcc signal (or node). However, as mentioned above... Figure 4 As discussed in the Learn_Delay_PC pseudocode, the preAcc node is designed to decay due to its combination with resistor 0721. As discussed above, decaying the preAcc node and adding a unit voltage for each other spike is mathematically equivalent to determining ( Figure 3 The Pre n+1 function 0321 is used to add its value to the non-decaying Pre accumulator. Figure 7 From a circuit implementation perspective, the attenuation preAcc node method is relatively simple to understand.

[0443] As discussed above, as part of initiating a new reference frame, the dual-electrode 0530 (at its out2 output) asserts a "Reset (FOR)" signal. Regarding Figure 7 As can be seen, the reset (FOR) signal causes the following capacitors to reset:

[0444] • The accumulated value of preAcc is reset to zero by switch 0741, which couples the preAcc node to ground.

[0445] • At the appropriate time, capacitor 0732 is used to hold a sample of the voltage at the postAcc node. It is reset by switch 0740, which couples capacitor 0732 to ground.

[0446] If the reset is performed at the preAcc node (via FOR) d If another spike appears after the first spike, then a double shot (0533) is triggered. (Regarding...) Figure 7 As can be seen, the assertion of the "Sampling (Other)" signal causes the current voltage to be sampled at the preAcc node by closing switch 0731.

[0447] Following the assertion of the "Sampling (Other)" signal, the following occurs:

[0448] • Switch 0731 is open, and the sampled voltage of the preAcc node is maintained by capacitor 0732.

[0449] • The voltage held by capacitor 0732 is summed with the unit voltage from voltage source 0714 by adder amplifier 0710.

[0450] Next, both transmitters use 0533 to assert the "Charging Acc (Other)" signal, which closes the connection. Figure 7 Switch 0711. This causes comparator 0712 to compare the voltage at the preAcc node with the output of adder amplifier 0710. The voltage from the adder amplifier will be greater than the voltage at the preAcc node by the amount provided by the unit voltage source 0714. Therefore, comparator 0712 will cause 0713 to close and remain closed until the preAcc node has been charged to a voltage substantially equal to the output voltage of the adder amplifier.

[0451] As you may understand, the following is the net effect of the sequential assertions for the "Sampling (Other)" and "Charging Acc (Other)" signals. At each other spike, the voltage of the preAcc node increases by an amount equal to the unit voltage of voltage source 0714. After this increase, the preAcc node will continue its exponential decay until any of the following occurs:

[0452] • When FOR appears d In the case of a spike, the current reference frame ends.

[0453] • Another peak appears.

[0454] 9.2.3 Introduces Delayed - Lossy Version

[0455] 9.2.3.1 Conflict Resolution

[0456] As discussed above, in Section 9.2.1 (“Introduction”), another important aspect of the invention is to utilize the random nature of the spike stream of FOR inputs presented to each CCU to generate FOR at the output that produces the delay. d The option for a lossy version.

[0457] A single spike (once) of memory introduces latency (e.g., through...). Figure 2 Function block 0225) is sufficient in CCU's FOR d A useful correlated spike stream is generated at the output. In this case, the generation delay can be considered as a "timer". The timer is started when the spike appears at the FOR input of the generation delay. At the end of the delay period, the timer is the FOR of the generation delay. d The output produces a spike. The use of single-spik memory will be discussed below.

[0458] Since the lossy version that produces latency requires far less memory (only one spike) than the lossless version (whose memory requirement is potentially infinite), we refer to the lossy version as "memoryless".

[0459] A key problem when implementing a memoryless approach is what we call the "conflict resolution" problem. The conflict resolution problem can arise whenever the delay is greater than 0 seconds. Due to the random nature of the spike stream input to each CCU, whenever a delay occurs due to the FOR spike x while timing the delay period d, the next FOR spike x+1 can always arrive. Then there are two choices:

[0460] • Ignore the spike x+1 and continue timing the spike x until its delay period d is completed. We call this the "keep oldest" choice.

[0461] • Restart the timer so that the delay period d starts with a spike x+1. We call this the "keep up-to-date" option.

[0462] Either of these strategies, if applied consistently, could potentially be applied an unlimited number of times sequentially. For example:

[0463] • Keep the oldest: Although the delay d of the spike x is timed, there may be an infinite number of subsequent FORs. d The peak may be reached. All of this will be ignored.

[0464] • Keep up-to-date: If the delay d of peak x is restarted due to peak x+1, then peak x+2 may restart the time period of peak x+1, and peak x+3 may further restart the time period of peak x+2. The restarting of the delay period can continue to occur an infinite number of times.

[0465] Either of these two options, when applied exclusively as a conflict resolution strategy, has a FOR that introduces time skew into the learning delay. d Problems in comparing with other spike flows. Specifically:

[0466] • Keep the oldest: has the function of FOR d The effect is that the spike appears earlier than other spikes. The result is that the resulting delay is too large. This effect can be understood from the fact that the strategy of keeping the oldest causes later spikes (i.e., the spike after spike x) to decrease.

[0467] • Keep up-to-date: Features FOR d The effect is that the spike appears later than other spikes. The result is that the delay produced by the delay is too small. This effect can be understood based on the fact that a "keep-up" strategy causes earlier spikes (e.g., spike x that precedes spike x+1) to be ignored.

[0468] The time skew problem can be solved by any technique that typically results in an equal number of choices between the strategies of keeping the oldest and keeping the newest. Figure 8 and Figure 2 The main difference is the introduction of conflict resolution block 0224, within which the proposed implementation scheme can be seen. Figure 8 Function block 0220 (generate delay) contains elements that do not exist in Figure 2 The additional "Delayed Complete" output is located in function block 225. Delayed Complete is logic 0 whenever a delay occurs to time the delay period, and logic 1 otherwise. Whenever Delayed Complete is logic 1, AND gate 0230 will allow the spike at input 0211 to initiate the delay operation. This makes sense because there is no conflict with pre-existing delay periods under these conditions.

[0469] Conversely, we know that a conflict scenario exists when the FOR spike arrives at input 0211 and the delay completion is logic 0. This scenario is decoded by the AND gate 0233 of the conflict resolution block 0224. The AND gate 0233 that produces logic 1 depends on the pre-existing state of flip-flop 0234 and causes one of two operations:

[0470] If flip-flop 0234 happens to have already produced a logic 1 at its Q output, then the Q output, along with the logic 1 from AND gate 0233, will cause AND gate 0232 to produce (via OR gate 0231) a timed restart signal that causes a delay. This is, as you can understand, the execution of a "keep up-to-date" strategy.

[0471] Conversely, if trigger 0234 happens to produce a logic 0 at its Q output, then that logic 0 prevents the AND operation with 0232 from generating a timed restart signal that causes a delay. This is the execution of the "keep oldest" strategy.

[0472] Regardless of whether trigger 0234 happens to have generated a logic 1, each time "AND" 0233 generates a logic 1, it triggers trigger 0234 to change its state. The net result is that after each conflict scenario is detected, conflict resolution block 0224 immediately implements a strategy based on the current state of trigger 0234, and then changes the state of trigger 0234 so that the opposite strategy is executed next time.

[0473] 9.2.3.2 Electricity Implementation Plan

[0474] Figures 9 to 10 An example electrical implementation plan that generates delays is proposed.

[0475] Figure 9 Plotting the exponential decay curve through coupling (i.e., 0910 is e) -rtAn instance where latency is generated by implementing threshold detection (horizontal line 0911). Figure 9 In the example, the decay rate r equals 3, and the detection threshold (called th) d The threshold is 0.1. As can be seen, under these conditions, the resulting delay period (denoted as "d") is 0.77 seconds. It is understood that the delay can be increased or decreased by lowering or increasing the threshold, respectively.

[0476] Figure 10 Presentation for implementation Figure 8 The circuit system for generating delay functionality is shown for function block 0220.

[0477] Figure 10 The outline 1010 indicates the external interface that generates the delay, wherein each connection corresponds to an input or output of the delay generation function block 0220.

[0478] The exponential decay, formed by the combination of capacitor 1040 and resistor 1041, forms the basis for the timing capability that generates a delay. The decay applied to the negative input of comparator amplifier 1030 occurs at the "decay" node. The threshold applied to the positive input of the comparator (called the th)... d The voltage is set by an adjustable voltage source 1031. The voltage output by 1031 can be incrementally adjusted to be lower or higher by applying pulses to the "more d" or "less d" input to interface 1010, respectively. At any given time, the state of voltage source 1031 (i.e., its current setting as the output voltage) can be maintained by a capacitor (not shown).

[0479] Each spike at the start / restart input triggers a single-shot 1020. The single-shot 1020 generates a pulse that, upon assertion, prepares capacitor 1040 to generate a new exponentially decaying cycle via switches S1 and S2 of switching unit 1043. Specifically, during the duration of the single-shot pulse:

[0480] S1 couples capacitor 1040 to a unity-value voltage source 1042, and

[0481] S2 ensures that the decay node maintains the correct initial value for restarting exponential decay when capacitor 1040 is recharged.

[0482] Once the single-transmission signal 1020 ends, the combination of capacitor 1040 and resistor 1041 begins its exponential decay. When the voltage at the decay node drops below the voltage output by voltage source 1031, the output of comparator 1030 generates a logic 1. Logic 1 causes the following two:

[0483] • Assert the “Delayed completion” output at interface 1010.

[0484] • Triggering a single 1021, its pulse constitutes the FOR signal at interface 1010. d The spikes output at the output point.

[0485] 9.2.4 Learning Rate (All)

[0486] As presented above, the function blocks for generating delays and learning delays (e.g., Figure 8 Both blocks 0220 and 0226 operate using exponential decay curves. The decay rate r of these functions can be selected based on the expected peak frequency for a particular application.

[0487] However, the CCU contains an average peak rate (which we call r) that can be found at its FOR input. ALL The function block ) can be useful. Generally, for the decay function that generates the delay and the learning delay, r ALL It is a good value to use as r.

[0488] For example, regarding such Figure 3 The learning delay shown in the figure, r ALL This can be used with the Post and Pre functions. Using this value for r tends to ensure that other spikes are located in regions where each function changes relatively quickly and are therefore easier to measure. This is achieved by measuring the rate of decay of the delay against the region that produces the delay (see, for example, the rate of decay of the delay). Figure 9 The function 0910) uses r ALL To achieve similar advantages.

[0489] Figure 11 Describing and Figure 8 The same CCU, except for the following:

[0490] • Add a "Learning Rate All" (or LRA) function block 0223. As can be seen, LRA 0223 accepts the FOR spike as input and outputs r. ALL .

[0491] · r ALL Inputs are added to each of the production delay and the learning delay (hence their labels are from...). Figure 8 0220 and 0226 changed to Figure 11 (0227 and 0228). These r ALL Input from LRA 0223's r ALL Output driver.

[0492] The learning rate is entirely based on the following property of a random spike stream s: if a random spike stream has r ALL If the correct value is found, then the following expression provides the probability that the next spike will occur at time t or at any later time:

[0493] Equation 1:

[0494] This also means that if a random spike flow exhibits exponential decay according to Equation 1, the time P = 0.5 is the median expected arrival (or MEA) time of the next spike in flow s. We also call this the MEA. ALL The median expected arrival time has the following special properties:

[0495] Special property 1: Among the numerous sharp peaks of s, we can expect to see peaks appearing in MEA. ALL The number of peaks preceding the MEA will be equal to the number appearing in the MEA. ALL The number of subsequent spikes.

[0496] for Figure 12 Assuming the actual MEA ALL For r ALL =3 is 0.23 seconds. As can be seen (for clarity of explanation), the peaks a through d have been chosen to be evenly distributed across the MEA. ALL On both sides.

[0497] Special property 1 has the following meanings:

[0498] • If MEA ALL Guessing the value (called MEA) guess Too high (i.e., in fact, MEA) guess MEA ALL ), then among the numerous peaks of s, in MEA guess The spikes that appear earlier will be more pronounced than those in MEA. guess The subsequent appearance of sharp peaks is more frequent. Figure 13 This demonstrates an extreme example of this situation, where MEA guess It is 0.345 seconds (for r=2), and the spikes a to d (relative to their positions for r=2, labeled a' to d') are all in MEA. guess Front.

[0499] • If MEA ALL Guessing the value (called MEA) guess Too low (i.e., in fact, MEA) guess <MEA ALL ), then among the numerous peaks of s, in MEA guess The subsequent spikes will be more pronounced than those in MEA. guess There are many sharp peaks appearing earlier. Figure 14 This demonstrates an example of this situation, where MEA guess It is 0.115 seconds (for r=6), and the same spikes a through d (now labeled a" through d relative to r=6) all appear in MEA. guesslater.

[0500] Special property 1, along with its meaning, indicates that MEA can be found. ALL The search procedure provides the foundation. The procedure can be described as containing the following two main steps:

[0501] 1. Select MEA guess Reasonable initial values:

[0502] For example, MEA guess The choice of the initial value of r can be limited to a range of possible values ​​based on the specific system design and its intended application. Alternatively, the initial value of r can be guessed (called r0). guess ) to determine MEA guess The value can be determined based on r. guess Determine MEA guess The MEA can then be determined based on Equation 1. guess The corresponding time. Specifically, when P = 0.5 and r = r guess In this case, Equation 1 becomes:

[0503] Equation 2:

[0504] 2. For each pair of peaks n and n+1 in flow s, the time interval (t) between the peaks is... n+1 -t n ) and MEA guess Comparison:

[0505] ○If (t) n+1 -t n ) <MEA guess Assuming (based only on this latest data point) MEA guess If the predicted value is too high, then:

[0506] ■ Reduce MEA for the purpose of subsequent comparisons between peak pairs guess The value of .

[0507] ■By making r guess Increment the standard quantity (called Δr) and then redefine Equation 2 to determine MEA. guess The value has been reduced.

[0508] ○If (t) n+1 -t n MEA guess Assuming (based only on this latest data point) MEA guess The guessed value is too low, so:

[0509] ■ Increase MEA when comparing subsequent peak pairs guess The value of .

[0510] ■By making r guess Decrease the standard quantity (called Δr) and then redetermine Equation 2 to determine MEA. guess The value increases with time.

[0511] For each of the above assumptions regarding MEA guess Too high or too low? Among the search procedures listed above, the following possibilities exist:

[0512] • If MEA is present in a large number of spikes guess In fact, it is too high, so this fact is indicated by the MEA. guess More comparisons, rather than too high rather than too low, were used to determine this, and MEA guess The value experiences a net decrease (by means of r) guess (Net increase).

[0513] • If MEA is present in a large number of spikes guess In fact, it is too low, so this fact is indicated by the MEA. guess More comparisons, rather than too high, were used to determine this, and MEA guess The value experiences a net increase (by means of r) guess (Net decrease).

[0514] MEA guess Only when it is factually correct (i.e., in MEA) guess =MEA ALL And r guess =r ALL Net dynamic stability is achieved at that time.

[0515] Therefore, among a sufficient number of peaks, r will be determined. ALL , where Δr is chosen to provide convergence to r ALL The speed (also known as the "learning rate") and the determined r ALL A suitable trade-off between the accuracy of the values:

[0516] A larger value for Δr increases the learning rate but reduces the accuracy of the results.

[0517] A smaller value for Δr decreases the learning rate but increases the accuracy of the results.

[0518] Except for solving for the points that produce half of the total range of Equation 1 (e.g., P = 0.5), Figure 15 It also describes alternative methods for finding the MEA. The alternative method is a time-series solution to Equation 1 that is equal to Equation 3 below (where Equation 3 defines the cumulative probability distribution):

[0519] Equation 3:

[0520] like Figure 15 As can be seen, finding equal points helps to locate previous information about... Figures 12 to 14 Each of the MEA discussed.

[0521] This equality test method is Figure 16 The hardware implementation scheme is based on the following description.

[0522] Figure 16 Outline 1610 indicates the external interface of the LRA, where each connection corresponds to Figure 11 The input or output of LRA function block 0223.

[0523] exist Figure 16 In this process, the exponential decay of Equation 1 is executed through the combination of capacitor 1630 and variable resistor 1631. The decay value can be obtained at the "decay" node 1641. Equation 3 (exponential increase) is executed by subtraction amplifier 1621 as follows:

[0524] • Apply a unit voltage to the amplifier's "A" input.

[0525] • Apply the attenuation node 1641 (i.e., Equation 1) to the “B” input.

[0526] The output of the subtraction amplifier 1621, which can be obtained at node 1640, is therefore a voltage level representation of Equation 3.

[0527] The comparator amplifier 1622 performs the equality test between Equations 1 and 3, where the result can be obtained at node 1642 (corresponding to the MEA explained above). guess ).

[0528] Whenever a spike n is present, the dual transmitter 1620 is triggered at the FOR input of interface 1610. The first step activated by the dual transmitter's out1 is to complete the MEA measurement starting with the last FOR spike n-1. Out1 operates this step by enabling AND gates 1623 and 1624 to read the output of comparator 1622.

[0529] The output of comparator 1622 can be interpreted as follows:

[0530] • If the time period between the comparison indicator spike n-1 and n is less than the current MEA guess Then comparator 1622 outputs logic 1. This is because the exponential decay node 1641 drives the + input of the comparator.

[0531] • If the duration between the comparison indicator spike n-1 and n is greater than the current MEA guessThen comparator 1622 outputs logic 0. This is because the exponentially increasing node 1640 drives the -input of the comparator.

[0532] If the current measurement indication of comparator 1622 is MEA guess If the value is too high, then the logic 1 on node 1642 causes AND gate 1623 to be enabled, and the out1 pulse is applied to the R-input of variable resistor 1631. It is understood that reducing the resistance causes a faster decay rate at node 1641 and a decrease in the MEA (Mean Adjustment Aspect). guess The downward adjustment.

[0533] Conversely, if the current measurement of comparator 1622 indicates MEA guess If the value is too low, then the logic 0 on node 1642 causes the AND gate 1624 to be enabled, and the out1 pulse is applied to the R+ input of the variable resistor 1631. It is understood that increasing the resistance causes a slower decay rate at node 1641 and a decrease in the MEA. guess The upward adjustment.

[0534] For example, the duration of the out1 pulse and the specific construction of the variable resistor 1631 are factors that determine r. guess The increment of change, where the magnitude of each increment is referred to in the above discussion as Δr, the “learning rate”.

[0535] The state of the variable resistor 1631 (i.e., its current resistance level) can be maintained by an internal state capacitor (not shown). For example, the voltage across this capacitor can increase with each pulse to the R- input and decrease with each pulse to the R+ input. Furthermore, this can be maintained via the external interface 1610 driving the LRA. ALL The output voltage follows the voltage of the internal state capacitor obtained by the amplifier (also not shown).

[0536] As mentioned above Figure 11 As discussed, LRA 0223 can be used to... ALL The output is provided to each of the production delay 0227 and the learning delay 0228. ALL enter.

[0537] Figure 6 and 7 By adding r ALL Part of the circuit implementation for learning delay 0226, which is changed by input. For the circuit implementation for learning delay 0228, Figure 6 and 7 Replace with Figure 17 and 18 . Figure 17 and 18 and Figure 6 and7 The differences are as follows:

[0538] ·Use accept r ALL Input 0601 variable resistor 0644 ( Figure 17 Replace fixed resistor 0641 ( Figure 6 ).

[0539] ·Use accept r ALL Input 0701 variable resistor 0722 ( Figure 18 Replace fixed resistor 0721 Figure 7 ).

[0540] For the circuit implementation scheme that generates a delay of 0227, Figure 10 Replace with Figure 19 . Figure 19 and Figure 10 The differences are as follows: r is used as part of its external interface 1011 ALL Input variable resistor 1044 ( Figure 19 Replace fixed resistor 1041 ( Figure 10 ).

[0541] In order to make LRA's r ALL The output voltage exhibits an exponential decay curve (for generation delay 0227 and learning delay 0228), where r is equal to the value of r found in LRA 0223. ALL It can perform the following tasks:

[0542] • Capacitor 0640 (see Figure 17 The implementation plan for postAcc), 0720 (see Figure 18 The implementation plan for preAcc) and 1040 (see Figure 19 The implementation scheme for generating delay has a capacitor 1630 with LRA (see Figure 16 The same capacitance.

[0543] • Enables the use of variable resistor 0644 (see...) Figure 17 The implementation plan for postAcc), 0722 (see Figure 18 The implementation scheme of preAcc) and 1044 (see Figure 19 The implementation scheme for generating delay) and the variable resistor 1631 of LRA (see Figure 16 The same applies, except as follows: each of 0644, 0722, and 1044 uses its external interface r. ALL An input-driven voltage follower, instead of maintaining the internal state.

[0544] 9.3 Summary

[0545] This invention relates to a multi-stream cross-correlator for a spike neural network, wherein each stream contains significant random content. At least one event occurs across at least two streams with a fixed temporal relationship. Each stream is considered a frame of reference (FOR) and undergoes an adjustable delay based on comparisons with other streams. For each spike of the FOR, timing analysis is performed relative to the last and current FOR spike by comparing a Post accumulator with a Pre accumulator. Furthermore, a new timing analysis begins with the current FOR spike by restarting the generation of the Post and Pre weighting functions, accumulating the values ​​of the Post and Pre weighting functions immediately after each other spike occurs until the next FOR spike. If a time-neutral conflict resolution solution is used, a single spike delay unit can be employed. The average spike rate of the FOR can be determined and used in the Post and Pre weighting functions.

[0546] Although the invention has been described with reference to specific embodiments, it will be apparent from the foregoing description that many alternatives, modifications, and variations will be understood. Therefore, the invention is intended to encompass all such alternatives, modifications, and variations that fall within the spirit and scope of the appended claims and their equivalents.

Claims

1. A method for identifying a pair of spikes sharing a common underlying event, comprising: The process is executed at least in part using electronic hardware configuration, receiving a first spike stream that primarily contains random content, excluding a first spike subgroup, wherein each spike in the first spike subgroup shares a base event with spikes in a second spike subgroup of a second spike stream. The process is executed, at least in part, using electronic hardware configuration, to receive the second spike stream, which mainly contains random content, excluding the second spike subgroup. The identification of a first crossflow spike pair, comprising a first spike from the first spike stream and a second spike from the second spike stream, is performed at least partially using electronic hardware configuration. The first exponential decay unit is activated immediately upon receiving the first spike by using electronic hardware configuration. The first exponential decay unit is stopped immediately upon receiving the second spike, at least partially by utilizing electronic hardware configuration. The operation is performed at least in part using electronic hardware configuration. If the first decay output is not less than a first threshold when the first exponential decay unit is stopped, then the output indicates that both the first spike and the second spike are first signals caused by a shared underlying event. The second threshold is set as a first fraction of the first threshold, at least partially implemented using electronic hardware configuration. The first decay rate of the first exponential decay unit is increased and the first threshold is decreased if the first decay output is less than the first threshold and not less than the second threshold when the first exponential decay unit is stopped. and The first decay rate of the first exponential decay unit is reduced and the first threshold is increased if the first decay output is less than the first threshold and less than the second threshold when the first exponential decay unit is stopped. This is done at least partially using electronic hardware configuration.

2. A method for identifying a pair of spikes sharing a common underlying event, comprising: The process is executed at least in part using electronic hardware configuration, receiving a first spike stream that primarily contains random content, excluding a first spike subgroup, wherein each spike in the first spike subgroup shares a base event with spikes in a second spike subgroup of a second spike stream. The process is executed, at least in part, using electronic hardware configuration, to receive the second spike stream, which mainly contains random content, excluding the second spike subgroup. The identification of a first crossflow spike pair, comprising a first spike from the first spike stream and a second spike from the second spike stream, is performed at least partially using electronic hardware configuration. The first exponential decay unit is activated immediately upon receiving the first spike by using electronic hardware configuration. The process is executed, at least in part, using electronic hardware configuration. Upon receiving the second spike, the first attenuation output is immediately compared with a discrimination threshold, a first threshold of a first region, and a second threshold of the first region, wherein the discrimination threshold is greater than or equal to the first threshold of the first region and the first threshold of the first region is greater than the second threshold of the first region. The comparison is performed at least in part using electronic hardware configuration. If, during the comparison, the first attenuation output is not less than the discrimination threshold, then the output indicates that both the first spike and the second spike are first signals caused by a shared underlying event. The comparison is performed at least partially using electronic hardware configuration. If, during the comparison, the first attenuation output is less than the first threshold of the first region and not less than the second threshold of the first region, then the first attenuation rate of the first exponential attenuation unit is increased and the discrimination threshold is decreased. The identification of a second crossflow spike pair, comprising a third spike from the first spike flow and a fourth spike from the second spike flow, is performed at least partially using electronic hardware configuration. The first exponential decay unit is activated immediately upon receiving the third spike using the first decay output, at least partially utilizing electronic hardware configuration. The process is executed, at least in part, using electronic hardware configuration. Upon receiving the fourth spike, the first attenuation output is immediately compared with a discrimination threshold, a first threshold of the second region, and a second threshold of the second region, wherein the second threshold of the first region is greater than or equal to the first threshold of the second region, and the first threshold of the second region is greater than the second threshold of the second region. The operation is performed, at least partially using electronic hardware configuration, whereby if, during the comparison, the first attenuation output is not less than the discrimination threshold, the output indicates that both the third and fourth spikes are second signals caused by a shared underlying event; and The comparison is performed at least in part using electronic hardware configuration. If, during the comparison, the first attenuation output is less than the first threshold of the second region and not less than the second threshold of the second region, then the first attenuation rate of the first exponential attenuation unit is reduced and the discrimination threshold is increased, wherein the first region and the second region correspond to a range of values ​​along the time axis.

3. The method according to claim 2, wherein the first peak of the first crossflow peak pair is the same as the third peak of the second crossflow peak pair, and the second peak of the first crossflow peak pair is the same as the fourth peak of the second crossflow peak pair.

4. The method according to claim 2, wherein the first peak and the second peak of the first crossflow peak pair are different from the third peak and the fourth peak of the second crossflow peak pair.

5. The method of claim 2, wherein the second threshold of the second region is zero.

6. The method of claim 5, wherein the first difference between the first threshold of the first region and the second threshold of the first region is approximately equal to the second difference between the first threshold of the second region and the second threshold of the second region.

7. The method of claim 2, wherein the first difference between the first threshold of the first region and the second threshold of the first region is approximately equal to the second difference between the first threshold of the second region and the second threshold of the second region.

8. The method of claim 7, wherein the first difference and the second difference are each approximately the same and approximately constant fraction of the difference between the discrimination threshold and zero.

9. The method of claim 2, further comprising the following steps: This makes the first and second spike flows correlated.

10. The method of claim 9, further comprising the following steps: Receive a first undelayed spike stream that primarily contains random content, excluding a first undelayed spike subgroup, wherein each spike in the first undelayed spike subgroup shares a base event with spikes in the second undelayed spike subgroup of the second undelayed spike stream; The first undelayed spike stream is input into the first delay unit to generate the first spike stream with a first delay, wherein the first delay has a lower limit of zero seconds; The second undelayed spike stream is input into the first delay unit to generate the second spike stream with a second delay, wherein the second delay has a lower limit of zero seconds; Upon receiving the first delayed spike from the first spike stream, the first accumulated value is immediately compared with the second accumulated value to generate a first comparison result; If the first comparison result indicates that the first accumulated value is greater than the second accumulated value, then increase the first delay; If the first comparison result indicates that the first accumulated value is less than the second accumulated value, then reduce the first delay; After generating the first comparison result, reset the first accumulated value and the second accumulated value; After the first comparison result is generated, the first process for generating the first weighting function and the second weighting function is restarted, wherein the first weighting function decreases monotonically and the second weighting function increases monotonically and is symmetrical and opposite to the first weighting function. Upon receiving the second delayed spike from the second spike stream, the first weighted value is immediately accumulated into the first accumulator according to the first weighting function; and Upon receiving the second delayed spike from the second spike stream, the second weighted value is immediately added to the second accumulator according to the second weighting function.

11. The method of claim 10, further comprising: The first delay is increased by increasing the length of the first queue including the first delay unit; and The first delay is reduced by decreasing the length of the first queue.

12. The method of claim 10, further comprising: If the timing of the first delay unit has not yet been started, then the duration equal to the first delay is timed immediately after the first undelayed spike from the first spike stream is input into the first delay unit. The spike is output immediately upon completion of any timing of the first delay; Based on the first state of the first decision variable and the receipt of the second undelayed spike during the duration of the previous undelayed spike, it is decided to continue the duration of the previous undelayed spike; The timing for restarting the first delay performed by the first delay unit is determined based on the second state of the first decision variable and the receipt of the second undelayed spike during the duration of the previous undelayed spike; The probability of the first state being equal to the second state is ensured for the first decision variable in multiple instances where the second undelayed spike is received during the duration of the previously undelayed spike.

13. The method of claim 10, further comprising: If the first exponentially decreasing function is greater than the first exponentially increasing function when the first undelayed spike is received from the first spike stream, then the first average spike rate is increased to generate both the first exponentially decreasing function and the first exponentially increasing function. If the first exponentially decreasing function is less than the first exponentially increasing function when the first undelayed spike is received from the first spike stream, then the first average spike rate is reduced to generate both the first exponentially decreasing function and the first exponentially increasing function; and The first average peak rate is used to generate the first weighting function and the second weighting function.

14. The method of claim 12, further comprising: If the first exponentially decreasing function is greater than the first exponentially increasing function when the first undelayed spike is received from the first spike stream, then the first average spike rate is increased to generate both the first exponentially decreasing function and the first exponentially increasing function. If the first exponentially decreasing function is less than the first exponentially increasing function when the first undelayed spike is received from the first spike stream, then the first average spike rate is reduced to generate both the first exponentially decreasing function and the first exponentially increasing function; and The first average peak rate is used to time the first delay.

15. A method for identifying a pair of spikes sharing a common underlying event, comprising: The process is executed at least in part using electronic hardware configuration, receiving a first spike stream that primarily contains random content, excluding a first spike subgroup, wherein each spike in the first spike subgroup shares a base event with spikes in a second spike subgroup of a second spike stream. The process is executed, at least in part, using electronic hardware configuration, to receive the second spike stream, which mainly contains random content, excluding the second spike subgroup. The identification of a first crossflow spike pair, comprising a first spike from the first spike stream and a second spike from the second spike stream, is performed at least partially using electronic hardware configuration. The first exponential decay unit is activated immediately upon receiving the first spike by using electronic hardware configuration. At least partially implemented using electronic hardware configuration, upon receiving the second spike, the first attenuation output is immediately compared with a discrimination threshold, a first threshold of a first increasing region, and a second threshold of the first increasing region, wherein the discrimination threshold is greater than or equal to the first threshold of the first increasing region, and the first threshold of the first increasing region is greater than the second threshold of the first increasing region. The comparison is performed at least in part using electronic hardware configuration. If, during the comparison, the first attenuation output is not less than the discrimination threshold, then the output indicates that both the first spike and the second spike are first signals caused by a shared underlying event. The comparison is performed at least partially using electronic hardware configuration. If, during the comparison, the first decay output is less than the first threshold of the first incrementing region and not less than the second threshold of the first incrementing region, then the first decay rate of the first exponential decay unit is increased and the discrimination threshold is decreased. The identification of a second crossflow spike pair, comprising a third spike from the first spike flow and a fourth spike from the second spike flow, is performed at least partially using electronic hardware configuration. The second exponential decay unit is activated immediately upon receiving the third spike by using at least some of the electronic hardware configuration. The process is executed, at least in part, using electronic hardware configuration. Upon receiving the fourth spike, the second attenuation output is immediately compared with a discrimination threshold, a first threshold of a first decreasing region, and a second threshold of the first decreasing region, wherein the first threshold of the first decreasing region is greater than the second threshold of the first decreasing region. The operation is performed at least in part using electronic hardware configuration. If, during the comparison, the second attenuation output is not less than the discrimination threshold, then the output indicates that both the third and fourth spikes are second signals caused by a shared underlying event. and The comparison is performed at least in part using electronic hardware configuration. If, during the comparison, the second decay output is less than the first threshold of the first decreasing region and not less than the second threshold of the first decreasing region, then the first decay rate of the second exponential decay unit is reduced and the discrimination threshold is increased, wherein the first increasing region and the first decreasing region correspond to a range of values ​​along the time axis.

16. The method of claim 15, wherein the second threshold of the first increasing region is greater than or equal to the first threshold of the first decreasing region.

17. The method of claim 15, wherein the same exponential decay unit is used as both the first exponential decay unit and the second exponential decay unit.

18. The method of claim 15, wherein the first increasing region and the first decreasing region have probabilistic symmetry.

19. The method of claim 15, further comprising the following steps: Operate the first increasing region and the first decreasing region with the same scale.

20. The method of claim 19, further comprising the following steps: The first increasing region and the first decreasing region are operated on different samples.

21. The method of claim 15, further comprising the following steps: The first increasing region is operated on with a first scale, and the first decreasing region is operated on with a second scale, wherein the first scale is different from the second scale.

22. The method of claim 21, further comprising the following steps: The first increasing region and the first decreasing region are operated on different samples.

23. The method of claim 15, further comprising the following steps: Based on at least one threshold different from the first threshold and the second threshold of the first incremental region, operate one or more additional incremental regions in the first group; Operate a second group of one or more additional decreasing regions based on at least one threshold different from the first threshold and the second threshold of the first decreasing region; The first set of additional incrementing regions is operated according to the same procedure as the first incrementing region; The second set of additional decreasing regions is operated according to the same procedure as the first decreasing region; and The first increasing region and the first group of additional increasing regions are operated with probability symmetry relative to the first decreasing region and the second group of additional decreasing regions.

24. The method of claim 15, wherein the first peak of the first crossflow peak pair is the same as the third peak of the second crossflow peak pair, and the second peak of the first crossflow peak pair is the same as the fourth peak of the second crossflow peak pair.

25. The method of claim 15, wherein the first peak and the second peak of the first crossflow peak pair are different from the third peak and the fourth peak of the second crossflow peak pair.

26. A system for identifying a pair of spikes sharing a common underlying event, comprising: A first subsystem, which utilizes at least part of an electronic hardware configuration, receives a first spike stream that primarily contains random content, excluding a first spike subgroup, wherein each spike in the first spike subgroup shares a base event with spikes in a second spike subgroup of a second spike stream. The second subsystem, which utilizes at least part of an electronic hardware configuration, receives the second spike stream, which mainly contains random content, in addition to the second spike subgroup. The third subsystem utilizes at least part of electronic hardware configuration to identify a first crossflow spike pair, comprising a first spike from the first spike stream and a second spike from the second spike stream; The fourth subsystem, which utilizes at least part of electronic hardware configuration, immediately activates the first exponential decay unit with a first decay output upon receiving the first spike. The fifth subsystem, which utilizes at least part of electronic hardware configuration, immediately compares the first attenuation output with a discrimination threshold, a first threshold of a first increasing region, and a second threshold of the first increasing region upon receiving the second spike, wherein the discrimination threshold is greater than or equal to the first threshold of the first increasing region, and the first threshold of the first increasing region is greater than the second threshold of the first increasing region. The sixth subsystem, which utilizes at least part of electronic hardware configuration, if the first attenuation output is not less than the discrimination threshold when the comparison is performed through the fifth subsystem, then the output indicates that both the first spike and the second spike are first signals caused by a shared underlying event. The seventh subsystem, which utilizes at least part of electronic hardware configuration, increases the first decay rate of the first exponential decay unit and decreases the discrimination threshold if, during the comparison performed through the fifth subsystem, the first decay output is less than the first threshold of the first incrementing region and not less than the second threshold of the first incrementing region. The eighth subsystem utilizes at least part of an electronic hardware configuration to identify a second crossflow spike pair, comprising a third spike from the first spike stream and a fourth spike from the second spike stream; The ninth subsystem, which utilizes at least part of an electronic hardware configuration, immediately activates the second exponential decay unit with a second decay output upon receiving the third spike. The tenth subsystem, which utilizes at least part of an electronic hardware configuration, immediately compares the second attenuation output with a discrimination threshold, a first threshold of a first decreasing region, and a second threshold of the first decreasing region upon receiving the fourth spike, wherein the first threshold of the first decreasing region is greater than the second threshold of the first decreasing region. The eleventh subsystem, which utilizes at least part of electronic hardware configuration, if the second attenuation output is not less than the discrimination threshold when the comparison is performed through the tenth subsystem, then the output indicates that both the third and fourth spikes are second signals caused by a shared underlying event. as well as The twelfth subsystem, which utilizes at least part of electronic hardware configuration, reduces the first decay rate of the second exponential decay unit and increases the discrimination threshold if, during the comparison via the tenth subsystem, the second decay output is less than the first threshold of the first decreasing region and not less than the second threshold of the first decreasing region. The first increasing region and the first decreasing region correspond to a range of values ​​along the time axis.

27. The system of claim 26, further comprising: The thirteenth subsystem receives a first undelayed spike stream that mainly contains random content, excluding the first undelayed spike subgroup, wherein each spike in the first undelayed spike subgroup shares a base event with spikes in the second undelayed spike subgroup of the second undelayed spike stream. The fourteenth subsystem inputs the first undelayed spike stream into the first delay unit and generates the first spike stream with a first delay, wherein the first delay has a lower limit of zero seconds; The fifteenth subsystem inputs the second undelayed spike stream into the first delay unit and generates the second spike stream with a second delay, wherein the second delay has a lower limit of zero seconds; The sixteenth subsystem, upon receiving the first delayed spike from the first spike stream, immediately compares the first accumulated value with the second accumulated value to generate a first comparison result; The seventeenth subsystem performs the following: if the first comparison result indicates that the first accumulated value is greater than the second accumulated value, then the first delay is increased; The eighteenth subsystem performs the following: if the first comparison result indicates that the first accumulated value is less than the second accumulated value, then the first delay is reduced; The nineteenth subsystem resets the first accumulated value and the second accumulated value after generating the first comparison result; The twentieth subsystem, after generating the first comparison result, restarts the first process for generating the first weighting function and the second weighting function, wherein the first weighting function decreases monotonically and the second weighting function increases monotonically and is symmetrical and opposite to the first weighting function; The 21st subsystem, upon receiving the second delayed spike from the second spike stream, immediately adds the first weighted value to the first accumulator according to the first weighting function; and The 22nd subsystem, upon receiving the second delayed spike from the second spike stream, immediately adds the second weighted value to the second accumulator according to the second weighting function.

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