Closed-Loop Programming of Phase Change Memory

Abstract

A computer-implemented method, comprising: updating initial weight values ​​associated with a plurality of simulated synapses in a crossbar array implementing an artificial neural network by sending a pulse train to the plurality of simulated synapses, each of the simulated synapses comprising a conductance unit, wherein the updated weight value of the simulated synapse is based on a conductance value of the conductance unit. The pulse train changes the conductance value. The method further comprises: comparing the weight values ​​of the plurality of simulated synapses with target weight values ​​associated with the simulated synapses; and selecting a set of simulated synapses based on the comparison. The method further comprises updating the weight values ​​of the selected simulated synapses by sending a set of electrical pulses having different durations.

Description

Background Art

[0001] The present invention relates generally to computer technology and, more particularly, to programming phase change memory (PCM) cells using closed-loop programming.

[0002] PCMs exploit the properties of materials that have the property of switching between two phases with different electrical properties. For example, these materials can switch between (i) an amorphous, disordered phase and (ii) a crystalline or polycrystalline, ordered phase, where the two phases are associated with significantly different resistivity values. In addition, intermediate configurations in which the material only partially switches to the amorphous phase or the crystalline phase can be associated with intermediate values ​​of resistivity. Summary of the invention

[0003] According to one or more embodiments, a computer-implemented method includes updating weight values ​​associated with simulated synapses in a crossbar array implementing an artificial neural network by sending a pulse train to the simulated synapses. Each simulated synapse includes a conductance unit, wherein the weight value of the simulated synapse is based on the conductance value of the conductance unit. The pulse train changes the conductance value of the conductance unit. The method further includes comparing the weight value of the simulated synapse with a target weight value associated with the simulated synapse. The method further includes selecting the group of simulated synapses from the crossbar array based on the comparison. The selection is indicated using a selection flag associated with the simulated synapse. The method further includes updating the weight value of each simulated synapse in the selected group of simulated synapses by sending a group of electrical pulses with different durations to the group of simulated synapses. The group of electrical pulses changes the conductance value of the conductance unit corresponding to the group of simulated synapses.

[0004] In one or more examples, the pulse train sent to the simulated synapses has a predetermined duration, wherein the uniform weight pulse train includes a plurality of current pulses having decreasing amplitudes. In one or more examples, the conductance unit is a set of non-volatile memory devices. Further, the weight value associated with the simulated synapse is calculated based on the conductance value of each of the non-volatile memory devices. In one or more examples, the non-volatile memory device is a phase change memory device. In one or more examples, the non-volatile memory device is a resistive random access memory device.

[0005] In one or more examples, the group of non-volatile memory devices includes four non-volatile memory devices configured to form a more significant pair (MSP) and a less significant pair (LSP). The weight value of the simulated synapse is calculated as W=F x(G+-G-)+g+-g-, where F is a scaling factor, G+ and G- are conductance values ​​of the MSP, and g+ and g- are conductance values ​​of the LSP.

[0006] In one or more examples, changing the conductance value of the conductance unit includes changing the conductance value of each non-volatile memory device from the conductance unit according to a predetermined order for updating the conductance value. In one or more examples, the conductance values ​​of the non-volatile memory devices in the MSP are updated first according to the predetermined order. In addition, the conductance values ​​of the non-volatile memory devices in the MSP are updated according to the sign flags associated with the non-volatile memory devices according to the predetermined order.

[0007] In one or more examples, selecting the set of simulated synapses includes selecting the set of simulated synapses for which a difference between a weight value and a target value is greater than a predetermined threshold.

[0008] In one or more examples, the method further includes removing a first simulated synapse from the set of simulated synapses, wherein a weight value of the first simulated synapse differs from a target weight value within the predetermined threshold. For example, in response to the weight value of the first simulated synapse being updated by the set of electrical pulses having varying durations, removing the first simulated synapse from the set of simulated devices.

[0009] In one or more examples, the set of electrical pulses having varying durations includes a first electrical pulse for a first simulated synapse based on a first difference between a weight value of the first simulated synapse and a target weight value.

[0010] In addition to other types of implementations, the above features may be provided by at least a system, a computer program product, and a machine. According to one or more embodiments of the present invention, a system includes a processor, a coprocessor including one or more crossbar arrays, and the processor is configured to implement an artificial neural network by mapping a layer of the artificial neural network with the crossbar array using the coprocessor. According to one or more embodiments, a computer program product includes a computer-readable storage medium having program instructions embodied therewith, the program instructions being executable by a processing circuit to perform a method for implementing an artificial neural network by mapping a layer of the artificial neural network with a crossbar array.

[0011] According to one or more embodiments, a crossbar array includes a plurality of phase change memory devices, wherein a phase change memory device is at each crosspoint in the crossbar array. Each group of four phase change memory devices forms a conductance unit, and such a group of conductance units represents a group of simulated synapses in an artificial neural network. The conductance value of the phase change memory device is programmed by executing a method circuit comprising the following steps: receiving a pulse train of the plurality of simulated synapses in the crossbar array, wherein the weight value of the simulated synapse is based on the conductance value of the conductance unit, and the pulse train changes the conductance value of the conductance unit. The method also includes updating the weight value of each simulated synapse from a group of simulated synapses, the group of simulated synapses being selected by receiving a group of electrical pulses having different durations for the group of simulated synapses. The group of electrical pulses changes the conductance value of the conductance unit corresponding to the group of simulated synapses. The group of simulated synapses from the crossbar array is selected based on comparing the weight values ​​of the plurality of simulated synapses with target weight values ​​associated with the simulated synapses.

[0012] According to one or more embodiments, a computer-implemented method includes configuring two pairs of phase change memory devices from a set of phase change memory devices in a crossbar array as conductance units, wherein the set of conductance units represents a plurality of simulated synapses in an artificial neural network. The method further includes sending a pulse train to the set of simulated synapses in the crossbar array, wherein a weight value of the simulated synapse is based on a conductance value of the conductance unit, and the pulse train changes the conductance value of the conductance unit. The method also includes updating a weight value of each simulated synapse from the selected set of simulated synapses by sending a set of electrical pulses having varying durations to the set of simulated synapses. The set of electrical pulses changes the conductance value of the conductance unit corresponding to the set of simulated synapses. The set of simulated synapses from the crossbar array is selected based on comparing the weight values ​​of the set of simulated synapses with target weight values ​​associated with the simulated synapses.

[0013] Additional technical features and benefits are achieved through the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein, and these embodiments and aspects are considered to be part of the claimed subject matter. For a better understanding, reference is made to the specific implementation and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The details of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of this specification. The foregoing and other features and advantages of the embodiments of the present invention are apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 Depicts a block diagram of a deep neural network;

[0016] Figure 2A , Figure 2B and Figure 2C depicts a block diagram of a deep neural network using a crossbar array of analog memories in accordance with one or more embodiments of the present invention;

[0017] Figure 3 depicts a block diagram of a phase change memory array device according to one or more embodiments of the present invention;

[0018] Figure 4 Describes the structure of a neuromorphic system implemented as a network using a crossbar array coupled to a plurality of neurons according to one or more embodiments of the present invention;

[0019] Figure 5 Depicted is a schematic diagram for mapping weights into a phase change memory device according to one or more embodiments of the present invention;

[0020] Figure 6 depicts a visualization of mapping desired weights to conductance units in accordance with one or more embodiments of the present invention;

[0021] Figure 7 An example of a reduced current scan is shown according to one or more embodiments of the present invention;

[0022] Figure 8 describing a sequence of pulses sent to a conductance cell according to one or more embodiments of the present invention; and

[0023] Fig. 9 Depicted is a flow chart of a method for programming neural network weights as simulated synapses implemented using a crossbar array in accordance with one or more embodiments of the present invention.

[0024] The figures described herein are illustrative. Without departing from the scope of the present invention, many changes may be made to the diagrams or operations described herein. For example, these actions may be performed in different orders, or actions may be added, deleted or modified. Similarly, the term "coupling" and its variants describe having a communication path between two elements and do not imply a direct connection between these elements, without an intermediate element / connection between them. All these changes are considered as a part of the specification.

[0025] In the drawings and the following detailed description of the disclosed embodiments, the various elements shown in the drawings are provided with two or three digital reference numerals. In the case of minor exceptions, the leftmost digit of each reference numeral corresponds to the figure in which its element is first shown. DETAILED DESCRIPTION

[0026] Different embodiments of the present invention are described herein with reference to the accompanying drawings. Without departing from the scope of the present invention, alternative embodiments of the present invention may be designed. Various connections and positional relationships (e.g., above, below, adjacent, etc.) are described between the elements in the following description and the accompanying drawings. Unless otherwise indicated, these connections and / or positional relationships may be direct or indirect, and the present invention is limited in this respect by the schematic diagram. Thus, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive program or process with additional steps or functions not described in detail herein.

[0027] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0028] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" may be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect "connections" and direct "connections."

[0029] The terms "about", "substantially", "approximately" and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing this application. For example, "about" may include a range of ±8% or 5%, or 2% of a given value.

[0030] For the sake of brevity, conventional techniques related to making and using aspects of the present invention may or may not be described in detail herein. Specifically, various aspects of computing systems and specific computer programs for implementing the various technical features described herein are well known. Thus, for the sake of brevity, many conventional implementation details are only briefly mentioned herein, or omitted entirely, without providing well-known system and / or process details.

[0031] As mentioned above, phase change memory (PCM) elements utilize the properties of materials that have the property of switching between two phases with different electrical properties. Currently, alloys of Group VI of the periodic table, such as Te or Se, known as chalcogenides or chalcogenide materials, can be advantageously used in phase change cells. In chalcogenides, the resistivity changes by two or more orders of magnitude when the material passes from an amorphous phase (larger resistance) to a crystalline phase (smaller resistance) and vice versa.

[0032] This property enables PCM elements to be used to provide memory cells and arrays for digital data storage. Specifically, in phase change memory, a portion of a chalcogenide material is used as a programmable resistor that can be electrically heated by a controlled current so as to switch between a high resistance state and a low resistance state and vice versa, with a first logic value and a second logic value associated therewith, respectively. The state of the chalcogenide can be read by applying a sufficiently low voltage without causing sensible heating and by measuring the current passing through it. Since the current is proportional to the conductivity of the chalcogenide material, the two states can be distinguished. For example, chalcogenides (Ge2Sb2Te5, GST) formed by an alloy of Ge, Sb and Te are widely used to store information in rewritable memory devices, such as computers and other types of digital storage devices.

[0033] The phase transition between a highly resistive amorphous state and a highly conductive crystalline state can be electrically induced by a current pulse of appropriate amplitude and duration. Specifically, the transition towards the amorphous state ("reset") is obtained by applying a current pulse of amplitude sufficient to heat the chalcogenide to beyond the melting point by the Joule effect. The current pulse used has steep edges (e.g. a rectangular current pulse) so that the cooling of the chalcogenide is so rapid as to prevent crystallization. Different techniques can be used to induce the transition towards the crystalline state ("freezing"). Thus, because the conductance of the phases of the PCM device is different, this can be used to store bits. The temperature can also be controlled so that the bit enters a state with an intermediate conductance. In addition to storing bits, this can be used to perform calculations, because a predetermined group (or set) of subthreshold phase transitions can be gradually accumulated to a bit flip.

[0034] The advantages of doing computations in this way are twofold: Since the operations occur in memory, jumping back and forth to memory is avoided, and operations can be performed in parallel. Those differences have a natural parallel to the behavior of a population of neurons, which makes PCM devices suitable for artificial neural networks (ANNs), such as deep neural networks (DNNs).

[0035] PCM is further suitable for use in DNNs (or other types of neural networks). This is because neuronal activity is not binary, all-or-nothing stateful—it can adopt a range of intermediate behaviors between on and off. Therefore, the ability of a PCM device to adopt states between 1 and 0 allows it to directly model the behavior of neurons.

[0036] To use this for training, a grid (or array) of PCM devices (bits) can be mapped to each layer of the DNN. A communication network made of wiring allows neurons to communicate between themselves. The strength of this communication is set by the state of the memory - where it is on a spectrum between fully on and fully off. The state is in turn set by all the bits fed into it. The communication hardware converts the variable intensity signals from the phase-changing bits into signals of varying durations that are compatible with the digital communication network.

[0037] Typically, forward inference calculations can be slow and energy intensive to implement DNNs due to the need to transfer the network's weight data between conventional digital memory chips and processor chips and the need to constantly maintain weights in memory. As described above, using PCM-based byte-based analog non-volatile memory can speed up forward inference and reduce energy consumption by performing parallelized multiplication-accumulation operations at the location of weight data in the analog domain and reducing the need to refresh the stored weight data in memory. The practical applications of such DNNs are not limited and may include real-time sensor data processing and inference for IoT devices, etc.

[0038] The accuracy of forward inference strongly depends on the accuracy of weight programming. However, programming an analog memory such as PCM to a desired analog conductance value is not trivial, especially in the presence of variability in the analog memory array. For example, depending on the size of the memory cell and the bottom electrode, PCM devices can have different maximum conductances. Therefore, one single programming condition cannot bring all PCM devices in the array to the same analog conductance value. Further, there are some additional technical issues with the practical implementation of such DNN-based PCM devices. For example, the hardware does not have the same state range between 1 and 0 that makes the neural network effective. Further, there is bit-to-bit variability in how the PCM devices respond. Another technical challenge of programming PCM is to program multiple devices simultaneously in a finite time, because the iteration of each device can be different and can take infinitely long.

[0039] The techniques described herein using one or more embodiments of the present invention overcome such technical challenges. One or more embodiments of the present invention facilitate programming multiple PCM devices to specific analog conductance states simultaneously within a predetermined time frame. Based on the description herein, other advantages and practical applications provided by one or more embodiments of the present invention will be apparent to those skilled in the art.

[0040] One or more embodiments of the present invention facilitate intermediate analog conductance programming of non-volatile memory devices, such as PCM devices, by overcoming device-to-device variability. Thus, one or more embodiments of the present invention provide row-by-row closed-loop programming of non-volatile memory to specific analog conductance states. Experimental results of one or more embodiments of the present invention have shown that the described techniques are robust to device variability, thereby achieving a desired programming quality in a predefined time frame.

[0041] Figure 1 A block diagram of a deep neural network is depicted. The depicted DNN 100 has an input layer 110, a hidden layer 120, and an output layer 130, each layer including neurons 105. DNNs are loosely inspired by biological neural networks. Neurons 105 act as parallel processing units interconnected by plastic synapses. By adjusting the weights of the interconnections, DNN 100 can efficiently solve certain problems, such as classification problems. The training of DNN 100 is generally based on a global supervised learning algorithm commonly referred to as back propagation. During training, input data is forward propagated through neuron layers 110, 120, and 130, where the synaptic network performs multiplication and accumulation operations. The final layer (output layer 130) response is compared with the input data label, and the error is back propagated. Both the forward propagation and the backward propagation steps involve a sequence of matrix-vector multiplications. Subsequently, the synaptic weights are updated to reduce errors. Because these operations need to be performed repeatedly using very large data sets (multi-gigabytes) to very large neural networks, such brute force optimization methods may take days or weeks to train state-of-the-art networks on von Neumann machines. Thus, in one or more embodiments of the present invention, a coprocessor including multiple crossbar arrays of PCM devices and other analog communication links and peripheral circuits is used to accelerate such deep learning steps.

[0042] Figure 2A , Figure 2B and Figure 2CA block diagram of a deep neural network using a crossbar array of analog memory is depicted in accordance with one or more embodiments of the present invention. Synapses are weighted in association with each layer (110, 120, and 130) of the DNN 100 according to the conductance values ​​of non-volatile memory (NVM) devices 210 organized in the crossbar array 200. The NVM devices 210 may be PCM devices, resistive random access memory (RRAM) devices, etc. In Figure 2A , Figure 2B and Figure 2C The various stages of implementing DNN 100 are depicted in Figure 2A The forward propagation in Figure 2B Back propagation in , and Figure 2C The weight update in .

[0043] In one or more examples, there are multiple such crossbar arrays corresponding to each of the multiple layers (110, 120, and 130) of the DNN 100. According to one or more embodiments of the present invention, the coprocessor / chip / system includes such a crossbar array 200 and additional peripheral circuits to implement communication between the neuron activation function and the crossbar array 200.

[0044] Figure 3 A block diagram of a phase change memory array device according to one or more embodiments of the present invention is depicted. The architecture depicts multiple identical array blocks 310 connected by a flexible routing network on a chip / system 300. Each array block 310 represents a crossbar array 200 of NVM devices 210. The flexible routing network has at least three tasks: (1) convey chip inputs (such as example data, example labels, and weight coverage) from the edge of the chip 300 to the device array 310, (2) carry chip outputs (such as inferred classifications and updated weights) from the array 310 to the edge of the chip 300, and (3) interconnect different arrays 310 to implement a multi-layer neural network. Each array 310 has input neurons 110 (shown here on the "west" side of each array) and output neurons 130 ("south" side) connected to a dense grid of synaptic connections 115. The peripheral circuitry is divided into circuits assigned to individual rows (row circuits 320) and columns (column circuits 330), and circuits shared between multiple adjacent rows and columns.

[0045] According to one or more embodiments of the present invention, crossbar array 200 provides neuromorphic networks, including spiking neural networks based on spike timing dependent plasticity (STDP) learning rules of neuromorphic integrated circuits. For example, one or more embodiments of the present invention provide spike-based computing using complementary metal oxide semiconductor (CMOS) electronic neurons that interact with each other through nanoscale memory synapses such as NVM devices 210 (e.g., PCM devices).

[0046] In this neuron morphology network, electronic neurons are interconnected via programmable electronic synapses represented by NVM devices 210. The synaptic conductance changes over time as a function of the relative spike times of the presynaptic and postsynaptic neurons according to STDP. Specifically, if its postsynaptic neuron starts after its presynaptic neuron starts, and if the order of the two starts is opposite, the conductance of the synapse will be reduced. The STDP learning rule programs the synapse (NVM device 210) by increasing the conductance of the synapse if the postsynaptic neuron triggers after the presynaptic neuron triggers; if the order of the two triggers is opposite, the conductance of the synapse is reduced. The learning rule is defined by STDP, in which the synaptic conductance changes over time as a function of the relative spike times of the presynaptic and postsynaptic neurons. The change in synaptic conductance depends on the precise delay between the excitation events at the corresponding postsynaptic and presynaptic neurons. The longer the delay, the smaller the amplitude of the change in synaptic conductance.

[0047] Figure 4 The structure of a neuromorphic system according to one or more embodiments of the present invention is depicted, which is implemented as a network using a crossbar array coupled to a plurality of neurons. The depicted neuromorphic system 400 includes a plurality of neurons 414, 416, 418, and 420 interconnected using a crossbar array 200. In one example, the crossbar array 200 has a pitch in the range of about 0.1 nm to 10 μm. The system 400 also includes a synaptic device 422, which includes an NVM device 210 used as a variable state resistor at the intersection junction of the crossbar array 412. The synaptic device 422 is connected to an axon path 424, a dendrite path 426, and a membrane path 427, such that the axon path 424 and the membrane path 427 are orthogonal to the dendrite 426. The terms "axon path", "dendritic path", and "membrane path" are sometimes referred to as "axon", "dendrite", and "membrane", respectively.

[0048] Spiking electronic neurons integrate inputs from other neurons through programmable NVM synapses (e.g., PCM devices) and spike when the integrated input exceeds a predetermined threshold. For example, in an implementation of STDP in a neuromorphic network (referred to as binary probabilistic STDP), each electronic neuron uses a simple resistor-capacitor (RC) circuit to remember its last spike event. Thus, when an electronic neuron spikes, several events occur, as described below. In one example, a spiking neuron charges an internal "memory" capacitor to V0, where the potential across the capacitor varies according to V t =V0e -t / RC Attenuation, where RC = 50ms.

[0049] Spiking neurons send nanosecond "warning" pulses on their axons and dendrites. If the alert pulse generated at the axon is a voltage spike, downstream neurons receive a current signal weighted by the conductance of the synapse (PCM device) between each pair of involved neurons (which can then be integrated by downstream neurons). Alert pulses generated at the dendrites are not integrated by upstream neurons, but act as handshake signals, relaying information to those neurons indicating that a programming pulse to the synapse is imminent.

[0050] After a finite delay, the spiking neuron generates a semi-programming pulse which by itself cannot induce programming of the synapse (PCM device). The upstream and downstream neurons that receive the alarm pulse respond earlier (depending on the time elapsed since the last firing of each neuron, as retained in the internal capacitor) via appropriate pulses with modulated amplitudes. Each response pulse is combined with a semi-programming pulse to program each synapse (PCM device) at the cross-point junction of the neurons involved to achieve STDP. The postsynaptic neuron responds by sending a rectangular pulse that effectively increases the resistance of the synapse (i.e., decreases the conductance), while the presynaptic neuron responds by sending a triangular pulse that effectively decreases the resistance of the synapse (i.e., increases the conductance).

[0051] The arbitrary and plastic connectivity between the electronic neurons is achieved using a crossbar array 200 (which may be a nanoscale crossbar array including NVM devices 210 at the crossbars). Each synaptic device 422 further includes an access or control device 425, which may include a field effect transistor (FET) that is not wired as a diode at each crossbar joint to prevent crosstalk during signal communication (neuron firing events) and minimize leakage and power consumption. It should be noted that in other embodiments, other types of circuits may be used as control devices 425, and FETs are used as a possible example in the description herein.

[0052] Electronic neurons 414, 416, 418, and 420 are configured as circuits at the periphery of the crossbar array 200. In addition to being simple in design and manufacture, the crossbar architecture also provides efficient use of available space. The full neuron connectivity inherent to the full crossbar array can be converted into any arbitrary connectivity by electrical initialization or by omitting masking steps at undesirable locations during manufacturing. The crossbar array 200 can be configured to customize communication between neurons (e.g., a neuron never communicates with another neuron). Arbitrary connections can be obtained by blocking certain synapses at the manufacturing level. Therefore, the architectural principles of system 400 can mimic all direct wiring combinations observed in biological neuron morphological networks.

[0053] The crossbar array 200 further includes driver devices X2, X3 and X4, such as Figure 4 As shown. Devices X2, X3, and X4 may include interface driver devices. Specifically, dendrite 426 has driver device X2 on one side of crossbar array 200 and level converter device (e.g., sense amplifier) ​​X4 on the other side of the crossbar array. Axon 424 has driver device X3 on one side of crossbar array 200. The driver devices may include CMOS logic circuits that implement the functions described herein, such as the "west" side and the "south" side ( Figure 3 ).

[0054] Sense amplifier device X4 feeds excitation spike electronic neurons (Ne) 414, 416 and 418, which in turn are connected to axon driver device X3 and dendrite driver device X2. Neuron 420 is an inhibitory spike electronic neuron (Ni). In general, an excitation spike electronic neuron makes its target neuron more likely to excite, while an inhibitory spike electronic neuron makes its target neuron less likely to excite. Various implementations of spike electronic neurons can be used. In general, such neurons include a counter that increases when receiving input from a source excitatory neuron and decreases when receiving input from a source inhibitory neuron. The amount of increase or decrease depends on the strength of the connection from the source neuron to the target neuron. If the counter reaches a certain threshold, the neuron then generates its own spike (i.e., excitation) and the counter undergoes a reset to a baseline value. The term spike electronic neuron is referred to herein as an "electronic neuron".

[0055] In one example scenario, neurons 414, 416, 418, and 420 are dendritic neurons. Each dendritic neuron receives an input from a corresponding converter device X4. Neurons 414, 416, 418, and 420 also include outputs and generate signals to multiple devices X2, X3 along paths 415 and 417, respectively. Thus, neurons 414, 416, 418, and 420 can act as axon neurons when generating outputs along axon connections. When any of neurons 414, 416, 418, and 420 fire, they send pulses to their axons and their dendritic connections.

[0056] In this example, each of the excitatory neurons 414, 416, 418 (Ne) is configured to provide integration and firing. Each inhibitory neuron 420 is configured to modulate the activity of the excitatory neurons, depending on the overall network activity. As will be appreciated by those skilled in the art, the exact number of excitatory neurons and inhibitory neurons may vary depending on the nature of the problem to be solved using the neuromorphic system 400.

[0057] A read spike of short duration may be applied to the axon driver device X3 for communication. An extended pulse may be applied to the axon driver device X3 midway through the axon driver pulse, and a short negative pulse may be applied to the dendrite driver device X2 for programming. In this manner, the axon driver device X3 provides a long programming pulse and a communication spike. The dendrite driver device X2 provides a programming pulse with a delay. In one or more embodiments of the present invention in which analog logic circuits are used to implement the neuron circuit, the corresponding sense amplifier X4 converts the synaptic current level into a neuron current level for integration. Alternatively or additionally, in the case where a digital logic circuit is used to implement the neuron circuit, the corresponding sense amplifier X4 converts the synaptic current level into a binary digital signal for integration.

[0058] FET driven synaptic device 422 implements STDP in a time phased manner. Such an implementation allows for the implementation of high density electronic spike neural networks, where the spikes of neurons are confined to certain time phases or global timing references, thereby providing programmed activity in synapses that are phased. Generally speaking, according to embodiments of the present invention, an axonal neuron "spikes" or "excites" (fires a pulse) when the input it receives from a dendritic input connection exceeds a threshold. In one example, the typical frequency required to simulate biological phenomena is about 10KHz, leaving ample time windows for communication and programming of nanoscale electronic components.

[0059] In one or more embodiments of the present invention, synaptic weight updates and communications in the neuromorphic network 10 are limited to specific phases of a global timing reference signal (i.e., a global clock) to implement STDP. Since communications in the network are limited to certain phases of the global timing reference signal, FET devices 425 are used as access or control devices in synapses (PCM devices) 422. When a neuron fires a spike, the spike is transmitted to the X2 and X3 drivers, where each X3 driver controls the source and gate of the FET 425 in the corresponding synapse 422 via two conductive paths 424 and 427, respectively. In each synapse 422, the gate terminal of each FET is used as a connection to the membrane of the presynaptic neuron to achieve precise control of the current flowing through the connected programmable resistor.

[0060] Typically, the combined action of the signals from drivers X2 and X3 in response to spike signals from an excited neuron in the crossbar array 412 causes the NVM device 210 in the synapse 422 at the junction of its crossbar array to change value based on the spike timing action of the excited neuron. This provides programming of the NVM device 210. In an analog implementation of neurons, each stage of converter device X4 includes circuitry configured to convert the amount of current from each corresponding synapse 422 for integration by the corresponding neuron. For a digital implementation of neurons, each stage of converter device X4 is a sense amplifier for implementing the same function.

[0061] The timing of passing signals from neurons in the crossbar array 200 to devices X2, X3, X4, and the timing of devices X2, X3, X4 in generating signals, allows programming of synapses. One implementation includes changing the state of NVM device 210 by increasing or decreasing the conductance of NVM device 210 as a function of time since the last spike of the electronic neuron fired spike signals into the axon driver and dendrite driver coupled by NVM device 210. In general, neurons generate spike signals and devices X2, X3, and X4 interpret these spike signals and, in response, generate the signals described above for programming synapses 422. Synapses and neurons can be analog or digital.

[0062] In one example, a read spike of short duration (e.g., about 0.1 ms long) is applied to the axon driver device X3 for communication. An extended pulse (e.g., about 200 ms long) is applied to the axon driver device X3. A short negative pulse (e.g., about 50 ns long) is applied to the dendrite driver device X2 approximately midway through the axon driver pulse to program the synapse 422. In this manner, the axon driver device X3 provides a long programming pulse and a communication spike.

[0063] These signaling techniques are used to use Figure 2A , Figure 2B and Figure 2C The crossbar array 200 depicted in FIG. 1 implements the operation of DNN 100. Figure 2A , the forward pass includes processing data through the neuron layers (110, 120, and 130), using the synaptic network to perform multiply-accumulate operations. The matrix-vector multiplication associated with the forward pass can be implemented with O(1) complexity using the depicted crossbar array 200. For example, to perform Ax=b, where A is a matrix and x and b are vectors, the elements of A are linearly mapped to the conductance values ​​of the PCM devices 210 organized in the crossbar 200. The x value is encoded as the amplitude or duration of the read voltage applied along the row. The positive and negative elements of A are encoded on separate devices along with the subtraction circuit. Alternatively, in one or more instances, the negative vector elements are applied as negative voltages. The resulting current along the column is proportional to the result b. If the input is encoded as a duration, the result b is the total charge (e.g., the current integrated over time). The properties of the NVM device 210 used are multi-level storage capability and Kirchhoff's circuit laws: Ohm's law and Kirchhoff's current law.

[0064] Figure 2B Depicted is the backward propagation performed by the crossbar array 200. The same crossbar configuration can be used to perform matrix-vector multiplication with the transpose A. To do this, the input voltage is applied to the column lines and the resulting current is measured along the rows. Thus, backward propagation involves multiplication with the transpose of the matrix representing the synaptic weights, which can be implemented with O(1) complexity in the same manner as described above for forward propagation.

[0065] Figure 2C A weight update is depicted where matrix elements are mapped to conductance values ​​of NVM device 210. Such a mapping may be achieved by iterative programming using programming curves as described herein.

[0066] It should be noted that the description of the crossbar array 210 and the neuromorphic system 400 is one possible example implementation, and that one or more embodiments of the present invention may be used in other types of implementations.

[0067] Typically, programming (updating weights) of the NVM device 210 is accomplished by iteratively applying set pulses with a steadily increasing compliance current. Unlike a RESET pulse that may cause an abrupt switch to a lower conductance value, the continuous application of partial SET pulses is believed to result in a more gradual increase in the conductance value of the NVM device 210. Therefore, for the neuromorphic system 400 using the NVM device 210, in existing solutions, partial SET pulses are used to implement synaptic plasticity rules.

[0068] For example, a typical programming strategy for analog conductance tuning of NVM devices 210 is to iteratively apply SET pulses with steadily increasing compliance current (while also potentially increasing pulse duration) to reach a target analog conductance value. However, this technique presents technical challenges. For example, after reaching a certain current threshold, a subset of NVM devices 210 may partially reset during the applied pulse, resulting in a decrease in conductance rather than an increase. As the number of NVM devices 210 increases, the current threshold varies with the PCM devices, making it difficult to control a crossbar array.

[0069] One or more embodiments of the present invention address this technical challenge by using programming techniques. One or more embodiments of the present invention use a strategy to iteratively apply RESET pulses with decreasing compliance current (while also potentially increasing pulse duration) to achieve a target conductance. When the compliance current drops below the current threshold for reset, the pulse becomes a set pulse, but even if the programming conditions are no longer valid, the PCM conductance value remains at or near the highest conductance value. In addition, as experiments have shown, the accuracy at low conductance values ​​is significantly improved compared to the prior art. The programming techniques demonstrated using one or more embodiments of the present invention are compatible with row-by-row programming schemes and can be completed in a limited number of cycles. The programming results tolerate device-to-device variability in the array. Further, the techniques described herein minimize the circuit area and power costs associated with physical implementation by using only two bits per weight: one participating bit and one sign bit. From the description herein, other advantages and practical applications of one or more embodiments of the present invention will be apparent.

[0070] One or more embodiments of the present invention solve the technical challenges of the prior art by using an iterative programming sequence that achieves a desired analog conductance value in a crossbar array of PCM devices in the presence of variability. The programming sequence is iterative, but uses a finite number of programming steps to bring the conductance value to within a desired range from the target analog conductance.

[0071] The programming sequence begins by initializing all NVM devices in a soft reset state, and then iterates programming by first tuning the reset pulse length at a certain compliance current, and then gradually reducing the compliance current until the NVM conductance is within the target range. The exact programming parameters, such as the compliance current and the duration of the pulse, depend on the crossbar array. One or more embodiments of the present invention facilitate how to determine these programming parameters through crossbar array characterization. The programmed weights in the crossbar array are displayed to achieve reasonable performance of the DNN (e.g., for forward inference). Using multiple pairs of conductances to represent a weight in the DNN also improves programming accuracy.

[0072] Figure 5A schematic diagram for mapping weights into phase change memory devices according to one or more embodiments of the present invention is depicted. A group of NVM neighboring devices 210 from a crossbar array 200 are configured to form a "conductance cell" 510. The conductance cell 510 is used to represent a weight value from a DNN 100. Figure 5 In the illustrated example of FIG. 5 , two pairs (i.e., four PCM devices 210 from the crossbar array 200) are mapped to weights by programming the conductance values ​​of the four PCM devices 210 in the conductance cell 510. The total weight (in conductance, e.g., μS) is the weighted sum of the four PCM conductance values, which are divided into more significant pairs (MSPs) 512 and less significant pairs (LSPs) 514 whose significance factor of conductance value is F. Thus, the weight associated with the conductance cell 510 including two pairs of PCM devices 210 can be represented by W=F(G+-G-)+g+-g-, where (G + , G - ) are conductance values ​​of the PCM devices 210 in the MSP 512, and (g+, g-) are conductance values ​​of the PCM devices 210 in the LSP 514. Initially, + and - signs are assigned to the PCM devices 210. Designating the PCM devices 210 as part of the MSP / LSP and further assigning signs to the PCM devices 210 may be part of assigning a "role" to each PCM device 210 in the crossbar array 200. The significance factor F is a predetermined value and may be a different value associated with each column of the PCM devices 210 in the crossbar array.

[0073] The weights in conductance units are then mapped to software weights 520 of the DNN 100 using a scaling factor α. For example, the software weights may have to be scaled to a dynamic range supported by the non-volatile memory device 210. The dynamic range indicates the range of current values ​​that the NVM device 210 can contribute based on the range of device conductances that it can maintain. The set of distinguishable current values ​​represents the effective bit resolution of the analog memory device. The dynamic range reflects the maximum and minimum values ​​of the weights or conductances that appear in the target set of weights / conductances. The effective bit resolution is determined by device characteristics (such as read and write noise); the dynamic range in conductance depends on the F factor and the conductance range of each analog memory device, while the dynamic range in software weights depends on the software training process (e.g., hyperparameters, optimizer, etc.). The dynamic range can be a given range of values ​​of pre-trained weights to be programmed.

[0074] The significance factor F and the scaling factor α are optimized using a configurable value referred to herein as "Probability of Programming Failure (Pfail)". When the target weights are mapped to a low conductance range, the conductance response of the PCM device 210 is rough. On the other hand, when the target weights are mapped to a high conductance range, Pfail increases due to the limited conductance range of the PCM device 210. A high F indicates an imbalance between the MSP 512 and the LSP 514, which may adversely affect the weight convergence on the PCM device 210 in the cross-array. A low F (e.g., F<1) effectively reverses the roles of the MSP 512 and the LSP 514 and also results in a higher Pfail. In one or more embodiments of the present invention, Pfail is dynamically calculated by counting the number of weights that are not within the target conductance range.

[0075] According to one or more embodiments of the present invention, the conductance unit 510 further includes a selection / participation flag 516, which is used to indicate that the conductance unit 510 is selected for subsequent conductance value updates. For example, the selection flag 516 can be a bit, where a bit of 1 (or 0) can indicate that the conductance unit 510 will be updated in a subsequent iteration. In this case, marking the selection flag 516 as 0 (or 1) can indicate that the conductance unit 510 is removed from a group of conductance units to be updated in subsequent iterations. It should be understood that the selection flag 516 can be implemented in any other way besides using a bit.

[0076] Figure 6 Depicted is a visualization of mapping desired weights to conductance cells in accordance with one or more embodiments of the present invention. The mapping is performed over four stages (602, 604, 606, and 608), in each stage the conductance of one of the four PCM devices 210 from the conductance cell 510 is adjusted. The adjustment is performed using closed-loop programming to reduce the error between the desired weight (WD) to be configured for the conductance cell 510 and the actual weight W of the conductance cell 510. The error = WW D Alternatively, the error can be calculated as W D -W, or the absolute value of the subtraction. The error threshold 620 is used to check whether the conductance value that has been adjusted is satisfactory or whether further adjustment of the conductance value is required. Closed-loop programming is performed to ensure that the calculated error is within the predetermined error threshold 620, and the conductance value is adjusted until the condition is met.

[0077] Closed loop programming includes pulse width and compliance current modulation. In one or more embodiments of the invention, pulse width modulation is used to account for conductance cells 510 below and above a predetermined threshold as a target. Once a conductance cell 510 has a weight that is substantially within a predetermined threshold 620 (e.g., ±0.25uS) of the desired weight, the conductance cell 510 is removed from the set of conductance cells that must be adjusted in subsequent iterations. According to one or more embodiments of the invention, the compliance current is adjusted from hard reset to partial reset to partial set to reset the PCM device 510 so as to gradually increase the PCM conductance until it reaches near the desired target conductance. Here, "near the desired target conductance" indicates that the weight (W) of the conductance cell 510 is within a certain distance from the target weight (W D ) is within the threshold of 620.

[0078] In one or more embodiments of the present invention, positive weights are mapped using W = FG++g+, and negative weights G - and g - Keep in reset state. Further, for negative weights, negative weights are mapped in the opposite way. In addition, first G + Program it and then use g+ or g- to correct the residual. + (or G - ) programming operation, so that G - (or G + ) is in reset state, resulting in a symmetrical noise distribution. The programming error on G is multiplied by a factor of F (eg, F=3).

[0079] Figure 7 An example of a reduced current scan according to one or more embodiments of the present invention is shown. The depicted graph 700 shows a reduced current scan performed as an initial pulse sequence, where each conductance unit 510 receives a reduced value (amplitude) of compliance current for a predetermined duration (i.e., pulse width), for example, tp=24ns. The compliance current value received by each conductance unit 510 is based on a uniform target, for example, 2μS. In other embodiments, the pulse width and uniform target predetermined for the conductance units 510 may be different. The compliance current value may be a predetermined value based on the cross-array 200.

[0080] After this first sequence of compliance current sweeps, errors are calculated at each conductance cell 510 to determine which of the conductance cells 510 have reached their target weights. Based on the calculated errors, only certain conductance cells 510 (i.e., certain groups of PCM devices 210) are selected to participate in subsequent pulse sweeps. PCM devices 210 that successfully fall within the "target confidence" range are not selected (removed from) in the group of PCM devices 210 that receive subsequent pulses. Here, the "target confidence" range is based on the conductance response to the previous programming pulses, as well as the conductance cells 510. Further, when the error between the target weight and the actual weight is within a predetermined threshold 620, the PCM devices in such conductance cells are marked as being within the target confidence range. In addition, multiple sequences of pulses of different constant durations (each sequence comprising a full sweep from a high current value to a low current value) are applied to the selected conductance cells 510.

[0081] Figure 8 Depicted are pulse trains sent to a conductance cell according to one or more embodiments of the present invention. As shown in graph 800, an initial compliance current sweep 700 of a predetermined uniform target is completed as the current sweep is reduced at a constant pulse duration. Additional pulse trains 810 are sent with variable pulse widths based on a target confidence range for the conductance cell 510 after the initial current sweep 700. The pulse width of each pulse train 810 depends on the error at the conductance cell 510 receiving the pulse train.

[0082] After each set of variable width pulse trains 810, selection of conductance cells 510 within a target confidence range is performed based on the error at each conductance cell 510. For those conductance cells 510 that are not yet within the target confidence range, the process is iterated by sending additional variable width pulse trains 810 and checking the corresponding errors.

[0083] Programming the conductance cells 510 in the crossbar array 200 in this manner achieves accurate conductance programming despite the variability of the devices in the crossbar array 200. Further, weight programming using one or more conductance pairs to represent each weight shows lower noise compared to the conductance programming noise from a single device. Moreover, in one or more embodiments of the present invention, mapping the weights to 4 PCM devices 210 (2 pairs of PCM) significantly reduces the weight error. However, it should be noted that in other embodiments of the present invention, the weights can be mapped to a different number of PCM devices 210 configured as conductance cells 510. Different experiments performed have demonstrated that in one or more embodiments of the present invention, software equivalent accuracy is achieved for DNNs (e.g., long-short-term-memory networks) using weight mapping and programming techniques.

[0084] Fig. 9A flow chart of a method for programming neural network weights into simulated synapses implemented using a crossbar array according to one or more embodiments of the present invention is depicted. In this case, the synapse is a conductance unit 510 and is a pair or more pairs of non-volatile memory devices, such as PCM devices 210 in a crossbar array 200. The method includes mapping the neural network weights to the set of target weight values ​​representing the desired read current at 910. The mapping may include calibrating what current value represents what weight value in the synapse based on the dynamic range of the PCM device 210.

[0085] The method further includes assigning each PCM device 210 within each simulated synapse 510 to one of a set of roles at 920, wherein each role is uniquely identified by both simulated significance and sign. Setting the role includes configuring a group of one or more PCM devices 210 as part of a conductance cell 510, wherein the conductance of the conductance cell 510 represents a weight value of the simulated synapse. In other words, the conductance cell 510 represents a simulated synapse from the DNN 100. Further, setting the role may include associating the PCM device 210 as part of the MSP 514 or the LSP 512, and the position in either. The position may be set using a sign flag (e.g., a bit). The sign flag indicates the order in which the PCM devices 210 in the conductance cell 510 are updated during weight update / programming.

[0086] The method further includes programming the synapses with the weights at 930. Programming the synapses includes extracting, at 932, a vector of target weight values ​​representing a corresponding subset of the set of PCM devices 210 from each row, column, or other addressable subset of the crossbar array 200 simulating synapses. Further, the method includes assigning, at 934, a target sign bit corresponding to the sign of its target weight value to each of the PCM devices 210. Further, the method includes iteratively programming, at 936, each PCM device 210 within the vector simulating synapses from the MSP 512 to the LSP 514 with a sign bit identifying the order in which the members of the pair should be programmed. For example, in one or more embodiments of the present invention, the positive (+) PCM devices 210 are programmed first. In other embodiments, the negative (-) assigned PCM devices 210 are programmed first.

[0087] Further, for each pulse duration in a set of pulse durations representing active pulse durations, a participation bit vector is assigned, each participation bit corresponding to one of the PCM devices 210 in the target weight vector, wherein the participation bit is activated for any synapse requiring additional programming of the conductance role programmed in each synapse at 938. The participation bit indicates that the conductance value must be further adjusted using one or more pulse sequences.

[0088] At 940, the method further includes iteratively applying conductance programming pulses to all PCM devices in the conductance cell using the active participation bits within the activity vectors of the synapses. In one or more examples, the (multiple) pulse trains are applied starting from a higher programming current and progressing (decreasing) toward a lower programming current. In each iteration, the method includes measuring, at 942, a total effective weight of each member of the vector of active synapses and comparing it to an associated target weight value. At 942, based on the comparison, for synapses whose measured weight values ​​have reached the associated target weight value (i.e., the error is less than (or equal to) the predetermined threshold 620), clearing the participation bits of the active synapses.

[0089] The above programming steps are repeated with a sequence of programming pulses, but with (i) longer pulses at 944 to account for under-programmed conductance values, and (ii) shorter pulses at 946 to account for over-programmed conductance values. Here, under-programming indicates that the desired conductance is greater than the actual conductance, while over-programming indicates that the desired conductance is less than the actual conductance in the PCM device 210.

[0090] At 950 , programming is repeated until all conductance roles are resolved from higher importance to lower importance across the crossbar array 200 .

[0091] The nonvolatile memory device 210 in the crossbar array 200 may be any one of a phase change memory (PCM) device, a resistive random access memory (RRAM), and the like.

[0092] Accordingly, one or more embodiments of the present invention provide an iterative programming sequence that achieves a desired analog conductance value in a crossbar array of NVM devices (such as PCM devices) in the presence of variability. The provided programming sequence is iterative and uses a finite number of programming steps to bring the conductance value to within a desired range from a target analog conductance. As described in detail, the programming sequence begins by initializing all PCM devices in a soft reset state and then iteratively programming by first tuning the reset pulse length at a certain compliance current and then gradually reducing the compliance current until the PCM conductance is within the target range. The exact programming parameters (such as the compliance current and the duration of the pulse) will depend on the crossbar array and can be configurable predetermined parameters. The programmed weights in the crossbar array can be used to implement a DNN, such as for forward inference.

[0093] According to one or more embodiments of the invention, multiple pairs of conductances are used to represent a weight in a DNN to improve programming accuracy.

[0094] The present invention may be a system, method, and / or computer program product of any possible integrated technical detail level. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, and the computer-readable program instructions are used to cause a processor to perform various aspects of the present invention.

[0095] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punch card or a raised structure in a groove with instructions recorded thereon), and any suitable combination of the above. As used herein, a computer-readable storage medium should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by a fiber optic cable), or an electrical signal transmitted by a wire.

[0096] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0097] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and procedural programming languages, such as "C" programming language or similar programming languages. The computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (for example, by using the Internet of an Internet service provider). In some embodiments, an electronic circuit (including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA)) can execute a computer-readable program instruction to personalize the electronic circuit by utilizing the state information of the computer-readable program instructions, so as to perform various aspects of the present invention.

[0098] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0099] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine that is executed by a processor of a computer or other programmable data processing device to create a device for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing device, and / or other device to function in a particular manner, such that a computer-readable storage medium having instructions stored therein includes an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0100] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other apparatus (which causes a series of operational steps to be performed on the computer, other programmable apparatus, or other device) to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0101] The flow chart and block diagram in the accompanying drawings show the architecture, function and operation of the possible implementation of the system, method and computer program product according to various embodiments of the present invention. To this end, each box in the flow chart or block diagram can represent a part of a module, segment or instruction, which includes one or more executable instructions for realizing the specified logical function. In some alternative embodiments, the function marked in the box may not occur in the order marked in the figure. For example, depending on the function involved, the two boxes shown in succession can actually be executed substantially at the same time, or these boxes can sometimes be executed in reverse order. It will also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a system based on special-purpose hardware, and the system based on special-purpose hardware performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0102] The description of different embodiments of the present invention has been presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments described herein.

[0103] In one example of the present invention, a computer-implemented method is provided, the method comprising: configuring two pairs of phase change memory devices from a plurality of phase change memory devices in a crossbar array as conductance units, wherein the plurality of conductance units represent a plurality of simulated synapses in an artificial neural network; sending a pulse sequence to the plurality of simulated synapses in the crossbar array, wherein a weight value of the simulated synapse is based on a conductance value of the conductance unit, and the pulse sequence changes the conductance value of the conductance unit; and updating a weight value of each simulated synapse from the selected group of simulated synapses by sending a pulse sequence to the group of simulated synapses, the group of electrical pulses changing the conductance value of the conductance unit corresponding to the group of simulated synapses, wherein the group of simulated synapses from the crossbar array is selected based on comparing the weight values ​​of the plurality of simulated synapses with target weight values ​​associated with the simulated synapses.

[0104] In another example of the present invention, a crossbar array is provided, comprising: a plurality of phase change memory devices, one of the phase change memory devices being located at each of a plurality of crossbars in the crossbar array, wherein each group of four phase change memory devices forms a conductance unit, and the plurality of conductance units represent a plurality of simulated synapses in an artificial neural network; a circuit is configured to program conductance values ​​of the phase change memory devices by executing a method, the method comprising: receiving a pulse train of a plurality of simulated synapses in the crossbar array, wherein a weight value of the simulated synapse is based on a conductance value of the conductance unit, the pulse train changing the conductance value of the conductance unit; and updating a weight value of each simulated synapse in a selected group of simulated synapses by receiving a group of electrical pulses with varying durations for the group of simulated synapses, the group of simulated synapses changing the conductance value of the conductance unit corresponding to the group of simulated synapses, wherein the group of simulated synapses from the crossbar array is selected based on comparing the weight values ​​of the plurality of simulated synapses with target weight values ​​associated with the simulated synapses.

Claims

1. A computer-implemented method comprising: updating initial weight values ​​associated with a plurality of simulated synapses in a crossbar array implementing an artificial neural network by sending a pulse train to the plurality of simulated synapses, each of the simulated synapses comprising a conductance unit, wherein the updated weight value of the simulated synapse is based on a conductance value of the conductance unit, the pulse train changing the conductance value of the conductance unit; comparing the updated weight values ​​of the plurality of simulated synapses to target weight values ​​associated with the simulated synapses; selecting a set of simulated synapses from the crossbar array based on the comparing, the selecting being indicated using selection flags associated with the simulated synapses; as well as The weight value of each simulated synapse in the selected set of simulated synapses is updated by sending a set of electrical pulses of varying duration to the set of simulated synapses, the set of electrical pulses changing the conductance value of the conductance unit corresponding to the set of simulated synapses.

2. The method of claim 1, wherein: The pulse train sent to the plurality of simulated synapses has a predetermined duration, and wherein the uniform weight pulse train includes a plurality of current pulses having decreasing amplitudes.

3. The method of claim 1, wherein: The conductance unit includes a plurality of non-volatile memory devices.

4. The method of claim 3, wherein: A weight value associated with the simulated synapse is calculated based on the conductance value of each of the plurality of non-volatile memory devices.

5. The method of claim 4, wherein: The non-volatile memory device is a phase change memory device.

6. The method of claim 4, wherein: The non-volatile memory device is a resistive random access memory device.

7. The method of claim 4, wherein: The plurality of nonvolatile memory devices include four nonvolatile memory devices configured to form a more significant pair (MSP) and a less significant pair (LSP).

8. The method of claim 7, wherein the weight value of the simulated synapse is calculated as W=Fx(G + -G - )+g + -g - , where F is the scaling factor and G + and G - is the conductance value of the MSP, and g + and g - is the conductance value of the LSP.

9. The method of claim 7, wherein: Changing the conductance value of the conductance unit includes changing the conductance value of each of the non-volatile memory devices from the conductance unit according to a predetermined sequence for updating the conductance values.

10. The method of claim 9, wherein: According to the predetermined sequence, the conductance values ​​of the non-volatile memory devices in the MSP are updated first.

11. The method of claim 10, wherein: Further in accordance with the predetermined sequence, the conductance value of the non-volatile memory device in the MSP is updated according to a flag flag associated with the non-volatile memory device.

12. The method of claim 1, wherein: Selecting the set of simulated synapses includes selecting the set of simulated synapses whose weight values ​​have a difference with a target value greater than a predetermined threshold.

13. The method of claim 1, further comprising: A first simulated synapse is removed from the set of simulated synapses, wherein the difference between the weight value of the first simulated synapse and the target weight value is within the predetermined threshold.

14. The method of claim 13, wherein: In response to the weight value of the first simulated synapse being updated by the set of electrical pulses having varying durations, the first simulated synapse is removed from the set of simulated devices.

15. The method of claim 1, wherein: The set of electrical pulses having varying durations includes a first electrical pulse for a first simulated synapse, the first electrical pulse being based on a first difference between the weight value and the target weight value of the first simulated synapse.

16. A system comprising: A processor; as well as A coprocessor comprising one or more crossbar arrays; and among them The processor is configured to implement the artificial neural network using the coprocessor by mapping the layers of the artificial neural network with a crossbar array, wherein implementing the artificial neural network comprises a method comprising: updating initial weight values ​​associated with a plurality of simulated synapses in a crossbar array implementing an artificial neural network by sending a pulse train to the plurality of simulated synapses, each of the simulated synapses comprising a conductance unit, wherein the updated weight value of the simulated synapse is based on a conductance value of the conductance unit, the pulse train changing the conductance value of the conductance unit; comparing the updated weight values ​​of the plurality of simulated synapses to target weight values ​​associated with the simulated synapses; selecting a set of simulated synapses from the crossbar array based on the comparing, the selecting being indicated using selection flags associated with the simulated synapses; and The weight value of each simulated synapse in the selected set of simulated synapses is updated by sending a set of electrical pulses of varying duration to the set of simulated synapses, the set of electrical pulses changing the conductance value of the conductance unit corresponding to the set of simulated synapses.

17. The system of claim 16, wherein: The conductance unit includes a plurality of non-volatile memory devices.

18. The system of claim 17, wherein: A weight value associated with the simulated synapse is calculated based on the conductance value of each of the plurality of non-volatile memory devices.

19. The system of claim 18, wherein: The plurality of nonvolatile memory devices include four nonvolatile memory devices configured to form a more significant pair (MSP) and a less significant pair (LSP), and wherein the weight value of the simulated synapse is calculated as W=Fx(G + -G - )+g + -g - , where F is a scaling factor and G + and G - is the conductance value of the MSP, and g + and g - is the conductance value of the LSP.

20. A computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a processing circuit to perform a method of implementing an artificial neural network by mapping layers of the artificial neural network with a crossbar array, wherein implementing the artificial neural network comprises: updating initial weight values ​​associated with a plurality of simulated synapses in a crossbar array implementing an artificial neural network by sending a pulse train to the plurality of simulated synapses, each of the simulated synapses comprising a conductance unit, wherein the updated weight value of the simulated synapse is based on a conductance value of the conductance unit, the pulse train changing the conductance value of the conductance unit; comparing the updated weight values ​​of the plurality of simulated synapses to target weight values ​​associated with the simulated synapses; selecting a set of simulated synapses from the crossbar array based on the comparing, the selecting being indicated using selection flags associated with the simulated synapses; as well as The weight value of each simulated synapse in the selected set of simulated synapses is updated by sending a set of electrical pulses of varying duration to the set of simulated synapses, the set of electrical pulses changing the conductance value of the conductance unit corresponding to the set of simulated synapses.

21. The computer program product of claim 20, wherein: The conductance unit includes a plurality of non-volatile memory devices.

22. The computer program product of claim 21, wherein: A weight value associated with the simulated synapse is calculated based on the conductance value of each of the plurality of non-volatile memory devices.

23. The computer program product of claim 22, wherein: The plurality of nonvolatile memory devices include four nonvolatile memory devices configured to form a more significant pair (MSP) and a less significant pair (LSP), and wherein the weight value of the simulated synapse is calculated as W=Fx(G + -G - )+g + -g - , where F is a scaling factor and G + and G - is the conductance value of the MSP, and g + and g - is the conductance value of the LSP.

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