Memory components equipped with a JTAG test interface including an instruction register matrix.

Abstract

A memory component includes: a memory cell comprising an array of memory cells; a controller for the memory cell; and a JTAG test interface including a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine, wherein the test interface further includes a plurality of test registers configured to store operational instructions for performing the tests on the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. Related system-on-a-chip devices and related methods are also disclosed.

Description

Technical Field

[0001] This disclosure relates to memory devices, and more specifically, to memory components provided with test interfaces. Background Technology

[0002] Non-volatile flash memory is now a fundamental building block of modern electronic systems, especially real-time operating systems (RTOS). Typically, the operation of non-volatile flash memory is managed by a controller containing embedded firmware, which performs the necessary write / read / erase operations.

[0003] Flash memory’s performance in terms of speed, power consumption, modifiability, non-volatility, and increasingly important system reconfigurability has so far driven its integration into system-on-chip (SoC) devices.

[0004] A System-on-a-Chip (SoC) is a semiconductor integrated circuit that integrates all the components of a computer or other electronic system. These components typically include a central processing unit (CPU), an SoC controller, a memory section, input / output ports, and secondary storage components, all of which reside on a single semiconductor substrate. Depending on the application, an SoC can contain digital, analog, mixed-signal, and commonly used radio frequency (RF) signal processing functions. Because these functions are integrated on a single electronic substrate, SoC devices consume significantly less power and occupy a much smaller area compared to multi-chip designs with equivalent functionality. SoC devices are now ubiquitous in mobile computing, embedded systems, and the Internet of Things (IoT).

[0005] As lithography technology nodes drop below 28nm, it becomes increasingly difficult to manage the non-volatile memory portion (i.e., eFlash) embedded in SoCs. The increasing demand for on-board memory in SoCs is reaching physical limits, and with current technology, it is no longer convenient to use eFlash components whose size is increasingly close to these physical limits.

[0006] Therefore, there is a need for new interface architectures that can be easily integrated into SoCs and improve the performance of non-volatile memory. Simultaneously, there is a need to improve the interface between the memory and the SoC or test machine by enabling efficient testing of such memory via the SoC or dedicated test machine. Summary of the Invention

[0007] According to one aspect of this disclosure, a memory component is provided. The memory component includes: a memory cell comprising an array of memory cells; a controller for the memory cell; and a JTAG test interface including a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine, wherein the test interface further includes a plurality of test registers configured to be loaded with operational instructions for performing the tests on the memory component, and wherein the test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address.

[0008] According to another aspect of this disclosure, a system-on-a-chip (SoC) device including a memory component is provided. The memory component includes: a memory cell comprising an array of memory cells; a controller for the memory cell; and a JTAG test interface including a plurality of contact pads adapted to connect the memory component to the SoC and / or a test machine, wherein the test interface further includes a plurality of test registers configured to be loaded with operational instructions for performing the tests on the memory component, and wherein the test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address.

[0009] According to another aspect of this disclosure, a method is provided for performing tests on a memory component of the type comprising memory cells, the memory cells including an array of memory cells. The method includes the steps of: providing a plurality of test registers for the memory component, the test registers being organized into a matrix configuration, each row of the matrix being associated with a specific address; loading operational instructions for performing the tests on the memory component into the test registers; connecting the pad of the memory component to a host device and / or a test machine; and addressing one or more test registers for retrieving the test information. Attached Figure Description

[0010] Figure 1 This is a schematic perspective view of a system-on-a-chip device according to the present disclosure, which includes a memory component that replaces the embedded memory of a prior art device;

[0011] Figure 2 This is a schematic diagram of a memory component according to the present disclosure;

[0012] Figure 3 This is a schematic portion of the test interface for the memory component according to this disclosure;

[0013] Figure 4 This is a schematic diagram of a typical test access port used for the test interface of this disclosure;

[0014] Figure 5The diagram schematically illustrates test signals sent to corresponding pads of the memory components of this disclosure; and

[0015] Figure 6 A diagram illustrating method 600 according to this disclosure is shown. Detailed Implementation

[0016] Referring to those diagrams, this document discloses systems and methods relating to memory components (specifically, including non-volatile memory) with improved test interfaces.

[0017] More specifically, as will be described in detail below, an example memory component includes: a memory cell containing an array of memory cells; a controller for the memory cell; and a JTAG test interface including a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine, wherein the JTAG test interface further includes a plurality of test registers configured to be loaded with operational instructions for performing the tests on the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A system-on-a-chip (SoC) device including the memory component mentioned above is also disclosed below.

[0018] Furthermore, an example method for performing tests on a memory component of the type including memory cells (which in turn contain memory cell arrays) includes the following steps: providing a plurality of test registers for the memory component, the test registers being organized into a matrix configuration, each row of the matrix being associated with a specific address; loading operation instructions for performing the tests on the memory component into the test registers; connecting the pad of the memory component to a host device and / or a test machine; and addressing one or more test registers for retrieving the test information via an output bus.

[0019] Non-volatile memory retains its contents when power is cut off, making it a good choice for storing information that will be retrieved after the system restarts.

[0020] Flash memory is a type of non-volatile memory that retains stored data and is characterized by very fast access times. Furthermore, it can be erased in blocks, rather than one byte at a time. Each erasable memory block comprises multiple non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cell is programmed and erased by manipulating the voltages on the access and data lines.

[0021] Flash memory can be associated with a host device. According to this disclosure, such as Figure 1As shown, SoC 100 is associated with memory device 110. SoC 100 and memory device 110 are fabricated on corresponding dies obtained through different photolithography processes.

[0022] Clearly, even more complex electronic devices coupled to memory components can be provided without departing from the scope of this disclosure.

[0023] according to Figure 1 In one embodiment, the SoC 100 is associated with a new, structurally independent memory component 110, which is coupled to the SoC structure 100, for example, via multiple coupling elements 120 (sometimes referred to as pads, such as pillars, through-silicon vias (TSVs), and ball grids, flip-chip technology, wireless interconnects (coils), etc.). In a preferred embodiment, the coupling element is a pillar arranged in a semiconductor region 130 previously dedicated to a conventional embedded memory component.

[0024] More generally, memory component 110 is smaller in size compared to the larger size of SoC structure 100 and partially overlaps with SoC structure 100. The term “partially overlaps” means that memory component 110 may only partially or not completely cover an area of ​​SoC structure 100.

[0025] As will be disclosed in more detail below, multiple corresponding pads or pin terminals facing each other will be interconnected in the circuit layout to create coupling between the SoC structure 100 and the memory component 110, in which pad alignment is maintained even if the size of the memory component 110 is modified.

[0026] Now, for more specific reference Figure 2 An example will be disclosed, which will reveal the main structure of the memory component 210 according to an embodiment of the present disclosure, wherein Figure 2 Reference 210 corresponds to Figure 1 The memory component 110.

[0027] The memory component 210 includes at least I / O circuitry, a micro sequencer, a memory cell array 220 and a circuit system (specifically, array peripherals) surrounding the memory array, a charge pump architecture, an address decoder, a sense amplifier 280 and a corresponding latch, service logic connecting all parts of the memory, a command user interface (e.g., a CUI block), and a JTAG interface.

[0028] The memory cell array 220 contains non-volatile flash memory cells.

[0029] The memory array 220 of memory component 210 is constructed as a series of subarrays. The advantage of this architecture is its high scalability, where the density expansion and / or reduction of the final device only occurs when mirroring the subarrays and creating connections.

[0030] In one embodiment of this disclosure, memory component 210 implements a direct memory access type memory to replace the embedded memory array of a known SoC device.

[0031] Furthermore, the use of a JTAG interface 230 for testing and control of the memory component 210 also allows for the reuse of test tools. Therefore, the memory component 210 includes JTAG logic.

[0032] In this regard, memory component 210 includes a plurality of JTAG pads 240 that allow connection to an external test machine, and such JTAG pads 240 have the ability to manage high voltage values ​​(both positive and negative).

[0033] Clearly, the JTAG interface is also used in read and program operations.

[0034] In addition, as previously mentioned, memory component 210 includes a high-speed pad 250 that allows interconnection with the SoC structure, and memory component 210 is associated with the SoC structure.

[0035] In one embodiment of this disclosure, pads 250 for the memory component 210 are arranged on the surface of the memory component 210. More specifically, the pads 250 are arranged above the array such that when the memory component 210 is inverted, it faces the corresponding pads of the SoC structure. Semiconductor regions in known on-chip system devices that were originally occupied by embedded non-volatile memory portions are now dedicated to accommodating interconnect pads corresponding to the pads 250 of the memory component 210. This region can be used for additional user-mode interfaces and functionality.

[0036] Even larger memory components can be supported and interconnected by pads in the SoC structure, thus maintaining the position and dislocation of its interconnect pads.

[0037] Therefore, in the context of this disclosure, the SoC structure links its top side to the inverted side of the memory component 210, and the pads of the SoC structure are aligned with the mating pads 250 of the inverted memory component 210.

[0038] The memory component 210 is therefore a standalone structure, but is closely associated with the host device (i.e., with the SoC architecture).

[0039] As previously disclosed, the arrangement of the memory component pads 250 has been made on the surface of the memory components, actually on top of the array. In any case, Figure 1 and 2 The schematic diagram is not to scale and shows the position and orientation of the pad 250; it is only indicative. Furthermore, in Figure 2 The text only indicates a reduction in the number of pads, 250.

[0040] The preferred configuration of the memory component according to this disclosure thus provides a face-to-face interconnect SoC / flash array, wherein the sense amplifier 280 of the memory component 210 is connected to the SoC in a direct memory access configuration.

[0041] As previously seen, the interconnects of memory component 210 also include a JTAG interface 230 and a JTAG pad 240 for testing and other purposes.

[0042] In this way, it is possible to maintain a relatively low number of required interconnects.

[0043] Furthermore, according to embodiments of this disclosure, the memory component 210 is equipped with a flash array controller 260 (hereinafter referred to as a flash array controller), which has an architecture that allows sharing some flash array resources with the SoC controller without compromising the confidentiality of certain information stored therein (e.g., algorithms, flash array voltages, currents, and more generally, process information) and guarantees end-customer back-to-management.

[0044] Furthermore, advantageously according to this disclosure, test operations of memory component 210 (hereinafter also referred to as "test mode") are managed using a protocol based on JTAG interface 230. JTAG interface 230 is a special interface added to the chip, which, as is known in the art, is appropriately modified to improve the test mode.

[0045] More specifically, test modes can be managed via an external controller (e.g., the controller of the SoC outside the flash array) or via an external test machine.

[0046] In any case, the two methods mentioned above are based on the built-in self-test (BIST) performed by the internal flash array controller 260, in order to maintain the confidentiality of firmware portions related to sensitive technical parameters (such as timing, voltage, etc.), which are stored in the memory component 210 and should not be shared with external users.

[0047] The system controller accesses the JTAG interface through a first pad set (e.g., pad 250), but other configurations may also be provided.

[0048] Typically, pad 250 is not suitable for managing analog voltages. For this purpose, the required analog (high) voltage is managed by a dedicated module (not shown) in memory component 210. Such a module has the capability to generate and measure such analog values ​​(voltage / current).

[0049] On the other hand, the JTAG pad 240 is adapted to connect to the probes of the test machine in order to test certain specific internal structures of the memory component 210, such as the array 220. Such pads 240 typically have the ability to manage both positive and negative HV values.

[0050] The test extension performed via pad 240 is based on the system controller's (i.e., with pad 250) ability to impose maximum speed constraints on the exchanged data.

[0051] JTAG interface 230 generates address and control signals as output data and transmits them to internal flash controller 260. A memory address decoder then drives the correct voltage at the desired address. Decoder activity is enabled by charge pump 290, which is structured to maintain the secrecy of the voltage and timing used to manage the array. This decoder is coupled to a read interface, which communicates with the host or SoC device via a control and status bus. The output of the read interface is represented by a 168-bit sequence for each subarray 220. This mechanism ensures optimized read operations for the memory array. The controller checks the operation to update the status registers that can be read via JTAG. The read finite state machine uses a high-speed pad to prepare data for the SoC.

[0052] like Figure 3 As shown in more detail, all test methods are based on multiple (e.g., hundreds) test registers (hereinafter referred to as T_reg) that can be written / read via an external controller (i.e., the SoC controller) via the JTAG interface 230, via the test machine via the JTAG interface 230, and via the flash array controller 260 via the internal bus.

[0053] In other words, according to this disclosure, the memory component includes a test interface comprising a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine. Such a test interface further includes components operably connected to a controller 360 (corresponding to...). Figure 2 The controller 260) is connected to a portion 300, which in turn includes multiple test registers T_reg configured to store operational instructions for performing tests on the memory components. The test mode architecture of the memory components is therefore based on these registers.

[0054] The test register T_reg therefore contains instructions for testing memory components (e.g., parameters such as current / voltage). Typically, the test register T_reg not only contains voltage and current settings, but also enables special paths or BIST functions within the memory, or other test variations.

[0055] According to this disclosure, the test registers are organized into a matrix configuration, with each row of the matrix associated with a specific address. The controller 360 can therefore access a specific row of the matrix by selecting a specific address (hereinafter referred to as T_reg_addr).

[0056] In other words, the test register T_reg is organized into several groups, each containing a specific number of registers (e.g., N=8, 16, etc.) and associated with a specific address.

[0057] Each group (i.e., each row of the matrix) is dedicated to driving one or more macro functions (analog or digital) used to perform tests on memory components. In this way, each register in a row corresponds to a single bit, such as... Figure 3 As indicated in the diagram, each bit corresponds to a specific operation (sub-function). In other words, each row of the matrix is ​​associated with multiple bits, and each bit is associated with a sub-function (i.e., a specific test instruction).

[0058] Once an address is selected, the stored test instructions (T_reg_data) can be retrieved via a dedicated bus running on each matrix column.

[0059] For example, group 0 can be dedicated to reading the charge pump, and each bit in the group corresponds to a specific function. For instance, in a group with 8 bits, bit 0 = pump enabled, bits 5:1 = clock frequency, and bits 7:6 = drive capability (maximum current). Similarly, group 1 can be dedicated to reading the charge pump, for example, bits 7:0 = pump regulator output value, etc. In this way, each pump is mapped to each group, with each bit corresponding to a specific operation.

[0060] Other groups (such as group 12) can be dedicated to the sense amplifier, such as bit 0 = sense enable, bit 4:1 = delayed BL precharge, bit 7:6 = sense time, etc.

[0061] Figure 3 The flash array controller 360 thus interfaces with multiple test registers T_reg, each associated with a specific address of a group T_reg_addr, thereby allowing testing of the functionality of memory components, or typically used to interface memory components with test machines and / or external controllers in a very simple and efficient manner.

[0062] The testing machine connected its probe wires with Figure 2 The JTAG pad 240 is connected and communicates with the flash array via the Test Access Port (hereinafter referred to as TAP), which is a set of dedicated pads used to interface the test machine with the memory components.

[0063] Typically, four or five pads are used. Specifically, according to the TAP of this disclosure, the provided pads are Test Data Input (TDI), Test Data Output (TDO), Test Clock (TCK), and Test Mode Selection (TMS), each configured to receive specific signals, such as... Figure 4 As shown in the diagram. Sometimes, an optional test reset (TRST) pad is used.

[0064] The TRST pad can optionally reset the test logic to a valid low state, which is typically asynchronous but sometimes synchronous, depending on the chip. If the pad is unavailable, the test logic can be reset by synchronously switching to the reset state using TCK and TMS. It should be noted that resetting the test logic does not necessarily imply resetting anything else. There are usually some processor-specific JTAG operations that can reset all or part of the chip being debugged.

[0065] Because only one data line is available, the protocol is serial. The clock input is at the TCK pad; the clock cycle is J2, and its half-cycle is J3 or J4. One bit of data is input from TDI (TDI input active) and output to TDO (TDO output active) on each rising clock edge of TCK. Different instructions can be loaded. Instructions for typical ICs can read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (connecting the TDI to the TDO to logically shorten the chain of multiple chips), etc.

[0066] For any timing signal, the data presented to TDI must be valid for a chip-specific set time (J9) before the relevant (here, rising) clock edge and for a subsequent hold time (J10). TDO data is valid for a chip-specific time (J1) after the falling edge of TCK. TMS must be valid for a chip-specific set time (J7) before the relevant (here, rising) clock edge and for a subsequent hold time (J8).

[0067] Refer again Figure 2 According to this disclosure, the architecture also includes a finite state machine, named TAP controller 270, which receives three signals TCK, TMS, and TRST as inputs. The TAP controller is a 16-state finite state machine that controls each step of the test operation.

[0068] For example, a boundary scan architecture can be used, and each instruction executed through the boundary scan architecture is stored in an instruction register 270' that is operatively connected to the TAP controller 270.

[0069] This architecture also includes a boundary scan shift register 270", which is coupled in series to the TDI pin and provides an output to the TDO output pin via a multiplexer MUX. A test clock TCK is fed in via a dedicated input pin, and the operating mode is controlled by a series control signal TMS applied to the TAP controller 270. Subsequently, individual control signals associated with the instructions are provided via a decoder.

[0070] The command user interface represented by the TAP controller 270 is based on the IEEE 1149 and IEEE 1532 standards and implements a low-signal count interface, which has the ability to modify the internal contents of the associated memory subarray via the TMS, TCK, TDI, TDO, and TRST (optional) pins.

[0071] The standard IEEE 1149 is therefore based on the TAP finite state machine, namely the TAP controller 270, which contains sixteen states, two of which are called the shift instruction register (ShiftIR) and the shift data register (ShiftDR), allowing interaction with the system during writes and / or reads.

[0072] More specifically, the shift data register ShiftDR reports the state in which the TDI is connected to the register, and in that state, the register contents are transferred into and / or out of the device.

[0073] Similarly, the shift instruction register ShiftIR also reports the status of the connection between its TDI and the register, in which the instruction is loaded.

[0074] When the ShiftDR state is reached, TDI and TDO are connected to the registers, and at each TCK, data enters from TDI and exits from TDO.

[0075] The host device / test machine uses TAP to communicate by controlling TMS and TDI through a combination of TCK and the read result of TDO (which is a standard host-side input only). The TMS / TDI / TCK output transformation creates the basic JTAG communication primitive, and higher-layer protocols are built on top of the basic JTAG communication primitive.

[0076] More specifically, TMS is simply the signal that moves the TAP controller 270 at each edge of the clock. TDI is the data input signal for the instruction and data registers.

[0077] Therefore, in order to address the boundary scan, the instruction is loaded in the instruction register in ShiftIR state; then the boundary scan register is selected internally.

[0078] At the basic level, using JTAG involves reading and writing instructions and their associated data test registers, as well as running several test loops.

[0079] The JTAG pad uses the TAP controller to provide instructions and data to the memory controller.

[0080] In addition, extra pads are added to enable the performance of analog measurements and interaction with memory while the test machine is testing the die.

[0081] Specifically, according to embodiments of this disclosure, such as Figure 5 As shown, the JTAG interface further includes at least one of the following: an analog pad (T_analog), a pad for querying test execution (T_run), and a device busy pad (T_busy, indicating that a test is in progress and the internal controller is on). Additionally, a bus is provided for initializing the test registers (TMI, used to set some internal registers).

[0082] More specifically, TMI refers to the register addressed via JTAG, T_analog is the analog input that provides voltage or current to the device, T_run is used to trigger the start / continue of a test, and T_busy is the memory output that indicates that the memory is busy.

[0083] Therefore, in its simplest form, the padding of the test interface includes at least: TDI, TDO, TCK, TMS, T_busy, T_analog, and T_run, as described above.

[0084] In this context, such additional pads improve the interface with the test machine and can be used to implement special test algorithms. More specifically, by using a suitable combination of T_run and T_busy, it is possible to transmit specific test operations with the test interface while maintaining a low number of contact pads, as will be described below. Furthermore, this allows for the possibility of steps within the same test, such as block-by-block erasure, that can be performed by using a combination of T_run and T_busy to inspect all blocks in a subarray.

[0085] Therefore, according to this disclosure, the test machine is adapted to provide several bus cycles to load the internal register T_reg, query command execution T_run, and poll T_busy while waiting for the command to complete, which may occur in a loop-back sequence. Finally, the results are collected by readings from the output lines, which have been previously set in the same manner as the internal lines. More specifically, the results are collected in the JTAG register and subsequently read.

[0086] Therefore, the test is initiated via a signal provided by the T_run pad; the additional pins T_analog and T_busy serve as mechanisms for proper interaction with the test machine. In principle, the test machine operates synchronously with the memory components to use the busy state as an interrupt, providing appropriate analog signals to the memory components.

[0087] This allows for better interfacing with memory components by using a suitable combination of the pads. For example, a combination of T_run, T_busy, and T_analog allows testing with different currents: when t_busy is low, a new current can be applied from T_analog, and then T_run starts testing again.

[0088] The memory components also include efficient and secure ESD protection, thereby improving component reliability.

[0089] As previously mentioned, it is possible that a test in progress requires the measurement and / or generation of some current or voltage. This can be accomplished internally using a dedicated simulation module of the memory component.

[0090] Alternatively, the required voltage / current can be applied via a test machine using the T_analog pad. This is also suitable for debugging purposes. Furthermore, T_analog can provide additional boost voltage or current to improve the speed of modifications.

[0091] Figure 6 A diagram illustrating method 600 according to this disclosure is shown. The method can be used to execute memory components of the type comprising memory cells including arrays of memory cells (e.g., those described above). Figure 1 , 2 Tests of memory components (3 and 3).

[0092] At step 610, method 600 provides a plurality of test registers for a memory component, the test registers being organized into a matrix configuration, each row of the matrix being associated with a specific address; as referenced above. Figure 1 , 2 As described in section 3, multiple test registers may be provided.

[0093] At step 620, method 600 loads operation instructions for performing tests on the memory components into the test register; as described above. Figure 1-5 As described in the document, it can load operation instructions.

[0094] At step 630, method 600 connects the pad of the memory component to a host device and / or a test machine; the pad of the memory component may be temporarily connected to the test machine, or may be connected via multiple coupling elements (e.g., pillars, through-silicon vias (TSVs), and ball grids, flip-chip technology, as referenced above). Figure 1 (As described) Connects to SoC 100. In some cases, alternatively, a wireless interconnect can be established.

[0095] At step 640, method 600 addresses one or more test registers for retrieving test information. (Refer to the above reference.) Figure 1-5 The description will perform this operation.

[0096] In some embodiments, the method is performed via the JTAG protocol. The method may also include a step (not shown) to prevent selection of a specific test register. In some embodiments, such a step to prevent selection of a specific test register applies different restrictions based on the different permissions of the different users performing the test. In some embodiments, the method is performed using at least one of a simulation pad (T_analog), a pad for querying test execution (T_run), and a device busy pad (T_busy), the combination of which is used to interact with the test machine.

[0097] In summary, testing of the memory component according to this disclosure is managed using the contents of the test register T_reg via a JTAG-based protocol. This interface includes padding for receiving TAP signals and other additional signals for managing test operations. As previously observed, the testing can be controlled by the SoC controller or by an external test machine.

[0098] According to embodiments of this disclosure, the test register is in the form of a latch or a flip-flop.

[0099] According to this disclosure, two sets of registers are used: more specifically, the memory component also includes configuration registers loaded with stored (non-volatile) information (e.g., bgap settings). In embodiments, these configuration registers are loaded with information during power-up of the device.

[0100] On the other hand, the test register is used in test mode and is reset whenever a component enters user mode. The contents of the test register T_reg can be easily manipulated according to user needs, and in some cases, the contents of the test register can overwrite the contents of the configuration register. Advantageously, the two register sets can be mixed together using appropriate logic.

[0101] Non-volatile information can then be mapped in a dedicated register set as needed, thus providing great flexibility to the system.

[0102] In other words, both volatile and non-volatile information can be used during testing, with the non-volatile information stored in appropriate configuration registers. Alternatively, the user can initialize test registers with volatile data (elements used to configure memory components), which are set whenever a new test operation begins and are generally not maintained at the end of the operation. Some registers can therefore be loaded with contents stored in configuration blocks completed by the flash unit. The user can change other registers for testing purposes, but they are not connected to the factory configuration.

[0103] In this way, some registers of the memory components are adapted to be initialized with volatile information for test modes, whereby the user can write to some of these registers when they wish to perform a specific test operation; another category of registers is then adapted to be initialized with non-volatile information.

[0104] In this way, the test register T_reg is advantageously adapted to contain test operation instructions (parameters, settings, and special bits allowing signal paths for test purposes) at the basic level (user level), while managing higher-level test protocols through other dedicated registers of the TAP controller and JTAG interface. Users do not need to specify such high-level protocols during testing and can only use the information in the test register T_reg.

[0105] Furthermore, according to embodiments of this disclosure, the controller of the memory component is configured to prevent, specifically, the selection of a particular test register when the test mode is inoperable.

[0106] More specifically, to allow access to certain test registers and disable access to other reserved test registers, the memory component controller includes a filtering block. In this way, not all test registers T_reg are accessible to external users, and the filtering block is configured to disable access to some test registers T_reg in certain situations, such as when a user does not have permission to access such test registers. Therefore, some reserved registers are not addressable, and the controller's filtering masks specific addresses of these registers, so that the output of such filtering blocks only receives the first enabled register T_reg.

[0107] In one embodiment, some registers T_reg may never be accessed by the user firmware and may only be accessed by the manufacturer, who has the necessary permissions to execute a specific test mode that requires the use of such disabled registers.

[0108] Furthermore, the internal controller can be configured to apply different constraints (i.e., different constraints on the test register T_reg) to different users with different access permissions. Specifically, the controller can receive additional input considering a particular test mode to be executed, each test mode associated with a specific user with specific permissions, allowing the controller to apply different constraints to different users, as indicated above. Thus, different test modes can be executed with different permissions, and access to some registers can be disabled based on such permissions.

[0109] In other words, filter blocks can be configured differently based on different users, and these different users can be identified by a controller during authentication, which then configures the filters accordingly. In this way, memory components have different levels of testability: the manufacturer has full access to the registers, while the SoC may only have limited access. Different rights are associated with authentication: depending on the identified instruction source, testing a portion of register T_reg may be prohibited.

[0110] In summary, according to this disclosure, test modes are executed in a highly efficient manner by means of multiple test registers grouped in the matrix configuration described above. According to this disclosure, the machine performing the tests does not need to be familiar with higher-level test protocols; the machine can access information from the test registers simply by selecting the desired address. Maintaining a low number of JTAG pads simplifies parallel testing.

[0111] The disclosed system has a wide range of applications, allowing users to implement personal test interfaces by using dedicated test registers.

[0112] Furthermore, the disclosed memory component offers several other advantages, which are reported below without regard to importance. The previously disclosed solution reduces silicon costs for the memory component and improves the overall quality and reliability of the entire device, including the host device and the memory component.

[0113] This disclosure also allows for improved field testability, for example, by specific firmware distributed by the SoC using a memory component factory.

[0114] The device disclosed herein provides a good option for performing component testing, particularly for real-time operational systems in automotive applications.

[0115] Furthermore, the combined use of test pads allows for efficient interaction between the test machine and the memory component under test, maintains a low pin count, and improves the overall test operation.

[0116] The memory components and host or SoC are coupled with an interface using extremely high parallelism. This feature can also be used to improve overall performance.

[0117] In the preceding detailed description, reference has been made to the accompanying drawings, which form part of the invention, and specific examples are illustrated in the drawings by way of illustration. Throughout the drawings, the same reference numerals describe substantially similar components. Other examples may be utilized, and structural, logical, and / or electrical changes may be made without departing from the scope of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the drawings are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0118] As used herein, “a,” “an,” or “several” something can refer to one or more of such things. “Multiple” something means two or more. As used herein, the term “coupling” can include electrical coupling, direct coupling, and / or direct connection without an intermediary element (e.g., through direct physical contact), or indirect coupling and / or connection with an intermediary element. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship).

[0119] Although specific examples have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of one or more embodiments of this disclosure. It should be understood that the above description has been carried out illustratively and not restrictively. Therefore, the scope of one or more examples of this disclosure should be determined by reference to the appended claims and the full scope of equivalents to which such claims are given.

Claims

1. A memory component comprising: A memory cell, which contains an array of memory cells; The controller of the memory unit; and A JTAG test interface includes a plurality of contact pads adapted to connect the memory component to a host device and / or a test machine, wherein the plurality of contact pads include: Simulated pads are used to provide voltage or current to the memory component; A pad used to request test execution to trigger the start of a test on the memory component; and A busy pad is included to indicate that the memory component is busy, wherein: The test interface further includes multiple test registers; The test register is configured to be loaded with operation instructions for performing the test on the memory component; and The test registers are organized into a matrix configuration, with each row of the matrix associated with a specific address.

2. The memory component of claim 1, wherein the test register is a latch and / or a trigger.

3. The memory component of claim 1, further comprising a set of registers adapted to load non-volatile information when the host device is powered on.

4. The memory component of claim 1, wherein the test register is configured to be loaded with base-level test instructions received whenever a new test mode is executed.

5. The memory assembly of claim 1, wherein the controller of the memory cell is configured to perform a built-in self-test (BIST).

6. The memory component of claim 1, wherein the JTAG test interface includes a pad for receiving a Test Access Port (TAP) signal.

7. The memory assembly of claim 1, wherein the plurality of contact pads are configured to allow the host device and the test machine to interact with the memory assembly in combination therewith.

8. The memory component of claim 1, wherein each row of the matrix is ​​configured to drive one or more macro functions for performing the test of the memory component.

9. The memory component of claim 8, wherein each row of the matrix is ​​associated with a plurality of bits, and each bit is associated with a subfunction.

10. The memory component of claim 1, further comprising an analog voltage / current generator.

11. The memory component of claim 1, wherein the controller is configured to select a specific test register.

12. A system-on-a-chip (SoC) device, comprising: The memory component includes: A memory cell, which contains an array of memory cells; The controller of the memory unit; and A JTAG test interface includes a plurality of contact pads adapted to connect the memory component to the SoC device and / or test machine, wherein the plurality of contact pads include: Simulated pads are used to provide voltage or current to the memory component; A pad used to request test execution to trigger the start of a test on the memory component; and A busy pad is included to indicate that the memory component is busy. The test interface further includes multiple test registers; The test register is configured to be loaded with operation instructions for performing the test on the memory component; and The test registers are organized into a matrix configuration, with each row of the matrix associated with a specific address.

13. The SoC device of claim 12, wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping with the SoC device structure.

14. The SoC device of claim 13, further comprising a pad connected to the memory component for communication therewith.

15. A method comprising: Provide multiple test registers for a memory component, wherein the test registers are organized into a matrix configuration, and each row of the matrix is ​​associated with a specific address; The operation instructions for performing tests on the memory components are loaded into the test register; The tests on the memory component are performed using a simulation pad, a pad for requesting test execution, and a device busy pad, the combination of which is used to interact with the test machine. Connect the pad of the memory component to the host device and / or the test machine; and One or more addresses of the test registers are used to retrieve test information.

16. The method of claim 15, further comprising performing the test on the memory component via the JTAG protocol.

17. The method of claim 15, further comprising preventing the selection of a specific test register.

18. The method of claim 17, wherein the prevention of selection of a specific test register applies different restrictions based on the different permissions of different users performing the test.

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