Electronic Systems

Abstract

The present invention provides an electronic system, which includes a platform controller and a plurality of peripheral components. The platform controller has a first bus. The peripheral components are respectively coupled to the platform controller through the first bus. The peripheral components include a master peripheral component and a slave peripheral component. The master peripheral component and the slave peripheral component are connected to a communication signal line. The master peripheral component communicates with the platform controller through the first bus. When the master peripheral component receives a communication request from the slave peripheral component through the communication signal line, the master peripheral component provides a communication signal corresponding to the communication request to the first bus, so that the slave peripheral component communicates with the platform controller through the first bus.

Description

Technical Field

[0001] The present invention relates to a system, and in particular to an electronic system. Background Art

[0002] In the electronic system of the prior art, the platform controller can only be connected to a single peripheral component through a single Enhanced Serial Peripheral Interface (eSPI) bus. Therefore, if multiple peripheral components are to be controlled or read, multiple buses must be connected to multiple peripheral components to achieve control or read operations with multiple peripheral components. Therefore, in the traditional electronic system, the communication and connection between the platform controller and the peripheral components will not only increase the manufacturing cost of the electronic system, but also the number of peripheral components connected to the electronic system is also limited by the number of physical buses, resulting in poor compatibility of the electronic system. Summary of the invention

[0003] The invention provides an electronic system, which enables a platform controller in the electronic system to simultaneously connect multiple peripheral components via a single bus.

[0004] The electronic system of the present invention includes a platform controller and a plurality of peripheral components. The platform controller has a first bus. The peripheral components are respectively coupled to the platform controller through the first bus. The peripheral components include a master peripheral component and a slave peripheral component. The master peripheral component and the slave peripheral component are connected to a communication signal line. The master peripheral component communicates with the platform controller through the first bus. When the master peripheral component receives a communication request from the slave peripheral component through the communication signal line, the master peripheral component provides a communication signal corresponding to the communication request to the first bus, so that the slave peripheral component communicates with the platform controller through the first bus.

[0005] The electronic system of the present invention includes a platform controller and a plurality of peripheral components. The platform controller has a first bus. The peripheral components are respectively coupled to the platform controller through the first bus. The peripheral components include a master peripheral component and a slave peripheral component. The master peripheral component and the slave peripheral component are connected to an interrupt signal line. The master peripheral component communicates with the platform controller through the first bus. When the master peripheral component receives an interrupt request provided by the slave peripheral component through the interrupt signal line, the master peripheral component provides an interrupt signal to the platform controller through the first bus, and the platform controller communicates with the slave peripheral component through the first bus according to the interrupt signal.

[0006] Based on the above, the platform controller in the electronic system can simultaneously connect multiple peripheral components via a single bus, and the multiple peripheral components will not generate signal conflicts on the bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a schematic diagram of an electronic system according to an embodiment of the present invention;

[0008] Figure 1B is a schematic diagram of an electronic system according to an embodiment of the present invention;

[0009] Figure 1C is a schematic diagram of an electronic system according to an embodiment of the present invention;

[0010] Figure 2 A signal waveform diagram of an electronic system according to an embodiment of the present invention;

[0011] Figure 3A and Figure 3B FIG. 1 is a signal waveform diagram of an interrupt signal line according to an embodiment of the present invention.

[0012] Description of Reference Numerals

[0013] 1, 2, 3: electronic system;

[0014] 10: Platform controller;

[0015] 11, 21, 31: Main peripheral components / peripheral components;

[0016] 12-14, 22-24, 32-34: subordinate peripheral components / peripheral components;

[0017] CMD: command time interval;

[0018] CRC1, CRC2: cyclic redundancy check interval;

[0019] CS: bus;

[0020] D1, D2, D3: time interval;

[0021] GND: ground voltage;

[0022] L1: communication signal line;

[0023] L2: interrupt signal line;

[0024] S_CK: clock signal;

[0025] S_CS: bus signal;

[0026] S_IRQ1, S_IRQ2: interrupt request signals;

[0027] T0: reset time interval;

[0028] T00: enabling time interval;

[0029] T1~T15: sub-time interval;

[0030] T11: synchronization time interval;

[0031] T12: signal judgment time interval;

[0032] STS: status interval;

[0033] VCC: operating voltage. DETAILED DESCRIPTION

[0034] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0035] Figure 1A It is a schematic diagram of an electronic system 1 according to an embodiment of the present invention. The electronic system 1 includes a platform controller (Platform Controller Hub, PCH) 10, and a plurality of peripheral components 11 to 14. The platform controller 10 is connected to the peripheral components 11 to 14 via a bus CS, and the platform controller 10 can communicate with the peripheral components 11 to 14 via a single bus CS. In one embodiment, the platform controller 10 is, for example, a platform controller hub (Platform Controller Hub, PCH), and the bus CS can be a bus compatible with an enhanced serial peripheral interface (Enhanced Serial Peripheral Interface, eSPI) to connect the platform controller 10 and the peripheral components 11 to 14. Although the following is based on Figure 1A The exemplary embodiment shown is used for illustration, that is, the platform controller 10 in the electronic system 1 is connected to four peripheral components 11-14, but those skilled in the art can certainly adjust the number of peripheral components connected to the platform controller 10 in the electronic system 1 to make the electronic system 1 adaptively meet different design requirements and usage concepts.

[0036] Since the peripheral components 11-14 communicate with the platform controller 10 only through a single bus CS, in order to avoid signal conflicts caused by multiple peripheral components 11-14 communicating on the bus CS at the same time, one of the peripheral components 11-14, the peripheral component 11, can be pre-set as a master peripheral component, and the other peripheral components 12-14 can be set as slave peripheral components. In this way, the peripheral components 11-14 can be responsible for most of the communication on the bus CS through the master peripheral component. The other slave peripheral components can monitor the communication content on the bus, so that when communication is needed or requested, the slave peripheral component can notify the master peripheral component, and the master peripheral component then communicates with the platform controller 10.

[0037] In one embodiment, the peripheral elements 11-14 may respectively have setting pins, and the peripheral elements 11-14 may be set as master peripheral elements or slave peripheral elements according to the voltage received by the setting pins. Figure 1A As shown, the peripheral element 11 is set as a master peripheral element according to the setting pin receiving the operation voltage VCC, and the other peripheral elements 12 to 14 are set as slave peripheral elements 12 to 14 according to the setting pin receiving the ground voltage GND.

[0038] Furthermore, the peripheral components 11-14 are connected to each other via a communication signal line L1 for mutual communication. When one or more of the slave peripheral components 12-14 want to communicate, the slave peripheral components 12-14 can provide a communication request to the communication signal line L1. When the master peripheral component 11 receives the communication request via the communication signal line L1, it can be known that one or more of the slave peripheral components 12-14 want to communicate with the platform controller 10. The master peripheral component 11 can provide a communication signal to the platform controller 10 via the bus CS, so the controller 10 can communicate with one or more of the slave peripheral components 12-14 according to the communication signal.

[0039] Please refer to Figure 1A and Figure 2 , Figure 2 1 is a signal waveform diagram of an electronic system 1 according to an embodiment of the present invention. The platform controller 10 and the peripheral components 11 to 14 can communicate with each other through the bus CS according to the clock signal S_CK, thereby generating the bus signal S_CS. More precisely, the clock signal S_CK is a signal for the platform controller 10 to communicate with the peripheral components 11 to 14 when the platform controller 10 wants to communicate with one of the slave peripheral components 12 to 14. Therefore, the clock signal S_CK can be, for example, an input / output read command signal or a memory read command signal, indicating communication with one of the slave peripheral components 12 to 14.

[0040] The bus signal S_CS includes a command time interval CMD, a time interval D1, a cyclic redundancy check interval CRC1, time intervals D2 and D3, a status interval STS, and a cyclic redundancy check interval CRC2. Further, in the command time interval CMD, the time interval D1, and the cyclic redundancy check interval CRC1, the bus signal S_CS can be provided by the platform controller 10 to the bus CS, so that the peripheral components 11 to 14 can read. Then, after turning around (TAR), in the time intervals D2 and D3, the status interval STS, and the cyclic redundancy check interval CRC2, in response to the command signal of the platform controller 10, the bus signal S_CS can be provided by one of the master peripheral component 11 and the slave peripheral components 12 to 14 to the bus CS to provide the data to be read by the platform controller 10. Therefore, the platform controller 10 can provide a read command signal according to the bus signal S_CS and instruct the peripheral components 11 to 14 to provide the data to be read.

[0041] In the command time interval CMD, the platform controller 10 may provide a command code to the bus CS, so that the peripheral components 11-14 may determine the operation content to be performed by the platform controller 10 according to the command code. The command code provided by the platform controller 10 may be, for example, a command code of an input / output read command (e.g., PUT_IORD_SHORT) or a memory read command (e.g., PUT_MEMRD32_SHORT), so the peripheral components 11-14 may know the operation content to be performed by the platform controller 10 according to the command code received in the command time interval CMD.

[0042] In the time interval D1, the platform controller 10 can provide address information to the bus CS. The slave components 11-14 can read the address information and determine the read object of the platform controller 10. Further, the address information stores the physical address information (for example, 32-byte physical address information) that the platform controller 10 wants to read. After reading the address information, each slave component 11-14 can determine whether it is the object to be read by the platform controller 10. When the slave component 11-14 corresponds to the object to be read by the platform controller 10 according to the address information, the corresponding slave component 11-14 will respond to the read command or memory read command of the platform controller 10 through the bus CS in the subsequent time interval.

[0043] In the cyclic redundancy check interval CRC1, the platform controller 10 can provide a corresponding verification code to the bus CS according to the data content transmitted in the command time interval CMD and the time interval D1, so that the slave components 11~14 can determine whether the data received in the command time interval CMD and the time interval D1 is correct according to the verification code.

[0044] In the time interval D2, the master peripheral component 11 can sense the communication signal line L1 to determine whether the slave peripheral components 12-14 need to transmit data. When the master peripheral component 11 receives a communication request from the communication signal line L1, the master peripheral component 11 can provide a communication signal to the platform controller 10 through the bus CS, so that one or more of the slave peripheral components 12-14 can communicate with the platform controller 10 through the bus CS.

[0045] When the address information provided by the platform controller 10 in the time interval D1 corresponds to the slave peripheral element 12, it means that the platform controller 10 intends to perform a read operation on the slave peripheral element 12. The master peripheral element 11 can sense the voltage level of the communication signal line L1 to determine whether a communication request is received. For example, the communication signal line L1 can be driven by a driving circuit (not shown) in the electronic system 1. Figure 1A ) drives the communication signal line L1 to set the voltage level of the communication signal line L1 to a first voltage level (e.g., a high voltage level). When the slave peripheral component 12 changes the voltage level of the communication signal line L1 from the first voltage level (e.g., a high voltage level) to the second voltage level (e.g., a low voltage level), when the master peripheral component 11 senses the above-mentioned voltage level change of the communication signal line L1, it can be determined that the communication request provided by one of the slave peripheral components 12 to 14 is received. Therefore, the master peripheral component 11 can provide a waiting signal (e.g., WAIT_STATE) of the communication signal to the bus CS. Then, when the slave peripheral component 12 reads or obtains the data content that the platform controller 10 wants to read, the slave peripheral component 12 can change the voltage level of the communication signal line L1 from the second voltage level (e.g., a low voltage level) to the first voltage level (e.g., a high voltage level). Accordingly, the master peripheral component 11 can provide a receiving signal (e.g., ACCEPT) of the communication signal to the bus CS. Therefore, the platform controller 10 can receive the communication signal including the waiting signal and the receiving signal in the time interval D2 to better determine whether the read command is correctly transmitted to the slave peripheral elements 11 - 14 and whether the peripheral elements 11 - 14 are in a readable state.

[0046] In the time interval D3, the master peripheral element 11 does not provide a signal to the bus CS, but the slave peripheral element 12 providing the communication request provides data to the bus CS to avoid data conflict on the bus CS. The platform controller 10 can obtain the data to be read according to the data in the time interval D3.

[0047] In the status section STS, the master peripheral component 11 and the platform controller 10 may provide information about the status of data transmission through the bus CS, for example, whether the peripheral components 11 to 14 still have data to transmit or whether the data to be transmitted is ready for transmission.

[0048] In the cyclic redundancy check interval CRC2, the master peripheral component 11 can provide a corresponding verification code to the bus CS according to the data content transmitted in the time intervals D2, D3 and the status interval STS, so that the platform controller 10 can determine whether the data received in the time intervals D2, D3 and the status interval STS is correct based on the verification code.

[0049] Therefore, the platform controller 10 in the electronic system 1 can be connected to multiple peripheral components 11-14 through a single bus CS. The peripheral components 11-14 are arranged as master peripheral components and slave peripheral components, so that the master peripheral component 11 can effectively integrate and manage the communication between the peripheral components 11-14 and the platform controller 10 on the bus CS through the communication signal line L1. Therefore, the electronic system 1 can be connected to multiple peripheral components 11-14 at the same time without generating signal conflicts on the bus CS, thereby reducing the manufacturing cost of the electronic system 1 and improving the expandability of the electronic system 1.

[0050] Next, please refer to Figure 1B , Figure 1B FIG. 2 is a schematic diagram of an electronic system 2 according to an embodiment of the present invention. Figure 1B The electronic system 2 shown is similar to Figure 1A The electronic system 1 is shown in the figure, and the same elements are marked with the same symbols. Figure 1A and Figure 1B The difference is that Figure 1A The peripheral components 11 to 14 in Figure 1B are replaced by peripheral components 21 to 24, and Figure 1A The communication signal line L1 in Figure 1B In the electronic system 2, the peripheral element 21 is set as the master peripheral element 21 and the peripheral elements 22 to 24 are set as the slave peripheral elements 22 to 24. All the peripheral elements 21 to 24 are connected to each other through the interrupt signal line L2.

[0051] In the electronic system 2, in order to avoid signal conflicts, the master peripheral component 21 can be responsible for most of the communication on the bus CS to communicate with the platform controller 10. When one of the slave peripheral components 22-24 needs to issue an interrupt request and needs to communicate with the platform controller 10, the slave peripheral component 22-24 can provide an interrupt request through the interrupt signal line L2 to notify the master peripheral component 21, so that the master peripheral component 21 issues an interrupt request (Interrupt Request, IRQ) to the platform controller 10.

[0052] Please refer to Figure 1B , Figure 3A and Figure 3B . Figure 3A and Figure 3B The signal waveform diagram of the interrupt signal line L2 of an embodiment of the present invention. In detail, when one or more of the slave peripheral components 22-24 send an interrupt request to the master peripheral component 21 through the interrupt signal line L2, the master peripheral component 21 can determine whether to send an interrupt request (IRQ) to the platform controller by monitoring the signal on the interrupt signal line L2.

[0053] Figure 3A The interrupt request signal S_IRQ1 is a signal waveform diagram on the interrupt signal line L2. The signal waveform diagram of the interrupt request signal S_IRQ1 has thin lines, thick lines and dotted lines. The thin lines represent the signal waveform of the interrupt request signal S_IRQ1 generated by the driving circuit (not shown) in the electronic system 2. Figure 1B ) drives the interrupt signal line L2 to set the voltage level of the interrupt signal line L2 to a first voltage level (e.g., a high voltage level). The bold line represents that the interrupt request signal S_IRQ1 on the interrupt signal line L2 is driven by the master peripheral element 22 to change the voltage level. The dotted line represents that the interrupt request signal S_IRQ1 on the interrupt signal line L2 is driven by one or more of the slave peripheral elements 22 to 24 to change the voltage level.

[0054] like Figure 3A As shown, in the interrupt request signal S_IRQ1, the interrupt request signal S_IRQ1 has a reset time interval T0 and a plurality of sub-time intervals T1-T15. The sub-time intervals T1-T15 may together constitute the interrupt request time interval in the interrupt request signal S_IRQ1, and the reset time interval T0 may precede the interrupt request time interval. Figure 3A The number of sub-time intervals shown in FIG. 1 is 15, but the number of sub-time intervals can be adjusted according to different design requirements, and the present invention is not limited thereto.

[0055] In the reset time interval T0, the master peripheral component 21 can change the voltage level of the interrupt signal line L2 from a first voltage level (e.g., a high voltage level) to a second voltage level (e.g., a low voltage level) to provide a reset signal to the interrupt signal line L2, so that the slave peripheral components 22-24 can perform a reset procedure according to the reset signal. For example, the reset signal can be a second voltage level signal (e.g., a low voltage level) that lasts for 16 time periods.

[0056] In the sub-time intervals T1 to T15 after the reset time interval T0, the sub-time intervals T1 to T15 may respectively have a synchronization time interval and a determination time interval. The master peripheral element 21 may provide a synchronization signal in the synchronization time interval to synchronize the operation of each slave peripheral element 22 to 24, and allow each slave peripheral element 22 to 24 to distinguish each sub-time interval. Then, in the determination time interval after the synchronization time interval, one or more of the slave peripheral elements 22 to 24 may provide an interrupt request to the interrupt signal line L2, and the master peripheral element 21 may sense the interrupt signal line L2 to determine whether the interrupt request is received.

[0057] Taking the sub-time interval T1 as an example, in the synchronization time interval T11, the master peripheral element 11 can provide a synchronization signal to the interrupt signal line L2 to synchronize the operations of the slave peripheral elements 12-14, and the slave peripheral elements 12-14 can identify the sub-time interval T1 according to the synchronization signal. For example, the synchronization signal can be a second voltage level signal (e.g., a low voltage level) that lasts for 2 time periods.

[0058] In the signal judgment time interval T12 after the synchronization time interval T11, one or more of the slave peripheral components 22 to 24 may provide an interrupt request to the interrupt signal line L2. In detail, the sub-time intervals T1 to T15 may correspond to different types of interrupt request, and the master peripheral component 21 may determine the type of interrupt request that the slave peripheral components 22 to 24 intend to make based on the sub-time interval in which the interrupt request is received. For example, one or more of the slave peripheral components 22 to 24 may change the voltage level on the interrupt signal line L2 from a first voltage level (e.g., a high voltage level) to a second voltage level (e.g., a low voltage level) for two time periods to provide an interrupt request to the interrupt signal line L2. After one or more of the slave peripheral components 22 to 24 provide an interrupt request, the voltage level on the interrupt signal line L2 may be controlled by a driving circuit (not shown) in the electronic system 2. Figure 1B ) changes back to the first voltage level (eg, a high voltage level).

[0059] In this embodiment, the master peripheral element 21 performs a reset time interval T0 and sub-time intervals T1-T15 to determine whether an interrupt request needs to be issued to the platform controller 10 according to the interrupt request issued by the slave peripheral elements 22-24. After the reset time interval T0 and the sub-time intervals T1-T15 are over, the master peripheral element 21 periodically repeats the reset time interval T0 and the sub-time intervals T1-T15 to continuously sense whether the slave peripheral elements 22-24 intend to issue an interrupt request.

[0060] like Figure 3B As shown, in the interrupt request signal S_IRQ2, the interrupt request signal S_IRQ2 has an enabling time interval T00, a reset time interval T0 and a plurality of sub-time intervals T1-T15. For details on the operation of the reset time interval T0 and the plurality of sub-time intervals T1-T15, please refer to the above Figure 3A The interrupt request signal S_IRQ1 and the interrupt request signal S_IRQ2 are different in that the interrupt request signal S_IRQ1 is a periodic signal. The interrupt request signal S_IRQ2 is a one-time signal generated after being triggered by one of the slave peripheral components 22 to 24, and the voltage level on the interrupt signal line L2 can be controlled by the driving circuit (not shown) in the electronic system 2. Figure 1B ) is driven so that the voltage level on the interrupt signal line L2 can be set to a first voltage level (for example, a high voltage level).

[0061] In the enable time interval T00 of the interrupt request signal S_IRQ2, one of the slave peripheral components 22-24 may provide an enable signal to the interrupt signal line L2 to change the voltage level on the interrupt signal line L2 from a first voltage level (e.g., a high voltage level) to a second voltage level (e.g., a low voltage level). For example, the enable signal may be a second voltage level signal (e.g., a low voltage level) that lasts for three time periods. After receiving the enable signal, the master peripheral component 21 may know that one of the slave peripheral components 22-24 needs to issue an interrupt request, so the master peripheral component 21 may perform a one-time reset time interval T0 and sub-time intervals T1-T15 after the enable time interval T00 to determine the type of interrupt request to be issued. After the reset time interval T0 and the interrupt request time interval (sub-time intervals T1-T15) are completed, the voltage level on the interrupt signal line L2 may be driven to the first voltage level (e.g., a high voltage level) by the driving circuit of the electronic system 2. The master peripheral element 21 may wait for the next time when it receives the trigger of the enable signal, and then the master peripheral element 21 will repeat the reset time interval T0 and the interrupt request time interval (sub-time intervals T1 to T15) again.

[0062] Therefore, in the electronic system 2, the platform controller 10 can be connected to multiple peripheral components 21-24 via a single bus CS. The peripheral components 21-24 can effectively integrate whether an interrupt request needs to be issued between the peripheral components 21-24 via the interrupt signal line L2, so the electronic system 2 can be connected to multiple peripheral components 21-24 at the same time without generating signal conflicts on the bus CS, thereby achieving the goal of reducing the manufacturing cost of the electronic system 2 and improving the expandability of the electronic system 1.

[0063] Please refer to Figure 1C , Figure 1C FIG. 1 is a schematic diagram of an electronic system 3 according to an embodiment of the present invention. Figure 1C The electronic system 3 shown is similar to Figure 1A The electronic system 1 shown and Figure 1B The electronic system 2 is shown in the figure, and the same elements are marked with the same symbols. Figure 1A and Figure 1B and Figure 1C The difference is that Figure 1C The peripheral components 31-34 in the electronic system 3 have both the communication signal line L1 and the interrupt signal line L2. Therefore, in the electronic system 3, the peripheral components 31-34 can communicate with each other through the communication signal line L1 and the interrupt signal line L2 at the same time. The slave peripheral components 32-34 can notify the master peripheral component 31, and then communicate with the platform controller 10 on the bus CS, and the master peripheral component 31 can determine whether the slave peripheral components 32-34 need to issue an interrupt request.

[0064] In summary, the platform controller in the electronic system can simultaneously connect multiple peripheral components through a single bus. By setting one of the peripheral components as a master peripheral component and the other peripheral components as slave peripheral components, the master peripheral component can integrate the communication between the slave peripheral components and the platform controller through the communication signal line and / or interrupt signal line connected between the peripheral components, or determine whether the slave peripheral component needs to issue an interrupt request. In this way, when the platform controller in the electronic system simultaneously connects multiple peripheral components with a single bus, signal conflicts can be effectively avoided. Therefore, while the manufacturing cost of the electronic system can be effectively reduced, the expandability of the electronic system is also improved.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic system, characterized in that: The electronic system comprises: A platform controller having a first bus; A plurality of peripheral components are directly coupled to the first bus and coupled to the platform controller through the first bus. The plurality of peripheral components include: a master peripheral element and a slave peripheral element, wherein the master peripheral element and the slave peripheral element are connected to a communication signal line, and the master peripheral element communicates with the platform controller through the first bus, When the master peripheral component receives a communication request from the slave peripheral component through the communication signal line, the master peripheral component provides a communication signal corresponding to the communication request to the first bus, so that the slave peripheral component communicates with the platform controller through the first bus.

2. The electronic system according to claim 1, wherein when the slave peripheral element receives address information corresponding to the slave peripheral element from the first bus in a first data time interval, the slave peripheral element provides the communication request to the master peripheral element through the communication signal line. 3 . The electronic system according to claim 2 , wherein the slave peripheral component changes the communication signal line from a first voltage level to a second voltage level to provide the communication request to the master peripheral component.

4. The electronic system according to claim 3, wherein when the master peripheral component senses that the communication signal line changes from the first voltage level to the second voltage level, the master peripheral component provides a wait signal of the communication signal to the first bus in a second data time interval after the first data time interval, When the master peripheral element senses that the communication signal line changes from the second voltage level to the first voltage level, the master peripheral element provides a receiving signal of the communication signal to the first bus in the second data time interval. The electronic system of claim 4 , wherein the first voltage level is greater than the second voltage level. 6 . The electronic system of claim 4 , wherein the slave peripheral component provides read data to the first bus in a third data time interval after the second data time interval to communicate with the platform controller.

7. The electronic system according to claim 1, wherein the master peripheral component is further connected to the slave peripheral component through an interrupt signal line, wherein when the master peripheral component receives an interrupt request provided by the slave peripheral component through the interrupt signal line, the master peripheral component provides an interrupt signal to the platform controller through the first bus, and the platform controller communicates with the slave peripheral component through the first bus based on the interrupt signal.

8. The electronic system according to claim 7, wherein in an interrupt request time interval, the master peripheral component divides the interrupt request time interval into a plurality of sub-time intervals, and the master peripheral component provides the corresponding interrupt signal to the platform controller according to each of the sub-time intervals corresponding to the received interrupt request.

9. The electronic system according to claim 8, wherein the master peripheral component provides a reset signal to the interrupt signal line in a reset time interval before the interrupt request time interval, wherein each of the sub-time intervals has a synchronization time interval and a signal determination time interval, and the master peripheral component determines whether the interrupt request is received in the signal determination time interval of each of the sub-time intervals. 10 . The electronic system according to claim 9 , wherein the master peripheral element provides a plurality of synchronization signals in the synchronization time interval of each of the sub-time intervals, and the slave peripheral element identifies each of the sub-time intervals according to the plurality of synchronization signals. 11 . The electronic system according to claim 10 , wherein the master peripheral device periodically provides the reset signal and a plurality of the synchronization signals to the interrupt signal line. 12 . The electronic system according to claim 9 , wherein after the master peripheral component receives the enable signal provided by the slave peripheral component to the interrupt signal line, the master peripheral component provides the reset signal to the interrupt signal line.

13. An electronic system, characterized in that: The electronic system comprises: A platform controller having a first bus; A plurality of peripheral components are directly coupled to the first bus and coupled to the platform controller through the first bus. The plurality of peripheral components include: a master peripheral element and a slave peripheral element, wherein the master peripheral element and the slave peripheral element are connected to an interrupt signal line, and the master peripheral element communicates with the platform controller through the first bus, When the master peripheral element receives an interrupt request provided by the slave peripheral element through the interrupt signal line, the master peripheral element provides an interrupt signal to the platform controller through the first bus, and the platform controller communicates with the slave peripheral element through the first bus according to the interrupt signal.

14. The electronic system according to claim 13, wherein in an interrupt request time interval, the master peripheral component divides the interrupt request time interval into a plurality of sub-time intervals, and the master peripheral component provides the corresponding interrupt signal to the platform controller according to each of the sub-time intervals corresponding to the received interrupt request.

15. The electronic system according to claim 14, wherein the master peripheral component provides a reset signal to the interrupt signal line in a reset time interval before the interrupt request time interval, wherein each of the sub-time intervals has a synchronization time interval and a signal determination time interval, and the master peripheral component determines whether the interrupt request is received in the signal determination time interval of each of the sub-time intervals. 16 . The electronic system according to claim 15 , wherein the master peripheral component provides a plurality of synchronization signals in the synchronization time interval of each of the sub-time intervals, and the slave peripheral component identifies each of the sub-time intervals according to the plurality of synchronization signals. 17 . The electronic system according to claim 16 , wherein the master peripheral device periodically provides the reset signal and a plurality of the synchronization signals to the interrupt signal line. 18 . The electronic system as claimed in claim 15 , wherein after the master peripheral component receives the enable signal provided by the slave peripheral component to the interrupt signal line, the master peripheral component provides the reset signal to the interrupt signal line.

Images