Sharp pulse generation circuit including a single silicon device

Abstract

The present invention relates to a spike pulse generation circuit including a single silicon device that generates spike pulses aperiodically or periodically. In particular, the present invention relates to a spike pulse generation circuit including a single silicon device that selectively outputs spike pulses related to a neural oscillation function similar to biological oscillation by interrelatedly using a positive feedback loop and a negative feedback loop, thereby enabling the operation of a ring oscillator and a neuron function.

Description

Technical Field

[0001] The present invention relates to a spike generation circuit including a single silicon device that generates non-periodic or periodic spikes in a single silicon device. In particular, the present invention relates to a spike generation circuit including a single silicon device that selectively outputs spikes related to a neural oscillation function similar to biological oscillation by using a positive feedback loop and a negative feedback loop in an interrelated manner, thereby enabling the operation of a ring oscillator and a neuron function. Background Art

[0002] In the fourth industry, due to the explosion of data generated by the Internet of Things, existing von Neumann computing faces physical limitations in data processing.

[0003] That is, in sequential mathematical calculations, existing von Neumann computers exhibit fast working speeds. However, when calculating synchronous concurrent inputs and outputs, there are limitations in terms of speed and power consumption.

[0004] Moreover, complementary metal oxide semiconductor (CMOS) technology cannot be continuously extended any longer.

[0005] Therefore, in order to process a large amount of data, neuromorphic computing is required as a new computing paradigm.

[0006] As artificial neural networks have received increasing attention, the research and development of electronic devices that imitate biological nerves and brain actions, such as convolutional neural networks (CNNs), recurrent neural networks (RNNs), and spiking neural networks (SNNs), is accelerating.

[0007] Among various neuromorphic technologies, spiking neural network technology can achieve more sophisticated thinking abilities by imitating the neural network and brain waves of the brain.

[0008] To implement such a spiking neural network, neurons and synapses need to be implemented by electronic devices. In particular, globally, research is underway to use electronic devices to implement synapses responsible for brain memory and learning.

[0009] Synapse mimicking devices require characteristics such as bidirectional parallel operation, synaptic plasticity, low power, and high integration.

[0010] Existing storage devices cannot perform bidirectional parallel operations and it is difficult to achieve synaptic plasticity. Therefore, research is underway on resistive random-access memory (ReRAM), phase change memory (PCM), conductive bridge memory (CBRAM), etc., which are storage devices with various materials and structures.

[0011] In particular, due to high-speed, real-time operation and biological emulation, spiking neural networks are regarded as the most powerful computational tools for complex pattern recognition, classification, and function evaluation.

[0012] Different from the widely used deep neural network (DNN)-based technology, a spiking neural network is a network that mimics the actions of the human brain. It can process information by adjusting the connection strength of synapses through the interaction between neurons and sending or receiving electrical signals.

[0013] In a spiking neural network, a neuron circuit transmits information by generating a series of spikes and encodes the input signal to generate spikes. In a spiking neural network, multiple neuron circuits are connected to a microchip to process the accumulated and interconnected inputs and outputs.

[0014] Therefore, in order to construct a hardware-based spiking neural network, designing an effective neuron circuit with a small area and low power consumption is the most important consideration.

[0015] A ring oscillator oscillates by connecting an odd number of terminals in the form of complementary metal-oxide-semiconductor inverters to an odd number of cascades. The above complementary metal-oxide-semiconductor includes a complementary metal-oxide-semiconductor of a p-type metal-oxide-semiconductor field-effect transistor (MOSFET) and an n-type metal-oxide-semiconductor field-effect transistor.

[0016] As an essential circuit element for constructing an electronic circuit, a single-structured ring oscillator is used as a clock generator in analog integrated circuits and digital integrated circuits such as logic switch circuits, microprocessors, and memories.

[0017] On the other hand, in existing von Neumann-based systems, the memory and the processor are separated and connected by a bus. However, with the improvement of performance, the data processing speed has encountered a bottleneck, and limitations have started to emerge in processing large-capacity data. To solve the above problems, research on neuromorphic technologies that perform parallel processing by hardware imitating the human neural structure is accelerating. Moreover, in order to imitate biological signals, ring oscillators are essential circuit elements in neuromorphic technologies.

[0018] Different from the centralized and sequential computing of von Neumann computer systems, distributed computing, parallel computing, and event-driven computing in biological neuron systems may be effective.

[0019] Recently, bionic computing systems have been implemented at the software level, but the hardware is still based on the existing von Neumann architecture.

[0020] Although complementary metal-oxide-semiconductor-based neuromorphic circuits for spike-based computing have been developed, the complexity of the circuits and the lack of important dynamics in biological systems can promote the use of new memory device technologies such as phase change memory, resistive memory, and ferroelectric memory.

[0021] In biological cells, interconnected positive and negative feedback loops of chemical reactions generate biological oscillations and must play a role in providing high precision even in the high noise of biological neurons.

[0022] Therefore, it has been proposed to use memristor devices based on artificial neurons to implement biologically inspired systems. However, the spike response of neurons is caused by innate memory dynamics, not vibration dynamics, so it is explained by using stochastic switching dynamics through stochastic neuron functionality.

[0023] Moreover, when emulating biological neurons that only work with input signals, the external bias voltage or the necessary power supply for circuit operation may become a limitation.

[0024] In particular, to improve the integration of neuromorphic technologies, in addition to ring oscillators based on complementary metal-oxide-semiconductor integrated circuit technology, research is also underway on the use of VO 2 and NbO xResearch on a negative differential resistance oscillator with the negative differential resistance (NDR) phenomenon of metal-insulator transition (MIT) materials.

[0025] The negative differential resistance oscillator is composed of a metal-insulator transition device and a resistor. Therefore, compared with the existing complementary metal-oxide-semiconductor (CMOS)-based ring oscillator, it has better performance in terms of integration.

[0026] The existing negative differential resistance oscillator using metal-insulator transition materials cannot use the existing CMOS. Although the CMOS-based ring oscillator has excellent performance, due to the use of a large number of transistors, it exposes limitations in terms of integration when applied to neuromorphic technologies.

[0027] Therefore, it is necessary to develop an oscillator that uses CMOS technology and has few devices like the negative differential resistance oscillator.

[0028] Prior art documents

[0029] Patent documents

[0030] Patent Document 1: Korean Patent Publication No. 2017-0138047, "Neuron Simulation Devices and Circuits"

[0031] Patent Document 2: Korean Patent Publication No. 2018-0127153, "Neural System Simulation Integrated Circuit Combining a Neuron Circuit and a Synaptic Element Array and Manufacturing Method Thereof"

[0032] Non-patent documents

[0033] Non-patent Document 1: M. Vardhana, N. Arunkumar, S. Lasrado, E. Abdulhay, and G. Ramirez. "Convolutional neural network for bio-medical image segmentation with hardware acceleration." Cognitive Systems, vol. 50, pp. 10-14, Aug. 2018, doi: 10.1016 / j.cogsys.2018.03.005.

[0034] Non-Patent Document 2: G. Cauwenberghs. “An analog VLSI recurrent neural network learning a continuous-time trajectory.” IEEE Transactions on Neural Networks, vol.7, no.2, pp.346-361, Mar.1996, doi:10.1109 / 72.485671. Summary of the Invention

[0035] An object of the present invention is to provide a spiking circuit that can selectively generate spikes in such a way that it operates as a neuron simulation circuit by generating spikes non-periodically and as a ring oscillator by generating spikes periodically.

[0036] An object of the present invention is to provide a complementary metal-oxide-semiconductor-based spiking circuit including a single-silicon device having oscillatory neuronal dynamics and stochastic neuronal dynamics.

[0037] An object of the present invention is to provide a spiking circuit that improves the processing speed and integration limitations based on the separation of memory and processor by using an oscillator of a single-silicon device and a resistor that can use existing complementary metal-oxide-semiconductor processes, and can perform processing like the human brain.

[0038] An object of the present invention is to provide a spiking circuit including a single-silicon device that utilizes a positive feedback loop and a negative feedback loop of charge carrier interconnections, and the charge carriers generate neuronal oscillations similar to biological neurons.

[0039] An object of the present invention is to provide a spiking circuit including a single-silicon device in which a potential well formed in a channel region of the single-silicon device acts as a membrane and can continuously store charge carriers in the potential well, thereby performing neuronal behavior sensitive to analog inputs.

[0040] An object of the present invention is to provide a spiking circuit including a single-silicon device that has a two-terminal structure similar to the input and output terminals of a biological neuron and does not require an external power supply or bias input.

[0041] An object of the present invention is to provide a spike generation circuit including a single silicon device, that is, to implement oscillatory neuronal functionalities and stochastic neuronal functionalities by using stochastic feedback switching dynamics.

[0042] In the spike generation circuit including a single silicon device according to an embodiment of the present invention, when a potential generated by an input voltage is greater than a threshold value, a spike corresponding to the generated potential is selectively generated and output according to a firing event occurring due to a positive feedback loop generated in the single silicon device. Based on the generated firing event, a negative feedback loop is triggered in the single silicon device, so that the selectively generated spike can be reset.

[0043] The spike generation circuit can accumulate the input voltage in a channel region of the single silicon device to generate the potential.

[0044] The channel region includes a first channel region doped with n- and a second channel region doped with p-. The channel region generates a potential well for accumulating charge carriers to accumulate the input voltage. When the input voltage is applied, holes can accumulate or recombine in the second channel region.

[0045] The channel region has a potential barrier that can block the injection of charge carriers before the potential is greater than the threshold value.

[0046] In the channel region, as the holes accumulate in the second channel region, the height of the potential barrier becomes lower, so that the positive feedback loop can be generated and the potential barrier is removed only for a specified time.

[0047] When the positive feedback loop is generated, the single silicon device can be set to a latch-up state. When the negative feedback loop is triggered, the single silicon device can be set to a latch-down state.

[0048] In the single silicon device, in the latch-up state, the voltage decreases due to an internal resistance, so that the negative feedback loop can be triggered.

[0049] When the ratio of the combined resistance of the internal resistance in the above-mentioned locked state, the first resistor, and the second resistor, which is related to the combination of the above-mentioned input voltage and the internal resistance in the above-mentioned locked state, is greater than or equal to the latching voltage, the monolithic device can generate the above-mentioned positive feedback loop.

[0050] When the ratio of the combined resistance of the internal resistance in the above-mentioned latching state, the first resistor, and the second resistor, which is related to the combination of the above-mentioned input voltage and the internal resistance in the above-mentioned latching state, is less than or equal to the locking voltage, the monolithic device can generate the above-mentioned negative feedback loop.

[0051] As the magnitude of the above-mentioned input voltage increases, the magnitude and emission speed of the above-mentioned spike pulse can increase.

[0052] The interval of the above-mentioned spike pulse can be changed according to the magnitude of the above-mentioned input voltage.

[0053] The present invention can provide a spike pulse generation circuit as follows, that is, it can selectively generate spike pulses in a manner that generates spike pulses non-periodically for working as a neuron simulation circuit and generates spike pulses periodically for working as a ring oscillator.

[0054] The present invention can provide a complementary metal oxide semiconductor-based spike pulse generation circuit including a monolithic device with oscillatory neuron dynamics and stochastic neuron dynamics.

[0055] The present invention can provide a spike pulse generation circuit as follows, that is, by using an oscillator of a monolithic device and a resistor that can use existing complementary metal oxide semiconductor processes, it improves the processing speed and integration limitations based on the separation of memory and processor, and can perform processing like the human brain.

[0056] The present invention can provide a spike pulse generation circuit including a monolithic device that utilizes positive and negative feedback loops interconnected by charge carriers, and the above-mentioned charge carriers generate neuron oscillations similar to biological neurons.

[0057] The present invention can provide a spike pulse generation circuit including a monolithic device as follows, that is, the potential well formed in the channel region of the monolithic device acts as a membrane, and charge carriers can be continuously stored in the potential well, thereby performing neuron behavior sensitive to analog inputs.

[0058] The present invention can provide a spike pulse generation circuit including a monolithic device as follows, that is, it has a two-terminal structure similar to the input and output terminals of biological neurons and does not require an external power supply or bias input.

[0059] The present invention can provide a spike pulse generation circuit including a monolithic device as follows, that is, it utilizes random feedback switching dynamics to achieve oscillatory neuron functions and stochastic neuron functions. Description of the Drawings

[0060] FIG. 1A to Figure 2D is a diagram for explaining a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0061] Figure 3A is a diagram for explaining the current and voltage characteristics of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0062] Figure 3B is a diagram for explaining the spike response characteristics of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0063] Figures 4A to 4C is a diagram for explaining the operating state of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0064] Figures 5A to 5D is a diagram for explaining the experimental results of neuron spiking behavior of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0065] Figures 6A to 6D is a diagram for explaining the random spike characteristics of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0066] Figure 7 is a diagram for explaining the positive feedback loop generation and negative feedback loop triggering operations of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0067] Figure 8 and Figure 9 is a diagram for comparatively explaining the input and output of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0068] Figure 10 is a diagram for explaining the experimental environment of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0069] Description of Reference Numerals

[0070] 100: Spike generation circuit

[0071] 110: Single silicon device 111: Drain region

[0072] 112: First channel region 113: Second channel region

[0073] 114: Source region 115: Gate region Detailed Description of the Invention

[0074] Hereinafter, various embodiments are described with reference to the accompanying drawings in this document.

[0075] The embodiments and the terms used therein are not intended to limit the technology described in this document to specific embodiments, and should be understood to include various modifications, equivalent technical solutions, and / or alternative technical solutions of the corresponding embodiments.

[0076] Moreover, in the process of describing the present invention below, in cases where it is determined that a detailed description of relevant known functions or structures would obscure the gist of the present invention, the detailed description thereof will be omitted.

[0077] Furthermore, the terms described hereinafter are defined in consideration of their functions in various embodiments, and may vary depending on the intentions or customs of users, operators, etc. Therefore, the definitions should be based on the content throughout the specification.

[0078] In connection with the description of the accompanying drawings, similar reference numerals may be used for similar structural elements.

[0079] Unless clearly indicated otherwise in the context, singular expressions may include plural expressions.

[0080] In this document, expressions such as "A or B" or "at least one of A and / or B" may include all possible combinations of all the items listed simultaneously.

[0081] Expressions such as "first", "second", "the first", or "the second" may modify the corresponding structural elements regardless of order or importance, and are only used to distinguish one structural element from another, without limiting the corresponding structural element.

[0082] When referring to one (e.g., the first) structural element being "connected" or "coupled" (functionally or communicatively) to another structural element (e.g., the second), the above-mentioned one structural element may be directly connected to the above-mentioned another structural element or connected through yet another structural element (e.g., the third).

[0083] In this specification, "configured to" may be used interchangeably, depending on the circumstances, with, for example, "suitable for", "capable of", "changed to", "made into", "able to do", or "designed to" in terms of hardware or software.

[0084] In some cases, the expression "a device configured to..." may mean that the above-mentioned device "is capable of" "doing" together with other devices or components simultaneously.

[0085] For example, the sentence "The processor is configured (or set) to execute A, B, and C" may mean a dedicated processor for executing the corresponding actions (e.g., an embedded processor), or a general-purpose processor (e.g., a CPU or an application processor) that can execute the corresponding actions by executing one or more software programs stored in a memory device.

[0086] Moreover, the term "or" refers to an inclusive "inclusive or" rather than an exclusive "exclusive or".

[0087] That is, unless otherwise mentioned or clearly indicated in the context, the expression "x uses a or b" refers to one of the natural inclusive permutations.

[0088] The terms such as "...... part" and "...... device" used hereinafter refer to a unit that processes at least one function or action, which can be implemented by hardware, software, or a combination of hardware and software.

[0089] Figures 1A to 2D FIG. for illustrating a spike pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0090] Figure 1A Structural elements of a spike pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0091] As an example, the single silicon device can be interpreted as a device such as a diode structure.

[0092] Refer to Figure 1A , the spike pulse generation circuit 100 including the single silicon device 110 includes an input terminal V in and an output terminal V out two terminals, between the input terminal V in and the output terminal V out may include the single silicon device 110 and a plurality of resistors. For example, in the case of periodically generating spike pulses, the spike pulse generation circuit 100 including a single silicon device may refer to an oscillator circuit, and in the case of non-periodically generating spike pulses, the spike pulse generation circuit 100 including a single silicon device may refer to a neuron simulation circuit.

[0093] Therefore, the present invention can provide a spike pulse generation circuit as follows, that is, it can selectively generate spike pulses in a manner that can work as a neuron simulation circuit by non-periodically generating spike pulses and work as a ring oscillator by periodically generating spike pulses.

[0094] According to an embodiment of the present invention, the single-silicon device 110 includes a drain region 111, a first channel region 112, a second channel region 113, a source region 114, and a gate region 115. The gate region 115 can be formed on the first channel region 112.

[0095] As an example, the single-silicon device 110 includes a drain region 111, a channel region including a first channel region 112 and a second channel region 113, and a source region 114. The gate region 115 can be formed on the first channel region 112 in the channel region. That is, the gate region 115 can be located on the channel region.

[0096] Moreover, the drain end of the drain region 111 and the gate end of the gate region 115 can be connected in parallel to the input terminal V for applying an input voltage. in The source end of the source region 114 can be connected in series to the output terminal V for outputting a sharp pulse. out

[0097] For example, the single-silicon device can also refer to one of a SiNW feedback field-effect electron device (FBFET), a p-n-p-n transistor, a memory device, a semiconductor device, a diode structure, a gate-controlled p-n-p-n diode, and a storage device.

[0098] According to an embodiment of the present invention, the single-silicon device can be associated with the applied voltage to be set to a high-resistance state or a low-resistance state, and can store data of a first logic state and data of a second logic state.

[0099] Moreover, the single-silicon device can output a current corresponding to the stored data or maintain the stored data without loss.

[0100] For example, the data of the first logic state can represent "1", and the data of the second logic state can represent "0". On the other hand, in the above description, it is described that the data of the first logic state represents "1" and the data of the second logic state represents "0", but it can be changed flexibly according to the setting of the memory.

[0101] On the other hand, the operation of the single-silicon device storing data of the first logic state as a memory can also be called programming.

[0102] Moreover, the operation of the single-silicon device storing data of the second logic state as a memory can also be called erasing.

[0103] According to an embodiment of the present invention, the drain region 111 is a region doped with a high concentration of p-type impurities, and the drain end can be connected to the input terminal V through the first resistor R. 1 in ​​Connected in series and in parallel with the gate terminal of the gate region 115.

[0104] As an example, the first channel region 112 is a region doped with n-type impurities, the second channel region 113 is a region doped with p-type impurities, and the first channel region 112 and the second channel region 113 can form a potential well and include a potential barrier.

[0105] For example, the potential barrier can block the injection of charge carriers before the electric potential is greater than the threshold value.

[0106] That is, the potential barrier can prevent charge carriers from flowing into the second channel region 113 before the electric potential is greater than the threshold value.

[0107] That is, the channel region can include a first channel region 112 doped with n- and a second channel region 113 doped with p-.

[0108] The channel region generates a potential well for accumulating charge carriers to accumulate the above input voltage V in , when the above input voltage V is applied in , holes accumulate or recombine in the second channel region 113.

[0109] The source region 114, as a region doped with a high concentration of n-type impurities, can be connected in parallel with the second resistor R 2 and the parasitic capacitance, and is connected in series with the output terminal V out .

[0110] p+ can represent the case of being doped with a high concentration of p-type impurities, and n+ can represent the case of being doped with a high concentration of n-type impurities.

[0111] For example, the first resistor R 1 can be 10 MΩ, and the second resistor R 2 can be 1 MΩ.

[0112] According to an embodiment of the present invention, the sharp pulse generation circuit 100 including a single-silicon device can accumulate an input voltage in the channel region of the single-silicon device 110, thereby generating an electric potential. For example, the input voltage can correspond to an electrical signal input from a synapse.

[0113] For example, the voltage accumulated in the channel region can include a process of accumulating as a current in a state where it is changed to a current through a resistor or the like.

[0114] As an example, when the electric potential is greater than the threshold value, the sharp pulse generation circuit 100 including the single-silicon device 110 can selectively generate and output a sharp pulse corresponding to the electric potential according to a discharge event occurring by generating a positive feedback loop in the single-silicon device 110.

[0115] That is, the spike pulse generation circuit 100 including the single silicon device 110 can generate and output spike pulses periodically or generate and output spike pulses aperiodically.

[0116] For example, the threshold value can be a reference value for generating a positive feedback loop or a reference value for removing a barrier.

[0117] According to an embodiment of the present invention, the spike pulse generation circuit 100 including the single silicon device 110 can trigger a negative feedback loop in the single silicon device based on a discharge event, thereby resetting the selectively generated spike pulses.

[0118] According to an embodiment of the present invention, in the channel region, as holes accumulate in the second channel region 113, the height of the barrier becomes lower, thereby generating a positive feedback loop and removing the above-mentioned barrier only within a specified time.

[0119] As an example, in the case of generating a positive feedback loop, the single silicon device can be set to a latch state, and in the case of triggering a negative feedback loop, the single silicon device can be set to a locked state.

[0120] According to an embodiment of the present invention, in the single silicon device, in the latch state, the voltage decreases due to the internal resistance, thereby triggering a negative feedback loop.

[0121] According to an embodiment of the present invention, the spike pulse generation circuit 100 including the single silicon device can generate a positive feedback loop based on the following Mathematical Formula 1 and Mathematical Formula 2.

[0122] Mathematical Formula 1

[0123]

[0124] In Mathematical Formula 1, V in can represent the input voltage, R latch-down can represent the internal resistance in the locked state, R 1 can represent the first resistor, R 2 can represent the second resistor, V latch-up can represent the latch voltage.

[0125] Mathematical Formula 2

[0126]

[0127] In Mathematical Formula 2, V in can represent the input voltage, R latch-up can represent the internal resistance in the latch state, R 1 can represent the first resistor, R 2 can represent the second resistor, V latch-down can represent the lock voltage.

[0128] As an example, when the ratio of the combined resistance of the internal resistance in the locked state, the first resistor, and the second resistor, which is related to the input voltage and the internal resistance in the locked state, is greater than or equal to the latching voltage, the monolithic device can generate a positive feedback loop.

[0129] Moreover, when the ratio of the combined resistance of the internal resistance in the latched state, the first resistor, and the second resistor, which is related to the input voltage and the internal resistance in the latched state, is less than or equal to the locking voltage, the monolithic device can generate a negative feedback loop.

[0130] According to an embodiment of the present invention, when the input voltage is swept from 0V to 3V, the monolithic device generates a positive feedback loop, and when the input voltage is swept from 3V to 0V, a negative feedback loop can be triggered.

[0131] As an example, as the magnitude of the input voltage increases, the magnitude and emission speed of the sharp pulse can increase.

[0132] For example, when the magnitude of the input voltage increases, the occurrence speed of adjacent peaks, which is the interval of the sharp pulses, can increase, and the occurrence speed of adjacent peaks can be associated with the emission speed of the sharp pulses.

[0133] Moreover, the interval of the sharp pulses can be changed according to the magnitude of the input voltage.

[0134] That is, the interval of the sharp pulses can become narrower as the magnitude of the input voltage increases, and can become wider as the magnitude of the input voltage decreases.

[0135] For example, the sharp pulse can be an oscillation signal.

[0136] The sharp pulse generation circuit 100 including a monolithic device according to an embodiment of the present invention can adjust the gains of the positive feedback loop and the negative feedback loop through resistance value and design changes, thereby changing the oscillation waveform.

[0137] As an example, if the gain of the positive feedback loop is increased and the gain of the negative feedback loop is decreased, the sharp pulse generation circuit 100 including a monolithic device is delayed until the locking phenomenon caused by the negative feedback loop occurs after the latching phenomenon caused by the positive feedback loop. Therefore, a square wave pulse in a quadrilateral shape can be repeatedly generated, and since the square wave pulse can be repeatedly generated, the square wave pulse can be used as a clock signal.

[0138] For example, the feedback loop is formed by injecting carriers, so the oscillation frequency can be adjusted by the input voltage. That is, if the input voltage is increased, the carrier injection increases, thereby increasing the oscillation frequency, and if the input voltage is decreased, the oscillation frequency decreases.

[0139] Moreover, the feedback phenomenon occurs through the process of accumulating and dissipating charges in the potential well in the channel of a single-silicon device, indicating that it can be used as a membrane for an existing sharp pulse generation circuit that charges and discharges charges in a capacitor.

[0140] Since it can perform a leaky integrate-and-fire function that can carry out leaky integration in the potential well, discharge based on the latching phenomenon occurring due to the positive feedback loop, and reset process based on the locking phenomenon occurring due to the negative feedback loop, the present invention can be used as a sharp pulse generation circuit that can perform neuron operations through the input flowing into the input terminal of the circuit without an external power supply and without a capacitor.

[0141] Figure 1B An electron microscope photograph of a sharp pulse generation circuit including a single-silicon device for illustrating an embodiment of the present invention.

[0142] Refer to Figure 1B , the sharp pulse generation circuit including a single-silicon device includes a single-silicon device, and the single-silicon device includes a drain region 111, a first channel region 112, a second channel region 113, a source region 114, and a gate region 115.

[0143] Figure 1C and Figure 1D For illustrating various structures of the single-silicon device in the sharp pulse generation circuit including a single-silicon device in an embodiment of the present invention.

[0144] Refer to Figure 1C , the single-silicon device 120 includes a drain region 121, a first channel region 122, a second channel region 123, a source region 124, and a gate region 125.

[0145] As an example, the gate region 125 can be generated and located on the second channel region 123.

[0146] The single-silicon device 120 of an embodiment of the present invention can replace Figure 1A the single-silicon device 110 described in

[0147] Refer to Figure 1D , the single-silicon device 130 includes a drain region 131, a first channel region 132, a second channel region 133, and a source region 134.

[0148] According to an embodiment of the present invention, the single-silicon device 130 can replace Figure 1A the single-silicon device 110 described in

[0149] Figures 2A to 2DA sharp pulse generation circuit with multiple structures based on resistance structure change in a sharp pulse generation circuit including a single silicon device for illustrating an embodiment of the present invention.

[0150] Referring to Figure 2A , in the sharp pulse generation circuit 200 including the single silicon device 201 according to an embodiment of the present invention, a plurality of resistors are located at both ends of the single silicon device 201, and the input voltage at the input end is input through the resistor, and the output end is connected in parallel with the resistor.

[0151] Referring to Figure 2B , in the sharp pulse generation circuit 210 including the single silicon device 211 according to an embodiment of the present invention, a plurality of resistors are located at both ends of the single silicon device 211, and the input end and the output end may have a structure connected to the drain terminal of the single silicon device 211.

[0152] Referring to Figure 2C , the sharp pulse generation circuit 220 including the single silicon device 221 according to an embodiment of the present invention may have the following structure, that is, both ends of the single silicon device 221 are connected to the input end and the output end without a resistor.

[0153] Referring to Figure 2D , in the sharp pulse generation circuit 230 including the single silicon device 231 according to an embodiment of the present invention, the input end is connected to the drain terminal of the single silicon device 231 through a resistor, and the output end is connected to the drain terminal of the single silicon device 231 without a resistor.

[0154] Figures 2A to 2D The single silicon devices 201, 211, 221, 231 of Figure 1A , Figure 1C and Figure 1D may be the single silicon devices 110, 120, 130 described in

[0155] Figure 3A is a diagram for explaining the current and voltage characteristics of a sharp pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0156] Figure 3A For illustrating the current and voltage characteristics of a sharp pulse generation circuit including a single silicon device according to an embodiment of the present invention at room temperature.

[0157] Referring to Figure 3A of the curve graph 300, the curve graph 300 shows the change of the drain current I DD with respect to the change of the drain voltage V DD , indicating that when the drain voltage V DD is swept from 0V to 3V, a positive feedback loop is generated, so that at the latch voltage V latch-up , with the corresponding sharp current increase (1) in the latch state, the drain current I DD increases.

[0158] Moreover, the graph 300 shows that when the drain voltage V DD is swept from 3V to 0V, the negative feedback loop is triggered, resulting in a sharp current decrease (3) corresponding to the locked state at the locked voltage V latch-down , and the drain current I DD decreases.

[0159] That is, in a spike generation circuit including a single silicon device, when a drain voltage equivalent to the input voltage of about 2.3V or more is applied, a positive feedback loop is generated, a discharge event occurs, and thus spikes are generated and output.

[0160] Moreover, in a spike generation circuit including a single silicon device, when a discharge event occurs, as the internal resistance increases, the input drain voltage V DD decreases, thereby triggering the negative feedback loop and resetting the spike.

[0161] Figure 3B It is a diagram for explaining the spike response characteristics of a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0162] Figure 3B It is used to explain the integration time for generating spike responses in a spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0163] Referring to Figure 3B graph 310, graph 310 illustrates the change of the output voltage V in based on the input voltage V out .

[0164] As an example, when an input voltage V in of 2.3V is applied, after integration for a specified time, a positive feedback loop is generated, and thus spikes (1) are generated and output. While the spikes are being output, due to the internal resistance, the input voltage V in decreases by 2.3V (2), thereby triggering the negative feedback loop and resetting the spikes (3).

[0165] As an example, a spike generation circuit including a single silicon device, as a device similar to a biological neuron channel, generates a positive feedback loop according to the accumulation and discharge kinetics, and can trigger a feedback loop according to the output spikes, thereby automatically resetting to the initial state after a discharge event.

[0166] According to an embodiment of the present invention, a spike generation circuit including a single silicon device can generate multiple consecutive spikes by repeatedly performing positive feedback loops and negative feedback loops, thereby generating neuron oscillations.

[0167] For example, a spike pulse generation circuit including a single silicon device can adjust an input amplitude to the number of spike events within a preset time interval.

[0168] According to an embodiment of the present invention, when a specified voltage is applied to a spike pulse generation circuit including a single silicon device, spike pulses corresponding to oscillations are generated and output based on a latching phenomenon based on a positive feedback loop and a locking phenomenon based on a negative feedback loop.

[0169] Figures 4A to 4C FIG. is a diagram for explaining an operation state of a spike pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0170] Figure 4A FIG. is a band diagram for explaining a leaky integration operation state of a spike pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0171] Referring to Figure 4A In the band diagram 400, in a spike pulse generation circuit including a single silicon device, in order to implement a stochastic firing response of a neural network based on a spike response function of an analog input, after reaching 5 pulses, spike pulses are generated after a membrane potential reaches a threshold.

[0172] Moreover, a spike pulse generation circuit including a single silicon device can implement Shockley-Read-Hall generation and recombination based on stochastic feedback switching dynamics or accumulate and recombine charge carriers in a potential well through an interband tunneling process.

[0173] For example, a spike response associated with the generation of analog or mixed-signal spike pulses in an artificial neuron is one of the neuron functions for analog computing in a neural network.

[0174] Referring to the band diagram 400, in a second channel region, a potential barrier is being formed and holes are being accumulated or recombined. The more holes are accumulated, the more the potential barrier in the second channel region can be reduced.

[0175] Moreover, when a sine wave is applied to an input node, analog tuning in an artificial neuron is achieved by modulating a neuron oscillation frequency. Although the sine wave input signal can be greater than a stimulation threshold, each spike amplitude can be kept almost constant.

[0176] Figure 4B FIG. is a band diagram for explaining a discharge operation state of a spike pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0177] Referring to Figure 4BThe energy band diagram 410 shows that when the electric potential exceeds the threshold value, the potential barrier collapses, and a positive feedback loop is generated simultaneously. As the potential barrier collapses, charge (electron) carriers move towards the channel region.

[0178] Figure 4C It is an energy band diagram for explaining the reset operation state of a spike pulse generation circuit including a single-silicon device according to an embodiment of the present invention.

[0179] Refer to Figure 4C In the energy band diagram 420, charge carriers accumulate and recombine in the potential well. As the charge carriers move towards the channel region, a negative feedback loop is triggered, causing the spike pulse generation circuit including the single-silicon device to return to its initial state.

[0180] Among them, the group of charge carriers in the potential well may be different from the charge carriers in the potential well in the initial state.

[0181] According to an embodiment of the present invention, the function of the potential well in the single-silicon device of the spike pulse generation circuit including the single-silicon device is to store and release charges, thereby playing the role of a membrane. The latching phenomenon based on the positive feedback loop can selectively discharge the spike pulse, and the negative feedback loop can selectively reset the spike pulse through the locking phenomenon.

[0182] For example, the spike pulse generation circuit including the single-silicon device can generate spike pulses periodically with a specified period or non-periodically without a specified period.

[0183] Figures 5A to 5D It is a graph for explaining the experimental results of the neuron spike behavior of a spike pulse generation circuit including a single-silicon device according to an embodiment of the present invention.

[0184] Figures 5A to 5D It is used to illustrate the operation characteristics of a spike pulse generation circuit including a single-silicon device according to an embodiment of the present invention.

[0185] Refer to Figure 5A In the curve graph 500, it shows the change of the output voltage based on the input voltage. When the input voltage is above 2.3V, spike pulses are confirmed at specified intervals in the output voltage.

[0186] That is, the intrinsic probability of the spike pulse generation circuit including the single-silicon device can represent the distribution of the interspike interval, and the above interspike interval is defined as the time difference between continuously generated spike pulses in multiple leaky integration and discharge cycles.

[0187] When the distribution of the spike intervals is periodic, the spike pulse generation circuit including the single-silicon device can operate as a ring oscillator circuit.

[0188] For example, for a spiking circuit including a single silicon device, the random dynamics sensitive to the input noise of the spiking circuit maintains a symmetric peak-to-peak interval distribution.

[0189] Refer to Figure 5B Graph 510, which shows the spiking event occurrence frequency based on the increase in the input voltage.

[0190] For example, in a spiking circuit including a single silicon device, when the input voltage increases from 2.3V to 3.1V, the peak-to-peak interval around the average response of consecutive spikes can decrease.

[0191] That is, if the input voltage increases, the spiking circuit including a single silicon device can output spikes at a higher frequency and can be reset.

[0192] For example, by increasing the magnitude of the input voltage from 2.3V to 3.1V, the average emission speed of consecutive spikes can be adjusted from 61.0Hz to 210.5Hz, but the consistency of the spike amplitude and the probability of the frequency response are maintained.

[0193] Moreover, the distribution of the active potential duration determined by the interconnected positive feedback loop and negative feedback loop can be achieved through random feedback switching dynamics.

[0194] Refer to Figure 5C Graph 520, which is used to illustrate the output change of spikes as the input voltage is periodically changed from 2.3V to 0V.

[0195] According to Graph 520, it shows that spikes are output at a specified interval regardless of whether the input voltage decreases or increases.

[0196] That is, it can be seen from Graph 520 that the variation in the action duration does not depend on the magnitude of the input stimulus, which can indicate that the interconnected positive feedback loop and negative feedback loop of the spiking circuit including a single silicon device are similar to the feedback mechanism of biological cells.

[0197] Refer to Figure 5D Graph 530, the effective refractory period within the input voltage range can be shown as an irregular and distorted distribution.

[0198] For example, the effective refractory period can represent the random characteristics of the feedback switching dynamics according to the result that can be evaluated through the accumulation and recombination process of charge carriers in the potential well.

[0199] According to an embodiment of the present invention, the spiking circuit including a single silicon device can periodically or aperiodically adjust the frequency of the output spikes by adjusting the magnitude of the input voltage.

[0200] That is, the spike generation circuit including a single silicon device can be controlled in the following manner, that is, by constantly maintaining the magnitude of the input voltage to periodically output spikes, or by repeatedly changing the magnitude of the input voltage to non-periodically output spikes.

[0201] In other words, the spike generation circuit including a single silicon device can adjust the interval for generating spikes according to the magnitude of the input voltage, thereby generating spikes periodically or non-periodically.

[0202] Figures 5A to 5D Shows the following characteristics, that is, as charges are accumulated and discharged in the potential well of the single silicon device in the spike generation circuit including a single silicon device, the oscillation phenomenon in the single silicon device is utilized to perform the leakage integration discharge operation.

[0203] Moreover, the spike generation circuit including a single silicon device can perform neuron actions for analog inputs by utilizing the change in oscillation frequency based on charge input.

[0204] That is, the spike generation circuit including a single silicon device can utilize the change in oscillation frequency based on charge input, and according to the spikes non-periodically generated for the analog input, operate as a neuron analog circuit.

[0205] In other words, the spike generation circuit including a single silicon device can operate as a ring oscillator circuit as spikes are generated periodically, and can operate as a neuron analog circuit as spikes are generated non-periodically.

[0206] Figures 6A to 6D It is a diagram for explaining the random spike characteristics of the spike generation circuit including a single silicon device according to an embodiment of the present invention.

[0207] Figure 6A The curve graph 600 is used to illustrate the peak-to-peak interval based on the increase in the input voltage.

[0208] According to the curve graph 600, embodiments 601, 602, 603, 604, 605, 606, 607, 608, and 609 are shown based on the magnitude of the voltage.

[0209] Observing the peak-to-peak intervals of embodiments 601 to 609, the peak-to-peak interval can decrease as the input voltage increases.

[0210] That is, the larger the magnitude of the input voltage, the higher the frequency at which the spike generation circuit including a single silicon device outputs and resets spikes, and the narrower the peak-to-peak interval at which it outputs and resets spikes.

[0211] Figure 6BThe curve graph 610 is used to illustrate the interspike frequency based on the increase of the input voltage.

[0212] According to the curve graph 610, embodiments 611, 612, 613, 614, 615, 616, 617, 618, and 619 are shown based on the magnitude of the voltage.

[0213] Observing the interspike frequencies of embodiments 611 to 619, the interspike frequency can increase as the input voltage increases.

[0214] That is, the larger the magnitude of the input voltage, the higher the frequency at which the spike generation circuit including a single silicon device outputs and resets spikes.

[0215] Figure 6C The curve graph 620 is used to illustrate the action potential duration based on the increase of the input voltage.

[0216] According to the curve graph 620, embodiments 621, 622, 623, 624, 625, 626, 627, 628, and 629 are shown based on the magnitude of the voltage.

[0217] Observing the action potential durations of embodiments 621 to 629, the action potential duration can increase as the input voltage increases.

[0218] That is, the larger the magnitude of the input voltage, the higher the action potential duration at which spikes are output and reset.

[0219] Figure 6D The curve graph 630 is used to illustrate the effective refractory period based on the increase of the input voltage.

[0220] According to the curve graph 630, embodiments 631, 632, 633, 634, 635, 636, 637, 638, and 639 are shown based on the magnitude of the voltage.

[0221] Observing the effective refractory periods of embodiments 631 to 639, the effective refractory period can increase as the input voltage increases.

[0222] That is, the larger the magnitude of the input voltage, the higher the effective refractory period at which spikes are output and reset.

[0223] According to an embodiment of the present invention, a spike pulse generation circuit including a single silicon device can perform neuron actions in the single silicon device based on a random feedback phenomenon caused by phenomena such as tunneling and random recombination / generation.

[0224] Therefore, the spike pulse generation circuit including a single silicon device according to an embodiment of the present invention can operate as a ring oscillator circuit with periodic generation of spike pulses and can operate as a neuron simulation circuit with non-periodic generation of spike pulses.

[0225] Figure 7 It is a diagram for explaining the positive feedback loop generation and negative feedback loop triggering actions of the spike pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0226] Refer to Figure 7 In the case of generating a positive feedback loop, the single silicon device 700 of the spike pulse generation circuit including a single silicon device is converted from a high resistance state (HRS) to a low resistance state (LRS). In the case of triggering a negative feedback loop, the single silicon device 700 of the spike pulse generation circuit including a single silicon device can be converted from a low resistance state to a high resistance state.

[0227] That is, the spike pulse generation circuit including a single silicon device can generate a latching phenomenon and a locking phenomenon in the single silicon device 700 through a feedback action mechanism of electrons and holes.

[0228] The latching phenomenon caused by the positive feedback loop can serve to reduce the resistance of the single silicon device 700, and the locking phenomenon caused by the negative feedback loop can serve to increase the resistance of the single silicon device 700.

[0229] In the spike pulse generation circuit including a single silicon device, when an input voltage is applied, latching occurs in the single silicon device 700 due to the positive feedback loop, and at the same time, the voltage applied to the single silicon device 700 is reduced due to the voltage division with the resistor, and locking occurs due to the negative feedback loop.

[0230] Therefore, in the spike pulse generation circuit including a single silicon device, the voltage applied to the single silicon device 700 is increased, and a positive feedback loop can be formed again thereby. Oscillation can be generated while repeating the above process.

[0231] Therefore, the spike pulse generation circuit including a single silicon device can generate spike pulses periodically or non-periodically.

[0232] Figure 8 and Figure 9 It is a diagram for comparing and explaining the input and output of the spike pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0233] Reference Figure 8 The graphs 800 to 880 are used to illustrate the change in the output voltage when an input voltage is applied in a square wave and increased.

[0234] In graph 800, the input voltage is 2.3 V, in graph 810, the input voltage is 2.4 V, in graph 820, the input voltage is 2.5 V, in graph 830, the input voltage is 2.6 V, in graph 840, the input voltage is 2.7 V, in graph 850, the input voltage is 2.8 V, in graph 860, the input voltage is 2.9 V, in graph 870, the input voltage is 3.0 V, and in graph 880, the input voltage is 3.1 V.

[0235] Referring to FIGS. 800 to 880, the peak-to-peak interval can decrease as the input voltage increases from 2.3 V to 3.1 V.

[0236] That is, the frequency of generating and resetting the sharp pulses can increase as the input voltage increases.

[0237] Figure 9 Shows the change characteristics of the oscillation frequency based on the input voltage applied to a sharp pulse generation circuit including a single silicon device according to an embodiment of the present invention.

[0238] Reference Figure 9 The graphs 900 to 980 are used to illustrate the change in the output voltage when an input voltage is applied while maintaining the same voltage and increased.

[0239] In graph 900, the input voltage is 2.3 V, in graph 910, the input voltage is 2.4 V, in graph 920, the input voltage is 2.5 V, in graph 930, the input voltage is 2.6 V, in graph 940, the input voltage is 2.7 V, in graph 950, the input voltage is 2.8 V, in graph 960, the input voltage is 2.9 V, in graph 970, the input voltage is 3.0 V, and in graph 980, the input voltage is 3.1 V.

[0240] Referring to FIGS. 900 to 980, the peak-to-peak interval can decrease as the input voltage increases from 2.3 V to 3.1 V.

[0241] That is, the frequency of generating and resetting the sharp pulses can increase as the input voltage increases.

[0242] Moreover, in the sharp pulse generation circuit including a single silicon device, the carrier injection is changed according to the input voltage. Therefore, the interaction of the positive feedback loop and the negative feedback loop phenomena is changed, which causes the oscillation frequency to change.

[0243] That is, as the input voltage applied to the sharp pulse generation circuit including a single silicon device increases, the oscillation frequency can also increase.

[0244] In other words, the sharp pulse generation circuit including a single silicon device can adjust the interval for generating sharp pulses according to the magnitude of the applied input voltage.

[0245] Therefore, the sharp pulse generation circuit including a single silicon device can be controlled in such a way that the interval for generating sharp pulses is determined to be periodic by making the magnitudes of the applied input voltages the same, or the interval for generating sharp pulses is determined to be non-periodic by repeatedly changing the magnitudes of the input voltages.

[0246] Figure 10 FIG. is a diagram of an experimental environment of a sharp pulse generation circuit including a single silicon device for illustrating an embodiment of the present invention.

[0247] Refer to Figure 10 , the experimental environment 1000 of the sharp pulse generation circuit including a single silicon device exemplifies an environment in which the sharp pulse generation circuit including a single silicon device is connected to the output and input ends of an oscilloscope to export Figure 9 and Figure 10 the curve graph of as an output result.

[0248] The devices described above can be implemented by hardware structure elements, software structure elements, and / or a combination of hardware structure elements and software structure elements. For example, like a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any device that executes and responds to instructions, the devices and structure elements described in the embodiments can be implemented using one or more general-purpose computers or special-purpose computers. The processing device can execute an operating system (OS) and one or more application programs executed on the above operating system. Also, the processing device can access, store, operate, process, and generate data in response to the execution of software. For ease of understanding, the case of using one processing device is described. As long as those of ordinary skill in the art can understand, the processing device can include multiple processing elements and / or multiple types of processing elements. For example, the processing device can include multiple processors or one processor and one controller. Also, other processing configurations such as a parallel processor can be included.

[0249] Software may include a computer program, code, instruction, or a combination of more than one of them, and can be configured to form a processing device in a manner that works as required or to transfer instructions to the processing device independently or collectively. In order to interpret or provide instructions or data to the processing device, software and / or data may be permanently or temporarily embodied in any type of machine, structural component, physical device, virtual equipment, computer storage medium or device, or the transmitted signal wave. Software may be distributed on computer systems connected through a network and stored or executed in a distributed manner. Software and data may be stored on more than one computer-readable recording medium.

[0250] As described above, the embodiments have been described through defined embodiments and drawings. As long as they are ordinary technical personnel in the technical field, various modifications and deformations can be made through the above records. For example, the described technology is executed in an order different from the described method and / or the structural components of the described system, structure, device, circuit, etc. are combined or combined in a form different from the described method, or even if they are replaced or substituted by other structural components or equivalent technical solutions, appropriate results can still be achieved.

[0251] Therefore, other examples, other embodiments, and solutions within the equivalent scope of the invention claimed also belong to the scope of the appended invention claimed.

Claims

1. A sharp pulse generating circuit including a single silicon device, characterized in that, the single silicon device includes a drain region, a first channel region, a second channel region, a source region and a gate region, wherein an input voltage is applied from an input terminal of the single silicon device to the drain region and the gate region, when the potential generated by the charge carriers accumulated in the potential well in the first channel region is greater than the threshold corresponding to the energy level for removing the potential barrier in the second channel region when the input voltage is applied, the charge carriers move from the source region to the first channel region and the second channel region to generate a positive feedback loop that causes the single silicon device to change from a high-resistance state to a low-resistance state, and according to the discharge event generated by generating the positive feedback loop, a sharp pulse corresponding to the generated potential is output to an output terminal connected to the source region, wherein the potential barrier causes holes to accumulate or recombine in the second channel region when the input voltage is applied, as the internal resistance in the single silicon device increases based on the discharge event to generate a negative feedback loop, so that the input voltage decreases and the single silicon device changes from the low-resistance state to the high-resistance state, thereby resetting the generated sharp pulse.

2. The sharp pulse generating circuit including a single silicon device according to claim 1, characterized in that, before the potential is greater than the threshold, the potential barrier blocks the injection of charge carriers from the source region into the second channel region.

3. The sharp pulse generating circuit including a single silicon device according to claim 2, characterized in that, in the second channel region, as the holes accumulate in the second channel region, the height of the potential barrier becomes lower, thereby generating the positive feedback loop and removing the potential barrier only within a specified time.

4. The sharp pulse generating circuit including a single silicon device according to claim 1, characterized in that, when the positive feedback loop is generated, the single silicon device is set to a latching state corresponding to the low-resistance state, and when the negative feedback loop is generated, the single silicon device is set to a locked state corresponding to the high-resistance state.

5. The sharp pulse generating circuit including a single silicon device according to claim 4, characterized in that, when the ratio of the product of the voltage value of the input voltage and the resistance value of the internal resistance in the locked state to a combined value is greater than or equal to the latching voltage, the single silicon device generates the positive feedback loop, wherein the combined value is the sum of the resistance value of the internal resistance in the locked state, the resistance value of a first resistor connected between the input terminal and the drain region, and the resistance value of a second resistor connected between the output terminal and the source region.

6. The sharp pulse generating circuit including a single silicon device according to claim 5, characterized in that, When the ratio of the product of the voltage value of the above input voltage and the resistance value of the internal resistance in the above latch state to another combined value is less than or equal to the locking voltage, the above single-silicon device generates the above negative feedback loop, where the above another combined value is the sum of the resistance value of the internal resistance in the above latch state, the resistance value of the above first resistor, and the resistance value of the above second resistor.

7. The sharp pulse generating circuit including a single-silicon device according to claim 1, wherein, as the magnitude of the above input voltage increases, the emission speed of the above sharp pulse increases, where the above emission speed is associated with the frequency occurring within a predetermined time interval.

8. The sharp pulse generating circuit including a single-silicon device according to claim 7, wherein, when the time interval associated with the above occurring frequency changes with the change in the magnitude of the above input voltage, the above sharp pulse generating circuit generates the above sharp pulse periodically or aperiodically.

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