Semiconductor memory device

Abstract

A semiconductor device includes a plurality of first conductive patterns extending in parallel on a substrate in a first direction, a plurality of second conductive patterns extending in parallel on the substrate in a second direction crossing the first direction, a plurality of buried contacts connected to the substrate between the plurality of first conductive patterns and between the plurality of second conductive patterns, and a landing pad connected to each buried contact on the plurality of buried contacts. The landing pad includes a first side surface extending in the first direction in a plan view and a second side surface extending in a third direction in the plan view. In the plan view, the third direction is different from the first direction and the second direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices and / or methods for manufacturing such semiconductor memory devices. More specifically, this disclosure relates to semiconductor memory devices including capacitors and / or methods for manufacturing such semiconductor memory devices. Background Technology

[0002] As semiconductor memory devices become more highly integrated, individual circuit patterns have become smaller to accommodate more semiconductor memory devices within the same area. To compensate for this, the aspect ratio of each circuit pattern tends to increase; however, increasing the aspect ratio can increase fabrication complexity and lead to defects such as pattern collapse. Summary of the Invention

[0003] This disclosure provides a semiconductor memory device having a fine circuit pattern that can be implemented with low process difficulty.

[0004] The present disclosure also provides a method for manufacturing a semiconductor memory device having a fine circuit pattern that can be implemented with low process difficulty.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description.

[0006] According to one embodiment, a semiconductor memory device may include: a substrate; a plurality of first conductive patterns extending parallel to each other in a first direction on the substrate; a plurality of second conductive patterns extending parallel to each other in a second direction intersecting the first direction on the substrate; a plurality of buried contacts connected to the substrate between the plurality of first conductive patterns and between the plurality of second conductive patterns; and a landing pad on and connected to each of the plurality of buried contacts via a mask contact. The landing pad may include a first side surface extending in the first direction in a plan view and a second side surface extending upward in a third direction different from the first and second directions in a plan view.

[0007] According to another embodiment, a semiconductor memory device may include: a substrate; a first conductive pattern extending in a first direction on the substrate; a first buried contact on the substrate and connected to the substrate on one side of the first conductive pattern; a second buried contact on the substrate and connected to the substrate on the other side of the first conductive pattern; a first landing pad connected to the first buried contact; a second landing pad connected to the second buried contact; and capacitors respectively connected to the first landing pad and the second landing pad. The first landing pad may include a first side surface forming an acute angle with the first direction in a plan view. The second landing pad may include a second side surface coplanar with the first side surface.

[0008] According to another embodiment, a semiconductor memory device may include: a substrate; a device isolation layer defining a plurality of active regions on and within the substrate; word lines extending in a first direction intersecting each active region in the substrate; bit lines on the substrate and connected to each of the plurality of active regions, the bit lines extending in a second direction intersecting the first direction; a plurality of buried contacts on the side surfaces of the bit lines, the plurality of buried contacts being respectively connected to the plurality of active regions; a plurality of landing pads on the plurality of buried contacts, the plurality of landing pads being respectively connected to the buried contacts; and a plurality of capacitors, respectively connected to the landing pads. The plurality of landing pads may be arranged in a honeycomb structure. Each of the plurality of landing pads may include a first side surface extending in the first direction in a plan view and a second side surface extending upward in a third direction different from the first and second directions in a plan view.

[0009] According to one embodiment, a method for manufacturing a semiconductor memory device may include: forming a plurality of first conductive patterns on a substrate, the plurality of first conductive patterns extending parallel in a first direction; forming a plurality of second conductive patterns on the substrate, the plurality of second conductive patterns extending parallel in a second direction intersecting the first direction; forming a plurality of buried contacts connected to the substrate between the plurality of first conductive patterns and between the plurality of second conductive patterns; forming initial landing pads on the plurality of buried contacts, the initial landing pads overlapping at least two of the plurality of buried contacts, and the initial landing pads extending upward in a third direction different from the first and second directions; and patterning the initial landing pads to form landing pads connected to the at least two buried contacts. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 This is an example layout diagram illustrating a semiconductor memory device according to some embodiments.

[0012] Figure 2 It is shown Figure 1 Partial layout diagram of the unit area and core / peripheral area.

[0013] Figure 3 Show along Figure 2 The sectional view taken by lines AA and BB.

[0014] Figure 4 It is along Figure 2 The sectional view taken by the CC line.

[0015] Figure 5 It is along Figure 2 The sectional view taken by line DD.

[0016] Figure 6 It is shown Figures 2 to 5 A partial layout diagram of the landing pads.

[0017] Figures 7 to 11 These are partial layout diagrams used to illustrate various implementations of semiconductor memory devices.

[0018] Figures 12 to 25 This is a view illustrating intermediate operations of a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0019] In the following text, reference will be made to Figures 1 to 5 Describes semiconductor memory devices according to some implementation methods.

[0020] Although the terms first, second, etc., may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are used to distinguish one element or component from another. Therefore, the first element or component discussed below may be referred to as the second element or component without departing from the teachings of this disclosure.

[0021] Figure 1 This is an example layout diagram illustrating a semiconductor memory device according to some embodiments. Figure 2 It is shown Figure 1 Partial layout diagram of the unit area and core / peripheral area. Figure 3 Show along Figure 2 The sectional view taken by lines AA and BB. Figure 4 It is along Figure 2 The sectional view taken by the CC line. Figure 5 It is along Figure 2 The sectional view taken by line DD.

[0022] Reference Figure 1According to some implementations, semiconductor memory devices include cell regions (CELL) and core / peripheral regions (CORE / PERI).

[0023] In the cell area CELL, a component isolation layer 110, a substrate insulating layer 120, word lines WL, bit lines BL, direct contacts DC, bit line spacers 140, buried contacts BC, landing pads LP, capacitors 190, etc. (which will be described later) can be formed to realize semiconductor memory elements on the substrate 100.

[0024] The core / peripheral region (CORE / PERI) can be arranged around the cell region (CELL). For example, the core / peripheral region (CORE / PERI) can surround the cell region (CELL). In the core / peripheral region (CORE / PERI), control elements and dummy elements such as the third conductive pattern 230 and wiring pattern BP (which will be described later) can be formed to control the function of the semiconductor memory element formed in the cell region (CELL).

[0025] Reference Figures 2 to 5 According to some embodiments, a semiconductor memory device includes a substrate 100, a component isolation layer 110, a substrate insulating layer 120, a word line WL, a bit line BL, a direct contact DC, a bit line spacer 140, a buried contact BC, a landing pad LP, a capacitor 190, a third conductive pattern 230, and a wiring pattern BP.

[0026] Substrate 100 may have a structure in which a base substrate and an epitaxial layer are stacked, but the inventive concept is not limited thereto. Substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate. For example, in the following description, substrate 100 may be a silicon substrate.

[0027] The substrate 100 may include an active region AR. As the design specifications of semiconductor memory devices decrease, the active region AR can be formed as a slanted strip. For example, as... Figure 2 As shown, the active region AR can have a stripe extending in a third direction D1, different from the first direction X and the second direction Y, on a plane extending in the first direction X and the second direction Y. In some embodiments, the third direction D1 can form a first acute angle θ1 with the first direction X. The first acute angle θ1 can be, for example, 60 degrees, but is not limited thereto.

[0028] The active region AR can be in the form of multiple strips extending in directions parallel to each other. Furthermore, one of the multiple active region ARs can be arranged such that its center is positioned close to the end of another active region AR.

[0029] The active region AR may include impurities to serve as source / drain regions. In some implementations, the center of the active region AR may be connected to the bit line BL via a direct contact DC, and the two ends of the active region AR may be connected to the capacitor 190 via a buried contact BC and a landing pad LP.

[0030] Component isolation layer 110 can define the plurality of active regions AR. Although in Figures 2 to 5 The element isolation layer 110 shown has a sloping side surface due to the characteristics of the process used, but the inventive concept is not limited thereto.

[0031] The component isolation layer 110 may include, but is not limited to, at least one of silicon oxide, silicon nitride, and combinations thereof. The component isolation layer 110 may be a single layer made of an insulating material or a multilayer made of a combination of several insulating materials.

[0032] The substrate insulating layer 120 may be formed on the substrate 100 and the component isolation layer 110. In some embodiments, the substrate insulating layer 120 may extend along the top surface of the substrate 100 and the top surface of the component isolation layer 110 in areas where no direct contact DC and buried contact BC are formed.

[0033] As shown in the accompanying drawings, the substrate insulating layer 120 may be a single layer or multiple layers. For example, the substrate insulating layer 120 may include a first insulating layer 122, a second insulating layer 124, and a third insulating layer 126 sequentially stacked on the substrate 100.

[0034] The first insulating layer 122 may include, for example, silicon oxide. The second insulating layer 124 may include a material having an etch selectivity different from that of the first insulating layer 122. For example, the second insulating layer 124 may include silicon nitride. The third insulating layer 126 may include a material having a dielectric constant smaller than that of the second insulating layer 124. For example, the third insulating layer 126 may include silicon oxide.

[0035] The word line WL can extend in the first direction across the active region AR and the bit line BL. For example, as Figure 2 As shown, word lines WL can obliquely cross the active region AR and vertically cross the bit line BL. Word lines WL can be interposed between the direct contact DC and the buried contact BC, as will be described later. The multiple word lines WL can extend parallel to each other. For example, the multiple word lines WL can be formed to be spaced at equal intervals and extend in a first direction X.

[0036] like Figure 4 and Figure 5As shown, the word line WL may include a first conductive pattern 160. As illustrated in the figures, the first conductive pattern 160 may be a single layer or multiple layers. For example, the first conductive pattern 160 may include a first sub-conductive pattern 164 and a second sub-conductive pattern 166 sequentially stacked on the substrate 100. The first sub-conductive pattern 164 and the second sub-conductive pattern 166 may each include at least one of, for example, metal, polysilicon, and combinations thereof, but are not limited thereto.

[0037] The word line dielectric layer 162 may be interposed between the first conductive pattern 160 and the substrate 100. The word line dielectric layer 162 may include, but is not limited to, at least one of silicon oxide, silicon oxide nitride, silicon nitride, and a high dielectric constant (high k) material having a higher dielectric constant than silicon oxide.

[0038] The word line overlay pattern 168 may be formed on the first conductive pattern 160. The word line overlay pattern 168 may include, but is not limited to, silicon nitride.

[0039] In some embodiments, the word line WL may be buried in the substrate 100. For example, the substrate 100 may include a word line trench WT extending in a first direction. A word line dielectric layer 162 may extend along the contour of the word line trench WT. A first conductive pattern 160 may fill a portion of the word line trench WT on the word line dielectric layer 162. A word line overlay pattern 168 may fill another portion of the word line trench WT on the first conductive pattern 160. Thus, the top surface of the first conductive pattern 160 may be formed below the top surface of the substrate 100.

[0040] Bit lines BL can be formed on substrate 100, element isolation layer 110, and substrate insulating layer 120. Bit lines BL can extend in the second direction Y to pass through active region AR and word line WL. For example, bit lines BL can obliquely cross active region AR and vertically cross word line WL. Multiple bit lines BL can extend parallel to each other. For example, the multiple bit lines BL can be formed to be spaced apart at equal intervals and extend in the second direction Y.

[0041] like Figure 3 As shown, the bit line BL may include a second conductive pattern 130. As illustrated in the figures, the second conductive pattern 130 may be a single layer or multiple layers. For example, the second conductive pattern 130 may include a third sub-conductive pattern 132, a fourth sub-conductive pattern 134, and a fifth sub-conductive pattern 136 sequentially stacked on the substrate 100.

[0042] The third sub-conductive pattern 132, the fourth sub-conductive pattern 134, and the fifth sub-conductive pattern 136 may each include, for example, polysilicon, TiN, TiSiN, tungsten, tungsten silicide, or combinations thereof, but are not limited thereto. For example, the third sub-conductive pattern 132 may include polysilicon, the fourth sub-conductive pattern 134 may include TiSiN, and the fifth sub-conductive pattern 136 may include tungsten.

[0043] The first line cover pattern 138 and the second line cover pattern 139 may be sequentially formed on the second conductive pattern 130. The first line cover pattern 138 and the second line cover pattern 139 may extend along the top surface of the second conductive pattern 130. The first line cover pattern 138 and the second line cover pattern 139 may include, but are not limited to, silicon nitride.

[0044] Direct contacts (DCs) can be formed on substrate 100 and component isolation layer 110. The direct contacts (DCs) can penetrate substrate insulating layer 120 to connect the active region AR of substrate 100 to bit line BL. For example, substrate 100 may include a first contact trench CT1. The first contact trench CT1 can penetrate substrate insulating layer 120 to expose at least a portion of the active region AR. Direct contacts (DCs) can be formed in the first contact trench CT1 to connect the active region AR of substrate 100 to second conductive pattern 130.

[0045] In some embodiments, the first contact trench CT1 may expose the center of each active region AR. Therefore, the direct contact DC may be connected to the center of the active region AR. In some embodiments, a portion of the first contact trench CT1 may overlap with a portion of the component isolation layer 110. Therefore, the first contact trench CT1 may expose a portion of the component isolation layer 110 and a portion of the active region AR.

[0046] In some embodiments, the direct contact DC may be smaller in width than the first contact trench CT1. For example, the direct contact DC may only contact a portion of the substrate 100 exposed by the first contact trench CT1, such as... Figure 3 As shown. In some embodiments, the bit line BL may be smaller in width than the first contact trench CT1. For example, the bit line BL may be equal in width to the direct contact DC.

[0047] Direct contact with DC can include conductive materials. Therefore, the bit line BL can be electrically connected to the active region AR of the substrate 100. The active region AR of the substrate 100 connected to the direct contact with DC can be used as the source / drain region of a semiconductor element including the word line WL.

[0048] In some embodiments, the direct contact DC may comprise the same material as the third sub-conductive pattern 132. For example, the direct contact DC may comprise polysilicon. However, the inventive concept is not limited thereto, and depending on the manufacturing process, the direct contact DC may comprise a material different from the material of the third sub-conductive pattern 132.

[0049] Bit line spacers 140 can be formed on the side surface of the bit line BL. Bit line spacers 140 can extend along the side surface of the bit line BL. For example, bit line spacers 140 can extend in the second direction Y, such as... Figure 2 and Figure 3 As shown.

[0050] In some embodiments, bit line spacers 140 may be multilayered, formed by a combination of several insulating materials. For example, bit line spacers 140 may include a first spacer 141, a second spacer 142, a third spacer 143, a fourth spacer 144, and a fifth spacer 145.

[0051] The first spacer 141 may extend along the side surface of the bit line BL. For example, the first spacer 141 may extend along the side surface of the second conductive pattern 130, the side surface of the first bit line overlay pattern 138, and the side surface of the second bit line overlay pattern 139.

[0052] The first spacer 141 may extend along the side surface of the bit line BL and the top surface of the substrate insulating layer 120 in the region where the first contact trench CT1 is not formed. The first spacer 141 may extend along the side surface of the bit line BL, the side surface directly contacting the DC, and the first contact trench CT1 in the region where the first contact trench CT1 is formed. In some embodiments, the first spacer 141 may contact both the bit line BL and the DC.

[0053] The second spacer 142 may be formed in the first contact groove CT1 on the first spacer 141. For example, the second spacer 142 may extend in the first contact groove CT1 along the contour of the first spacer 141.

[0054] The third spacer 143 can be formed in the first contact trench CT1 on the second spacer 142. The third spacer 143 can fill the area of ​​the first contact trench CT1 remaining after the formation of the first spacer 141 and the second spacer 142.

[0055] A fourth spacer 144 may be formed on the second spacer 142 and the third spacer 143. The fourth spacer 144 may extend along at least a portion of the side surface of the bit line BL. For example, the fourth spacer 144 may extend along a portion of the side surface of the first spacer 141.

[0056] A fifth spacer 145 may be formed on the third spacer 143. The fifth spacer 145 may extend along at least a portion of the side surface of the bit line BL. For example, the fifth spacer 145 may extend along the side surface of the fourth spacer 144.

[0057] In some embodiments, the bottom surface of the fifth spacer 145 may be formed below the uppermost surface of the third spacer 143. For example, the lower part of the fifth spacer 145 may be embedded in the third spacer 143.

[0058] The first spacer 141, the second spacer 142, the third spacer 143, the fourth spacer 144, and the fifth spacer 145 may each include at least one of silicon oxide, silicon oxide nitride, silicon nitride, and combinations thereof. For example, the first spacer 141 may include a silicon nitride, the second spacer 142 may include a silicon oxide, the third spacer 143 may include a silicon nitride, the fourth spacer 144 may include a silicon oxide, and the fifth spacer 145 may include a silicon nitride.

[0059] In some embodiments, bit line spacers 140 may include air spacers. Air spacers may be formed of air or voids. Because air spacers can have a dielectric constant smaller than that of silicon oxide, parasitic capacitance of semiconductor memory devices can be effectively reduced according to some embodiments. For example, a fourth spacer 144 may be an air spacer.

[0060] Buried contacts BC may be formed on substrate 100 and component isolation layer 110. The buried contacts BC may penetrate substrate insulating layer 120 to connect the active region AR of substrate 100 to landing pad LP, which will be described later. For example, substrate 100 may include a second contact trench CT2. The second contact trench CT2 may penetrate substrate insulating layer 120 to expose at least a portion of the active region AR. Buried contacts BC may be formed in the second contact trench CT2 to connect the active region AR of substrate 100 to landing pad LP.

[0061] In some embodiments, the second contact trench CT2 may expose both ends of each active region AR. Therefore, the buried contact BC may connect to both ends of the active region AR. In some embodiments, a portion of the second contact trench CT2 may overlap with a portion of the component isolation layer 110. Therefore, the second contact trench CT2 may expose a portion of the component isolation layer 110 and a portion of the active region AR.

[0062] The buried contact BC can be formed on the side surface of the bit line BL. Furthermore, the buried contact BC can be spaced apart from the bit line BL by the bit line spacer 140. For example, as... Figure 3As shown, the buried contact BC can extend along the side surface of the bit line spacer 140. A plurality of buried contacts BC arranged along the first direction X can be separated from each other by the bit line BL and the bit line spacer 140 extending in the second direction Y. In some embodiments, the top surface of the buried contact BC can be formed below the top surface of the second bit line overlay pattern 139.

[0063] The buried contact BC can be formed on the side surface of the letter line WL. For example, as Figure 4 As shown, an insulating fence 170 extending in the first direction X can be formed on the letter line cover pattern 168. Buried contacts BC can extend along the side surface of the letter line cover pattern 168 or the side surface of the insulating fence 170. The plurality of buried contacts BC arranged along the second direction Y can be separated from each other by the letter line cover pattern 168 and / or the insulating fence 170 extending in the first direction X.

[0064] Burial contact BC can form multiple isolated zones that are separated from each other. For example, such as Figure 2 As shown, the plurality of buried contacts BC can be inserted between the plurality of bit lines BL and the plurality of word lines WL. In some embodiments, the buried contacts BC can be arranged in a grid structure.

[0065] The buried contact BC may include a conductive material. Therefore, the buried contact BC may be electrically connected to the active region AR of the substrate 100. The active region AR of the substrate 100 connected to the buried contact BC may be used as the source / drain region of a semiconductor device including a word line WL. The buried contact BC may include, for example, polysilicon, but is not limited thereto.

[0066] A landing pad LP may be formed on the buried contact BC. The landing pad LP may be configured to overlap with the buried contact BC. As used herein, the term "overlap" means overlap in the vertical direction Z perpendicular to the top surface of the substrate 100. The landing pad LP may be attached to the top surface of the buried contact BC to connect the active area AR of the substrate 100 to the capacitor 190, which will be described subsequently.

[0067] In some implementations, the landing pad LP can be configured to overlap with a portion of the buried contact BC and a portion of the bit line BL. For example, as... Figure 2 and Figure 3 As shown, the landing pad LP may overlap with a portion of the buried contact BC and a portion of the second bit line overlay pattern 139. In some embodiments, the top surface of the landing pad LP may be formed above the top surface of the second bit line overlay pattern 139. Therefore, the landing pad LP may cover a portion of the top surface of the second bit line overlay pattern 139.

[0068] Landing pads (LPs) can form multiple isolated regions that are separated from each other. For example, as... Figure 3 As shown, a pad trench PT can be formed to define a plurality of pads LP. In some embodiments, a portion of the pad trench PT may expose a portion of the second bit line overlay pattern 139. For example, the pad trench PT may be formed to extend from the top surface of the landing pads LP such that its bottom surface is lower than the top surface of the second bit line overlay pattern 139. Thus, the plurality of landing pads LP can be separated from each other by the second bit line overlay pattern 139 and the pad trench PT.

[0069] The landing pad LP may include a conductive material. Therefore, the capacitor 190, which will be described subsequently, can be electrically connected to the active region AR of the substrate 100 via the buried contact BC and the landing pad LP. The landing pad LP may include, for example, tungsten, but is not limited thereto.

[0070] In some embodiments, the plurality of landing pads LP may be arranged in a honeycomb structure. Furthermore, each landing pad LP may include a side surface extending in a fourth direction D2, different from the first direction X and the second direction Y, in the plan view. See then on... Figure 6 Provide a detailed description.

[0071] In some embodiments, a first interlayer insulating layer 180 may be formed to fill the pad trench PT. The first interlayer insulating layer 180 may be formed on the landing pad LP and the second bit line overlay pattern 139. Thus, the first interlayer insulating layer 180 may define the area of ​​the landing pad LP where multiple isolation regions are formed.

[0072] The first interlayer insulating layer 180 may include an insulating material to electrically isolate the plurality of landing pads LP from each other. For example, the first interlayer insulating layer 180 may include at least one of silicon oxide, silicon oxide nitride, silicon nitride, and a low dielectric constant (low k) material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0073] A capacitor 190 may be disposed on the first interlayer insulating layer 180 and the landing pad LP. The capacitor 190 may be connected to the top surface of the landing pad LP. For example, the first interlayer insulating layer 180 may be patterned to expose at least a portion of the top surface of the landing pad LP. The capacitor 190 may be connected to the portion of the top surface of the landing pad LP exposed by the first interlayer insulating layer 180. Therefore, the capacitor 190 may be electrically connected to the active region AR of the substrate 100 via the buried contact BC and the landing pad LP. Therefore, the capacitor 190 may be controlled by the bit line BL and the word line WL to store data.

[0074] In some embodiments, capacitor 190 may include a lower electrode 192, a capacitor dielectric layer 194, and an upper electrode 196. Capacitor 190 can store charge in capacitor dielectric layer 194 by using the potential difference generated between lower electrode 192 and upper electrode 196.

[0075] The lower electrode 192 and the upper electrode 196 may include, for example, doped polysilicon, metal, or metal nitride, and are not limited thereto. Furthermore, the capacitor dielectric layer 194 may include, for example, silicon oxide or a high-k material, and is not limited thereto.

[0076] The third conductive pattern 230 can be formed on the substrate 100 in the core / peripheral region (CORE / PERI). The third conductive pattern 230 can control the function of the semiconductor memory element formed in the cell region (CELL). For example, the third conductive pattern 230 can be used as the gate electrode of a transistor.

[0077] Although the third conductive pattern 230 is in Figure 2 The pattern is shown as an isolated island, but it is only an example. For example, the third conductive pattern 230 may have a shape that extends in the first direction X or the second direction Y.

[0078] As shown in the accompanying drawings, the third conductive pattern 230 may be a single layer or multiple layers. For example, the third conductive pattern 230 may include a sixth sub-conductive pattern 232, a seventh sub-conductive pattern 234 and an eighth sub-conductive pattern 236 that are sequentially stacked on the substrate 100.

[0079] The sixth sub-conductive pattern 232, the seventh sub-conductive pattern 234, and the eighth sub-conductive pattern 236 may each include, but are not limited to, at least one of, for example, polysilicon, TiN, TiSiN, tungsten, tungsten silicide, and combinations thereof. For example, the sixth sub-conductive pattern 232 may include polysilicon, the seventh sub-conductive pattern 234 may include TiSiN, and the eighth sub-conductive pattern 236 may include tungsten.

[0080] In some embodiments, the second conductive pattern 130 and the third conductive pattern 230 may be formed at the same level. As used herein, the term "same level" means formed by the same manufacturing process. For example, the third sub-conductive pattern 132 and the sixth sub-conductive pattern 232 may include the same material, the fourth sub-conductive pattern 134 and the seventh sub-conductive pattern 234 may include the same material, and the fifth sub-conductive pattern 136 and the eighth sub-conductive pattern 236 may include the same material.

[0081] The gate dielectric layer 220 may be interposed between the third conductive pattern 230 and the substrate 100. The gate dielectric layer 220 may include, but is not limited to, at least one of, silicon oxide, silicon oxide nitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. In some embodiments, the first insulating layer 122 and the gate dielectric layer 220 may be formed at the same level.

[0082] Gate cover pattern 238 may be formed on third conductive pattern 230. Gate cover pattern 238 may extend along the top surface of third conductive pattern 230. Gate cover pattern 238 may include, but is not limited to, silicon nitride. In some embodiments, first line cover pattern 138 and gate cover pattern 238 may be formed at the same level.

[0083] Gate spacer 240 may be formed on the side surface of third conductive pattern 230. Gate spacer 240 may extend along the side surface of third conductive pattern 230 and / or the side surface of gate overlay pattern 238. Gate spacer 240 may include, for example, at least one of silicon oxide, silicon oxide nitride, silicon nitride, and combinations thereof, but is not limited thereto.

[0084] In some embodiments, the first pad layer 225 may be formed to extend along the top surface of the substrate 100, the top surface of the element isolation layer 110, and the side surface of the gate spacer 240. The first pad layer 225 may be used as an etch stop layer, but is not limited thereto.

[0085] In some embodiments, the second interlayer insulating layer 250 and the third interlayer insulating layer 239 may be formed to be stacked sequentially on the substrate 100. For example, the second interlayer insulating layer 250 may cover the top surface and side surface of the first pad layer 225. The third interlayer insulating layer 239 may cover the top surface of the gate cover pattern 238 and the top surface of the second interlayer insulating layer 250.

[0086] The wiring pattern BP can be formed on the third conductive pattern 230. For example, the wiring pattern BP can extend along the top surface of the second interlayer insulating layer 250. In some embodiments, the wiring pattern BP can be a bypass wiring. The wiring pattern BP can include, for example, tungsten (W) or aluminum (Al), but is not limited thereto.

[0087] In some embodiments, the second pad layer 241 may be formed between the wiring pattern BP and the third interlayer insulating layer 239. The second pad layer 241 may extend along the top surface of the third interlayer insulating layer 239. The second pad layer 241 may serve as an etch stop layer, but is not limited thereto. In some embodiments, the first spacer 141 and the second pad layer 241 may be formed at the same level.

[0088] A fourth interlayer insulating layer 280 may be formed on the wiring pattern BP. The fourth interlayer insulating layer 280 may be formed to cover the top surface of the wiring pattern BP. In some embodiments, the fourth interlayer insulating layer 280 and the first interlayer insulating layer 180 may be formed at the same level.

[0089] In the following text, see reference Figure 6 A detailed description of the landing pads of a semiconductor memory device according to some embodiments.

[0090] Figure 6 It is shown Figures 2 to 5 A partial layout diagram of the landing pads. For simplicity, refer to... Figures 1 to 5 Repeated parts of the description may be summarized or omitted below. Furthermore, for the sake of simplicity, Figure 6 Draw the buried contact BC and landing pad LP, omitting other components.

[0091] Reference Figure 6 Multiple landing pads LP can be formed to connect to the corresponding buried contact BC.

[0092] For example, the plurality of burial contacts BC may include a first burial contact BC1 and a second burial contact BC2 that are adjacent to each other. The first burial contact BC1 and the second burial contact BC2 may be arranged, for example, along a second direction Y.

[0093] The plurality of landing pads LP may include a first landing pad LP1 connected to a first buried contact BC1 and a second landing pad LP2 connected to a second buried contact BC2. In some embodiments, the first landing pad LP1 and the second landing pad LP2 may be arranged along a fourth direction D2, which is different from the first direction X and the second direction Y.

[0094] In some implementations, the fourth direction D2 can form a second acute angle θ2 with the first direction X. Although in Figure 2 and Figure 6 The diagram shows that the second acute angle θ2 is less than the first acute angle θ1, but this is only an example. For example, the second acute angle θ2 can be equal to or greater than the first acute angle θ1. The second acute angle θ2 can be equal to or greater than 60 degrees.

[0095] The first landing pad LP1 and the second landing pad LP2 may each have a side surface extending in a fourth direction D2, different from the first direction X and the second direction Y, in the plan view. For example, the first landing pad LP1 may include first to fourth side surfaces LS11, LS12, LS13 and LS14, and the second landing pad LP2 may include fifth to eighth side surfaces LS21, LS22, LS23 and LS24. The first to fourth side surfaces LS11, LS12, LS13 and LS14 may form a closed loop in the plan view, and the fifth to eighth side surfaces LS21, LS22, LS23 and LS24 may also form a closed loop in the plan view.

[0096] The first side surface LS11 may extend in the first direction X. In some embodiments, the first side surface LS11 may include a flat surface. For example, the first side surface LS11 may form a straight line in a plan view.

[0097] The second side surface LS12 may extend from the first side surface LS11 in the fourth direction D2. In some embodiments, the second side surface LS12 may form a second acute angle θ2 with the first side surface LS11.

[0098] The third side surface LS13 may be opposite to the second side surface LS12 and extend from the first side surface LS11. In some embodiments, the third side surface LS13 may be parallel to the second side surface LS12. For example, the third side surface LS13 may extend from the first side surface LS11 in a fourth direction D2. The third side surface LS13 may form a first obtuse angle θ3 with the first side surface LS11. The first obtuse angle θ3 may be equal to or less than 120 degrees. When the second side surface LS12 and the third side surface LS13 are parallel to each other, the sum of the second acute angle θ2 and the first obtuse angle θ3 may be 180 degrees.

[0099] The fourth side surface LS14 may be opposite the first side surface LS11 and connect the second side surface LS12 to the third side surface LS13. In some embodiments, the fourth side surface LS14 may include a curved surface. For example, the fourth side surface LS14 may form a convex curve in a plan view. This may be due to the nature of the etching process used to form the first landing pad LP1.

[0100] The fifth side surface LS21 may face the first side surface LS11. In some embodiments, the fifth side surface LS21 may include a flat surface. For example, the fifth side surface LS21 may form a straight line in a planar view. In some embodiments, the fifth side surface LS21 may be parallel to the first side surface LS11. For example, the fifth side surface LS21 may extend in a first direction X.

[0101] The sixth side surface LS22 may extend from the fifth side surface LS21 in the fourth direction D2. In some embodiments, the sixth side surface LS22 may form a second acute angle θ2 with the fifth side surface LS21. Therefore, when the first side surface LS11 and the fifth side surface LS21 are parallel to each other, the second side surface LS12 and the sixth side surface LS22 may be parallel to each other. In some embodiments, the sixth side surface LS22 may be coplanar with the third side surface LS13. That is, a plane may exist that includes both the third side surface LS13 and the sixth side surface LS22.

[0102] The seventh side surface LS23 may be opposite to the sixth side surface LS22 and extend from the fifth side surface LS21. In some embodiments, the seventh side surface LS23 may be parallel to the sixth side surface LS22. For example, the seventh side surface LS23 may extend from the fifth side surface LS21 in the fourth direction D2. The seventh side surface LS23 may form a second obtuse angle θ4 with the fifth side surface LS21. The second obtuse angle θ4 may be equal to or less than 120 degrees. When the sixth side surface LS22 and the seventh side surface LS23 are parallel to each other, the sum of the second acute angle θ2 and the second obtuse angle θ4 may be 180 degrees. In some embodiments, the seventh side surface LS23 may be coplanar with the second side surface LS12. That is, a plane may exist that includes both the second side surface LS12 and the seventh side surface LS23.

[0103] In some implementations, the first obtuse angle θ3 may be equal to the second obtuse angle θ4. As used herein, the term "identical" means not only completely identical, but also includes minor differences that may occur due to process allowances, etc.

[0104] The eighth side surface LS24 may be opposite the fifth side surface LS21 and connect the sixth side surface LS22 to the seventh side surface LS23. In some embodiments, the eighth side surface LS24 may include a curved surface. For example, the eighth side surface LS24 may form a convex curve in a planar view. This may be due to the nature of the etching process used to form the second landing pad LP2.

[0105] Although the plan view shows the second side surface LS12 as having the same length as the sixth side surface LS22 and the third side surface LS13 as having the same length as the seventh side surface LS23, this is merely an example. For instance, needless to say, the length of the second side surface LS12 may be shorter than the length of the sixth side surface LS22, and the length of the third side surface LS13 may be shorter than the length of the seventh side surface LS23.

[0106] Although only the first buried contact BC1 and the second buried contact BC2 are shown arranged along the second direction Y, the inventive concept is not limited thereto. For example, the first buried contact BC1 and the second buried contact BC2 may be arranged along the first direction X. In this case, the first side surface LS11 of the first landing pad LP1 and the fifth side surface LS21 of the second landing pad LP2 may extend in the second direction Y.

[0107] In the following text, reference will be made to Figures 7 to 11 This describes various semiconductor memory devices according to some implementation methods.

[0108] Figures 7 to 11 These are partial layout diagrams used to illustrate various embodiments of semiconductor memory devices. For simplicity of description, refer to... Figures 1 to 6 Repeated parts of the description may be summarized or omitted below.

[0109] Reference Figure 7 In a semiconductor memory device according to some embodiments, the fourth side surface LS14 of the first landing pad LP1 and the eighth side surface LS24 of the second landing pad LP2 may include flat surfaces.

[0110] For example, the fourth side surface LS14 and the eighth side surface LS24 can form a straight line in the planar view. This could be due to the nature of the etching process used to form the first landing pad LP1 and the second landing pad LP2.

[0111] Despite Figure 7 The diagram shows the fourth side surface LS14 orthogonal to the second side surface LS12 and the third side surface LS13, and the eighth side surface LS24 orthogonal to the sixth side surface LS22 and the seventh side surface LS23; however, this is merely an example. For instance, the fourth side surface LS14 could form an acute angle with the second side surface LS12 and an obtuse angle with the third side surface LS13. Similarly, the eighth side surface LS24 could form an acute angle with the sixth side surface LS22 and an obtuse angle with the seventh side surface LS23.

[0112] Reference Figure 8 In a semiconductor memory device according to some embodiments, the first to third side surfaces LS11, LS12 and LS13 of the first landing pad LP1 are connected to each other by a curved surface, and the fifth to seventh side surfaces LS21, LS22 and LS23 of the second landing pad LP2 are connected to each other by a curved surface.

[0113] For example, Figure 8 The first landing pad LP1 and the second landing pad LP2 can have the ability to be connected from... Figure 6The shape obtained by removing the tips from the first landing pad LP1 and the second landing pad LP2. In this case, short circuits caused by the landing pad LP being connected to another pattern adjacent to it (e.g., another landing pad LP or a buried contact BC connected to another landing pad LP) can be prevented. The landing pad LP from which the tip is removed can be formed, for example, by a trimming process, but is not limited thereto.

[0114] Reference Figure 9 In a semiconductor memory device according to some embodiments, the plurality of landing pads LP may further include a third landing pad LP3.

[0115] For example, the plurality of burial contacts BC may further include a third burial contact BC3 adjacent to the first burial contact BC1. The first burial contact BC1 and the third burial contact BC3 may be arranged along the second direction Y. In some embodiments, the second burial contact BC2 and the third burial contact BC3 may be arranged along a diagonal direction.

[0116] The third landing pad LP3 can be connected to the third buried contact BC3. In some embodiments, the second landing pad LP2, the third landing pad LP3, and the first landing pad LP1 can be arranged sequentially along the fourth direction D2.

[0117] The third landing pad LP3 may include a side surface extending in the fourth direction D2 in the plan view. For example, the third landing pad LP3 may include the ninth to twelfth side surfaces LS31, LS32, LS33 and LS34. The ninth to twelfth side surfaces LS31, LS32, LS33 and LS34 may form a closed loop in the plan view.

[0118] The ninth side surface LS31 may face the first side surface LS11. In some embodiments, the ninth side surface LS31 may include a flat surface. For example, the ninth side surface LS31 may form a straight line in a planar view. In some embodiments, the ninth side surface LS31 may be parallel to the first side surface LS11. For example, the ninth side surface LS31 may extend in a first direction X.

[0119] The tenth side surface LS32 may extend from the ninth side surface LS31 in the fourth direction D2. In some embodiments, the tenth side surface LS32 may form a second acute angle θ2 with the ninth side surface LS31. In some embodiments, the ninth side surface LS31 may be coplanar with the third side surface LS13 and the sixth side surface LS22. That is, a single plane may exist that includes the entirety of the third side surface LS13, the sixth side surface LS22, and the ninth side surface LS31.

[0120] The eleventh side surface LS33 may be opposite to the tenth side surface LS32 and extend from the ninth side surface LS31. In some embodiments, the eleventh side surface LS33 may be parallel to the tenth side surface LS32. For example, the eleventh side surface LS33 may extend from the ninth side surface LS31 in the fourth direction D2. In some embodiments, the eleventh side surface LS33 may be coplanar with the second side surface LS12 and the seventh side surface LS23. That is, a single plane may exist that includes the entirety of the second side surface LS12, the seventh side surface LS23, and the eleventh side surface LS33.

[0121] The twelfth side surface LS34 may face the fifth side surface LS21. In some embodiments, the twelfth side surface LS34 may include a flat surface. For example, the twelfth side surface LS34 may form a straight line in a planar view. In some embodiments, the twelfth side surface LS34 may be parallel to the fifth side surface LS21. For example, the twelfth side surface LS34 may extend in a first direction X.

[0122] Reference Figure 10 In a semiconductor memory device according to some embodiments, each landing pad LP has a diamond shape.

[0123] In some implementations, with Figure 6 In contrast, the fourth side surface LS14 may be parallel to the first side surface LS11, and the eighth side surface LS24 may be parallel to the fifth side surface LS21. For example, the fourth side surface LS14 and the eighth side surface LS24 may extend in the first direction X.

[0124] Reference Figure 11 In a semiconductor memory device according to some embodiments, the second acute angle θ2 may be equal to or greater than the first acute angle θ1.

[0125] That is, the fourth direction D2 can form a second acute angle θ2 with the first direction X, which is equal to or greater than the first acute angle θ1. Although for the sake of simplicity, the second acute angle θ2 is shown to be equal to the first acute angle θ1, the second acute angle θ2 can be greater than the first acute angle θ1.

[0126] For example, Figure 11 The first landing pad LP1 and the second landing pad LP2 can have the same characteristics as... Figure 6 The first landing pad LP1 and the second landing pad LP2 have an increased shape compared to the second acute angle θ2. In this case, each landing pad LP can be connected to the corresponding buried contact BC through an enlarged area (e.g., the overlap area between the first landing pad LP1 and the first buried contact BC1). This can improve the connection reliability and resistance between the landing pads LP and the buried contact BC.

[0127] In the following text, see reference Figures 2 to 5 and Figures 12 to 25 Methods for manufacturing semiconductor memory devices according to some embodiments are described.

[0128] Figures 12 to 25 This is a view illustrating intermediate operations used to explain a method for manufacturing a semiconductor memory device according to some embodiments. For simplicity of description, refer to... Figures 1 to 11 Repeated parts of the description may be summarized or omitted below. For reference, Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 They are along Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 and Figure 24 The sectional view taken by lines AA and BB.

[0129] Reference Figure 12 and Figure 13 A substrate insulating layer 120, a first conductive layer 332, a direct contact DC, a second conductive layer 334, a third conductive layer 336, and a first cover layer 338 are formed on the substrate 100 and the component isolation layer 110.

[0130] For example, the first insulating layer 122 and the first conductive layer 332 may be formed sequentially on the substrate 100 and the component isolation layer 110. In some embodiments, the second insulating layer 124 and the third insulating layer 126 may be further formed on the first insulating layer 122 of the cell region.

[0131] Then, a first contact trench CT1 exposing a portion of the active region AR can be formed in the substrate 100 within the cell region CELL. In some embodiments, the first contact trench CT1 may expose the center of the active region AR. A direct contact DC can then be formed to fill the first contact trench CT1.

[0132] Then, the second conductive layer 334, the third conductive layer 336, and the first cover layer 338 can be sequentially formed on the first conductive layer 332 and the direct contact DC.

[0133] Reference Figure 14 and Figure 15 The first conductive layer 332, the direct contact DC, the second conductive layer 334, the third conductive layer 336, and the first cover layer 338 are patterned.

[0134] Therefore, the second conductive pattern 130 (or bit line BL) extending in the second direction Y and the first bit line covering pattern 138 can be formed on the substrate 100 in the cell region CELL.

[0135] Furthermore, the gate dielectric layer 220, the third conductive pattern 230, and the gate overlay pattern 238 may be formed on the substrate 100 in the core / periphery region (CORE / PERI). In some embodiments, the gate spacer 240, the first pad layer 225, and the second interlayer insulating layer 250 may be further formed on the side surface of the third conductive pattern 230.

[0136] In some embodiments, a second bit line overlay pattern 139 and a third interlayer insulating layer 239 may be further formed. The second bit line overlay pattern 139 may extend along the top surface of the first bit line overlay pattern 138. The third interlayer insulating layer 239 may extend along the top surface of the gate overlay pattern 238 and the top surface of the second interlayer insulating layer 250.

[0137] Reference Figure 16 and Figure 17 Bit line spacers 140 are formed on the side surface of bit line BL.

[0138] For example, bit line spacers 140 may be formed to extend along the side surface that directly contacts the DC, the side surface of the second conductive pattern 130, the side surface of the first bit line cover pattern 138, the side surface of the second bit line cover pattern 139, and the top surface.

[0139] In some embodiments, bit line spacers 140 may include a first spacer 141, a second spacer 142, a third spacer 143, a fourth spacer 144, and a fifth spacer 145.

[0140] In some embodiments, the second liner layer 241 may be further formed on the third interlayer insulation layer 239 in the core / peripheral region (CORE / PERI). In some embodiments, the first spacer 141 and the second liner layer 241 may be formed at the same level.

[0141] In some embodiments, the fifth spacer 145 may extend along the top surface of the second liner layer 241.

[0142] Reference Figure 18 and Figure 19 Buried contacts BC are formed on the substrate 100 and the component isolation layer 110.

[0143] For example, a second contact trench CT2 that exposes a portion of the active region AR can be formed in the substrate 100 within the cell region CELL. In some embodiments, the second contact trench CT2 may expose both ends of the active region AR. Next, a buried contact BC can be formed to fill the second contact trench CT2.

[0144] In some embodiments, the top surface of the buried contact BC can be formed below the top surface of the second bit line overlay pattern 139. For example, the top surface of the buried contact BC can be formed below the top surface of the second bit line overlay pattern 139 by an etch-back process. Therefore, a buried contact BC can be formed that forms multiple isolation regions. The buried contact BC can include, but is not limited to, polysilicon.

[0145] Reference Figure 20 and Figure 21 The fourth conductive layer 400 is formed on the cell region CELL and the core / periphery region CORE / PERI.

[0146] For example, a fourth conductive layer 400 may be formed on the buried contact BC of the cell region and the second liner layer 241 of the core / periphery region. The fourth conductive layer 400 may be electrically connected to the buried contact BC. The fourth conductive layer 400 may include, for example, tungsten (W), but is not limited thereto.

[0147] In some embodiments, the top surface of the fourth conductive layer 400 may be formed above the top surface of the second bit line overlay pattern 139.

[0148] Reference Figure 22 and Figure 23 Multiple initial landing pads pLP are formed by performing a first patterning process on the fourth conductive layer 400 for patterning cell regions CELL.

[0149] For example, an initial pad trench pPT can be formed to define the plurality of initial landing pads pLP. In some embodiments, a portion of the initial pad trench pPT may expose a portion of the second bit line overlay pattern 139. For example, the initial pad trench pPT may be formed to extend from the top surface of the initial landing pad pLP such that its bottom surface is lower than the top surface of the second bit line overlay pattern 139. Thus, the plurality of initial landing pads pLP can be separated from each other by the second bit line overlay pattern 139 and the initial pad trench pPT.

[0150] In some implementations, the initial landing pad pLP may overlap with at least two of the plurality of buried contacts BC. Figure 22As an example, an initial landing pad pLP is shown, each initial landing pad pLP overlapping two buried contacts BC. In some embodiments, the two buried contacts BC overlapping an initial landing pad pLP may be arranged to be adjacent to each other along a second direction Y.

[0151] In some embodiments, the initial landing pads pLP may each extend in a fourth direction D2, different from the first direction X and the second direction Y. In some embodiments, the fourth direction D2 may form a second acute angle θ2 with the first direction X. Although in Figure 22 The diagram shows that the second acute angle θ2 is less than the first acute angle θ1, but this is only an example. For example, the second acute angle θ2 can be equal to or greater than the first acute angle θ1. The second acute angle θ2 can be equal to or greater than 60 degrees.

[0152] Reference Figure 24 and Figure 25 The plurality of landing pads LP are formed by performing a second patterning process for patterning the initial landing pad pLP.

[0153] For example, pad trenches PT can be formed to define the plurality of landing pads LP. In some embodiments, the pad trenches PT can be formed by cutting the initial landing pads pLP using an etch mask that extends in the first direction X. In some embodiments, the etch mask can be arranged to overlap with the word line WL. Thus, each initial landing pad pLP can be divided into two landing pads LP arranged along the fourth direction D2 (e.g., Figure 6 The first landing pad LP1 and the second landing pad LP2 in the process.

[0154] In some implementations, the plurality of landing pads LP of the cell region CELL can be formed simultaneously with the formation of the wiring pattern BP of the core / peripheral region CORE / PERI. For example, the second patterning process may include forming the wiring pattern BP by patterning the fourth conductive layer 400 of the core / peripheral region CORE / PERI.

[0155] Then, refer to Figure 2 and Figure 3 The first interlayer insulation layer 180 is formed on the landing pad LP.

[0156] For example, a first interlayer insulating layer 180 can be formed for filling the pad trench PT. Thus, the plurality of landing pads LP can be formed, which form the plurality of isolated regions separated from each other by the first interlayer insulating layer 180. In some embodiments, the first interlayer insulating layer 180 can be patterned to expose at least a portion of the top surface of each landing pad LP.

[0157] Then, a lower electrode 192 can be formed connected to the landing pad LP exposed by the first interlayer insulating layer 180. A capacitor dielectric layer 194 and an upper electrode 196 can then be formed sequentially on the lower electrode 192. Thus, a capacitor 190 connected to the landing pad LP can be formed.

[0158] Return to reference Figure 22 In a method for manufacturing a semiconductor memory device according to some embodiments, unlike those shown in the figures, the initial landing pad pLP can each overlap with three buried contacts BC. Then, reference [reference] can be performed. Figure 24 and Figure 25 The steps described above. Therefore, it is possible to manufacture a product that includes the above-mentioned references. Figure 9 The semiconductor memory device described is the landing pad LP.

[0159] In a method for manufacturing a semiconductor memory device according to some embodiments, unlike that shown in the accompanying drawings, each of the initial landing pads pLP can extend in the fourth direction D2. Subsequently, the above-described references can be performed. Figure 24 and Figure 25 The steps described above. Therefore, it is possible to manufacture a product that includes the above-mentioned references. Figure 10 The semiconductor memory device described is the landing pad LP.

[0160] As semiconductor memory devices become more highly integrated, individual circuit patterns have become smaller to accommodate more semiconductor memory devices within the same area. For example, it may be necessary to arrange landing pads into a fine honeycomb structure. To achieve this, there is a tendency to increase the aspect ratio of the patterning process; however, an increased aspect ratio increases the processing difficulty and leads to defects such as pattern collapse.

[0161] However, methods for manufacturing semiconductor memory devices according to some embodiments can achieve fine circuit patterns with relatively low process difficulty by performing patterning processes twice. For example, in a method for manufacturing semiconductor memory devices according to some embodiments, firstly, a plurality of initial landing pads pLP can be formed (first patterning process), and then the initial landing pads pLP can be cut to form the plurality of landing pads LP (second patterning process). Since the initial landing pads pLP are larger in size than the finally formed landing pads LP, the initial landing pads pLP can be formed with relatively low process difficulty.

[0162] Furthermore, each initial landing pad pLP can be formed to extend in a fourth direction D2, different from the first direction X and the second direction Y. Therefore, multiple landing pads LP arranged in a fine honeycomb structure can be formed, allowing semiconductor memory devices to be implemented with fine circuit patterns.

[0163] Although some exemplary embodiments have been described, the embodiments presented in this disclosure are used in a general and descriptive sense only and not for limiting purposes. Those skilled in the art will understand that many variations and modifications can be made to the embodiments of the inventive concept without substantially departing from the principles of the inventive concept as defined in this disclosure by the appended claims.

[0164] This application claims priority to Korean Patent Application No. 10-2020-0081645, filed on July 2, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: substrate; Multiple first conductive patterns extend parallel to each other in a first direction on the substrate; Multiple second conductive patterns extend parallel to each other in a second direction that intersects the first direction on the substrate; Multiple buried contacts are connected to the substrate between the multiple first conductive patterns and between the multiple second conductive patterns; as well as Landing pads are applied to and connected to each of the plurality of buried contacts. The landing pad includes a first side surface extending in the first direction in a plan view, a second side surface extending upward in a third direction different from the first and second directions in a plan view, and a third side surface parallel to the second side surface.

2. The semiconductor memory device of claim 1, wherein each of the plurality of second conductive patterns is connected to the substrate.

3. The semiconductor memory device according to claim 2, further comprising: A substrate insulating layer extends along the top surface of the substrate; and Direct contact, penetrating the substrate insulating layer and connecting to each of the plurality of second conductive patterns and the substrate. Each of the first conductive patterns is in the substrate and between the direct contact and each of the buried contacts.

4. The semiconductor memory device of claim 3, wherein the top surface of each of the plurality of first conductive patterns is lower than the top surface of the substrate.

5. The semiconductor memory device of claim 1, wherein the landing pad further comprises a fourth side surface, the fourth side surface being raised and connecting the second side surface to the third side surface.

6. The semiconductor memory device of claim 1, wherein the landing pad further comprises a fourth side surface parallel to the first side surface and connecting the second side surface to the third side surface.

7. The semiconductor memory device of claim 1, wherein the first side surface and the second side surface form an acute angle equal to or greater than 60 degrees.

8. A semiconductor memory device, comprising: substrate; A first conductive pattern extends on the substrate in a first direction; A first buried contact is located on the substrate and on one side of the first conductive pattern, and the first buried contact is connected to the substrate. A second buried contact is located on the substrate and on the other side of the first conductive pattern, the second buried contact being connected to the substrate; A first landing pad connected to the first buried contact, the first landing pad including a first side surface forming an acute angle with the first direction in a plan view; A second landing pad connected to the second buried contact, the second landing pad including a second side surface coplanar with the first side surface; as well as Capacitors are connected to the first landing pad and the second landing pad, respectively.

9. The semiconductor memory device according to claim 8, wherein The first landing pad also includes a third side surface extending from the first side surface in the first direction. The second landing pad also includes a fourth side surface extending from the second side surface in the first direction, and The third side surface and the fourth side surface are opposite to each other.

10. The semiconductor memory device of claim 9, wherein... The first landing pad also includes a fifth side surface, which forms an obtuse angle with the third side surface in a plan view. The second landing pad also includes a sixth side surface that is coplanar with the fifth side surface.

11. The semiconductor memory device of claim 10, wherein... The first side surface and the fifth side surface are parallel to each other, and The second side surface and the sixth side surface are parallel to each other.

12. The semiconductor memory device of claim 8, wherein the first side surface forms an acute angle equal to or greater than 60 degrees with the first direction.

13. The semiconductor memory device of claim 8, wherein the first buried contact and the second buried contact are arranged along a second direction perpendicular to the first direction.

14. The semiconductor memory device of claim 13, further comprising: The second conductive pattern on the substrate, wherein The second conductive pattern extends in the second direction and is connected to the substrate, and The first buried contact and the second buried contact are disposed on one side of the second conductive pattern.

15. A semiconductor memory device, comprising: substrate; A component isolation layer is provided on the substrate and defines a plurality of active regions in the substrate; The word line extends in a first direction intersecting each of the plurality of active regions in the substrate; The bit lines on the substrate are connected to each of the plurality of active regions and extend in a second direction intersecting the first direction; Multiple buried contacts on the side surface of the bit line, the multiple buried contacts being respectively connected to the multiple active regions; The plurality of landing pads on the plurality of buried contacts are respectively connected to the buried contacts. The plurality of landing pads are arranged in a honeycomb structure. Each of the plurality of landing pads includes a first side surface extending in the first direction in a plan view, a second side surface extending upward in a third direction different from the first direction and the second direction in a plan view, and a third side surface parallel to the second side surface. as well as Multiple capacitors are connected to the multiple landing pads, respectively.

16. The semiconductor memory device of claim 15, wherein the plurality of buried contacts are arranged in a lattice structure.

17. The semiconductor memory device of claim 15, wherein each of the plurality of active regions extends in a plan view in a fourth direction different from the first direction and the second direction.

18. The semiconductor memory device of claim 15, further comprising: A substrate insulating layer extends along the top surface of the substrate and the top surface of the element isolation layer; and Direct contact, penetrating the substrate insulating layer to connect the bit line to each of the plurality of active regions.

19. The semiconductor memory device of claim 18, wherein the word line is between each of the direct contact and each of the plurality of buried contacts.

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