Integrated circuit, power gating unit thereof, and manufacturing method thereof

Abstract

Embodiments of the present invention provide an integrated circuit, a power gating cell on the integrated circuit, and a method of manufacturing the same. The power gating cell includes a center region, a perimeter region surrounding the center region, a first active region in the center region having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, and a plurality of second active regions in the perimeter region, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to integrated circuits, power gating cells thereof, and methods of manufacturing the same. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. ICs have been in use for a number of years and recent advances in IC technology have resulted in very small feature sizes (e.g., submicron and even smaller sizes). However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to reach their full potential, it has become increasingly critical to find improved ways to create and test ICs. For example, a very small feature size allows more components to be incorporated into a chip. This, in turn, raises the need to test more components and to test components at a higher resolution to reliably determine whether each component is working properly. SUMMARY

[0003] According to one aspect of embodiments of the present invention, a power gating cell on an integrated circuit includes a center region, a perimeter region surrounding the center region, a first active region within the center region, the first active region having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, and a plurality of second active regions within the perimeter region, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

[0004] According to another aspect of embodiments of the present invention, an integrated circuit includes a standard logic cell configured to perform a function, a power gating cell coupled to the standard logic cell, the power gating cell configured to disconnect power to the standard logic cell in response to a control signal, the power gating cell having a center region and a perimeter region surrounding the center region, and wherein the power gating cell further includes a first active region within the center region, the first active region having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, and a plurality of second active regions within the perimeter region, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

[0005] According to yet another aspect of the embodiments of the present application, a method of fabricating a power gating cell on an integrated circuit is provided, comprising: providing a substrate, wherein the substrate has a first active area and a plurality of second active areas thereon, the first active area is located within a center region of the power gating cell and has a first width in a first direction, and the plurality of second active areas are located within a peripheral region of the power gating cell surrounding the center region, each second active area has a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in a second direction perpendicular to the first direction; forming fin structures over the first active area and the plurality of second active areas; doping a source region and a drain region of the fin structures, a width corresponding to at least four fin structures extending in the second direction perpendicular to the first direction; and forming a gate structure over the fin structures within the first active area and the plurality of second active areas. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to scale. On the contrary, the dimensions of the various features can be arbitrarily expanded or reduced for clarity. Included in the drawings are the following figures:

[0007] Figure 1 is a block diagram illustrating an integrated circuit (IC) layout incorporating a head cell and / or a foot cell (collectively referred to as "power gating cells") in accordance with some embodiments.

[0008] Figure 2A is a diagram illustrating a power gating cell in accordance with some embodiments.

[0009] Figure 2B is a diagram illustrating a first reference power gating cell to be compared with the power gating cell of Figure 2A .

[0010] Figure 2C is a diagram illustrating a second reference power gating cell to be compared with the power gating cell of Figure 2A .

[0011] Figure 3 is a diagram illustrating a power gating cell 102 in accordance with some embodiments.

[0012] Figure 4 is a diagram illustrating a power gating cell 102 in accordance with some embodiments.

[0013] Figure 5 is a diagram illustrating a power gating cell 102 in accordance with some embodiments.

[0014] Figure 6 is a diagram illustrating a power gating cell 102 in accordance with some embodiments.

[0015] Figure 7 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0016] Figure 8 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0017] Figure 9 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0018] Figure 10 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0019] Figure 11 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0020] Figure 12 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0021] Figure 13 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0022] Figure 14 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0023] Figure 15 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0024] Figure 16 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0025] Figure 17 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0026] Figure 18 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0027] Figure 19 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0028] Figure 20 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0029] Figure 21 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0030] Figure 22 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments. Figure 21 Figure 1 is a diagram illustrating a power gating unit 102 according to some embodiments.

[0031] Figure 23 FIG. 1 is a flowchart showing a method of fabricating a power gating cell according to some embodiments.

[0032] Figure 24 FIG. 2 is a block diagram of an IC fabrication system according to some embodiments. DETAILED DESCRIPTION

[0033] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application in any way. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features do not form direct contact. In addition, the present application can be repeated with variations and / or modifications in various examples. This repetition and these variations and / or modifications are not to be considered as limitations of the application but as examples of features of the application.

[0034] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component or portion as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0035] In today's standard cell-based application specific integrated circuit (ASIC) design, the logic function of a chip is modeled and simulated in a higher level hardware description language (e.g. VHDL or VERILOG). It is then synthesized in a silicon compiler (e.g. SYNOPSIS) to generate a netlist using standard logic cells from a target standard cell library. The netlist is used in the back-end physical design phase to perform "placement and routing" of the standard logic cells to generate the complete circuit layout of the ASIC for fabrication.

[0036] On-chip head switches and foot switches (collectively referred to as "power gating cells") are used to cut off power to certain standard logic cells in a standby mode or sleep mode to save power consumption of the chip. The head switches and foot switches are typically low-leakage metal-oxide-silicon (MOS) transistors. In some embodiments, the head switches and foot switches are fin field effect transistors (FinFETs). The head switches and foot switches are typically placed in head cells and foot cells next to the standard logic cells, respectively. But under the established architecture, the layout of the head cells and foot cells requires large chip area, high cost, and relatively high power consumption.

[0037] According to some embodiments of the present application, a power gating cell includes a wide active area in a central region of the power gating cell and a plurality of normal active areas in a peripheral region surrounding the central region. The normal active areas are active areas with one, two, or three fin structures, while the wide active area is an active area with more than three fin structures. Since the wide active area has better chip area utilization, the power gating cell can result in smaller chip area than the conventional cell layout in the same active area. From another perspective, the power gating cell can have a larger active area than the conventional cell with the same size. As a result, the larger active area of the wide active area results in smaller IR drop of the power gating cell. In summary, the power gating cell with the wide active area in the central region can achieve smaller chip area and better power conversion efficiency.

[0038] Figure 1 is a block diagram showing an integrated circuit (IC) layout incorporating head cells and / or foot cells (collectively referred to as "power gating cells") according to some embodiments. The head cells, foot cells, and standard logic cells are placed on the IC layout. The head cells and foot cells have various layout structures as described in Figures 2A to 20 ( Figure 2B and Figure 2C except) described in reference to Figure 1In the illustrated example, IC layout 100 includes: a plurality of standard logic cells 104, a plurality of head cells 120h on the left side of the plurality of standard logic cells 104, and a plurality of foot cells 120f on the right side of the plurality of standard logic cells 104. The plurality of head cells 120h and the plurality of foot cells 120f are collectively referred to as power gating cells 120. Each of the plurality of standard logic cells 104 (e.g., 104-1) can implement its specific function. Each of the plurality of standard logic cells 104 (e.g., 104-1) is connected to at least one head cell 102h (e.g., 102h-1) and at least one foot cell 102f (e.g., 102f-1), which is controlled to cut off power to the controlled standard logic cell (e.g., 104-1) in standby mode or sleep mode. In one example, each head cell 102h includes at least one low-leakage PMOS transistor, and each foot cell 102f includes at least one low-leakage NMOS transistor.

[0039] Figure 2A This is a diagram illustrating a power gating unit 102 according to some embodiments. Figure 2B It shows that you want to... Figure 2A The diagram shows a first reference power gating unit 292 compared to the power gating unit 102. Figure 2C It shows that you want to... Figure 2A The diagram shows a second reference power supply gating unit 292 compared to the power supply gating unit 102. Figure 2A As shown, the power gating unit 102 can be a head unit 102h or a foot unit 102f, such as Figure 1 As shown.

[0040] A power gate unit 102 located on substrate 190 has a boundary 218. Multiple active regions 202 are located within the boundary 218. A fin structure 204 is disposed on the active region 202. The fin structure 204 extends in the X direction. The fin structure 204 can serve as the gate, source, or drain of a transistor as needed. A gate strip (i.e., a polysilicon strip) 208 is disposed on the fin structure 204 or the active region 202. The gate strip 208 extends in the Y direction perpendicular to the X direction. The fin structure 204 below the gate strip 208 can serve as the gate of a transistor as needed.

[0041] Generally, there are two types of active regions 202: wide active regions 202w and ordinary active regions 202n. Ordinary active regions 202n are active regions 202 with one, two, or three fin structures 204. On the other hand, wide active regions 202w are active regions 202 with three or more fin structures 204. Figure 2AIn the illustrated example, a wide active region 202w is located in the middle of the power gating cell 102. More specifically, the wide active region 202w is located in the central region 212 of the power gating cell 102 within the boundary 214. The illustrated wide active region 202w has eight fin structures 204. The illustrated wide active region 202w has a length of X2in the X direction. On the other hand, ten normal active regions 202n are located in the peripheral region 216 of the power gating cell 102. The peripheral region 216 is the region outside the boundary 214 but within the boundary 218. Each of the ten normal active regions 202n has two fin structures 204.

[0042] Due to manufacturing process limitations (e.g., fin pitch), there is an upper limit on the number of fin structures 204 within a unit size of a chip. As a result, there is a fin grid 206 of the IC layout that reflects the case where the maximum number of fin structures 204 are placed. In other words, the fin grid 206 is the reference, and it is not necessary to place real fin structures 204 at the location of each fin grid 206. Assuming that the width of a fin structure 204 in the Y direction is w, and the distance between two adjacent fin structures 206 is d, the fin pitch p is equal to (w+d). Figure 2A The illustrated distances s1, s2, and s3 have the following relationship:

[0043] s1≠s2≠s3≠(w+d)*n,

[0044] where n is an integer.

[0045] In general, due to manufacturing process limitations, the normal active regions 202n located in the peripheral region 216 of the power gating cell 102 are off-grid, which means that the fin structures 204 are not aligned with the fin grid 206. In the illustrated example, the ten normal active regions 202n are all off-grid. Figure 2A In the illustrated example, the ten normal active regions 202n are all off-grid.

[0046] On the other hand, the wide active region 202w is on-grid, which means that the fin structures 204 of the wide active region 202w are aligned with the fin grid 206. For example, the fin structure 204-1 of the wide active region 202w is aligned with the fin grid 206-1. The other fin structures 204 of the wide active region 202w are also respectively aligned with one fin grid 206.

[0047] The power gating cell 102 can achieve smaller chip area and better power conversion efficiency, which is shown by comparison with Figure 2B the first reference power gating cell 292 and Figure 2C the second reference power gating cell 294.

[0048] The first reference power-gated cell 292 has the same active area as the power-gated cell 102, but has a larger chip area than the power-gated cell 102. Unlike the power-gated cell 102, the active regions 202 within the central region 212' of the first reference power-gated cell 292 within the boundary 214' are all normal active regions 202n. More specifically, both normal active regions 202n have two fin structures 204. Since there is a gap between the normal active regions 202n, the length X1 of the normal active regions 202n is longer than the length X2 of the wide active region 202w in the power-gated cell 102 to have the same active area. As a result, the total cell area of the first reference power-gated cell 292 is larger than the total cell area of the power-gated cell 102. Thus, under the same active area, the power-gated cell 102 can produce a smaller chip area than the conventional cell layout. Figure 2A

[0049] From another perspective, the second reference power-gated cell 294 has the same total cell area as the power-gated cell 102, but has a smaller active area than the power-gated cell 102. Unlike the power-gated cell 102, the active regions 202 within the central region 212" of the second reference power-gated cell 294 within the boundary 214" are all normal active regions 202n. More specifically, both normal active regions 202n have two fin structures 204. Since there is a gap between the normal active regions 202n, the active area of the second reference power-gated cell 294 is smaller than the active area of the wide active region 202w in the power-gated cell 102 when the length X1 of the normal active regions 202n is the same as the length X2 of the wide active region 202w. Figure 2A

[0050] In summary, the power-gated cell 102 with the wide active region 202w can achieve a smaller chip area and a higher power conversion efficiency.

[0051] Figure 3 is a diagram showing a power-gated cell 102 according to some embodiments. In the example shown, the wide active region 202w has four fin structures 204, and each of the four normal active regions 202n has one fin structure. The normal active regions 202n at the top and bottom of the power-gated cell 102 are relatively long in the X direction. H0 is the standard cell height (in the Y direction) of a single-fin active region cell. The height of the cell 102 is 2H0 (in the Y direction). The distances H0, a0, b0, c0 have the following relationships: Figure 3

[0052] H0≠a0≠b0≠c0≠p≠w,​​​

[0053] where p is the fin structure pitch, and w is the width of the fin structure 204.

[0054] Figure 4 is a diagram illustrating a power gating cell 102 according to some embodiments. In the example shown, the wide active area 202w has four fin structures 204, and each of the six normal active areas 202n has one fin structure. The normal active areas 202n on the right side of the power gating cell 102 are relatively longer in the X direction. H0 is the standard cell height (in the Y direction) of the single-fin active area cell. The height of the cell 102 is 2H0 (in the Y direction). The distances H0, a0, b0, c0 have the following relationships: Figure 4

[0055] H0≠a0≠b0≠c0≠p≠w,

[0056] where p is the fin structure pitch, and w is the width of the fin structure 204.

[0057] Figure 5 is a diagram illustrating a power gating cell 102 according to some embodiments. In the example shown, the wide active area 202w has six fin structures 204, and each of the four normal active areas 202n has one fin structure. The normal active areas 202n on the top and bottom of the power gating cell 102 are relatively longer in the X direction. H0 is the standard cell height (in the Y direction) of the single-fin active area cell. The height of the cell 102 is 2H0 (in the Y direction). The distances H0, a0, b0, c0 have the following relationships: Figure 5

[0058] H0≠a0≠b0≠c0≠p≠w,

[0059] where p is the fin structure pitch, and w is the width of the fin structure 204.

[0060] Figure 6 is a diagram illustrating a power gating cell 102 according to some embodiments. In the example shown, the wide active area 202w has six fin structures 204, and each of the six normal active areas 202n has one fin structure. The normal active areas 202n on the right side of the power gating cell 102 are relatively longer in the X direction. H0 is the standard cell height (in the Y direction) of the single-fin active area cell. The height of the cell 102 is 2H0 (in the Y direction). The distances H0, a0, b0, c0 have the following relationships: Figure 6

[0061] H0≠a0≠b0≠c0≠p≠w,

[0062] ​​​Where p is the fin structure spacing and w is the width of fin structure 204.

[0063] Figure 7 This is a diagram illustrating a power gating unit 102 according to some embodiments. Figure 7 In the example shown, the wide active region 202w has eight fin structures 204, and each of the four ordinary active regions 202n has two fin structures. The ordinary active regions 202n at the top and bottom of the power gating unit 102 are relatively long in the X direction. H1 is the standard cell height (along the Y direction) of the two-fin active region cell. Cell 102 has a height of 2H1 (along the Y direction). The distances H1, a1, b1, and c1 have the following relationship:

[0064] H1≠a1≠b1≠c1≠p,

[0065] Where p is the fin spacing.

[0066] Figure 8 This is a diagram illustrating a power gating unit 102 according to some embodiments. Figure 8 In the example shown, the wide active region 202w has eight fin structures 204, and each of the six ordinary active regions 202n has two fin structures. The ordinary active region 202n on the right side of the power gating unit 102 is relatively longer in the X direction. H1 is the standard cell height (along the Y direction) of the two-fin active region cell. Cell 102 has a height of 2H1 (along the Y direction). The distances H1, a1, b1, and c1 have the following relationship:

[0067] H1≠a1≠b1≠c1≠p,

[0068] Where p is the fin spacing.

[0069] Figure 9 This is a diagram illustrating a power gating unit 102 according to some embodiments. Figure 9 In the example shown, the wide active region 202w has sixteen fin structures 204, and each of the six ordinary active regions 202n has two fin structures. The ordinary active regions 202n at the top and bottom of the power gating unit 102 are relatively long in the X direction. H1 is the standard cell height (along the Y direction) of the two-fin active region cell. Cell 102 has a height of 3H1 (along the Y direction). The distances H1, a1, b1, and c1 have the following relationship:

[0070] H1≠a1≠b1≠c1≠p,

[0071] Where p is the fin spacing.

[0072] Figure 10is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 10 In the example shown, the wide active region 202w has sixteen fin structures 204, and each of the eight normal active regions 202n has two fin structures. The normal active regions 202n on the right side of the power gating cell 102 are relatively longer in the X direction. H1 is the standard cell height (in the Y direction) for a two-fin active region cell. The cell 102 has a height (in the Y direction) of 3H1. The distances H1, a1, b1, c1 have the following relationships:

[0073] H1≠ a1≠ b1≠ c1≠ p,

[0074] where p is the fin structure pitch.

[0075] Figure 11 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 11 In the example shown, the wide active region 202w has twenty-four fin structures 204, and each of the eight normal active regions 202n has two fin structures. The normal active regions 202n on the top and bottom of the power gating cell 102 are relatively longer in the X direction. H1 is the standard cell height (in the Y direction) for a two-fin active region cell. The cell 102 has a height (in the Y direction) of 4H1. The distances H1, a1, b1, c1 have the following relationships:

[0076] H1≠ a1≠ b1≠ c1≠ p,

[0077] where p is the fin structure pitch.

[0078] Figure 12 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 12 In the example shown, the wide active region 202w has twenty-four fin structures 204, and each of the ten normal active regions 202n has two fin structures. The normal active regions 202n on the right side of the power gating cell 102 are relatively longer in the X direction. H1 is the standard cell height (in the Y direction) for a two-fin active region cell. The cell 102 has a height (in the Y direction) of 4H1. The distances H1, a1, b1, c1 have the following relationships:

[0079] H1≠ a1≠ b1≠ c1≠ p,

[0080] where p is the fin structure pitch.

[0081] Figure 13 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 13In the example shown, the wide active region 202w has eight fin structures 204, and each of the four normal active regions 202n has three fin structures. The normal active regions 202n at the top and bottom of the power gating cell 102 are relatively long in the X direction. H2 is the standard cell height (in the Y direction) for a three-fin active region cell. The cell 102 has a height (in the Y direction) of 2H2. The distances H2, a2, b2, c2 have the following relationships:

[0082] H2≠ a2≠ b2≠ c2≠ p,

[0083] where p is the fin structure pitch.

[0084] Figure 14 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 14 In the example shown, the wide active region 202w has eight fin structures 204, and each of the six normal active regions 202n has three fin structures. The normal active regions 202n at the right side of the power gating cell 102 are relatively long in the X direction. H2 is the standard cell height (in the Y direction) for a three-fin active region cell. The cell 102 has a height (in the Y direction) of 2H2. The distances H2, a2, b2, c2 have the following relationships:

[0085] H2≠ a2≠ b2≠ c2≠ p,

[0086] where p is the fin structure pitch.

[0087] Figure 15 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 15 In the example shown, the wide active region 202w has sixteen fin structures 204, and each of the six normal active regions 202n has three fin structures. The normal active regions 202n at the top and bottom of the power gating cell 102 are relatively long in the X direction. H2 is the standard cell height (in the Y direction) for a three-fin active region cell. The cell 102 has a height (in the Y direction) of 3H2. The distances H2, a2, b2, c2 have the following relationships:

[0088] H2≠ a2≠ b2≠ c2≠ p,

[0089] where p is the fin structure pitch.

[0090] Figure 16 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 16In the example shown, the wide active region 202w has sixteen fin structures 204, and each of the eight normal active regions 202n has three fin structures. The normal active regions 202n on the right side of the power gating cell 102 are relatively long in the X direction. H2 is the standard cell height (in the Y direction) for a three-fin active region cell. The cell 102 has a height (in the Y direction) of 3H2. The distances H2, a2, b2, c2 have the following relationships:

[0091] H2≠ a2≠ b2≠ c2≠ p,

[0092] where p is the fin pitch.

[0093] Figure 17 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 17 In the example shown, the wide active region 202w has twenty-four fin structures 204, and each of the ten normal active regions 202n has three fin structures. The normal active regions 202n on the top and bottom of the power gating cell 102 are relatively long in the X direction. H2 is the standard cell height (in the Y direction) for a three-fin active region cell. The cell 102 has a height (in the Y direction) of 4H2. The distances H2, a2, b2, c2 have the following relationships:

[0094] H2≠ a2≠ b2≠ c2≠ p,

[0095] where p is the fin pitch.

[0096] Figure 18 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 18 In the example shown, the wide active region 202w has twenty-four fin structures 204, and each of the ten normal active regions 202n has three fin structures. The normal active regions 202n on the right side of the power gating cell 102 are relatively long in the X direction. H2 is the standard cell height (in the Y direction) for a three-fin active region cell. The cell 102 has a height (in the Y direction) of 4H2. The distances H2, a2, b2, c2 have the following relationships:

[0097] H2≠ a2≠ b2≠ c2≠ p,

[0098] where p is the fin pitch.

[0099] Figure 19 is a diagram illustrating a power gating cell 102 according to some embodiments. In Figure 19In the example shown, there are two wide active regions 202w (one with eight fin structures 204 and the other with four fin structures 204) and each of the four normal active regions 202n has two fin structures. In this example, H3 is the standard cell height (in the Y direction) for a two-fin active region cell. The height of the cell 102 is 2H3 (in the Y direction). The distances H3, a3, and b3 have the following relationships:

[0100] H3≠a3≠b3≠p,

[0101] where p is the fin structure pitch.

[0102] Figure 20 is a diagram illustrating a power-gated cell 102 according to some embodiments. In Figure 20 In the example shown, the wide active region 202w has twelve fin structures 204 and each of the four normal active regions 202n has two fin structures. The normal active regions 202n are not located near the long side of the wide active region 202w in the X direction. In this example, H3 is the standard cell height (in the Y direction) for a two-fin active region cell. The height of the cell 102 is 2H3 (in the Y direction). The distances H3, a3, and b3 have the following relationships:

[0103] H3≠a3≠b3≠p,

[0104] where p is the fin structure pitch.

[0105] Figure 21 is a flowchart illustrating a method of generating a power-gated cell layout according to some embodiments. Figure 22 is a block diagram of a system 2200 for implementing the method of Figure 21 according to some embodiments.

[0106] Referring to Figure 21 , at step 2102, placement and pitch rules for the power-gated cell are generated. The placement and pitch rules are a set of rules regarding the placement and pitch that must be followed when generating the layout. For example, as shown in Figure 20 , the relationship of H3≠a3≠b3≠p is one of the placement and pitch rules. In some embodiments, the placement and pitch rules are enforced for each new layout cell (e.g., the layout of one of the normal active regions 202n as shown in Figure 2A At step 2104, a center region (e.g., the center region 212 as shown in Figure 2A ) of the power-gated cell and a perimeter region (e.g., the perimeter region 216 as shown in Figure 2A ) of the power-gated cell surrounding the center region are defined based on the placement and pitch rules. Specifically, a boundary line (e.g., the boundary line 214 as shown in Figure 2AThe boundary line 214 is shown, and parameters for the central and peripheral regions are stored. In step 2104, placement and spacing rules are satisfied. For example, the peripheral region at the top of the central region cannot be too narrow to accommodate a typical active region. In step 2106, a first active region layout is selected from the layout unit library. The first active region layout is for wide active regions (e.g., such as...). Figure 2A The layout of the wide active region 202w shown is illustrated. The layout unit library includes various layout units, such as layouts for ordinary active regions and layouts for wide active regions. These layout units are used to construct layouts as needed. In step 2108, based on placement and spacing rules, the first active region layout selected in step 2106 is placed within the central region defined in step 2104. In step 2110, multiple active region layouts are selected from the layout unit library. The second active region layout is for ordinary active regions (e.g., such as...). Figure 2A The layout of the ordinary active region 202n shown is illustrated. In step 2112, based on placement and spacing rules, the second active region layout selected in step 2110 is placed within the peripheral area defined in step 2104. This generates a power gating unit (e.g., such as...). Figure 2A The layout of the power gating unit 102 shown is illustrated.

[0107] refer to Figure 22 System 2200 can be used for implementation Figure 21 The method. System 2200 includes processor 2202 and non-transitory computer-readable storage medium 2204 encoded (i.e., stored) with computer program code 2206 (i.e., a set of executable instructions). Processor 2202 is electrically coupled to computer-readable storage medium 2204 via bus 2208. Processor 2202 is configured to execute computer program code 2206 encoded in computer-readable storage medium 2204, so that system 2200 can be used to execute Figure 21 The aforementioned operations may include some or all of them. In some embodiments, the processor 2202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit. In some embodiments, the computer-readable storage medium 2204 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 2204 may be a semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a hard disk, and / or an optical disk, but other types of computer-readable storage media may also be used.

[0108] Among other things, computer-readable storage media 2204 stores placement and spacing rules 2222, a library of layout cells 2224, a center region parameter store 2226, a perimeter region parameter store 2228, and a power-gating cell layout 2230, which are needed to perform the method of Figure 21 or generated during the performance of the method of Figure 21 It should be noted that computer-readable storage media 2204 can store other information as needed. Placement and spacing rules 2222 are a set of rules regarding spacing and placement that must be followed when generating a layout as described above. Library of layout cells 2224 stores various layout cells used to build a layout as needed. Center region parameter store 2226 stores parameters regarding the center region defined at step 2104 as described above (e.g., size, number of wide active regions within the center region). Perimeter region parameter store 2228 stores parameters regarding the perimeter region defined at step 2104 as described above (e.g., size, number of normal active regions within the perimeter region). Power-gating cell layout 2230 is the layout generated by performing the method of Figure 21 Power-gating cell layout 2230 is stored in computer-readable storage media 2204. Power-gating cell layout 2230 can be used later to place next to standard logic cells to cut off power to the standard logic cells in standby or hibernate mode to save chip power consumption.

[0109] System 2200 also includes input / output (I / O) interface 2208 and network interface 2210. System 2200 is coupled to external circuitry through I / O interface 2208. Network interface 2210 is coupled to processor 2202. Network interface 2210 allows system 2200 to communicate with network 2212 that has one or more other computer systems connected thereto. Network interface 2210 can be a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA, etc. or a wired network interface, such as ETHERNET, USB, or IEEE- 1394.

[0110] System 2200 can further include manufacturing tools 2240 for performing processes and / or methods stored in storage media 2204. For example, synthesis can be performed on a design, where the design's desired behavior and / or functionality is transformed into a functionally equivalent logic gate-level circuit description by matching the design with standard cells selected from library of layout cells 2224. Synthesis produces a functionally equivalent logic gate-level circuit description, such as a gate-level netlist. Based on the gate-level netlist, photolithography masks can be generated that are used by manufacturing tools 2240 to manufacture integrated circuits. Other embodiments disclose devices manufactured. Figure 24 Figure 24 ​This is a block diagram of an IC manufacturing system 2400 according to some embodiments and an associated IC manufacturing process. In some embodiments, based on a layout diagram, the manufacturing system 2400 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) at least one element in a semiconductor integrated circuit layer.

[0111] Figure 23 This is a flowchart illustrating a method for manufacturing a power gating unit according to some embodiments. For example... Figure 23 As shown, in step 2302, a substrate is provided (e.g., such as...). Figure 2A The substrate 190 shown has a first active region and a plurality of second active regions. The first active region is located within the central region of the power gating unit. The plurality of second active regions are located within the peripheral region of the power gating unit surrounding the central region. The first active region has a first width in a first direction, which corresponds to at least four fin structures extending in a second direction perpendicular to the first direction. Each second active region has a second width in the first direction, which corresponds to at least one and no more than three fin structures extending in the second direction. In some instances, the substrate may be a bulk semiconductor substrate. In some embodiments, the semiconductor substrate is a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate may include a plurality of epitaxial layers (i.e., a multilayer substrate). The substrate may include a basic semiconductor such as silicon and germanium. Alternatively, the substrate may comprise compound semiconductors such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and / or cadmium telluride; alloy semiconductors such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The substrate may comprise various regions that have been appropriately doped (e.g., p-type or n-type conductivity). It should be noted that other types of substrate structures and semiconductor materials are also within the scope of this invention.

[0112] In step 2304, a fin structure is formed above the first active region and the plurality of second active regions. The fin structure (e.g., as shown in the image) Figure 2A The fin structure 204 shown may contain any suitable material. In one example, the fin structure is in the second direction (e.g., as shown in the image). Figure 2AThe fin structures extend in the X direction (as shown). In one embodiment, the fin structures are silicon fin structures. In another example, the fin structures can include multiple layers, such as one or more epitaxial layers grown on a bulk semiconductor substrate and / or the bulk semiconductor substrate itself. The fin structures can be formed by any suitable process including various deposition, lithography, etching, epitaxy, and / or other suitable processes. An example lithography process can include forming a photoresist layer ("resist") over the substrate, exposing the resist to a pattern using a mask, performing a post-exposure bake process, and developing the resist to form mask elements including the resist. The mask elements can then be used for etching to form the fin structures. The etching process can be a reactive ion etching (RIE) process and / or other suitable processes. In another example, the fin structures can be formed by a double pattern lithography (DPL) process. DPL is a method of building a pattern on a substrate by splitting the pattern into two interlaced patterns. DPL allows for enhanced fin structure density. Various DPL methods can be used, including two exposures (e.g., using two mask sets), forming spacers near the features and removing the features to provide a pattern of spacers, resist, and / or other suitable processes. It should be noted that other types of fin structures and fin structure materials are within the scope of the present application.

[0113] At step 2306, source / drain regions of the fin structures are doped. In one example, the source / drain regions of the fin structures are doped by performing an implant process to implant a suitable dopant to replenish dopants in the fin structures. In another example, the source / drain regions of the fin structures can be formed by forming a recess in the fin structures and epitaxially growing a material in the recess. It should be noted that other types of source / drain structures and formation processes are within the scope of the present application.

[0114] At step 2308, gate structures are formed over the fin structures within the first active region and the plurality of second active regions. Each gate structure (e.g., as shown in FIG. 27) can be formed by any suitable process including various deposition, lithography, etching, epitaxy, and / or other suitable processes. An example lithography process can include forming a photoresist layer ("resist") over the substrate, exposing the resist to a pattern using a mask, performing a post-exposure bake process, and developing the resist to form mask elements including the resist. The mask elements can then be used for etching to form the gate structures. The etching process can be a reactive ion etching (RIE) process and / or other suitable processes. In another example, the gate structures can be formed by a double pattern lithography (DPL) process. DPL is a method of building a pattern on a substrate by splitting the pattern into two interlaced patterns. DPL allows for enhanced gate structure density. Various DPL methods can be used, including two exposures (e.g., using two mask sets), forming spacers near the features and removing the features to provide a pattern of spacers, resist, and / or other suitable processes. It should be noted that other types of gate structures and gate structure materials are within the scope of the present application. Figure 2AThe illustrated gate strips 208) can include a gate dielectric layer, a gate electrode layer, and / or other suitable layers, such as a capping layer, an interface layer, a work function layer, a diffusion / straining layer, etc. The gate structures and / or fin structures can be patterned such that the gate structures wrap around a portion of the fin structures. In one example, the gate structures can contact at least three surfaces (e.g., a top surface and opposing side surfaces) of the fin structures. In another example, the gate structures surround or approximately surround the fin structures such that the gate structures contact a fourth surface (e.g., a bottom surface) of the fin structures. The gate dielectric layer includes a dielectric material, such as silicon oxide, silicon nitride, a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide (Hf02- Al203) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate electrode includes any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. It should be noted that other gate structures and materials are within the scope of the present application.

[0115] At step 2310, contact structures are deposited over the source and drain regions in the first active region and the plurality of second active regions. Specifically, depositing the source and drain contact structures can include, for example, depositing a barrier layer such as titanium nitride, tantalum nitride, tungsten nitride, ruthenium, or combinations thereof, and then depositing a conductive material such as aluminum, copper, tungsten, or combinations thereof. The depositing can be performed by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. Excess barrier layer material and / or conductive material can be later removed by, for example, chemical mechanical polishing (CMP). In some embodiments, the source and drain contact structures are deposited in an interlayer dielectric (ILD), such as a low-k dielectric layer or an extremely low-k dielectric layer. Specifically, the source and drain contact structures are formed by forming an interlayer dielectric (ILD), patterning the ILD by covering certain portions of the ILD with a mask and simultaneously exposing other portions of the ILD, etching the ILD to remove the exposed portions of the ILD to form recesses, and depositing a conductive material in the recesses. It should be noted that other types of formation processes and materials are within the scope of the present application. In this way, individual FinFETs are fabricated within the first active region and the plurality of second active regions.

[0116] At step 2312, an electrical interconnect structure is formed between the first active region and the plurality of second active regions. The electrical interconnect structure is configured to connect various components or structures of individual FinFETs located within the first active region and the plurality of second active regions. In some embodiments, the electrical interconnect structure includes a multi-layer interconnect including vertical interconnects such as conventional vias or contacts and horizontal interconnects such as metal lines. These electrical interconnect structures are made of various conductive materials including, but not limited to, copper, tungsten, and / or silicides. In one example, a damascene and / or dual damascene process is used to form the multi-layer interconnect structure in relation to copper. In this way, the individual FinFETs are connected as head switches or foot switches.

[0117] Figure 24 is a block diagram of an IC manufacturing system in accordance with some embodiments. In Figure 24 , the IC manufacturing system 2400 includes entities such as a design house 2420, a mask house 2430, and an IC manufacturer / foundry ("fab") 2450 that interact in a design, development, and manufacturing cycle and / or services related to IC devices 2460 such as the power gating cell 102 disclosed above. The entities in the system 2400 are connected through a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is various different networks such as an intranet and the Internet. The communications network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or accepts services from one or more other entities. In some embodiments, two or more of the design house 2420, the mask house 2430, and the IC foundry 2450 are owned by a single larger company. In some embodiments, two or more of the design house 2420, the mask house 2430, and the IC foundry 2450 coexist in a common facility and use common resources.

[0118] A design room (or design team) 2420 generates an IC design layout 2422. The IC design layout 2422 includes various geometric patterns or an IC layout designed for an IC device 2460 (e.g., an IC device including one or more of the above-discussed, disclosed power gating cells 102). The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various elements of the IC device 2460 to be fabricated. Various layers are combined to form various IC components. For example, a portion of the IC design layout 2422 includes various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnections, and openings for bond pads to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room 2420 implements a design process to form the IC design layout 2422. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 2422 is represented in one or more data files having information for the geometric patterns. For example, the IC design layout 2422 can be expressed in a GDSII file format or a DFII file format.

[0119] A mask room 2430 includes data preparation 2432 and mask manufacturing 2444. The mask room 2430 uses the IC design layout 2422 to manufacture one or more masks 2445 for use in fabricating various layers of the IC device 2460 according to the IC design layout 2422. The mask room 2430 performs mask data preparation 2432 in which the IC design layout 2422 is translated into a representative data file ("RDF"). The mask data preparation 2432 provides the RDF to the mask manufacturing 2444. The mask manufacturing 2444 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 2445 or a semiconductor wafer 2453. The design layout 2422 is manipulated by the mask data preparation 2432 to conform to the particular characteristics of the mask writer, and / or requirements of the IC foundry 2450. In some embodiments, the mask data preparation 2432 and the mask manufacturing 2444 are shown as separate elements. In some embodiments, the mask data preparation 2432 and the mask manufacturing 2444 can be collectively referred to as mask data preparation. Figure 24

[0120] ​In some embodiments, mask data preparation 2432 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors, e.g., that can be due to diffraction, interference, other processing effects, etc. OPC adjusts IC design layout 2422. In some embodiments, mask data preparation 2432 includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0121] In some embodiments, mask data preparation 2432 includes a mask rule checker (MRC) that checks IC design layout 2422 after it has been processed in OPC using a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure adequate margins to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies IC design layout 2422 to compensate for limitations during mask fabrication 2444, which can undo a portion of the modifications performed by OPC to comply with the mask creation rules.

[0122] In some embodiments, mask data preparation 2432 includes lithography process checking (LPC) that simulates the processing to be performed by IC foundry 2450 to fabricate IC device 2460. LPC emulates the processing based on IC design layout 2422 to produce a simulated fabricated device, such as IC device 2460. Processing parameters in the LPC emulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after a simulated fabricated device is produced by the LPC, if the simulated device is not close enough in shape to satisfy design rules, then OPC and / or MRC are repeated to further refine IC design layout 2422.

[0123] It should be appreciated that the above description of mask data preparation 2432 has been simplified for clarity. In some embodiments, data preparation 2432 includes additional components, such as logic operations (LOP), to modify IC design layout 2422 according to manufacturing rules. Furthermore, the processing applied to IC design layout 2422 during data preparation 2432 can be performed in various different orders.

[0124] After mask data preparation 2432 and during mask manufacturing 2444, a mask 2445 or a set of masks 2445 is manufactured based on the modified IC design layout 2422. In some embodiments, mask manufacturing 2444 includes performing one or more photolithography exposures based on the IC design layout 2422. In some embodiments, an e-beam or multiple e-beams mechanism is used to form a pattern on a mask (photomask or reticle) 2445 according to the modified IC design layout 2422. The mask 2445 can be formed in various techniques. In some embodiments, the mask 2445 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) that has been coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 2445 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated within the opaque regions of the binary mask. In another example, the mask 2445 is formed using phase shift techniques. In a phase shift mask (PSM) version of the mask 2445, various components in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask resulting from mask manufacturing 2444 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in a semiconductor wafer 2453, in etching processes to form various etched regions in the semiconductor wafer 2453, and / or in other suitable processes.

[0125] The IC foundry 2450 includes wafer fabrication 2452. The IC foundry 2450 is an IC manufacturing enterprise that includes one or more fabrication facilities for fabricating various different IC products. In some embodiments, the IC foundry 2450 is a semiconductor foundry. For example, there can be one fabrication facility for front end of the line (FEOL) fabrication of multiple IC products, while a second fabrication facility can provide back end of the line (BEOL) fabrication for interconnection and packaging of the IC products, and a third fabrication facility can provide other services for the foundry enterprise.

[0126] IC foundry 2450 uses the mask 2445, which was manufactured by the mask room 2430, to manufacture IC devices 2460. Thus, the IC foundry 2450 uses the IC design layout 2422, at least indirectly, to manufacture the IC devices 2460. In some embodiments, a semiconductor wafer 2453 is manufactured by the IC foundry 2450 using the mask 2445 to form the IC devices 2460. In some embodiments, the IC manufacturing includes performing one or more photolithography exposures based, at least indirectly, on the IC design layout 2422. The semiconductor wafer 2453 includes a silicon substrate or other suitable substrate having material layers formed thereon. The semiconductor wafer 2453 further includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0127] According to some disclosed embodiments, a power gating cell on an integrated circuit is provided. The power gating cell includes: a center region; a perimeter region surrounding the center region; a first active region in the center region, the first active region having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; a plurality of second active regions in the perimeter region, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

[0128] In the above power gating cell, the integrated circuit has a global fin grid group extending in the second direction, and the at least four fin structures corresponding to the first active region are aligned with the global fin grid group.

[0129] In the above power gating cell, the at least one and no more than three fin structures corresponding to each of the plurality of second active regions are not aligned with the global fin grid group.

[0130] In the above power gating cell, the power gating cell is a head cell configured to cut off power to a standard logic cell on the integrated circuit in response to a control signal.

[0131] In the above power gating cell, the power gating cell is a foot cell configured to cut off power to a standard logic cell on the integrated circuit in response to a control signal.

[0132] In the above power gating cell, the second width corresponds to one fin structure.

[0133] In the above power gating cell, the second width corresponds to two fin structures.

[0134] In the above power gating cell, the second width corresponds to three fin structures.

[0135] According to some disclosed embodiments, an integrated circuit is provided. The integrated circuit includes a standard logic cell configured to implement a function, and a power gating cell coupled to the standard logic cell, the power gating cell configured to disconnect a power supply to the standard logic cell in response to a control signal, the power gating cell having a central region and a peripheral region surrounding the central region. The power gating cell further includes a first active region located at the central region, the first active region having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, and a plurality of second active regions located at the peripheral region, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

[0136] In the above integrated circuit, the integrated circuit has a global fin grid group extending in the second direction, and the at least four fin structures corresponding to the first active region are aligned with the global fin grid group.

[0137] In the above integrated circuit, the at least one and no more than three fin structures corresponding to each of the plurality of second active regions are not aligned with the global fin grid group.

[0138] In the above integrated circuit, the power gating cell is a head cell, the head cell configured to disconnect the power supply to the standard logic cell on the integrated circuit in response to the control signal.

[0139] In the above integrated circuit, the power gating cell is a foot cell, the foot cell configured to disconnect the power supply to the standard logic cell on the integrated circuit in response to the control signal.

[0140] In the above integrated circuit, the second width corresponds to one fin structure.

[0141] In the above integrated circuit, the second width corresponds to two fin structures.

[0142] In the above integrated circuit, the second width corresponds to three fin structures.

[0143] According to further disclosed embodiments, a method of fabricating a power gated cell on an integrated circuit is provided. The method includes: providing a substrate, wherein the substrate has a first active region and a plurality of second active regions thereon, the first active region is located within a center region of the power gated cell and has a first width in a first direction, the first width corresponds to at least four fin structures extending in a second direction perpendicular to the first direction, the plurality of second active regions are located within a perimeter region of the power gated cell surrounding the center region, each of the second active regions has a second width in the first direction, the second width corresponds to at least one and no more than three fin structures extending in the second direction; forming fin structures over the first active region and the plurality of second active regions; doping source regions and drain regions of the fin structures; forming gate structures over the fin structures within the first active region and the plurality of second active regions.

[0144] In the above method, further comprising: depositing contact structures over the source regions and the drain regions.

[0145] In the above method, further comprising: forming electrical interconnect structures between the first active region and the plurality of second active regions.

[0146] In the above method, forming the gate structures includes: forming a gate dielectric layer; and depositing a gate electrode layer over the gate dielectric layer.

[0147] The features outlined herein facilitate an understanding of aspects of the application by persons of ordinary skill in the art. Those skilled in the art will readily understand that the present application can be varied in many ways and that the application can be practiced otherwise than as specifically described. Those skilled in the art will readily understand that the present application can be varied in many ways and that the application can be practiced otherwise than as specifically described. Those skilled in the art will readily understand that the present application can be varied in many ways and that the application can be practiced otherwise than as specifically described.

Claims

1. A power supply gating unit on an integrated circuit, comprising: Central area; The surrounding area, which is located around the central area; A first active region is located within the central region, the first active region having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; as well as Multiple second active regions are located within the surrounding area, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

2. The power gating unit according to claim 1, wherein, The integrated circuit has a global fin grid group extending in the second direction, and the at least four fin structures corresponding to the first active region are aligned with the global fin grid group.

3. The power gating unit according to claim 2, wherein, The at least one and no more than three fin structures corresponding to each of the plurality of second active regions are not aligned with the global fin grid group.

4. The power gating unit according to claim 1, wherein, The power gating unit is a head unit configured to cut off power to standard logic cells on the integrated circuit in response to a control signal.

5. The power gating unit according to claim 1, wherein, The power gating unit is a foot unit configured to cut off power to standard logic cells on the integrated circuit in response to a control signal.

6. The power gating unit according to claim 1, wherein, The second width corresponds to a fin structure.

7. The power gating unit according to claim 1, wherein, The second width corresponds to the two fin structures.

8. The power gating unit according to claim 1, wherein, The second width corresponds to the three fin structures.

9. An integrated circuit, comprising: Standard logic unit, configured to perform functions; A power gating unit coupled to the standard logic unit, the power gating unit being configured to disconnect power to the standard logic unit in response to a control signal, the power gating unit having a central region and a peripheral region surrounding the central region; and The power gating unit further includes: A first active region, located within the central region, has a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and Multiple second active regions are located within the surrounding area, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

10. The integrated circuit according to claim 9, wherein, The integrated circuit has a global fin grid group extending in the second direction, and the at least four fin structures corresponding to the first active region are aligned with the global fin grid group.

11. The integrated circuit according to claim 10, wherein, The at least one and no more than three fin structures corresponding to each of the plurality of second active regions are not aligned with the global fin grid group.

12. The integrated circuit according to claim 9, wherein, The power gating unit is a head unit configured to cut off power to standard logic cells on the integrated circuit in response to a control signal.

13. The integrated circuit according to claim 9, wherein, The power gating unit is a foot unit configured to cut off power to standard logic cells on the integrated circuit in response to a control signal.

14. The integrated circuit according to claim 9, wherein, The second width corresponds to a fin structure.

15. The integrated circuit according to claim 9, wherein, The second width corresponds to the two fin structures.

16. The integrated circuit according to claim 9, wherein, The second width corresponds to the three fin structures.

17. A method for manufacturing a power gating unit on an integrated circuit, comprising: A substrate is provided, wherein a first active region and a plurality of second active regions are provided on the substrate, the first active region being located within a central region of the power gating unit and having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, the plurality of second active regions being located within a peripheral region of the power gating unit surrounding the central region, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction; A fin structure is formed above the first active region and the plurality of second active regions; The source and drain regions of the fin structure are doped; and A gate structure is formed above the fin structure in the first active region and the plurality of second active regions.

18. The method of claim 17, further comprising: A contact structure is deposited above the source region and the drain region.

19. The method of claim 18, further comprising: An electrical interconnect structure is formed between the first active region and the plurality of second active regions.

20. The method of claim 17, wherein, The formation of the gate structure includes: forming a gate dielectric layer; and A gate electrode layer is deposited above the gate dielectric layer.

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