Integrated circuit structure and method of forming an integrated circuit structure

Abstract

An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active area and a first gate disposed on the first active area, wherein the first gate has a first effective gate length along a first direction parallel to the longitudinal direction of the first active area. The second transistor includes a second active area and a second gate disposed on the second active area, and includes a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length being n times the first effective gate length, and n being a positive integer greater than 1. According to other embodiments of the present application, a method for forming an integrated circuit structure is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit structures and methods of forming integrated circuit structures. Background Art

[0002] As integrated circuits become smaller, the layout of the integrated circuits is modified to reduce the total area occupied by the integrated circuits. This reduction in layout area is achieved by replacing integrated circuit components with new structures that are smaller than the previous versions of the integrated circuit components. The reduction in layout area is also achieved by reducing the distance between circuit components in the integrated circuit layers. Summary of the Invention

[0003] According to an embodiment of the present application, an integrated circuit (IC) structure is provided, comprising: a first transistor, comprising: a first active region; and a first gate, disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a longitudinal direction of the first active region; and a second transistor, comprising: a second active region; and a second gate, disposed on the second active region, and the second transistor includes a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.

[0004] According to another embodiment of the present application, an integrated circuit structure is provided, comprising: a first transistor, comprising: a first active area and a second active area, separated by an isolation structure, wherein the first active area and the second active area extend along a first direction; a gate, having a plurality of gate structures respectively disposed on the first active area and the second active area, wherein, along the first direction, an effective gate length of the gate is n times a critical dimension of a technology node of the first transistor, and n is a positive integer and greater than 1; a plurality of gate spacers, adjacent to each of the gate structures of the gate; and a first source / drain region, located in the first active area; and a second source / drain region, located in the second active area; and a second transistor, having a gate length substantially equal to the critical dimension of the technology node of the first transistor.

[0005] According to another embodiment of the present application, a method for forming an integrated circuit structure is provided, comprising: forming a first active region and a second active region extending along a first direction above a substrate, wherein the first active region and the second active region are separated by an isolation structure; forming a first gate structure above the first active region; forming a plurality of second gate structures above the second active region, wherein, along the first direction, the sum of the gate lengths of the second gate structures is n times the gate length of the first gate structure, and n is a positive integer and greater than 1; forming a first source / drain region in the first active region; and forming a second source / drain region in the second active region, wherein a dopant concentration of a portion of the second active region located between two adjacent second gate structures is lower than a dopant concentration of the second source / drain region.

[0006] Embodiments of the present application relate to integrated circuit layout and methods thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A and 1B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0009] Figure 1C Shown Figure 1A and 1B The equivalent circuit of .

[0010] Figure 2A and 2B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0011] Figure 2C Shown Figure 2A and 2B The equivalent circuit of .

[0012] Figure 3A and 3B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0013] Figure 3C Shown Figure 3A and 3B The equivalent circuit of .

[0014] Figure 4A and 4B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0015] Figure 4C Shown Figure 4A and 4B The equivalent circuit of .

[0016] Figure 5A and 5B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0017] Figure 5C Shown Figure 5A and 5B The equivalent circuit of .

[0018] Figure 6A and 6B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0019] Figure 6C Shown Figure 6A and 6B The equivalent circuit of .

[0020] Figure 7A and 7B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0021] Figure 7C Shown Figure 7A and 7B The equivalent circuit of .

[0022] Figure 8A and 8B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0023] Figure 8C Shown Figure 8A and 8B The equivalent circuit of .

[0024] Figure 8D is a block diagram of an integrated circuit according to some embodiments of the present invention.

[0025] Figure 9A and 9B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0026] Figure 9C Shown Figure 9A and 9B The equivalent circuit of .

[0027] Figure 9D is a block diagram of an integrated circuit according to some embodiments of the present invention.

[0028] Figure 10A and 10B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0029] Figure 10C Shown Figure 10A and 10B The equivalent circuit of .

[0030] Figure 11A and 11B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0031] Figure 11C Shown Figure 11A and 11B The equivalent circuit of .

[0032] Figure 12A and 12B A top view and a cross-sectional view of an integrated circuit according to some embodiments of the present invention are shown.

[0033] Figure 12C Shown Figure 12A and 12B The equivalent circuit of .

[0034] Figure 13 is a schematic diagram of an electronic design automation (EDA) system 1300 according to some embodiments of the present invention. DETAILED DESCRIPTION

[0035] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0036] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0037] Field effect transistors (FETs) are components of some integrated circuits. FETs contain a channel region and also have a source region and a drain region (collectively referred to as the source / drain region) separated by the channel region. A gate electrode is located above the channel region. By applying a voltage to the gate electrode, the conductivity of the channel region increases, allowing current to flow from the source region to the drain region. FETs utilize a conductive gate contact electrically connected to the gate electrode to apply a gate voltage to the FET, and utilize source / drain contacts electrically connected to the source / drain regions to conduct current to and from the FET.

[0038] Figure 1A 、 1B 1C show an integrated circuit 100A according to some embodiments of the present invention, wherein: Figure 1A is a top view of the integrated circuit 100A, and Figure 1B It is along Figure 1A Cross-sectional view along line BB. Figure 1C Shown as Figure 1A and 1B The equivalent circuit of the integrated circuit 100B is shown.

[0039] The integrated circuit 100A includes a first transistor T1 and a second transistor T2. The first transistor T1 includes an active region 112, and the second transistor T2 includes an active region 114. The active regions 112 and 114 extend along the X direction. Here, the X direction is the longitudinal direction of the active regions 112 and 114, and the Y direction is the longitudinal direction of the gate structures 122 and 124, wherein the X direction is perpendicular to the Y direction. In some embodiments, the active regions 112 and 114 are arranged along the X direction, but embodiments of the present invention are not limited thereto. In some embodiments, the active regions 112 and 114 may protrude from the substrate and may be separated by a plurality of isolation structures made of oxide, which provide electrical isolation between different active regions. Therefore, in some embodiments, the active regions 112 and 114 may also be referred to as oxide-defined (OD) regions. For example, in Figure 1B, active regions 112 and 114 are separated by at least isolation structure 105. In some embodiments, isolation structure 105 is a shallow trench isolation (STI) structure formed by, for example, etching one or more trenches in a substrate, depositing one or more dielectric materials (e.g., silicon oxide) into the one or more trenches, and then performing a chemical mechanical polishing (CMP) process to level the deposited one or more dielectric materials with the substrate.

[0040] The active region 112 of the first transistor T1 includes a source region and a drain region, which are collectively referred to as a source / drain region 132. Similarly, the active region 114 of the second transistor T2 includes a source region and a drain region, which are collectively referred to as a source / drain region 134.

[0041] The first transistor T1 includes a gate structure 122 located above and across the active region 112. Similarly, the second transistor T2 includes a gate structure 124 located above and across the active region 114. Figure 1B In FIG. 4 , a plurality of gate spacers 106 are disposed on opposite sidewalls of the gate structures 122 and 124 , respectively.

[0042] The gate structure 122 of the first transistor T1 has a gate length LG1, and the gate structure 124 of the second transistor T2 has a gate length LG2. Here, "gate length" refers to the length (or width, depending on the viewing angle) of the gate structure 122 and / or 124 measured in the X direction. The gate lengths LG1 and LG2 are different from each other. The gate length LG2 is greater than the gate length LG1. The channel region is defined as the overlapping area between the gate structure and the active region. Since the gate length LG1 of the first transistor T1 is less than the gate length LG2 of the second transistor T2, the channel length of the first transistor T1 is less than the channel length of the second transistor T2. Therefore, the first transistor T1 can be referred to as a short channel device, and the second transistor T2 can be referred to as a long channel device. In some embodiments, the gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2=n*LG1, where n is a positive integer. In some embodiments, n is a positive integer and greater than 1 (for example, n=2, 3, 4...).

[0043] In some embodiments, gate length LG1 is the minimum gate length in integrated circuit 100A. In some embodiments, gate length LG1 of gate structure 122 is a critical dimension (CD) in a technology node (e.g., a 10 nm node, a 7 nm node, a 5 nm node, a 3 nm node, or greater). Here, the term "critical dimension" refers to the smallest (or minimum) dimension of a pattern component, such as gate lengths LG1 and LG2. The critical dimension contributes to the overall pattern layout size and pattern layout density. In the depicted embodiment, each component of the pattern (e.g., gate structures 122 and / or 124) has a dimension or size, such as a length along the X direction. The size of each component can be greater than or equal to the critical dimension of the pattern. As described above, gate length LG1 is a critical dimension. That is, gate length LG1 of gate structure 122 of first transistor T1 is the smallest (or minimum) gate length of gate structures in the corresponding technology node. Because gate length LG2 is greater than gate length LG1, gate length LG2 is greater than the critical dimension.

[0044] In some embodiments, a long channel device, such as the second transistor T2, can be used as a transistor in the header circuit because the long channel device can save leakage in the header circuit. In some other embodiments, a long channel device, such as the second transistor T2, can be used as an n-channel metal oxide semiconductor (NMOS) device in a skew inverter. In the skew inverter, if the p-channel metal oxide semiconductor (PMOS) device in the skew inverter is designed to be stronger than the strength of the NMOS device in the skew inverter, the NMOS device can be a long channel device, and the PMOS device can be a short channel device. For example, the NMOS device of the skew inverter can be the second transistor T2 described herein, and the PMOS device of the skew inverter can be the first transistor T1 described herein. In some other embodiments, a long channel device, such as the second transistor T2, can be used as a transistor in a variation tolerance circuit because the long channel can provide smaller variations. Here, the variation tolerance circuit can include a sense amplifier in a memory device, a comparator in an analog-to-digital converter (ADC), etc.

[0045] Active regions 112 and 114 can be formed on a substrate including, but not limited to, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a silicon-germanium substrate. Other semiconductor materials containing Group III elements, Group IV elements, and Group V elements are within the scope of various embodiments. For example, active regions 112 and 114 can be formed by patterning a substrate, for example, using photolithography and etching techniques. In some embodiments, active regions 112 and 114 are electrically isolated from each other by an isolation structure (not shown). In some embodiments, the isolation structure is a shallow trench isolation (STI) structure comprising a trench filled with one or more dielectric materials. In some embodiments, the STI structure comprises silicon dioxide, silicon nitride, silicon oxynitride, or any other suitable insulating material.

[0046] Source / drain regions 132 and 134 are doped semiconductor regions located on opposite sides of corresponding gate structures 122 and 124. In some embodiments, source / drain regions 132 and 134 include p-type dopants, such as boron, for forming p-type FETs. In other embodiments, source / drain regions 132 and 134 include n-type dopants, such as phosphorus, for forming n-type FETs.

[0047] In some embodiments, the source / drain regions 132 and 134 can be epitaxially grown regions. For example, the gate spacer 106 can be formed next to the dummy gate structure (which will be replaced by the final gate structures 122 and 124) by depositing a spacer material and anisotropically etching the spacer material, and then the source / drain regions 132 and 132 are formed to be self-aligned with the gate spacer 106 by first etching the active regions 112 and 114 to form recesses and then depositing a crystalline semiconductor material in the recesses by a selective epitaxial growth (SEG) process. In some embodiments, the SEG process can fill the recesses in the active regions 112 and 114 and can also extend beyond the original surface of the active regions 112 and 114 to form raised source / drain epitaxial structures. The crystalline semiconductor material can be elemental (e.g., Si or Ge, etc.) or alloy (e.g., Si or Ge, etc.). 1-x C x or Si 1-x Ge x The SEG process can use any suitable epitaxial growth method, such as vapor phase / solid phase / liquid phase epitaxy (VPE, SPE, LPE), metal organic CVD (MOCVD) or molecular beam epitaxy (MBE).

[0048] The gate structures 122 and 124 extend across the active areas 112 and 114, respectively, along the Y direction. In some embodiments, the gate structures 122 and 124 are high-k metal gate (HKMG) gate structures that can be formed using a gate-last process flow (interchangeably referred to as a gate replacement process). In the gate-last process flow, a sacrificial dummy gate structure (e.g., a polysilicon gate, not shown) is formed above the active areas 112 and 114, respectively. Each of the dummy gate structures can include a dummy gate dielectric, a dummy gate electrode (e.g., a polysilicon gate), and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, etc.) can be deposited. Next, a dummy electrode material (e.g., polysilicon) can be deposited over the dummy gate dielectric and then planarized (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, etc.) can be formed over the dummy gate material. Then, a dummy gate structure is formed by patterning the hard mask layer and transferring the pattern to the dummy gate dielectric and dummy gate material using suitable photolithography and etching techniques. After forming the source / drain regions 132 and 134, as shown herein, the dummy gate structures are replaced with HKMG gate structures 122 and 124. The materials used to form the dummy gate structures and the hard mask may be deposited using any suitable method such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or by thermal oxidation of the semiconductor surface, or a combination thereof.

[0049] In some embodiments, each of the HKMG gate structures 122 and 124 includes a high-k gate dielectric material, a work function metal layer, and a fill metal. Exemplary high-k gate dielectric materials include, but are not limited to, silicon nitride, silicon oxynitride, hafnium oxide (HfO2), LaHfO x , ZrO2, hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the HKMG gate structures 122 and 124 may further include an interfacial layer between the high-k gate dielectric material and the active regions 112 and 114, respectively. The interfacial layer may include SiO2, SiON, or the like.

[0050] Exemplary work function metal layers include TiN (for PMOS), TiAl (for NMOS), etc. In some embodiments, the work function metal layer may include Rb, Eu, Sr, Ba, Sm, Tb, Y, Nd, La, Sc, Lu, Mg, Tl, Hf, Al, Mn, Zr, Bi, Pb, Ta, Ag, V, Zn, Ti, Nb, Sn, W, Cr, Fe, Mo, Cu, Ru, Sb, Os, TaN, TiN / TaN, Ta / Si / N, Te, Re, Rh, Be, Co, Au, Pd, Ni, Ir, Pt, Se.

[0051] Exemplary filler metals include, for example, copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN), or molybdenum nitride (MoN).

[0052] In some embodiments, the gate spacer 106 may be made of SiO2, Si3N4, SiO x N y , SiC, SiCN film, SiOC, silicon oxycarbonitride film and / or a combination thereof or may contain SiO2, Si3N4, SiO x N y , SiC, SiCN film, SiOC, silicon oxycarbonitride film, and / or combinations thereof. The gate spacer 106 can be formed, for example, by depositing a dielectric layer over the dummy gate structure (as discussed above) and subsequently performing an etching process to remove horizontal portions of the dielectric material. In some embodiments, the HKMG gate structures 122 and 124 can further include a barrier layer between the work function metal layer and the fill metal. The barrier layer can include TiN, TaN, Ti, Co, etc.

[0053] Figure 2A 、 2B 2C show an integrated circuit 100B according to some embodiments of the present invention, wherein: Figure 2A is a top view of integrated circuit 100B, and Figure 2B It is along Figure 2A Cross-sectional view along line BB. Figure 2C Shown as Figure 2A and 2B The equivalent circuit of the integrated circuit 100A is shown. Figure 2A 、 2B Some components of 2C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0054] The integrated circuit 100B includes a first transistor T1 and a second transistor T3 . Figure 2A 、 2B and the first transistor T1 described in 2C and Figure 1A 、 1B The gate length LG1 of the first transistor T1 is the same as the first transistor T1 described in FIG1C .

[0055] The second transistor T3 has an active area 214. The active area 214 extends along the X-direction. The second transistor T3 includes a plurality of gate structures 224 disposed on the active area 214. In some embodiments, each gate structure 224 has a gate length LG1. In other words, the gate length of each gate structure 224 of the second transistor T3 is the same as the gate length of the gate structure 122 of the first transistor T1, where the gate length LG1 is a critical dimension in the corresponding technology node. In some embodiments, gate spacers 106 are disposed on opposite sidewalls of each gate structure 224.

[0056] In some embodiments, the gate structures 224 are electrically connected (e.g., via one or more metal lines and one or more vias in a back-end-of-line (BEOL) interconnect structure, not shown) and can therefore be collectively referred to as gates 220, where the gates 220 serve as the gates of transistors T3. In some embodiments, the gate structures 224 are electrically connected to the same voltage node. In other words, the gate 220 of transistor T3 can be considered to have several sections (e.g., gate structures 224) arranged along the X direction, wherein each section has spacers 106 disposed on its opposite sidewalls. As mentioned above, each of the gate structures 224 has a gate length LG1. Therefore, if the number of gate structures 224 is n, the effective gate length of the gate 220 of transistor T3 is n*LG1, where n is a positive integer greater than 1. Therefore, the first transistor T1 can be referred to as a short channel device, and the second transistor T3 can be referred to as a long channel device.

[0057] The transistor T3 has a plurality of source / drain regions 234 disposed in the active region 214. In more detail, the source / drain regions 234 are disposed on opposite sides of the gate 220 of the transistor T3. That is, the source / drain regions 234 are disposed adjacent to the outermost gate structure 224. Figure 2A and 2BIn the example shown in FIG, one source / drain region 234 is positioned adjacent to the rightmost gate structure 224, while the other source / drain region 234 is positioned adjacent to the leftmost gate structure 224. It should be noted that in some embodiments, there is no source / drain region between any two adjacent gate structures 224 of transistor T3. In other words, the portions of the active region 214 located between any two adjacent gate structures 224 are undoped or lightly doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source / drain regions 234. In practice, a first voltage and a second voltage can be applied to the source / drain regions 234, respectively, and a third voltage can be applied to the gate 220 to operate transistor T3. That is, a single voltage (e.g., the third voltage described herein) is applied to the gate structure 224.

[0058] Figure 3A 、 3B 3C and 3C show an integrated circuit 100C according to some embodiments of the present invention, wherein: Figure 3A is a top view of the integrated circuit 100C, and Figure 3B It is along Figure 3A Cross-sectional view along line BB. Figure 3C Shown as Figure 3A and 3B The equivalent circuit of the integrated circuit is shown. Figure 3A 、 3B Similar to some components of 3C Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0059] Integrated circuit 100C includes transistor T4. Figures 3A to 3C Not shown, but the integrated circuit 100C may include Figures 1A to 1C It should be noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

[0060] Transistor T4 has an active area 314. Active area 314 extends along the X direction. Transistor T4 includes a plurality of gate structures 324, a plurality of gate structures 326, and a plurality of gate structures 328 disposed on active area 314. In some embodiments, the number of gate structures 324 can be x, the number of gate structures 326 can be y, and the number of gate structures 328 can be z, where x, y, and z are positive integers. In some embodiments, each of gate structures 324 has a gate length LG1, where gate length LG1 is a critical dimension in the corresponding technology node. The gate length LG2 of each gate structure 326 is greater than the gate length LG1 of gate structure 324. In some embodiments, gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 = n * LG1, where n is a positive integer. In some embodiments, n is a positive integer and greater than 1 (e.g., n = 2, 3, 4, etc.). On the other hand, the gate length LG3 of each gate structure 328 is greater than the gate length LG1 of gate structure 324. In some embodiments, the gate length LG2 is m times the gate length LG1, where m is a positive integer. That is, LG3 = m*LG1, where m is a positive integer. In some embodiments, m is a positive integer and is greater than 1 (e.g., m = 2, 3, 4, ...). Figures 3A to 3C In the embodiment of , n is greater than m. For example, n may be 3, and m may be 2, but the present invention is not limited thereto.

[0061] Gate structures 324 form a first group GR1, gate structures 326 form a second group GR2, and gate structures 328 form a third group GR3. In some embodiments, each of groups GR1, GR2, and GR3 includes at least one gate structure having substantially the same gate length, while the gate length of one group differs from the gate length of the other groups. In some embodiments, groups Gr1, GR2, and GR3 are arranged sequentially along the X direction. In some embodiments, gate structures 324, 326, and 328 are electrically connected (e.g., via one or more metal lines and one or more vias in a BEOL interconnect structure (not shown)) and can therefore be collectively referred to as gates 320, where gates 320 serve as the gates of transistor T4. In some embodiments, gate structures 324, 326, and 328 are electrically connected to the same voltage node. From another perspective, gate 320 of transistor T4 can be viewed as having several sections (e.g., gate structures 324, 326, and 328) arranged along the X direction, each section having spacers 106 disposed on opposing sidewalls thereof. Also, the segments may be divided into several groups (eg, groups GR1 , GR2 , and GR3 ), wherein the segments in each group have substantially the same gate length.

[0062] As mentioned above, the number of gate structures 324, 326 and 328 is x, y and z, respectively, where x, y and z are positive integers. Therefore, the effective gate length of the gate 320 of the transistor T4 is x*LG1+y*LG2+z*LG3. From another perspective, because the gate length LG2 of the gate structure 326 can be expressed as n*LG1, and the gate length LG3 of the gate structure 328 can be expressed as m*LG1. Therefore, the effective gate length of the gate 320 of the transistor T4 can also be expressed as x*LG1+y*n*LG1+z*m*Lg1, that is, (x+y*n+z*m)*LG1. Because x, y, z, n, m are all positive integers, the term x+y*n+z*m is also a positive integer. That is to say, the effective gate length of the gate 320 of the transistor T4 is several times (for example, x+y*n+z*m times) the gate length LG1 with the critical dimension. Therefore, the transistor T4 can be called a long channel device. It should be noted that Figures 3A to 3C The integrated circuit 100C may also include short channel devices, such as Figures 1A to 1C The transistor T1 described in FIG.

[0063] The transistor T4 has a plurality of source / drain regions 334 disposed in the active region 314. In more detail, the source / drain regions 334 are disposed on opposite sides of the gate 320 of the transistor T4. That is, the source / drain regions 334 are disposed adjacent to the outermost gate structure. Figure 3A and 3B In the example shown in FIG4 , one source / drain region 334 is positioned adjacent to the leftmost gate structure 324, while another source / drain region 334 is positioned adjacent to the rightmost gate structure 328. It should be noted that in some embodiments, there is no source / drain region between any two adjacent gate structures 324, 326, and 328 of transistor T4. In other words, portions of active region 314 located between any two adjacent gate structures 324, 326, and 328 are undoped or lightly doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source / drain region 334. In practice, a first voltage and a second voltage can be applied to the source / drain regions 334, respectively, and a third voltage can be applied to gate 320 to operate transistor T4. That is, a single voltage (e.g., the third voltage described herein) is applied to gate structures 324, 326, and 328.

[0064] Figure 4A 、 4B 4C show an integrated circuit 100D according to some embodiments of the present invention, wherein: Figure 4A is a top view of the integrated circuit 100D, and Figure 4B It is along Figure 4A Cross-sectional view along line BB. Figure 4C Shown as Figure 4A and 4B The equivalent circuit of the integrated circuit 100D is shown. Figure 4A 、 4B Some components of 4C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0065] like Figure 4A 、 4B and 4C. The integrated circuit 100D includes a transistor T5. Although Figures 4A to 4C Not shown, but the integrated circuit 100D may include Figures 1A to 1C It should be noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

[0066] Transistor T5 has an active region 414 extending along the X-direction. Transistor T5 includes a gate structure 424 having a gate length LG1, a gate structure 426 having a gate length LG2, and a gate structure 428 having a gate length LG3, where gate length LG1 is a critical dimension in the corresponding technology node. In some embodiments, gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 = n*LG1, where n is a positive integer. In some embodiments, n is a positive integer and greater than 1 (e.g., n = 2, 3, 4, ...). On the other hand, the gate length LG3 of each gate structure 328 is greater than the gate length LG1 of gate structure 324. In some embodiments, gate length LG2 is m times the gate length LG1, where m is a positive integer. That is, LG3 = m*LG1, where m is a positive integer. In some embodiments, m is a positive integer and greater than 1 (e.g., m = 2, 3, 4, ...). For example, n can be 2 and m can be 3, but the present invention is not limited to this.

[0067] The gate structure 424 forms a first group GR1, the gate structure 426 forms a second group GR2, and the gate structure 428 forms a third group GR3. In some embodiments, each of the groups GR1, GR2, and GR3 includes at least one gate structure having substantially the same gate length, while the gate length of one group is different from the gate length of the other groups. In some embodiments, the groups Gr1, GR2, and GR3 are arranged sequentially along the X direction. That is, the gate structure 426 and / or the gate structure 428 may not be present between two gate structures 424, and vice versa. In some embodiments, the gate structures 424, 426, and 428 are electrically connected and can be collectively referred to as a gate 420, wherein the gate 420 serves as the gate of the transistor T5. In some embodiments, the gate structures 424, 426, and 428 are electrically connected to the same voltage node. From another perspective, the gate 420 of the transistor T5 can be viewed as having several sections (e.g., gate structures 424, 426, and 428) arranged along the X direction, wherein each section has a spacer 106 disposed on its opposite sidewalls. Also, the segments may be divided into several groups (eg, groups GR1 , GR2 , and GR3 ), wherein the segments in each group have substantially the same gate length.

[0068] The effective gate length of the gate 420 of the transistor T5 is 3*LG1+2*LG2+1*LG3. From another perspective, because the gate length LG2 of the gate structure 426 can be expressed as n*LG1, and the gate length LG3 of the gate structure 428 can be expressed as m*LG1. Therefore, the effective gate length of the gate 420 of the transistor T5 can also be expressed as 3*LG1+2*n*LG1+1*m*LG1, that is, (3+2*n+1*m)*LG1. In some embodiments, where n=2 and m=4, the effective gate length of the gate 420 of the transistor T5 is 11 times (for example, 3+2*2+1*4 times) the gate length LG1 with the critical dimension. Therefore, the transistor T5 can be referred to as a long channel device. It should be noted that Figures 4A to 4C The integrated circuit 100D may also include short channel devices, such as Figures 1A to 1C Transistor T1 is described.

[0069] The transistor T5 has a plurality of source / drain regions 434 disposed in the active region 414. In more detail, the source / drain regions 434 are disposed on opposite sides of the gate 420 of the transistor T5. That is, the source / drain regions 434 are disposed adjacent to the outermost gate structure. Figure 4A and 4BIn the example shown in FIG5 , one source / drain region 434 is positioned adjacent to the leftmost gate structure 424, while another source / drain region 434 is positioned adjacent to the rightmost gate structure 428. It should be noted that in some embodiments, there is no source / drain region between any two adjacent gate structures 424, 426, and 428 of transistor T5. In other words, portions of active region 414 located between any two adjacent gate structures 424, 426, and 428 are undoped or lightly doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source / drain region 434. In practice, a first voltage and a second voltage can be applied to the source / drain regions 434, respectively, and a third voltage can be applied to gate 420 to operate transistor T5. That is, a single voltage (e.g., the third voltage described herein) is applied to gate structures 424, 426, and 428.

[0070] Figure 5A 、 5B 5C show an integrated circuit 100E according to some embodiments of the present invention, wherein: Figure 5A is a top view of the integrated circuit 100E, and Figure 5B It is along Figure 5A Cross-sectional view along line BB. Figure 5C Shown as Figure 5A and 5B The equivalent circuit of the integrated circuit 100E is shown. Figure 5A 、 5B Some components of 5C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0071] like Figure 5A 、 5B 5C. The integrated circuit 100D includes a transistor T6. Although Figures 5A to 5C Not shown, but the integrated circuit 100E may include Figures 1A to 1C It should be noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

[0072] The transistor T6 includes an active region 514 and a plurality of gate structures 524, 526, and 528 disposed on the active region 514. The gate structure 524 having a gate length LG1 is similar to Figures 4A to 4C The gate structure 424 having a gate length LG2 and the gate structure 526 having a gate length LG2 are similar to Figures 4A to 4C The gate structure 426 and the gate structure 528 having a gate length LG3 are similar to Figures 4A to 4CThe gate structures 524, 526, and 528 are electrically connected and may be collectively referred to as gate 520, where gate 520 serves as the gate of transistor T6. In some embodiments, gate structures 524, 526, and 528 are electrically connected to the same voltage node.

[0073] Figures 5A to 5C The transistor T6 is different from the transistor T6 in that at least the gate structures 524, 526 and 528 are randomly arranged along the X direction. Figures 4A to 4C That is, for example, the gate structure 524 and / or the gate structure 528 may exist between two gate structures 524 having the same gate length LG1, and vice versa.

[0074] The transistor T6 has a plurality of source / drain regions 534 disposed in the active region 514. In more detail, the source / drain regions 534 are disposed on opposite sides of the gate 520 of the transistor T5. That is, the source / drain regions 534 are disposed adjacent to the outermost gate structure. Figure 5A and 5B In the example shown in FIG5 , one source / drain region 534 is positioned adjacent to the leftmost gate structure 524, while another source / drain region 534 is positioned adjacent to the rightmost gate structure 524. It should be noted that in some embodiments, there is no source / drain region between any two adjacent gate structures 524, 526, and 528 of transistor T5. In other words, portions of active region 514 located between any two adjacent gate structures 524, 526, and 528 are undoped or lightly doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source / drain region 534. In practice, a first voltage and a second voltage can be applied to the source / drain regions 534, respectively, and a third voltage can be applied to gate 520 to operate transistor T6. That is, a single voltage (e.g., the third voltage described herein) is applied to gate structures 524, 526, and 528.

[0075] Figure 6A 、 6B 6C show an integrated circuit 100F according to some embodiments of the present invention, wherein: Figure 6A is a top view of the integrated circuit 100F, and Figure 6B It is along Figure 6A Cross-sectional view along line BB. Figure 6C Shown as Figure 6A and 6B The equivalent circuit of the integrated circuit is shown. Figure 6A 、 6B Some components of 6C are similar to Figure 1A 、 1Band those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0076] Integrated circuit 100F includes transistor T7. Figures 6A to 6C Not shown, but the integrated circuit 100F may include Figures 1A to 1C It should be noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

[0077] Transistor T7 has active regions 614 and 616 extending along the X direction, wherein active regions 614 and 616 are arranged along the Y direction. Transistor T7 has contacts 640 disposed on active regions 614 and 616, respectively, and metal lines 650 over and electrically connected to contacts 640. Therefore, active region 614 is electrically connected to active region 616 via contacts 640 and metal lines 650. In some embodiments, contacts 640 and metal lines 650 are formed of a suitable metal, such as copper, aluminum, tungsten, or a combination thereof.

[0078] The second transistor T7 includes a plurality of gate structures 624 disposed on the active regions 614 and 616. In some embodiments, each gate structure 624 has a gate length LG1. That is, each gate structure 224 of the second transistor T7 has substantially the same gate length, where the gate length LG1 is a critical dimension in the corresponding technology node. In some embodiments, gate spacers 106 are disposed on opposing sidewalls of each gate structure 624.

[0079] In some embodiments, the gate structure 624 is electrically connected and can therefore be Figure 6C are collectively referred to as gate 620 in the equivalent circuit of , where gate 620 acts as the gate of transistor T7. In some embodiments, the gate structure 624 is electrically connected to the same voltage node. In other words, the gate 620 of transistor T7 can be regarded as having several portions (e.g., gate structures 624) arranged along the X direction, wherein each portion has a spacer 106 disposed on its opposite sidewalls. As mentioned above, each of the gate structures 624 has a gate length LG1. Therefore, if the number of gate structures 624 is n, the effective gate length of the gate 620 of transistor T7 is n*LG1, where n is a positive integer greater than 1. Therefore, transistor T7 can be referred to as a long channel device. It should be noted that Figures 6A to 6C The integrated circuit 100F may also include short channel devices, such as Figures 1A to 1C Transistor T1 is described.

[0080] Transistor T7 has a plurality of source / drain regions 634 disposed in active regions 614 and 616, respectively. More specifically, one source / drain region 634 is disposed on a first side of active region 614, with a contact 640 disposed on a second side of active region 614 opposite the first side. On the other hand, another source / drain region 634 is disposed on a first side of active region 616, with a contact 640 disposed on a second side of active region 616 opposite the first side. In other words, the source / drain regions 634 are disposed on two separate active regions 614 and 616. It should be noted that in some embodiments, no source / drain region exists between any two adjacent gate structures 624 of transistor T7. In other words, portions of the active regions 614 and 616 located between any two adjacent gate structures 624 are undoped or lightly doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source / drain region 634. In operation of the transistor T7, a first voltage and a second voltage can be applied to the source / drain region 634, respectively, and a third voltage can be applied to the gate 620 to operate the transistor T7. That is, a single voltage (e.g., the third voltage described herein) is applied to the gate structure 624. For example, current can flow from the source / drain region 634 on the active region 614 to the source / drain region 634 on the active region 616 through the contact 640 and the metal line 650.

[0081] Figure 7A 、 7B 7C shows an integrated circuit 100G according to some embodiments of the present invention, wherein: Figure 7A is a top view of the integrated circuit 100G, and Figure 7B It is along Figure 7A Cross-sectional view along line BB. Figure 7C Shown as Figure 7A and 7B The equivalent circuit of the integrated circuit 100G is shown. Figure 7A 、 7B Some components of 7C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0082] Integrated circuit 100G includes transistor T8. Figures 7A to 7C Not shown, but the integrated circuit 100G may include Figures 1A to 1C It should be noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

[0083] Similar to Figures 6A to 6CThe transistor T7 and the transistor T8 have separate active regions 714 and 716. The transistor T8 has contacts 740 disposed on the active regions 714 and 716, respectively, and a metal line 750 over and electrically connecting the contacts 740.

[0084] Transistor T8 includes a plurality of gate structures 724, a plurality of gate structures 726, and a plurality of gate structures 728 disposed on active regions 714 and 716, respectively. Gate structures 724, 726, and 726 are electrically connected. In some embodiments, gate structures 724, 726, and 728 are electrically connected to the same voltage node. In some embodiments, the number of gate structures 724 can be x, the number of gate structures 726 can be y, and the number of gate structures 728 can be z, where x, y, and z are positive integers. In some embodiments, each of gate structures 724 has a gate length LG1, where gate length LG1 is a critical dimension in the corresponding technology node. The gate length LG2 of each gate structure 726 is greater than the gate length LG1 of gate structure 724. In some embodiments, gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 = n*LG1, where n is a positive integer. In some embodiments, n is a positive integer and greater than 1 (e.g., n = 2, 3, 4, ...). On the other hand, the gate length LG3 of each gate structure 728 is greater than the gate length LG1 of the gate structure 724. In some embodiments, the gate length LG2 is m times the gate length LG1, where m is a positive integer. That is, LG3 = m*LG1, where m is a positive integer. In some embodiments, m is a positive integer and greater than 1 (e.g., m = 2, 3, 4, ...). Figures 7A to 7C In the embodiment of , n is greater than m. For example, n may be 3, and m may be 2, but the present invention is not limited thereto.

[0085] The gate structure 724 forms a first group GR1, the gate structure 726 forms a second group GR2, and the gate structure 728 forms a third group GR3. In some embodiments, each of the groups GR1, GR2, and GR3 includes at least one gate structure having substantially the same gate length, while the gate length of one group is different from the gate length of the other groups. In some embodiments, the groups GR1, GR2, and GR3 are arranged sequentially along the X direction. In some embodiments, the gate structures 724, 726, and 726 are electrically connected and can be collectively referred to as a gate 720, wherein the gate 720 serves as the gate of the transistor T8. In some embodiments, the gate structures 724, 726, and 728 are electrically connected to the same voltage node. From another perspective, the gate 720 of the transistor T8 can be viewed as having several sections (e.g., gate structures 724, 726, and 728) arranged along the X direction, wherein each section has spacers 106 disposed on its opposite sidewalls. Furthermore, the sections can be divided into several groups (e.g., groups GR1, GR2, and GR3), wherein the sections in each group have substantially the same gate length.

[0086] As mentioned above, the number of gate structures 724, 726 and 728 is x, y and z, respectively, where x, y and z are positive integers. Therefore, the effective gate length of the gate 720 of the transistor T8 is x*LG1+y*LG2+z*LG3. From another perspective, because the gate length LG2 of the gate structure 726 can be expressed as n*LG1, and the gate length LG3 of the gate structure 728 can be expressed as m*LG1. Therefore, the effective gate length of the gate 720 of the transistor T8 can also be expressed as x*LG1+y*n*LG1+z*m*Lg1, that is, (x+y*n+z*m)*LG1. Because x, y, z, n, m are all positive integers, the term x+y*n+z*m is also a positive integer. That is to say, the effective gate length of the gate 720 of the transistor T8 is several times (for example, x+y*n+z*m times) the gate length LG1 with the critical dimension. Therefore, the transistor T8 can be called a long channel device. It should be noted that Figures 7A to 7C The integrated circuit 100G may also include short channel devices, such as Figures 1A to 1C Transistor T1 is described.

[0087] In some embodiments, the gate structures 724, 726, and 728 are randomly arranged along the X direction. That is, for example, the gate structure 724 and / or the gate structure 728 may exist between two gate structures 724 having the same gate length LG1, and vice versa. In some other embodiments, the gate structure 726 and / or the gate structure 728 may not exist between two gate structures 724, and vice versa.

[0088] Transistor T8 has a plurality of source / drain regions 734 disposed in active regions 714 and 716, respectively. More specifically, one source / drain region 734 is disposed on a first side of active region 714, with a contact 740 disposed on a second side of active region 714 opposite the first side. On the other hand, another source / drain region 734 is disposed on a first side of active region 716, with a contact 740 disposed on a second side of active region 716 opposite the first side. In other words, the source / drain regions 734 are disposed on two separate active regions 714 and 716. It should be noted that in some embodiments, no source / drain region exists between any two adjacent gate structures 724, 726, and 728 of transistor T8. In other words, portions of the active regions 714 and 716 located between any two adjacent gate structures 724, 726, and 728 are undoped or lightly doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source / drain region 734. In operation of transistor T7, a first voltage and a second voltage can be applied to the source / drain region 734, respectively, and a third voltage can be applied to the gate 720 to operate transistor T8. That is, a single voltage (e.g., the third voltage described herein) is applied to the gate structures 724, 726, and 728. For example, current can flow from the source / drain region 734 on the active region 714 to the source / drain region 734 on the active region 716 through the contact 740 and the metal line 750.

[0089] Figure 8A 、 8B 8C show an integrated circuit 100H according to some embodiments of the present invention, wherein: Figure 8A is a top view of the integrated circuit 100H, and Figure 8B It is along Figure 8A Cross-sectional view along line BB. Figure 8C Shown as Figure 8A and 8B The equivalent circuit of the integrated circuit 100H is shown. Figure 8A 、 8B Some components of 8C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0090] Integrated circuit 100H includes transistor T9. Although Figures 8A to 8C Not shown, but the integrated circuit 100H may include Figures 1A to 1C It should be noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

[0091] Transistor T9 has active regions 814, 816, and 818 extending along the X direction, wherein active regions 814, 816, and 818 are arranged along the Y direction. Transistor T9 has contacts 842 disposed on active regions 814 and 816, respectively, and a metal line 852 disposed above and electrically connected to contacts 842. Thus, active region 814 is electrically connected to active region 816 via contacts 842 and metal line 852. On the other hand, transistor T9 also has contacts 844 disposed on active regions 816 and 818, respectively, and a metal line 854 disposed above and electrically connected to contacts 844. Thus, active region 816 is electrically connected to active region 818 via contacts 844 and metal line 854.

[0092] Transistor T9 includes gate structures 821, 822, 823, 824, 825, 826, 827, 828, and 829 electrically connected using, for example, one or more metal lines and vias in a BEOL interconnect structure. In some embodiments, gate structures 821-829 are electrically connected to the same voltage node. Gate structures 821, 822, and 823 are disposed on active region 814, gate structures 824, 825, and 826 are disposed on active region 816, and gate structures 827, 828, and 829 are disposed on active region 818.

[0093] In some embodiments, each of the gate structures 821 to 829 may include a short gate length or a long gate length. Figure 8A and 8B In the example of FIG. 8 , gate structures 821 , 824 , 825 , and 828 have long gate lengths, while gate structures 822 , 823 , 826 , 827 , and 829 have short gate lengths. In some embodiments, gate structures 822 , 823 , 826 , 827 , and 829 have substantially the same gate length LG1 , where gate length LG1 is a critical dimension in the corresponding technology node. On the other hand, gate structures 821 , 824 , 825 , and 828 have substantially the same gate length LG2 . Gate length LG2 is greater than gate length LG1 . In some embodiments, gate length LG2 is n times greater than gate length LG1 , where n is a positive integer. That is, LG2 = n * LG1 , where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (e.g., n = 2, 3, 4 . . . ).

[0094] In some embodiments, the gate structures 821 to 829 are electrically connected and can be collectively referred to as a gate 820, wherein the gate 820 serves as the gate of the transistor T9. In some embodiments, the gate structures 821-829 are electrically connected to the same voltage node. In other words, the gate 820 of the transistor T9 can be considered to have several sections (e.g., gate structures 821 to 829) arranged along the X direction, wherein each section has a spacer 106 disposed on its opposite sidewalls.

[0095] In some embodiments, transistor T9 may include an x ​​gate structure having a short gate length LG1 and a y gate structure having a long gate length LG2 (for example, in this case, x=5 and y=4). Therefore, the effective gate length of the gate 820 of transistor T9 is x*LG1+y*LG2. From another perspective, because the gate length LG2 can be expressed as n*LG1, the effective gate length of the gate 820 of transistor T9 can also be expressed as x*LG1+y*n*LG1, that is, (x+y*n)*LG1. Because x, y, and n are all positive integers, the term x+y*n+z*m is also a positive integer. That is, the effective gate length of the gate 820 of transistor T9 is several times (for example, x+y*n times) the gate length LG1 having a critical dimension. Therefore, transistor T9 can be referred to as a long channel device. It should be noted that Figures 8A to 8C The integrated circuit 100H may also include short channel devices, such as Figures 1A to 1C The transistor T1 described in FIG.

[0096] Transistor T9 includes a plurality of source / drain regions 834 disposed in active regions 814 and 818, respectively. Specifically, one source / drain region 734 is disposed on a first side of active region 814, with a contact 842 disposed on a second side of active region 814 opposite the first side. Another source / drain region 734 is disposed on a first side of active region 818, with a contact 844 disposed on a second side of active region 818 opposite the first side. In other words, the source / drain regions 834 are disposed in two separate active regions 814 and 818. Furthermore, active region 816 between active region 814 and active region 818 does not include a source / drain region 834. In other words, the dopant concentration of the entire active region 816 is lower than the dopant concentration of the source / drain region 834. It should be noted that in some embodiments, there are no source / drain regions between any two adjacent gate structures 821 to 829 of transistor T9. In other words, the portions of active regions 814, 816, and 818 located between any two adjacent gate structures 821 to 829 are undoped or lightly doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source / drain region 834. In operation of transistor T8, a first voltage and a second voltage can be applied to the source / drain region 834, respectively, and a third voltage can be applied to the gate 820 to operate transistor T9. That is, a single voltage (e.g., the third voltage described herein) is applied to the gate structures 821 to 829. For example, current can flow from the source / drain region 834 on the active region 814 to the source / drain region 834 on the active region 818 through the active region 816. Furthermore, active region 814 is electrically connected to active region 816 through contact 842 and metal line 852 , and active region 816 is electrically connected to active region 818 through contact 844 and metal line 854 .

[0097] Figure 8D yes Figure 8A and 8D The block diagram of the integrated circuit 100H is shown in FIG. Figure 8D As shown, blocks 821A, 822A, 823A, 824A, 825A, 826A, 827A, 828A, and 829A are shown, wherein each of blocks 821A to 829A corresponds to a gate structure. For example, blocks 821A to 829A may correspond to Figure 8A In some embodiments, each of frames 821A to 829A may include a short gate length or a long gate length. For example, the short gate length may be Figure 8A and 8B The gate length LG1 described in , and the long gate length can be Figure 8A and8B Thus, each of blocks 821A to 829A may include two possibilities for gate length (e.g., short gate length or long gate length). In this regard, the combination of blocks 821A to 829A of integrated circuit 100H may include 29 variations.

[0098] Figure 9A 、 9B 9C show an integrated circuit 100I according to some embodiments of the present invention, wherein: Figure 9A is a top view of the integrated circuit 100I, and Figure 9B It is along Figure 9A Cross-sectional view along line BB. Figure 9C Shown Figure 9A and 9B Equivalent circuit of the integrated circuit 100I. Figure 9A 、 9B Some components of 9C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0099] The integrated circuit 100I includes a transistor T10. Figures 9A to 9C Not shown, but the integrated circuit 100I may include Figures 1A to 1C It should be noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

[0100] Similar to Figures 8A to 8C The transistor T9 and the transistor T10 have separate active regions 914, 916, and 918. The active region 914 is electrically connected to the active region 916 via a contact 942 and a metal line 952. On the other hand, the active region 916 is electrically connected to the active region 918 via a contact 944 and a metal line 954.

[0101] Transistor T10 includes gate structures 921, 922, 923, 924, 925, 926, 927, 928, and 929. Gate structures 921, 922, and 923 are disposed on active region 914, gate structures 924, 925, and 926 are disposed on active region 916, and gate structures 927, 928, and 929 are disposed on active region 918, respectively.

[0102] In some embodiments, the gate structures 921 - 929 have substantially the same gate length LG1 , where the gate length LG1 is a critical dimension in the corresponding technology node.

[0103] In some embodiments, the gate structures 921 to 929 are electrically connected and can be collectively referred to as a gate 920, wherein the gate 920 serves as the gate of the transistor T10. In some embodiments, the gate structures 921-929 are electrically connected to the same voltage node. In other words, the gate 920 of the transistor T10 can be considered to have several sections (e.g., gate structures 921 to 929) arranged along the X direction, wherein each section has a spacer 106 disposed on its opposite sidewalls.

[0104] In some embodiments, transistor T10 may include x gate structures having a gate length LG1 (e.g., in this case, x=9). Therefore, the effective gate length of the gate 920 of transistor T10 is x*LG1. Therefore, transistor T10 may be referred to as a long channel device. It should be noted that Figures 9A to 9C The integrated circuit 100I may also include short channel devices, such as Figures 1A to 1C The transistor T1 described in FIG.

[0105] In some embodiments, gate structures 921 to 929 may have different threshold voltages. The threshold voltage of each gate structure 921 to 929 may depend on the material composition and / or thickness of the gate dielectric and one or more work function metal layers therein. Therefore, the equivalent threshold voltage of gate 920 depends on the threshold voltage of gate structures 921 to 929.

[0106] Transistor T9 has a plurality of source / drain regions 934 disposed respectively in active regions 914 and 918. The relationship between the source / drain regions 934, active regions 914, 916, 918, gate structures 921 to 929, contacts 942, 944, and metal lines 952, 954 is similar to the relationship between the source / drain regions 834, active regions 814, 816, 818, gate structures 821 to 829, contacts 842, 844, and metal lines 852, 854, and therefore, for the sake of brevity, the relevant structural details are not repeated.

[0107] Figure 9D yes Figure 9A and 9D The block diagram of the integrated circuit 100I is shown in FIG. Figure 9D As shown, blocks 921A, 922A, 923A, 924A, 925A, 926A, 927A, 928A, and 929A are shown, where each of blocks 921A to 929A corresponds to a gate structure. For example, blocks 921A to 929A may correspond to Figure 9A921A to 929. As described above, each of blocks 921A to 929A can represent a gate structure having a different threshold voltage. For example, for the N7 technology node, there are three types of threshold voltages, such as ultra-low threshold voltage (ULVT), low threshold voltage (LVT), and standard threshold voltage (SVT). In this regard, each of blocks 921A to 929A can include three possibilities for threshold voltage. Therefore, the combination of blocks 921A to 929A of the integrated circuit 100I can include 39 variations. On the other hand, for the N5 technology node, there are five possible types of threshold voltages. Therefore, the combination of blocks 921A to 929A of the integrated circuit 100I can include 59 variations.

[0108] Figure 10A 、 10B and 10C show an integrated circuit 100J according to some embodiments of the present invention, wherein: Figure 10A is a top view of integrated circuit 100J, and Figure 10B It is along Figure 10A Cross-sectional view along line BB. Figure 10C Shown Figure 10A and 10B The equivalent circuit of . Figure 10A 、 10B Some components of 10C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0109] Integrated circuit 100J includes an active region 1014 and gate structures 1022, 1024, 1026, and 1028 disposed on active region 1014. Integrated circuit 100J also includes source / drain regions 1031, 1032, 1033, 1034, and 1035 disposed in active region 114. Source / drain regions 1031 and 1032 are located on opposite sides of gate structure 1022, wherein gate structure 1022 and source / drain regions 1031 and 1032 form transistor T111. Source / drain regions 1032 and 1033 are located on opposite sides of gate structure 1024, wherein gate structure 1024 and source / drain regions 1032 and 1033 form transistor T112. Source / drain regions 1033 and 1034 are on opposite sides of gate structure 1026, wherein gate structure 1026 and source / drain regions 1033 and 1034 form transistor T113. Source / drain regions 1034 and 1035 are on opposite sides of gate structure 1028, wherein gate structure 1028 and source / drain regions 1034 and 1035 form transistor T114.

[0110] In some embodiments, gate structures 1022 and 1028 have substantially the same gate length LG1, where gate length LG1 is a critical dimension in the corresponding technology node. On the other hand, gate structures 1024 and 1026 have substantially the same gate length LG2. Gate length LG2 is greater than gate length LG1. Therefore, transistors T111 and T114 can be referred to as short channel devices, and transistors T112 and T113 can be referred to as long channel devices. In some embodiments, gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 = n*LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (for example, n = 2, 3, 4 ...).

[0111] Integrated circuit 100J also includes contacts 1042 disposed on source / drain regions 1031 and 1035 , respectively, and metal lines 1052 over and electrically connecting contacts 1042 .

[0112] Figure 11A 、 11B 11C and 11C show an integrated circuit 100K according to some embodiments of the present invention, wherein: Figure 11A is a top view of the integrated circuit 100K, and Figure 11B It is along Figure 11A Cross-sectional view along line BB. Figure 11C Shown as Figure 11A and 11B The equivalent circuit of the integrated circuit 100K is shown. Figure 11A 、 11B Some components of 11C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0113] Integrated circuit 100K includes active regions 1114 and 1116 arranged along the Y direction, gate structures 1122 and 1124 disposed on active region 1114, and gate structures 1126 and 1128 disposed on active region 1116. Integrated circuit 100J further includes source / drain regions 1131, 1132, and 1133 disposed in active region 1114, and source / drain regions 1134, 1135, and 1136 disposed in active region 1116. Source / drain regions 1131 and 1132 are located on opposite sides of gate structure 1122, wherein gate structure 1122 and source / drain regions 1131 and 1132 form transistor T121. Source / drain regions 1132 and 1133 are located on opposite sides of the gate structure 1124, wherein the gate structure 1124 and the source / drain regions 1132 and 1133 form a transistor T122. Source / drain regions 1134 and 1135 are located on opposite sides of the gate structure 1126, wherein the gate structure 1126 and the source / drain regions 1134 and 1135 form a transistor T123. Source / drain regions 1135 and 1136 are located on opposite sides of the gate structure 1128, wherein the gate structure 1128 and the source / drain regions 1135 and 1136 form a transistor T124.

[0114] In some embodiments, gate structures 1122 and 1128 have substantially the same gate length LG1, where gate length LG1 is a critical dimension in the corresponding technology node. On the other hand, gate structures 1124 and 1126 have substantially the same gate length LG2. Gate length LG2 is greater than gate length LG1. Therefore, transistors T121 and T124 can be referred to as short channel devices, and transistors T122 and T123 can be referred to as long channel devices. In some embodiments, gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 = n*LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (for example, n = 2, 3, 4 ...).

[0115] Integrated circuit 100J also includes contacts 1142 disposed on source / drain regions 1033 and 1034 , respectively, and metal lines 1152 over and electrically connecting contacts 1142 .

[0116] Figure 12A 、 12B 12C show an integrated circuit 100L according to some embodiments of the present invention, wherein: Figure 12A is a top view of the integrated circuit 100L, and Figure 12B It is along Figure 12A Cross-sectional view along line BB. Figure 12C Shown Figure 12A and 12B The equivalent circuit of . Figure 12A 、 12B Some components of 12C are similar to Figure 1A 、 1B and those elements described in 1C, and therefore, for the sake of brevity, the relevant details are not repeated.

[0117] Integrated circuit 100L includes semiconductor fins 1211, 1212, 1213, 1214, and 1215 arranged along the Y direction. In some embodiments, along the X direction, semiconductor fins 1211, 1212, and 1213 are longer than semiconductor fins 1214 and 1215. Integrated circuit 100L further includes gate structures 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, and 1229, wherein gate structures 1220, 1221, 1222, 1223 intersect semiconductor fins 1211, 1212, and 1213, and gate structures 1224, 1225, 1226, 1227, 1228, and 1229 intersect semiconductor fins 1211, 1212, 1213, 1214, and 1215. In some embodiments, the gate structures 1220 - 1229 have substantially the same gate length LG1 , where the gate length LG1 is a critical dimension in the corresponding technology node.

[0118] Integrated circuit 100L also includes source / drain regions 1231, 1232, and 1233. In some embodiments, source / drain region 1231 is disposed in semiconductor fins 1211, 1212, and 1213 and is adjacent to gate structure 1220. Source / drain region 1232 is disposed in semiconductor fins 1211, 1212, 1213, 1214, and 1215 and is located between gate structures 1223 and 1225. Source / drain region 1233 is disposed in semiconductor fins 1211, 1212, and 1213 and is adjacent to gate structure 1229.

[0119] In some embodiments, gate structures 1220 to 1223 are electrically connected and can be collectively referred to as gate 1242. Gate 1242 and source / drain regions 1231 and 1232 form transistor T131. In some embodiments, gate structures 1220 to 1223 are electrically connected to the same voltage node. On the other hand, gate structures 1224 to 1229 are electrically connected and can be collectively referred to as gate 1244. Gate 1244 and source / drain regions 1232 and 1233 form transistor T132. In some embodiments, gate structures 1224 to 1229 are electrically connected to the same voltage node. From another perspective, gate 1242 of transistor T131 can be viewed as having several sections (e.g., gate structures 1220 to 1223) arranged along the X-direction, each section having spacers 106 disposed on opposite sidewalls thereof. As mentioned above, each gate structure 1220 to 1223 has a gate length LG1. Therefore, the effective gate length of the gate 1242 of the transistor T131 is 4*LG1. For example, if the gate length LG1 is about 5 nm, the effective gate length of the gate 1242 is about 20 nm. On the other hand, each of the gate structures 1224 to 1229 has a gate length LG1. Therefore, the effective gate length of the gate 1244 of the transistor T132 is 6*LG1. For example, if the gate length LG1 is about 5 nm, the effective gate length of the gate 1244 is about 30 nm. Therefore, in Figures 12A to 12C In the embodiment of FIG1 , the transistor T131 has three semiconductor fins 1211 , 1212 , and 1213 , and the gate 1242 of the transistor T131 has four portions (e.g., gate structures 1220 to 1223 ). On the other hand, the transistor T132 has five semiconductor fins 1211 , 1212 , 1213 , 1214 , and 1215 , and the gate 1244 of the transistor T132 has six portions (e.g., gate structures 1224 to 1229 ).

[0120] Figure 13100 is a schematic diagram of an electronic design automation (EDA) system 1300, according to some embodiments. According to one or more embodiments, the methods described herein for generating design layouts (e.g., layout drawings of integrated circuits 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 100H) can be implemented, for example, using EDA system 1300, according to some embodiments. In some embodiments, EDA system 1300 is a general-purpose computing device that includes a hardware processor 1302 and a non-volatile computer-readable storage medium 1304. Among other uses, computer-readable storage medium 1304 encodes (i.e., stores) an executable instruction set 1306, design layouts 1307, design rule checking (DRC) platforms 1309, or any intermediate data used to execute the instruction set. Each design layout 1307 includes a graphical representation of an integrated chip (e.g., integrated circuits 100A-100H), such as a GSII file. Each DRC platform 1309 includes a set of design rules specific to the semiconductor process selected for manufacturing the design layout 1307. Execution of instructions 1306 , design layout 1307 , and DRC platform 1309 by hardware processor 1302 represents, at least in part, an EDA tool that implements, for example, part or all of the methods described herein according to one or more (hereinafter, processes and / or methods).

[0121] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically coupled to input / output (I / O) interface 1310 via bus 1308. Network interface 1312 is also electrically coupled to processor 1302 via bus 1308. Network interface 1312 is coupled to network 1314, thereby enabling processor 1302 and computer-readable storage medium 1304 to connect to external components via network 1314. Processor 1302 is configured to execute instructions 1306 encoded in computer-readable storage medium 1304 to enable EDA system 1300 to perform layout design operations. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0122] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical fiber, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1304 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0123] In one or more embodiments, the computer-readable storage medium 1304 stores instructions 1306, a design layout (e.g., the layout of the integrated circuits 100A-100H discussed previously), and a DRC platform 1309 configured to enable an EDA system 1300 (where such execution (at least in part) represents an EDA tool) to perform part or all of the described processes and / or methods.

[0124] EDA system 1300 includes an I / O interface 1310. I / O interface 1310 is electrically connected to external circuitry. In one or more embodiments, I / O interface 1310 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor keys for transmitting information and commands to processor 1302.

[0125] EDA system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 allows EDA system 1300 to communicate with a network 1314 connected to one or more other computer systems. Network interface 1312 may include a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface, such as Ethernet. In one or more embodiments, some or all of the processes and / or methods described are performed on two or more EDA systems 1300.

[0126] EDA system 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1302. The information is transferred to processor 1302 via bus 1308. EDA system 1300 is configured to receive information related to user interface (UI) 13113 via I / O interface 1310. The information is stored in computer-readable medium 1304 as UI 1316.

[0127] In some embodiments, a layout diagram including standard cells is obtained by using a computer program such as that available from CADENCE DESIGN SYSTEMS, Inc. Or another suitable layout generation tool.

[0128] In some embodiments, these processes are implemented as program functions stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more optical disks such as DVDs, magnetic disks such as hard disks, and semiconductor memories such as ROMs, RAMs, and memory cards.

[0129] Figure 13 Also shown is a mask room 1330 that receives a verified layout generated from the EDA system 1300 via, for example, a network 1314. The mask room 1330 has a mask fabrication tool 1332 (e.g., a mask writer) for fabricating one or more photomasks (e.g., photomasks for fabricating, for example, ICs 100A-100H) based on the verified layout generated from the EDA system 1300. An IC fabricator ("Fab") 1320 can be connected to the mask room 1330 and the EDA system 1300 via, for example, the network 1314. The Fab 1320 includes IC fabrication tools 1322 for fabricating IC chips (e.g., ICs 100A-100H) using the photomasks fabricated by the mask room 1330. By way of example and not limitation, the IC fabrication tools 1322 can be cluster tools for fabricating IC chips. The cluster tool can be a multi-chamber type composite device, which includes a polyhedral transfer chamber at the center of which a wafer processing robot is inserted, multiple processing chambers (for example, CVD chambers, PVD chambers, etching chambers, annealing chambers, etc.) positioned at each wall of the polyhedron transfer chamber; and locking loading chambers installed at different walls of the transfer chamber.

[0130] In some embodiments, two or more of EDA system 1300, mask room 1330, and FAB 1320 are owned by a single company. For example, two or more of EDA system 1300, mask room 1330, and FAB 1320 coexist in a common facility and use common resources. In some other embodiments, EDA system 1300 is owned by a design house that is a separate entity from mask room 1330 and FAB 1320. In such embodiments, mask room 1330, FAB 1320, and the design house that owns EDA system 1300 each interact with one or more of the other entities and provide services to and / or receive services from one or more of the other entities.

[0131] The integrated circuit structures discussed above are examples of layout styles that describe long-channel device layout patterns suitable for advanced technology nodes. The concepts described above can also be integrated into other semiconductor devices, such as gate-all-around (GAA) FETs and / or nanowire FETs, and can be implemented in multiple technology nodes, such as the 10nm, 7nm, 5nm, and 3nm technology nodes.

[0132] Based on the above discussion, it can be seen that the present invention provides advantages. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages herein and no particular advantage is required for all embodiments. One advantage is that the gate of the long channel transistor can be divided into several sections arranged on one or more active areas. Each of the sections can include a gate length equal to the critical dimension of the corresponding technology node or can be several times the critical dimension. On the other hand, each of the sections can include a different threshold voltage. This allows for more flexible circuit layout design.

[0133] In some embodiments of the present invention, an integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a longitudinal direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along a first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length being n times the first effective gate length, and n being a positive integer greater than 1.

[0134] In some embodiments of the present invention, an IC structure includes a first transistor and a second transistor. The first transistor includes a first active area, a first gate, a plurality of gate spacers, a first source / drain region, and a second source / drain region. The first active area and the second active area are separated by an isolation structure and extend along a first direction. The first gate has a plurality of gate structures disposed on the first active area and the second active area, respectively, wherein, along the first direction, the effective gate length of the gate is n times the critical dimension of the technology node of the first transistor, and n is a positive integer and greater than 1. The gate spacers are disposed near each of the gate structures of the first gate. The first source / drain region is in the first active area. The second source / drain region is in the second active area. The second transistor has a gate length substantially equal to the critical dimension of the technology node of the first transistor.

[0135] In some embodiments of the present invention, a first active region and a second active region are formed above a substrate and extend along a first direction, wherein the first active region and the second active region are separated by an isolation structure; a first gate structure is formed above the first active region; a plurality of second gate structures are formed above the second active region, wherein, along the first direction, the sum of the gate lengths of the second gate structures is n times the gate length of the first gate structure, and n is a positive integer and greater than 1; a first source / drain region is formed in the first active region; and a second source / drain region is formed in the second active region, wherein a dopant concentration of a portion of the second active region located between two adjacent second gate structures is lower than a dopant concentration of the second source / drain region.

[0136] According to an embodiment of the present application, an integrated circuit (IC) structure is provided, comprising: a first transistor comprising: a first active region; and a first gate disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to the longitudinal direction of the first active region; and a second transistor comprising: a second active region; and a second gate disposed on the second active region, and the second transistor includes a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1. In some embodiments, the gate structures of the second gates are electrically connected to the same voltage node. In some embodiments, each of the gate structures has a gate length substantially the same as the first effective gate length, and wherein the number of gate structures is n. In some embodiments, the second transistor further includes a plurality of gate spacers adjacent to opposing sidewalls of each of the gate structures of the second gates. In some embodiments, the second transistor further comprises a plurality of source / drain regions in the second active region, the source / drain regions being respectively adjacent to the two outermost gate structures of the second gate, and a portion of the second active region located between the two outermost gate structures of the second gate having a lower dopant concentration than the dopant concentration of the source / drain regions. In some embodiments, the first group of gate structures of the second gate has a first gate length, the first gate length being m times the first effective gate length, and the second group of gate structures has a second gate length, the second gate length being o times the first effective gate length, where m and o are different positive integers. In some embodiments, wherein, along the first direction, the first group of gate structures is not located between two adjacent gate structures of the second group. In some embodiments, the first effective gate length is the minimum gate length in the IC structure. In some embodiments, the first active region comprises one or more semiconductor fins. In some embodiments, the second active region comprises one or more semiconductor fins.

[0137] According to another embodiment of the present application, an integrated circuit structure is provided, comprising: a first transistor, comprising: a first active region and a second active region separated by an isolation structure, wherein the first active region and the second active region extend along a first direction; a gate having a plurality of gate structures disposed on the first active region and the second active region, respectively, wherein, along the first direction, an effective gate length of the gate is n times the critical dimension of a technology node of the first transistor, and n is a positive integer and greater than 1; a plurality of gate spacers adjacent to each of the gate structures of the gate; and a first source / drain region located in the first active region; and a second source / drain region located in the second active region; and a second transistor having a gate length substantially equal to the critical dimension of the technology node of the first transistor. In some embodiments, the gate structure of the first transistor has a gate length substantially the same as the critical dimension of the technology node of the first transistor. In some embodiments, at least two gate structures of the gate structure of the first transistor have different threshold voltages. In some embodiments, the first group of gate structures has a first gate length, the first gate length being m times the critical dimension of the technology node of the first transistor, and the second group of gate structures has a second gate length, and the second gate length being o times the critical dimension of the technology node of the first transistor, wherein m and o are different positive integers. In some embodiments, the number of gate structures in the first group is different from the number of gate structures in the second group. In some embodiments, the integrated circuit structure further comprises: a first contact disposed on the first active region, wherein the first contact is at a first side of the first active region and the first source / drain region is at a second side of the first active region opposite to the first side of the first active region; a second contact disposed on the second active region, wherein the second contact is at a first side of the second active region and the second source / drain region is at a second side of the second active region opposite to the first side of the second active region; and a metal line electrically connecting the first contact and the second contact.

[0138] According to another embodiment of the present application, a method for forming an integrated circuit structure is provided, comprising: forming a first active region and a second active region extending along a first direction over a substrate, wherein the first active region and the second active region are separated by an isolation structure; forming a first gate structure over the first active region; forming a plurality of second gate structures over the second active region, wherein the sum of the gate lengths of the second gate structures along the first direction is n times the gate length of the first gate structure, and n is a positive integer greater than 1; forming a first source / drain region in the first active region; and forming a second source / drain region in the second active region, wherein a portion of the second active region located between two adjacent second gate structures has a lower dopant concentration than a dopant concentration in the second source / drain region. In some embodiments, forming the second gate structures is performed such that each gate length of the second gate structures is substantially the same as the gate length of the first gate structure. In some embodiments, forming the second gate structures is performed such that the gate length of each of the first set of second gate structures is m times the gate length of the first gate structure, and the gate length of each of the second set of second gate structures is o times the gate length of the first gate structure. In some embodiments, the method of forming an integrated circuit structure further includes forming gate spacers on opposite sidewalls of the second gate structure.

[0139] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit structure comprising: A first transistor comprising: a first active region; and a first gate disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a longitudinal direction of the first active region; and A second transistor comprising: a second active region; and a second gate disposed on the second active region, wherein the second transistor includes a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1; The multiple gate structures of the second gate are electrically connected to the same voltage node, the first group of the gate structures of the second gate have a first gate length, and the first gate length is m times the first effective gate length; the second group of the gate structures have a second gate length, and the second gate length is o times the first effective gate length, wherein m and o are different positive integers.

2. The integrated circuit structure according to claim 1, wherein: The gate structure includes a high-k gate dielectric material, a work function metal layer and a fill metal.

3. The integrated circuit structure according to claim 2, wherein: The filling metal includes copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN) or molybdenum nitride (MoN).

4. The integrated circuit structure according to claim 1, wherein: The second transistor also includes a plurality of gate spacers adjacent to opposing sidewalls of each of the gate structures of the second gate.

5. The integrated circuit structure according to claim 1, wherein: The second transistor also includes a plurality of source / drain regions in the second active region, the source / drain regions being respectively adjacent to the two outermost portions of the gate structure of the second gate, and a dopant concentration of a portion of the second active region located between the two outermost portions in the gate structure of the second gate being lower than a dopant concentration of the source / drain regions.

6. The integrated circuit structure according to claim 1, wherein: The first active region and the second active region are separated by an isolation structure, and the isolation structure includes silicon dioxide, silicon nitride or silicon oxynitride.

7. The integrated circuit structure according to claim 1, wherein: Along the first direction, the first group of gate structures is not located between two adjacent gate structures of the second group.

8. The integrated circuit structure according to claim 1, wherein: The first effective gate length is a minimum gate length in the integrated circuit structure.

9. The integrated circuit structure according to claim 1, wherein: The first active region includes one or more semiconductor fins.

10. The integrated circuit structure according to claim 1, wherein: The second active region includes one or more semiconductor fins.

11. An integrated circuit structure comprising: A first transistor comprising: A first active region and a second active region are separated by an isolation structure, wherein the first active region and the second active region extend along a first direction; a gate having a plurality of gate structures disposed on the first active region and the second active region, wherein an effective gate length of the gate along the first direction is n times a critical dimension of a technology node of the first transistor, and n is a positive integer and greater than 1; a plurality of gate spacers adjacent to each of the gate structures of the gate; and a first source / drain region located in the first active region; and a second source / drain region located in the second active region; and a second transistor having a gate length substantially equal to the critical dimension of the technology node of the first transistor; The multiple gate structures of the first transistor are electrically connected to the same voltage node, the first group of gate structures have a first gate length, and the first gate length is m times the critical dimension of the technology node of the first transistor; the second group of gate structures have a second gate length, and the second gate length is o times the critical dimension of the technology node of the first transistor, wherein m and o are different positive integers.

12. The integrated circuit structure according to claim 11, wherein: The gate structure of the first transistor has a gate length that is substantially the same as the critical dimension of the technology node of the first transistor.

13. The integrated circuit structure according to claim 12, wherein: At least two gate structures of the gate structures of the first transistor have different threshold voltages.

14. The integrated circuit structure according to claim 11, wherein: The m is 2, and the o is 3.

15. The integrated circuit structure according to claim 11, wherein: The number of the first group of gate structures is different from the number of the second group of gate structures.

16. The integrated circuit structure according to claim 11, further comprising: a first contact disposed on the first active region, wherein the first contact is at a first side of the first active region and the first source / drain region is at a second side of the first active region opposite the first side of the first active region; a second contact disposed on the second active region, wherein the second contact is at a first side of the second active region and the second source / drain region is at a second side of the second active region opposite the first side of the second active region; and A metal wire electrically connects the first contact and the second contact.

17. A method of forming an integrated circuit structure, comprising: forming a first active region and a second active region extending along a first direction over a substrate, wherein the first active region and the second active region are separated by an isolation structure; forming a first gate structure over the first active region; forming a plurality of second gate structures above the second active region, wherein, along the first direction, a sum of gate lengths of the second gate structures is n times the gate length of the first gate structure, and n is a positive integer and greater than 1; forming a first source / drain region in the first active region; and forming a second source / drain region in the second active region, wherein a dopant concentration of a portion of the second active region located between two adjacent second gate structures is lower than a dopant concentration of the second source / drain region; Wherein, the multiple second gate structures are electrically connected to the same voltage node, and the second gate structures are formed so that the gate length of the first group of the second gate structures is each m times the gate length of the first gate structure, and the gate length of the second group of the second gate structures is each o times the gate length of the first gate structure, wherein m and o are different positive integers.

18. The method according to claim 17, wherein Both m and o are positive integers greater than 1.

19. The method according to claim 17, wherein: The m is 3, and the o is 2.

20. The method of claim 17, further comprising forming gate spacers on opposite sidewalls of the second gate structure.

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