Memory and manufacturing method thereof

Abstract

The present invention provides a memory and a method for manufacturing the memory. Bitline trenches are formed by patterning a dielectric layer on a substrate, and then a bitline spacer and a bitline structure are formed within the bitline trenches. Compared to existing technologies, the present invention forms the bitline trenches first and then the bitline structure, eliminating the steps of forming a bitline contact window and then forming a bitline contact plug within the bitline contact window. This prevents conductive material from remaining at the bottom of the bitline contact window when etching to form the bitline contact plug, thus avoiding device leakage current issues and improving device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory and a manufacturing method thereof. Background Art

[0002] A memory, such as a dynamic random access memory (DRAM), typically has a memory cell array comprising a plurality of memory cells arranged in an array. The memory also has a plurality of bit line structures, each of which is electrically connected to a corresponding memory cell. The memory also includes a storage capacitor for storing charge representing stored information. The memory cell can be electrically connected to the storage capacitor via a node contact structure, thereby implementing the storage function of each memory cell.

[0003] As far as existing memories are concerned, there are still problems with the difficulty of manufacturing and the complicated preparation process. For example, when preparing a bit line contact plug embedded in a substrate, a bit line contact window is usually formed in the substrate first, and then a conductive material (such as polysilicon) is filled in the bit line contact window. Finally, an etching process is used to remove part of the conductive material in the bit line contact window to form a bit line contact plug. However, when etching to remove the conductive material in the bit line contact window, there is often a problem of incomplete etching, and conductive material remains at the bottom of the bit line contact window, which can easily cause device leakage current problems. Moreover, the bit line contact window formed by etching first has an abnormal morphology of the node contact window due to the residual conductive material (such as polysilicon), which affects the quality of the node contact portion finally formed and affects the stability of the semiconductor device. Summary of the Invention

[0004] The object of the present invention is to provide a memory and a manufacturing method thereof, so as to reduce device leakage current and improve device performance.

[0005] To achieve the above object, the present invention provides a memory, comprising:

[0006] A substrate comprising a plurality of active regions and an isolation structure surrounding the plurality of active regions;

[0007] a plurality of bit line structures located on the substrate and in direct contact with the active area;

[0008] The sidewall spacer at least covers the sidewall of the bit line structure and extends into the isolation structure along a portion of the sidewall of the bit line structure.

[0009] Optionally, the bit line structure includes a bit line contact plug, a bit line conductive layer, and a bit line shielding layer stacked in sequence, wherein a size of a top portion of the bit line conductive layer is larger than a size of a bottom portion of the bit line conductive layer.

[0010] Optionally, the bit line structure includes a U-shaped diffusion barrier layer, a conductive layer filled in the diffusion barrier layer, and a shielding pattern located above the diffusion barrier layer and the conductive layer.

[0011] Optionally, the diffusion barrier layer is in direct contact with the active region.

[0012] Optionally, the bottom and sidewalls of the diffusion barrier layer are in contact with the sidewall spacer.

[0013] Optionally, a liner layer is further included, and the liner layer is located between the bit line structure and the substrate.

[0014] Optionally, the diffusion barrier layer contacts the liner layer.

[0015] Optionally, the sidewall spacer layer includes a first spacer layer and a second spacer layer, wherein:

[0016] The second spacer layer covers the sidewall of the bit line structure and extends into the isolation structure along a portion of the sidewall of the bit line structure;

[0017] The first spacer layer covers a sidewall of the second spacer layer on the substrate.

[0018] Optionally, the sidewall spacer layer includes a first spacer layer and a second spacer layer, wherein:

[0019] The first spacer layer and the second spacer layer both extend deep into the isolation structure along a portion of the bit line structure, wherein the first spacer layer is in an "L" shape, and the second spacer layer is located above a horizontal end of the "L" shape.

[0020] Optionally, the sidewall spacer layer includes a first spacer layer, a second spacer layer and a third spacer layer, and the first spacer layer and the second spacer layer are both located on the substrate.

[0021] Among them, the first spacer layer is "L"-shaped, the second spacer layer is located above the horizontal end of the "L" shape, the third spacer layer contacts the side wall of the second spacer layer and the horizontal end of the "L" shape of the first spacer layer, and penetrates into the isolation structure along part of the side wall of the bit line structure.

[0022] Optionally, at least a portion of the sidewall spacer is arranged in a “U” shape to isolate the bit line structure from the bottom.

[0023] Accordingly, the present invention also provides a method for manufacturing a memory, comprising:

[0024] Providing a substrate comprising a plurality of active regions and an isolation structure surrounding the plurality of active regions;

[0025] forming a dielectric layer on the substrate and patterning the dielectric layer to form a plurality of bit line trenches, wherein at least a portion of the bit line trenches extends deep into the substrate;

[0026] forming a sidewall spacer on the sidewall of the bit line trench; and,

[0027] A bit line structure is formed in the bit line trench, wherein the sidewall spacer at least covers the sidewall of the bit line structure and extends into the isolation structure along a portion of the sidewall of the bit line structure.

[0028] Optionally, the sidewall spacer layer includes a first spacer layer and a second spacer layer, and the process of forming the sidewall spacer layer includes:

[0029] forming a first spacer layer and a second spacer layer in sequence along the sidewall and bottom of the bit line trench; and,

[0030] Partially etching bottoms of the first spacer layer and the second spacer layer to expose a portion of the active area.

[0031] Optionally, the sidewall spacer includes a first spacer and a second spacer, and the process of forming the bit line trench and the sidewall spacer includes:

[0032] patterning the dielectric layer to form an opening exposing the substrate;

[0033] forming a first spacer layer on the sidewalls and bottom of the opening;

[0034] Etching a portion of the bottom of the first spacer layer and the substrate downward along the opening to expose at least a portion of the isolation structure to form the bit line trench; and

[0035] A second spacer layer is formed on the sidewalls of the bit line trench.

[0036] Optionally, the sidewall spacer includes a first spacer, a second spacer, and a third spacer, and the process of forming the bit line trench and the sidewall spacer includes:

[0037] patterning the dielectric layer to form an opening exposing the substrate;

[0038] forming a first spacer layer and a second spacer layer in sequence on the sidewall and bottom of the opening;

[0039] Etching the second spacer layer, the bottom of the first spacer layer, and the substrate downward along the opening to expose at least a portion of the isolation structure to form the bit line trench; and

[0040] A third spacer is formed along the sidewalls of the bit line trench.

[0041] Optionally, at least a portion of the sidewall spacer is arranged in a “U” shape to isolate the bit line structure from the bottom.

[0042] Optionally, the process of forming the bit line structure includes:

[0043] A bit line contact plug, a bit line conductive layer and a bit line shielding layer are sequentially stacked in the bit line trench.

[0044] Optionally, a size of a top portion of the bit line conductive layer is larger than a size of a bottom portion of the bit line conductive layer.

[0045] Optionally, the process of forming the bit line structure includes:

[0046] forming a U-shaped diffusion barrier layer along the sidewalls and bottom of the bit line trench;

[0047] filling the bit line trench to form a conductive layer on the diffusion barrier layer;

[0048] A shielding pattern is formed on the diffusion barrier layer and the conductive layer.

[0049] Optionally, also include:

[0050] removing the dielectric layer so that the adjacent bit line structure defines a storage contact window located on the active area;

[0051] A storage contact plug is formed in the storage contact window and the storage contact plug is in contact with the corresponding active region.

[0052] In summary, the memory and memory fabrication method provided by the present invention form bitline trenches by patterning a dielectric layer on a substrate, and then form a bitline spacer layer and a bitline structure within the bitline trenches. Compared to the prior art, the present invention forms the bitline trenches first and then the bitline structure, eliminating the steps of forming a bitline contact window and then forming a bitline contact plug in the bitline contact window. This prevents conductive material from remaining at the bottom of the bitline contact window when etching to form the bitline contact plug, thus avoiding device leakage current issues and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A flowchart of a method for manufacturing a memory provided in the first embodiment of the present invention;

[0054] Figure 2 A simplified diagram of a portion of the structure of the memory provided in the first embodiment of the present invention;

[0055] Figures 3A to 3D Schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a memory provided in the first embodiment of the present invention;

[0056] Figures 4A to 4F A schematic cross-sectional structural diagram corresponding to each step in the method for manufacturing a memory provided in the second embodiment of the present invention;

[0057] Figures 5A to 5I Schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a memory provided in the third embodiment of the present invention;

[0058] Figures 6A to 6G Schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a memory provided in the fourth embodiment of the present invention;

[0059] Figures 7A to 7F Schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a memory provided in the fifth embodiment of the present invention;

[0060] Figures 8A to 8G Schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a memory provided in Example 6 of the present invention;

[0061] Figures 9A to 9G This is a schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a memory provided in Example 7 of the present invention.

[0062] Wherein, the accompanying drawings are marked as follows:

[0063] 100-substrate; 110-isolation structure; 120-active region;

[0064] 101-pad layer; 101a-oxide layer; 101b-nitride layer

[0065] 102 - dielectric layer; 130 - bit line trench; 103 - opening;

[0066] 140 - side wall spacer; 141 - first spacer; 142 - second spacer; 143 - third spacer;

[0067] 150 - bit line structure; 151 - bit line contact plug; 152 - bit line conductive layer; 153 - bit line shielding layer; 154 - diffusion barrier layer; 155 - conductive layer; 156 - shielding pattern. DETAILED DESCRIPTION

[0068] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0069] Example 1

[0070] Figure 2 A simplified diagram of a partial structure of a memory provided in this embodiment, Figure 3D After forming the bit line structure, the memory follows Figure 1 The cross-sectional structure diagram in the aa′ direction is shown in FIG. Figure 2 and Figure 3D As shown, the memory includes a substrate 100, including a plurality of active areas (AA) 120 and an isolation structure (STI) 110 surrounding the plurality of active areas 120; a plurality of bit line structures (BL) 150, located on the substrate 100 and in direct contact with the active areas 120; and a sidewall spacer 140, covering at least the sidewalls of the bit line structures 150 and extending into the isolation structure 110 along a portion of the sidewalls of the bit line structures 150.

[0071] Specifically, a plurality of active areas (AA) 120 are formed in the substrate 100. Each active area 120 includes a first source / drain region S / D1 and a second source / drain region S / D2. In this embodiment, the active areas AA extend obliquely relative to a first direction (i.e., the active areas AA extend along the Z direction). Furthermore, in each active area AA, the first source / drain region S / D1 corresponds to the middle region of the active area AA, and the second source / drain region S / D2 is formed at both ends of the active area AA (i.e., the two second source / drain regions S / D2 are arranged on either side of the first source / drain region S / D1). The active areas AA are used to form memory cells of a memory device, such as memory transistors. Furthermore, the first source / drain region S / D1 and the second source / drain region S / D2 may constitute the drain and source regions of the memory transistor, with the first source / drain region S / D1 being electrically connected to the bit line structure BL, and the second source / drain region S / D2 being electrically connected to a storage capacitor.

[0072] A plurality of word lines WL are further formed in the substrate 100 . The word lines extend along the second direction (X direction) and intersect corresponding active areas AA. The first doped regions S / D1 and the second doped regions S / D2 are respectively disposed on both sides of the word lines WL.

[0073] A plurality of bit line structures (BL) 120 are formed on the substrate 100 and extend along a third direction (Y direction) to pass through corresponding active areas AA. Figure 3DAs shown, the bitline structure 150 includes a bitline contact plug 151, a bitline conductive layer 152, and a bitline shielding layer 153 stacked in sequence. The bitline contact plug 151 is made of, for example, doped polysilicon. The bitline conductive layer 152 is made of, for example, a first conductive layer and a second conductive layer. The first conductive layer is made of, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co). The second conductive layer is made of, for example, at least one of titanium nitride (TiN), titanium / titanium nitride (Ti / TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). The bitline shielding layer 153 is made of, for example, at least one of silicon nitride (SiN) or silicon oxynitride (SiON).

[0074] Furthermore, sidewall spacers 140 are formed on the sidewalls of the bitline structure 150. The sidewall spacers 140 cover the sidewalls of the sequentially stacked bitline contact plugs 151, bitline conductive layer 152, and bitline shielding layer 153. The side of the sidewall spacers 140 that is closest to the bitline structure 150 is curved, and the size of the sidewall spacers 140 decreases from the bitline contact plugs 151 toward the bitline shielding layer 153. That is, the size D2 of the top of the bitline conductive layer 151 is larger than the size D1 of the bottom of the bitline conductive layer 151.

[0075] The memory provided in this embodiment further includes a liner layer 101, which is located between the bit line structure 150 and the substrate 100. The liner layer 101 can be formed of one or more insulating film layers. For example, the liner layer 101 can be composed of at least one film layer selected from the group consisting of a silicon oxide layer (SiO2), a silicon nitride layer (SiN), or a silicon oxynitride layer (SiON). In this embodiment, the liner layer 101 is a double-layer structure consisting of an oxide layer 101a and a nitride layer 101b. The oxide layer 101a is, for example, a silicon oxide layer, and the nitride layer 101b is, for example, a silicon nitride layer or a silicon oxynitride layer.

[0076] Accordingly, this embodiment also provides a method for manufacturing a memory, such as Figure 1 As shown, the manufacturing method of the memory includes:

[0077] S01: providing a substrate 100 including a plurality of active regions 120 and an isolation structure 110 surrounding the plurality of active regions 120;

[0078] S02: forming a dielectric layer 102 on the substrate 100 and patterning the dielectric layer 102 to form a plurality of bit line trenches 130 , wherein the bit line trenches 130 at least partially penetrate into the substrate 100 ;

[0079] S03: forming a sidewall spacer 140 on the sidewall of the bit line trench 130; and

[0080] S04 : forming a bit line structure 150 in the bit line trench 130 , wherein the sidewall spacer 140 at least covers the sidewall of the bit line structure 150 and extends into the isolation structure 110 along a portion of the sidewall of the bit line structure 150 .

[0081] Figures 3A to 3D The cross-sectional structural diagram corresponding to each step in the manufacturing method of the memory provided in this embodiment is shown below in conjunction with Figure 1 、 Figure 2 and Figures 3A to 3D The manufacturing method of the memory provided in this embodiment is described in detail.

[0082] See also Figure 2 and Figure 3A As shown, step S01 is performed to provide a substrate 100, including a plurality of active areas 120 and an isolation structure 110 surrounding the plurality of active areas 120. The substrate 100 is, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, etc. An isolation structure (STI) 110 is formed in the substrate 100, and the isolation structure defines a plurality of active areas (AA) 120. The active areas AA are distributed in an array, and each active area AA includes two source / drain regions, a first doped region S / D1 and a second doped region S / D2. The manufacturing process of the isolation structure STI is, for example, to first form at least one isolation trench in the substrate 100 by etching, and then fill the isolation trench with an insulating material (such as silicon oxide or silicon oxynitride, etc.), but the present invention is not limited thereto.

[0083] A plurality of word lines WL are further formed in the substrate 100 , which extend along a second direction (X direction) and intersect corresponding active areas AA, and the first doped regions S / D1 and the second doped regions S / D2 in the active areas AA are respectively arranged on both sides of the word lines WL.

[0084] Next, see Figure 3A and Figure 3B As shown, step S02 is performed to form a dielectric layer 102 on the substrate 100 and pattern it to form a plurality of bit line trenches 130 . The bit line trenches 130 at least partially penetrate into the substrate 100 .

[0085] Specifically, first, a liner layer 101 and a dielectric layer 102 are sequentially formed on the substrate 100. The liner layer 101 can be formed of one or more insulating film layers. For example, the liner layer 101 can be composed of at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. In addition to silicon oxide, the material of the dielectric layer 102 includes, but is not limited to, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), polymers, silicon nitride (SiN), and the like. The thickness of the dielectric layer 102 is greater than the thickness of the subsequently formed bitline structure 150. Next, a patterned photoresist layer is formed on the dielectric layer 102. The dielectric layer 102, the liner layer 101, and a portion of the substrate 100 are etched using the patterned photoresist layer to form a plurality of bitline trenches 130. The bitline trenches 130 at least partially extend into the substrate 100.

[0086] Next, see Figure 3C and Figure 3DAs shown, steps S03 and S04 are performed to form a spacer layer 140 on the sidewalls of the bitline trench 130, and to form a bitline structure 150 in the bitline trench 130. The spacer layer 140 at least covers the sidewalls of the bitline structure 150 and extends along a portion of the sidewalls of the bitline structure 150 into the isolation structure 110. First, the spacer layer 140 is formed along the sidewalls of the bitline trench 130. The side of the spacer layer 140 away from the sidewalls of the bitline trench 130 is curved, and its size decreases from the substrate 100 toward the dielectric layer 102. The spacer layer 140 may include a combination of any one or more suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric. Next, the bitline trench 130 is filled with a first conductive material, such as doped polysilicon, and an etch-back process is performed to form a bitline contact plug 151. Then, the bitline trench 130 is filled with a second conductive material, and an etch-back process is performed to form a bitline conductive layer 152. The bitline conductive layer 152 may include, for example, a stacked first conductive layer and a second conductive layer. The first conductive layer may be made of at least one of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co), and the second conductive layer may be made of at least one of titanium nitride (TiN), titanium / titanium nitride (Ti / TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). Next, the bitline trench 130 is filled with an insulating material, such as a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer, and a planarization process is performed to form a bitline shielding layer 153 on the bitline conductive layer 152. Since the sidewall spacer 140 is arc-shaped away from the sidewall of the bit line trench 130, the sidewall of the bit line structure 150 formed in the bit line trench 130 is covered by the sidewall spacer 140. Accordingly, the size D2 of the top of the bit line conductive layer 151 is larger than the size D1 of the bottom of the bit line conductive layer 151.

[0087] It should be noted that, after forming the bit line structure, the method for manufacturing the memory provided in this embodiment further includes: removing the dielectric layer 102 so that the adjacent bit line structure 150 defines a storage contact window located on the active area; forming a storage contact plug in the storage contact window and contacting the storage contact plug with the corresponding active area.

[0088] The memory and memory fabrication method provided in this embodiment form bitline trenches by patterning a dielectric layer on a substrate, and then form a bitline spacer layer and a bitline structure within the bitline trenches. Compared to the prior art, this embodiment forms the bitline trenches first and then the bitline structure, eliminating the steps of forming a bitline contact window and then forming a bitline contact plug within the bitline contact window. This prevents conductive material from remaining at the bottom of the bitline contact window when etching to form the bitline contact plug, thus avoiding device leakage current issues and improving device performance.

[0089] Example 2

[0090] This embodiment provides a memory and a method for manufacturing the same. Figure 4F After forming the bit line structure, the memory follows Figure 1 The cross-sectional structure diagram in the aa′ direction is shown in FIG. Figure 4F As shown, the memory includes a substrate 100, including a plurality of active areas (AA) 120 and an isolation structure (STI) 110 surrounding the plurality of active areas 120; a plurality of bit line structures (BL) 150, located on the substrate 100 and in direct contact with the active areas 120; and a sidewall spacer 140, covering at least the sidewalls of the bit line structures 150 and extending into the isolation structure 110 along a portion of the sidewalls of the bit line structures 150.

[0091] The difference between the memory provided in this embodiment and that in the first embodiment is that the specific structures of the bit line structure 150 and the sidewall spacer 140 are different. In this embodiment, the bit line structure 150 includes a diffusion barrier layer 154 arranged in a "U" shape, a conductive layer 155 filled in the diffusion barrier layer 154, and a shielding pattern 156 located above the diffusion barrier layer 154 and the conductive layer 155; the sidewall spacer 140 includes a first spacer 141 and a second spacer 142, wherein the first spacer 141 is in an "L" shape, and the second spacer 142 covers the sidewalls of the bit line structure 150 and is located above the horizontal end of the "L" shape. In this embodiment, in the bit line structure 150, the bottom and sidewalls of the diffusion barrier layer 154 are in contact with the sidewall spacer 140, and the diffusion barrier layer 151 is in direct contact with the active area 120. As Figure 4F As shown, the bottom of the diffusion barrier layer 154 contacts the horizontal end of the “L” shape of the first spacer layer 141 , and the sidewall of the diffusion barrier layer 154 contacts the second spacer layer 142 .

[0092] Accordingly, this embodiment also provides a method for manufacturing a memory. Figures 4A to 4FThis is a schematic diagram of the cross-sectional structure corresponding to each step in the memory manufacturing method provided in this embodiment. The memory manufacturing method provided in this embodiment also includes steps S01 to S04, the difference being that the manufacturing methods of the sidewall spacer 140 and the bit line structure 150 are different.

[0093] Specifically, first, see Figure 4A As shown, step S01 is performed to provide a substrate 100, which includes a plurality of active areas 120 and an isolation structure 110 surrounding the plurality of active areas 120. An isolation structure (STI) 110 is formed in the substrate 100, and the isolation structure defines a plurality of active areas (AA) 120. The active areas AA are distributed in an array.

[0094] Next, see Figure 4A and Figure 4B As shown, step S02 is performed to form a dielectric layer 102 on the substrate 100 and pattern it to form a plurality of bitline trenches 130, wherein the bitline trenches 130 at least partially extend into the substrate 100. Specifically, a liner layer 101 and a dielectric layer 102 are sequentially formed on the substrate 100. The thickness of the dielectric layer 102 is used to define the thickness of the subsequently formed bitline structure 150. Preferably, the thickness of the dielectric layer 102 formed in this step is greater than the thickness of the subsequently formed bitline structure 150. Next, a patterned photoresist layer is formed on the dielectric layer 102. The dielectric layer 102, the liner layer 101, and a portion of the substrate 100 are etched using the patterned photoresist layer to form a plurality of bitline trenches 130, wherein the bitline trenches 130 at least partially extend into the substrate 100.

[0095] Next, see Figure 4C and Figure 4D As shown, step S03 is performed to form sidewall spacers 140 on the sidewalls of the bit line trench 130. First, a first spacer 141 and a second spacer 142 are sequentially formed along the sidewalls and bottom of the bit line trench 130. Then, the bottoms of the first spacer 141 and the second spacer 142 are partially etched to expose a portion of the active area 120. The first spacer 141 is, for example, a silicon nitride layer, and the second spacer 142 is, for example, a silicon oxide layer.

[0096] Next, see Figure 4E and Figure 4FAs shown, step S04 is performed to form a bit line structure 150 in the bit line trench 130. First, a "U"-shaped diffusion barrier layer 154 is formed along the sidewalls and bottom of the bit line trench 130. Then, the bit line trench 130 is filled and a conductive layer 155 is formed on the diffusion barrier layer 154. Parts of the diffusion barrier layer and the conductive layer 155 are etched back, and a shielding pattern 156 is formed on the diffusion barrier layer 154 and the conductive layer 155. In the formed bit line structure 150, the bottom and sidewalls of the diffusion barrier layer 154 are in contact with the sidewall spacer 140, and the diffusion barrier layer 151 is in direct contact with the active area 120. Figure 4F As shown, the bottom of the diffusion barrier layer 154 contacts the horizontal end of the “L” shape of the first spacer layer 141 , and the sidewall of the diffusion barrier layer 154 contacts the second spacer layer 142 .

[0097] The material of the diffusion barrier layer 154 may include titanium nitride (TiN), aluminum-doped titanium carbide (TiAlC) or a combination thereof, the material of the conductive layer 155 may include but is not limited to tungsten, cobalt, nickel, copper, aluminum and polysilicon, and the material of the shielding pattern 156 may include, for example, at least one of silicon nitride (SiN) or silicon oxynitride (SiON).

[0098] It should be noted that the manufacturing method of the memory provided in this embodiment further includes, after forming the bit line structure 150: removing the dielectric layer 102 so that the adjacent bit line structure 150 defines a storage contact window located on the active area; forming a storage contact plug in the storage contact window and contacting the storage contact plug with the corresponding active area.

[0099] Example 3

[0100] This embodiment provides a memory and a method for manufacturing the same. Figure 5H After forming the bit line structure, the memory follows Figure 1 The cross-sectional structure diagram in the aa′ direction is shown in FIG. Figure 5H As shown, the memory includes a substrate 100, including a plurality of active areas (AA) 120 and an isolation structure (STI) 110 surrounding the plurality of active areas 120; a plurality of bit line structures (BL) 150, located on the substrate 100 and in direct contact with the active areas 120; and a sidewall spacer 140, covering at least the sidewalls of the bit line structures 150 and extending into the isolation structure 110 along a portion of the sidewalls of the bit line structures 150.

[0101] The memory provided in this embodiment differs from that in the second embodiment in the specific structure of the spacer spacer 140. In this embodiment, the spacer spacer 140 includes a first spacer 141, a second spacer 142, and a third spacer 143. The first spacer 141 and the second spacer 142 are both located on the substrate 100. The first spacer 141 is L-shaped, the second spacer 142 is located above the horizontal end of the L-shape, and the third spacer 143 contacts the sidewalls of the second spacer 142 and the horizontal end of the L-shape of the first spacer 141, and extends along a portion of the sidewalls of the bitline structure 150 into the isolation structure 110.

[0102] Accordingly, this embodiment also provides a method for manufacturing a memory. Figures 5A to 5I This is a schematic cross-sectional structural diagram corresponding to each step in the memory manufacturing method provided in this embodiment. The memory manufacturing method provided in this embodiment also includes steps S01 to S04, the difference being that the manufacturing method of the sidewall spacer 140 is different.

[0103] Specifically, first, see Figure 5A As shown, step S01 is performed to provide a substrate 100, which includes a plurality of active areas 120 and an isolation structure 110 surrounding the plurality of active areas 120. An isolation structure (STI) 110 is formed in the substrate 100, and the isolation structure defines a plurality of active areas (AA) 120. The active areas AA are distributed in an array.

[0104] Next, see Figures 5A to 5G As shown, step S02 and step S03 are performed to form a dielectric layer 102 on the substrate 100 and pattern it to form a plurality of bit line trenches 130. The bit line trenches 130 at least partially penetrate the substrate 100, and sidewall spacers 140 are formed on the sidewalls of the bit line trenches 130. Specifically, first, a liner layer 101 and a dielectric layer 102 are sequentially formed on the substrate 100, as shown in FIG. Figure 5A Then, the dielectric layer 102 is patterned to form an opening 103 exposing the substrate 100, as shown. Figure 5B Then, a first spacer layer 141 and a second spacer layer 142 are sequentially formed on the sidewalls and bottom of the opening 103, as shown in FIG. Figures 5C to 5E Then, the second spacer layer 142, the bottom of the first spacer layer 141 and the substrate 100 are etched downward along the opening 103, exposing at least a portion of the isolation structure 110 to form the bit line trench 130, as shown Figure 5F and forming a third spacer layer 143 along the sidewalls of the bit line trench 130, as shown Figure 5GThe first spacer layer 141 is, for example, a silicon oxide layer, the second spacer layer 142 is, for example, a silicon nitride layer, and the first spacer layer 141 is, for example, a silicon oxide layer.

[0105] Next, see Figure 5H As shown, step S04 is performed to form a bit line structure 150 in the bit line trench 130. First, a "U"-shaped diffusion barrier layer 154 is formed along the sidewalls and bottom of the bit line trench 130. Then, the bit line trench 130 is filled, a conductive layer 155 is formed on the diffusion barrier layer 154, and a portion of the diffusion barrier layer and the conductive layer 155 are etched back. A masking pattern 156 is formed on the diffusion barrier layer 154 and the conductive layer 155. In the formed bit line structure 150, the bottom and sidewalls of the diffusion barrier layer 154 are in contact with the spacer 140, and the diffusion barrier layer 151 is in direct contact with the active area 120.

[0106] It should be noted that the manufacturing method of the memory provided in this embodiment further includes, after forming the bit line structure 150: removing the dielectric layer 102 so that the adjacent bit line structure 150 defines a storage contact window located on the active area; forming a storage contact plug in the storage contact window and contacting the storage contact plug with the corresponding active area.

[0107] In addition, in some other embodiments of the present invention, the liner layer on the substrate may also be omitted, such as Figure 5I As shown, spacer spacers 140 (first spacer layer 141 and second spacer layer 142) are used to isolate the bit line structure 150 from the substrate 100. The present invention isolates the bit line structure from the substrate through the spacer spacers 140, omitting the liner layer on the substrate in the prior art, reducing process steps and lowering costs.

[0108] Example 4

[0109] This embodiment provides a memory and a method for manufacturing the same. Figure 6F After forming the bit line structure, the memory follows Figure 1 The cross-sectional structure diagram in the aa′ direction is shown in FIG. Figure 6F As shown, the memory includes a substrate 100, including a plurality of active areas (AA) 120 and an isolation structure (STI) 110 surrounding the plurality of active areas 120; a plurality of bit line structures (BL) 150, located on the substrate 100 and in direct contact with the active areas 120; and a sidewall spacer 140, covering at least the sidewalls of the bit line structures 150 and extending into the isolation structure 110 along a portion of the sidewalls of the bit line structures 150.

[0110] The memory provided in this embodiment differs from that in the second embodiment in the specific structure of the spacer spacer 140. In this embodiment, the spacer spacer 140 includes a first spacer 141 and a second spacer 142. The second spacer 142 covers the sidewalls of the bitline structure 150 and extends along a portion of the sidewalls of the bitline structure 150 into the isolation structure 110. The first spacer 141 covers the sidewalls of the second spacer 142 located on the substrate 100.

[0111] Figures 6A to 6G This is a schematic cross-sectional structural diagram corresponding to each step of the memory manufacturing method provided in this embodiment. The memory manufacturing method provided in this embodiment also includes steps S01 to S04, the difference being that the manufacturing method of the sidewall spacer 140 is different.

[0112] Specifically, first, see Figure 6A As shown, step S01 is performed to provide a substrate 100, which includes a plurality of active areas 120 and an isolation structure 110 surrounding the plurality of active areas 120. An isolation structure (STI) 110 is formed in the substrate 100, and the isolation structure defines a plurality of active areas (AA) 120. The active areas AA are distributed in an array.

[0113] Next, see Figures 6A to 6E As shown, step S02 and step S03 are performed to form a dielectric layer 102 on the substrate 100 and pattern it to form a plurality of bit line trenches 130. The bit line trenches 130 at least partially penetrate the substrate 100, and sidewall spacers 140 are formed on the sidewalls of the bit line trenches 130. Specifically, first, a liner layer 101 and a dielectric layer 102 are sequentially formed on the substrate 100, as shown in FIG. Figure 6A Then, the dielectric layer 102 is patterned to form an opening 103 exposing the substrate 100, as shown. Figure 6B Then, a first spacer layer 141 is sequentially formed on the sidewalls and bottom of the opening 103, as shown in FIG. Figure 6C Then, the bottom of the first spacer layer 141 and the substrate 100 are etched downward along the opening 103, exposing at least a portion of the isolation structure 110 to form the bit line trench 130, as shown. Figure 6D and forming a second spacer layer 142 on the sidewalls of the bit line trench 130, as shown Figure 6E The first spacer layer 141 is, for example, a silicon nitride layer, or a silicon oxide layer.

[0114] Next, see Figure 6FAs shown, step S04 is performed to form a bit line structure 150 in the bit line trench 130. First, a "U"-shaped diffusion barrier layer 154 is formed along the sidewalls and bottom of the bit line trench 130. Then, the bit line trench 130 is filled, a conductive layer 155 is formed on the diffusion barrier layer 154, and a portion of the diffusion barrier layer and the conductive layer 155 are etched back. A masking pattern 156 is formed on the diffusion barrier layer 154 and the conductive layer 155. In the formed bit line structure 150, the bottom and sidewalls of the diffusion barrier layer 154 are in contact with the first spacer layer 141, and the diffusion barrier layer 154 is in direct contact with the active area 120.

[0115] In addition, in some other embodiments of the present invention, the liner layer on the substrate may also be omitted, such as Figure 6G As shown, a sidewall spacer 140 (first spacer 141 ) is used to isolate the bit line structure 150 from the substrate 100 .

[0116] Example 5

[0117] This embodiment provides a memory and a method for manufacturing the same. Figure 7E After forming the bit line structure, the memory follows Figure 1 The cross-sectional structure diagram in the aa′ direction is shown in FIG. Figure 7E As shown, the memory includes a substrate 100, including a plurality of active areas (AA) 120 and an isolation structure (STI) 110 surrounding the plurality of active areas 120; a plurality of bit line structures (BL) 150, located on the substrate 100 and in direct contact with the active areas 120; and a sidewall spacer 140, covering at least the sidewalls of the bit line structures 150 and extending into the isolation structure 110 along a portion of the sidewalls of the bit line structures 150.

[0118] The memory provided in this embodiment differs from that in the first embodiment in that the specific structures of the spacer spacer 140 and the bit line structure 150 are different. In this embodiment, the bit line structure 150 includes a diffusion barrier layer 154 in a "U" shape, a conductive layer 155 filled in the diffusion barrier layer 154, and a shielding pattern 156 located above the diffusion barrier layer 154 and the conductive layer 155. At least a portion of the spacer spacer 140 is in a "U" shape to isolate the bit line structure 150 from the bottom. Figure 7EAs shown, the sidewall spacers 140 extend deep into the isolation structure 110 along the sidewalls of the bit line structure 150. For the bit line structure 150 located between adjacent isolation structures 110, the sidewall spacers 140 cover the sidewalls of the bit line structure 150. For the bit line structure 150 located on the isolation structure 110, the sidewall spacers 140 are in a "U" shape and cover the sidewalls and bottom of the bit line structure 150, so as to isolate the bit line structure 150 and the isolation structure 110 from the bottom.

[0119] Figures 7A to 7F This is a schematic diagram of the cross-sectional structure corresponding to each step in the memory manufacturing method provided in this embodiment. The memory manufacturing method provided in this embodiment also includes steps S01 to S04. The difference from the first embodiment lies in the different manufacturing methods of the sidewall spacer layer 140 and the bit line structure 150.

[0120] Specifically, first, see Figure 7A As shown, step S01 is performed to provide a substrate 100, which includes a plurality of active areas 120 and an isolation structure 110 surrounding the plurality of active areas 120. An isolation structure (STI) 110 is formed in the substrate 100, and the isolation structure defines a plurality of active areas (AA) 120. The active areas AA are distributed in an array.

[0121] Next, see 7A to 7D As shown, step S02 and step S03 are performed to form a dielectric layer 102 on the substrate 100 and pattern it to form a plurality of bit line trenches 130. The bit line trenches 130 at least partially penetrate the substrate 100, and sidewall spacers 140 are formed on the sidewalls of the bit line trenches 130. Specifically, first, a liner layer 101 and a dielectric layer 102 are sequentially formed on the substrate 100, as shown in FIG. Figure 7A Then, the dielectric layer 102 is patterned to form a bit line trench 130 exposing the active area 120 and the isolation structure 110, as shown Figure 7B Then, a sidewall spacer 140 is formed in sequence on the sidewalls and bottom of the bit line trench 130, as shown in FIG. Figure 7C Then, for the isolation trench 130 formed between adjacent isolation structures 110, the bottom of the sidewall spacer 140 is etched to expose a portion of the isolation structure 110, as shown Figure 7D shown.

[0122] Next, see Figure 7EAs shown, step S04 is performed to form a bitline structure 150 in the bitline trench 130. First, a "U"-shaped diffusion barrier layer 154 is formed along the sidewalls and bottom of the bitline trench 130. Next, a conductive layer 155 is formed on the diffusion barrier layer 154 to fill the bitline trench 130. The diffusion barrier layer and the conductive layer 155 are partially etched back, and a masking pattern 156 is formed on the diffusion barrier layer 154 and the conductive layer 155. The bottom and sidewalls of the diffusion barrier layer 154 in the bitline structure 150 formed between adjacent isolation structures 110 are in contact with the spacer 140 and directly in contact with the active area 120. The bottom of the diffusion barrier layer 154 in the bitline structure 150 formed above the isolation structure 110 is isolated from the isolation structure 110 by the spacer 140.

[0123] In addition, in some other embodiments of the present invention, the liner layer on the substrate may also be omitted, such as Figure 7F As shown, a sidewall spacer 140 is used to isolate the bit line structure 150 from the substrate 100 .

[0124] Example 6

[0125] This embodiment provides a memory and a method for manufacturing the same. Figure 8F After forming the bit line structure, the memory follows Figure 1 The cross-sectional structure diagram in the aa′ direction is shown in FIG. Figure 8F As shown, the memory includes a substrate 100, including a plurality of active areas (AA) 120 and an isolation structure (STI) 110 surrounding the plurality of active areas 120; a plurality of bit line structures (BL) 150, located on the substrate 100 and in direct contact with the active areas 120; and a sidewall spacer 140, covering at least the sidewalls of the bit line structures 150 and extending into the isolation structure 110 along a portion of the sidewalls of the bit line structures 150.

[0126] The memory provided in this embodiment differs from that in the fifth embodiment in that the specific structure of the sidewall spacer 140 is different. Figure 8F As shown, the sidewall spacer 140 includes a first spacer layer 141 and a second spacer layer 142, wherein the second spacer layer 142 is located on the sidewall of the bit line structure 150 and extends deep into the isolation structure 110 along the sidewall of the bit line structure 150, and the first spacer layer 141 is located on the substrate 100 and covers part of the sidewall of the second spacer layer 142.

[0127] Figures 8A to 8GThis is a schematic cross-sectional structural diagram corresponding to each step of the memory manufacturing method provided in this embodiment. The memory manufacturing method provided in this embodiment also includes steps S01 to S04. The difference from the fifth embodiment lies in the different manufacturing method of the sidewall spacer 140.

[0128] Specifically, first, see Figure 8A As shown, step S01 is performed to provide a substrate 100, which includes a plurality of active areas 120 and an isolation structure 110 surrounding the plurality of active areas 120. An isolation structure (STI) 110 is formed in the substrate 100, and the isolation structure defines a plurality of active areas (AA) 120. The active areas AA are distributed in an array.

[0129] Next, see Figures 8A to 8E As shown, step S02 and step S03 are performed to form a dielectric layer 102 on the substrate 100 and pattern it to form a plurality of bit line trenches 130. The bit line trenches 130 at least partially penetrate the substrate 100, and sidewall spacers 140 are formed on the sidewalls of the bit line trenches 130. Specifically, first, a liner layer 101 and a dielectric layer 102 are sequentially formed on the substrate 100, as shown in FIG. Figure 8A Then, the dielectric layer 102 is patterned to form an opening 103 exposing the substrate 100, as shown. Figure 8B Then, a first spacer layer 141 is sequentially formed on the sidewalls and bottom of the opening 103, as shown in FIG. Figure 8C Then, the bottom of the first spacer layer 141 and the substrate 100 are etched downward along the opening 103 to expose at least a portion of the isolation structure 110 to form the bit line trench 130, as shown. Figure 8D Then, a second spacer layer 142 is formed on the sidewalls and bottom of the bit line trench 130, and, for the isolation trench 130 formed between adjacent isolation structures 110, the bottom of the second spacer layer 142 is etched to expose a portion of the isolation structure 110, as shown. Figure 8E shown.

[0130] Next, see Figure 8FAs shown, step S04 is performed to form a bitline structure 150 in the bitline trench 130. First, a "U"-shaped diffusion barrier layer 154 is formed along the sidewalls and bottom of the bitline trench 130. Next, a conductive layer 155 is formed on the diffusion barrier layer 154 to fill the bitline trench 130. The diffusion barrier layer and the conductive layer 155 are partially etched back, and a masking pattern 156 is formed on the diffusion barrier layer 154 and the conductive layer 155. The bottom and sidewalls of the diffusion barrier layer 154 in the bitline structure 150 formed between adjacent isolation structures 110 are in contact with the second spacer layer 142 and directly in contact with the active area 120. The bottom of the diffusion barrier layer 154 in the bitline structure 150 formed above the isolation structure 110 is isolated from the isolation structure 110 by the second spacer layer 142.

[0131] In addition, in some other embodiments of the present invention, the liner layer on the substrate may also be omitted, such as Figure 8G As shown, a sidewall spacer 140 (second spacer 142 ) is used to isolate the bit line structure 150 from the substrate 100 .

[0132] Example 7

[0133] This embodiment provides a memory and a method for manufacturing the same. Figure 9F After forming the bit line structure, the memory follows Figure 1 The cross-sectional structure diagram in the aa′ direction is shown in FIG. Figure 9F As shown, the memory includes a substrate 100, including a plurality of active areas (AA) 120 and an isolation structure (STI) 110 surrounding the plurality of active areas 120; a plurality of bit line structures (BL) 150, located on the substrate 100 and in direct contact with the active areas 120; and a sidewall spacer 140, covering at least the sidewalls of the bit line structures 150 and extending into the isolation structure 110 along a portion of the sidewalls of the bit line structures 150.

[0134] The memory provided in this embodiment differs from that in the sixth embodiment in that the specific structure of the sidewall spacer 140 is different. Figure 9FAs shown, the spacer layer 140 includes a first spacer layer 141 and a second spacer layer 142. The second spacer layer 142 is located on the sidewalls of the bitline structure 150 and extends along the sidewalls of the bitline structure 150 into the isolation structure 110. The first spacer layer 141 is located on the substrate 100 and covers a portion of the sidewalls of the second spacer layer 142. For the bitline structure 150 formed between adjacent isolation structures 110, the first spacer layer 141 covers a portion of the sidewalls of the second spacer layer 142. For the bitline structure 150 formed above the isolation structure 110, the first spacer layer 141 is U-shaped and covers the sidewalls and bottom of the second spacer layer 142 and the bottom of the bitline structure 150, isolating the bitline structure 150 from the isolation structure 110 through the first spacer layer 141.

[0135] Figures 9A to 9G This is a schematic cross-sectional structural diagram corresponding to each step of the memory manufacturing method provided in this embodiment. The memory manufacturing method provided in this embodiment also includes steps S01 to S04. The difference from the sixth embodiment lies in the different manufacturing method of the sidewall spacer 140.

[0136] Specifically, first, see Figure 9A As shown, step S01 is performed to provide a substrate 100, which includes a plurality of active areas 120 and an isolation structure 110 surrounding the plurality of active areas 120. An isolation structure (STI) 110 is formed in the substrate 100, and the isolation structure defines a plurality of active areas (AA) 120. The active areas AA are distributed in an array.

[0137] Next, see Figures 9A to 9E As shown, step S02 and step S03 are performed to form a dielectric layer 102 on the substrate 100 and pattern it to form a plurality of bit line trenches 130. The bit line trenches 130 at least partially penetrate the substrate 100, and sidewall spacers 140 are formed on the sidewalls of the bit line trenches 130. Specifically, first, a liner layer 101 and a dielectric layer 102 are sequentially formed on the substrate 100, as shown in FIG. Figure 9A Then, the dielectric layer 102 and the liner layer 101 are patterned to form an opening 103 exposing the substrate 100, as shown. Figure 9B Then, a first spacer layer 141 is formed on the sidewalls and bottom of the opening 103, as shown Figure 9CAs shown; then, the bottom of the first spacer layer 141 and the substrate 100 are etched downward along the opening 103 to expose at least a portion of the isolation structure 110 to form the bit line trench 130. Specifically, for the opening 103 formed between adjacent isolation structures 110, the bottom of the first spacer layer 141 and the substrate 100 are etched, while for the opening 103 formed above the adjacent isolation structure 110, the bottom of the first spacer layer 141 is retained to isolate the subsequently formed bit line structure from the isolation structure 110, as shown. Figure 9D Next, a second spacer layer 142 is formed on the sidewall and bottom of the bit line trench 130, and the bottom of the second spacer layer 142 is removed by etching. Figure 9E As shown. For bitline trenches 130 formed between adjacent isolation structures 110, the bottom of the second spacer layer 142 and the substrate 100 are etched to expose a portion of the isolation structure 110. For bitline trenches 130 formed above adjacent isolation structures 110, the bottom of the first spacer layer 141 is exposed. Optionally, for bitline trenches 130 formed above adjacent isolation structures 110, the bottom of the second spacer layer 142 may not be etched. The first spacer layer 141 and the second spacer layer 142 together form a "U" shape, isolating the subsequently formed bitline structure from the isolation structure 110.

[0138] Next, see Figure 9F As shown, step S04 is performed to form a bitline structure 150 in the bitline trench 130. First, a "U"-shaped diffusion barrier layer 154 is formed along the sidewalls and bottom of the bitline trench 130. Next, a conductive layer 155 is formed on the diffusion barrier layer 154 to fill the bitline trench 130. The diffusion barrier layer and the conductive layer 155 are partially etched back, and a masking pattern 156 is formed on the diffusion barrier layer 154 and the conductive layer 155. The bottom and sidewalls of the diffusion barrier layer 154 in the bitline structure 150 formed between adjacent isolation structures 110 are in contact with the second spacer layer 142 and directly in contact with the active area 120. The bottom of the diffusion barrier layer 154 in the bitline structure 150 formed above the isolation structure 110 is isolated from the isolation structure 110 by the first spacer layer 141.

[0139] In addition, in some other embodiments of the present invention, the liner layer on the substrate may also be omitted, such as Figure 9G As shown, a sidewall spacer 140 (first spacer 141 ) is used to isolate the bit line structure 150 from the substrate 100 .

[0140] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0141] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0142] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0143] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

[0144] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A memory, characterized in that: include: A substrate comprising a plurality of active regions and an isolation structure surrounding the plurality of active regions; a plurality of bit line structures located on the substrate and in direct contact with the active area; a sidewall spacer layer, covering at least a sidewall of the bit line structure and extending into the isolation structure along a portion of the sidewall of the bit line structure; The bit line structure includes a U-shaped diffusion barrier layer, a conductive layer filled in the diffusion barrier layer, and a shielding pattern located above the diffusion barrier layer and the conductive layer. The diffusion barrier layer is in direct contact with the active area, and the bottom surface of the conductive layer is lower than the top surface of the substrate.

2. The memory according to claim 1, wherein The bottom and sidewalls of the diffusion barrier layer are in contact with the sidewall spacer.

3. The memory according to claim 1, wherein: A liner layer is also included, and the liner layer is located between the bit line structure and the substrate.

4. The memory according to claim 3, wherein: The diffusion barrier layer contacts the liner layer.

5. The memory according to claim 1, wherein: The sidewall spacer layer includes a first spacer layer and a second spacer layer, wherein: The second spacer layer covers the sidewall of the bit line structure and extends into the isolation structure along a portion of the sidewall of the bit line structure; The first spacer layer covers a sidewall of the second spacer layer on the substrate. The memory according to claim 1 , wherein: The sidewall spacer layer includes a first spacer layer and a second spacer layer, wherein: The first spacer layer and the second spacer layer both extend deep into the isolation structure along a portion of the bit line structure, wherein the first spacer layer is in an "L" shape, and the second spacer layer is located above a horizontal end of the "L" shape.

7. The memory according to claim 1, wherein: The sidewall spacer layer includes a first spacer layer, a second spacer layer and a third spacer layer, wherein the first spacer layer and the second spacer layer are both located on the substrate. Among them, the first spacer layer is "L"-shaped, the second spacer layer is located above the horizontal end of the "L" shape, the third spacer layer contacts the side wall of the second spacer layer and the horizontal end of the "L" shape of the first spacer layer, and penetrates into the isolation structure along part of the side wall of the bit line structure.

8. The memory according to claim 1, wherein: At least a portion of the sidewall spacer is arranged in a "U" shape to isolate the bit line structure from the bottom.

9. A method for manufacturing a memory, characterized in that: include: Providing a substrate comprising a plurality of active regions and an isolation structure surrounding the plurality of active regions; forming a dielectric layer on the substrate and patterning the dielectric layer to form a plurality of bit line trenches, wherein at least a portion of the bit line trenches extends deep into the substrate; forming a sidewall spacer on the sidewall of the bit line trench; as well as, forming a bit line structure in the bit line trench, wherein the sidewall spacer at least covers the sidewall of the bit line structure and extends into the isolation structure along a portion of the sidewall of the bit line structure; The process of forming the bit line structure includes: forming a U-shaped diffusion barrier layer along the sidewalls and bottom of the bit line trench, wherein the diffusion barrier layer is in direct contact with the active area; Filling the bit line trench to form a conductive layer on the diffusion barrier layer, wherein the bottom surface of the conductive layer is lower than the top surface of the substrate; A shielding pattern is formed on the diffusion barrier layer and the conductive layer.

10. The method for manufacturing a memory according to claim 9, wherein: The sidewall spacer layer includes a first spacer layer and a second spacer layer, and the formation process of the sidewall spacer layer includes: forming a first spacer layer and a second spacer layer in sequence along the sidewall and bottom of the bit line trench; and, Partially etching bottoms of the first spacer layer and the second spacer layer to expose a portion of the active area.

11. The method for manufacturing a memory according to claim 9, wherein: The sidewall spacer layer includes a first spacer layer and a second spacer layer, and the formation process of the bit line trench and the sidewall spacer layer includes: patterning the dielectric layer to form an opening exposing the substrate; forming a first spacer layer on the sidewalls and bottom of the opening; Etching a portion of the bottom of the first spacer layer and the substrate downward along the opening to expose at least a portion of the isolation structure to form the bit line trench; and A second spacer layer is formed on the sidewalls of the bit line trench.

12. The method for manufacturing a memory according to claim 9, wherein: The sidewall spacer layer includes a first spacer layer, a second spacer layer, and a third spacer layer. The formation process of the bit line trench and the sidewall spacer layer includes: patterning the dielectric layer to form an opening exposing the substrate; forming a first spacer layer and a second spacer layer in sequence on the sidewall and bottom of the opening; Etching the second spacer layer, the bottom of the first spacer layer, and the substrate downward along the opening to expose at least a portion of the isolation structure to form the bit line trench; and A third spacer is formed along the sidewalls of the bit line trench.

13. The method for manufacturing a memory according to claim 9, wherein: At least a portion of the sidewall spacer is arranged in a "U" shape to isolate the bit line structure from the bottom.

14. The method for manufacturing a memory according to claim 9, wherein: Also includes: removing the dielectric layer so that the adjacent bit line structure defines a storage contact window located on the active area; A storage contact plug is formed in the storage contact window and the storage contact plug is in contact with the corresponding active region.

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