Memory array including strings of memory cells and method of forming a memory array including strings of memory cells

Abstract

This application relates to memory arrays including strings of memory cells and methods for forming such memory arrays. One method for forming a memory array including strings of memory cells includes forming a stack comprising vertically alternating first and second layers. Strings of channel material are located in individual channel openings within the vertically alternating first and second layers. Conductive material contacts are located in the individual channel openings, directly abutting the channel material of the individual string of channel material. The conductive material contacts are vertically recessed into the individual channel openings. Conductive vias are formed in the individual channel openings, directly abutting the vertically recessed conductive material contacts. Other aspects disclosed include structures independent of the method.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory arrays and methods for forming memory arrays. Background Technology

[0002] Memory is an integrated circuit used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is conventionally specified as memory with a retention period of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention period of a few milliseconds or less. In any case, memory cells are configured to maintain or store stored content in at least two different selectable states. In binary systems, these states are considered as "0" or "1". In other systems, at least some individual memory cells may be configured to store information in more than two levels or states.

[0004] A field-effect transistor (FET) is an electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow is largely prevented through the channel region. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives instead of conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be a basic architecture for integrated flash memory. A NAND cell device includes at least one selection device series-coupled with a series combination of memory cells (and said series combination is generally referred to as a NAND string). NAND architectures can be configured in a three-dimensional arrangement, comprising vertically stacked memory cells, each of which includes a reversible programmable vertical transistor. Control or other circuitry may be formed beneath the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells, each individually including a transistor.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and portions of blocks (e.g., sub-blocks) and memory planes, as shown and described in, for example, any of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block may at least partially define the longitudinal profile of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called “step structure” at the ends or edges of the array of vertically stacked memory cells. A step structure includes individual “steps” (alternatively referred to as “steps” or “staircases”) that define contact areas for individual word lines, on which vertically extending conductive vias contact to provide electrical access to the word lines. Summary of the Invention

[0008] In one aspect, this disclosure provides a method for forming a memory array including strings of memory cells, comprising: forming a stack including vertically alternating first and second layers, with a string of channel material in an individual channel opening in the vertically alternating first and second layers, and a conductor material contact in the individual channel opening directly abutting the channel material of the individual channel material string; vertically recessing the conductor material contact into the individual channel opening; and forming a conductive via directly abutting the vertically recessed conductor material contact in the individual channel opening.

[0009] On the other hand, this disclosure provides a method for forming a memory array including strings of memory cells, comprising: forming a stack including vertically alternating first and second layers, with a string of channel material in individual channel openings in the vertically alternating first and second layers, each string of channel material individually including a cylindrical shell, an insulating material radially inward of the cylindrical shell, and a storage material radially outward of the cylindrical shell; vertically recessing the insulating material in the individual channel openings relative to the storage material and relative to the channel material; and causing conductor material contacts in the string of channel material... The cylindrical shell of the channel material of the individual channel material string is formed radially inside and directly abuts against the radially inner side of the cylindrical shell in the individual channel opening, and on the top of the vertically recessed insulating material; the conductor material contact and the cylindrical shell of the individual channel material string are vertically recessed relative to the storage material in the individual channel opening; and the conductive via is formed directly abutting against the top of the vertically recessed cylindrical shell of the channel material string and directly abutting against the top of the vertically recessed conductor material contact in the individual channel opening.

[0010] In another aspect, this disclosure provides a memory array including strings of memory cells, comprising: laterally spaced memory blocks, each comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers, the uppermost insulating layer comprising an insulating material, an insulating layer comprising an insulating body material being directly above and abutting the insulating material of the uppermost insulating layer, an insulating interface being between the insulating material and the insulating body material; a string of channel materials for memory cells in the insulating and conductive layers; conductor material contacts directly abutting the channel material of an individual string of channel materials, the conductor material contacts having a top lower than the insulating interface; and conductive vias being directly above and abutting the individual conductor material contacts, the conductive interface being between the conductor material contacts and the conductive vias, the conductive vias having a top at or below the insulating interface.

[0011] In another aspect, this disclosure provides a memory array including strings of memory cells, comprising: laterally spaced memory blocks, each comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers, the uppermost insulating layer comprising an insulating material, an insulating layer comprising an insulating material directly above and abutting the insulating material of the insulating layer, an insulating interface between the insulating material and the insulating material; a string of channel materials for memory cells in the insulating and conductive layers, storage material radially outside individual strings of channel materials in the string of channel materials, the individual strings of channel materials having a top below the insulating interface, the storage material having a top at or below the insulating interface; conductive material contacts directly abutting the channel material of the individual strings of channel materials; and conductive vias directly above and abutting individual conductive material contacts in the conductive material contacts, the conductive interface being located between the conductive material contacts and the conductive vias. Attached Figure Description

[0012] Figure 1 This is a schematic cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention, and through... Figure 2 Cut off line 1-1 in the middle.

[0013] Figure 2 Is it through Figure 1 A rough cross-sectional view taken from line 2-2 in the figure.

[0014] Figures 3 to 5 yes Figure 1 and 2 A magnified view of the portion.

[0015] Figures 6 to 14 It is in the process of processing according to some embodiments of the present invention. Figures 1 to 5 The general structure of or part thereof is shown in sequence as cross-section, unfolded, enlarged and / or partial views.

[0016] Figure 15 Alternative examples of methods and / or structural embodiments of the present invention are shown. Detailed Implementation

[0017] Embodiments of the present invention cover methods for forming memory arrays, such as NAND or other memory cell arrays, which may have at least some peripheral control circuitry (e.g., under-array CMOS) beneath the array. Embodiments of the present invention cover so-called "back-gate" or "replacement gate" processing, so-called "front-gate" processing, and other processing, whether existing or developed in the future, independent of the transistor gate formation timing. Embodiments of the present invention also cover a memory array (e.g., NAND architecture) independent of the manufacturing method. Reference Figures 1 to 14 Describe the first instance method implementation.

[0018] Figures 1 to 5 An example configuration 10 with an array 12 is shown, in which vertically extending strings 49 of transistors and / or memory cells 56 have been formed. This includes a substrate 11 having any one or more of a conductive, semiconductive, semiconductor, or insulating (i.e., electrically) material. Various materials are vertically formed on the substrate 11. The materials may be... Figures 1 to 5 The material depicted may be adjacent to, vertically inside, or vertically outside. For example, other partially or integrally manufactured integrated circuit components may be provided above, around, or inside the substrate 11. Control circuitry systems and / or other peripheral circuitry systems for operating components within a vertically extending string array (e.g., array 12) of memory cells may also be manufactured, and these circuitry systems may or may not be fully or partially within the array or subarray. Furthermore, multiple subarrays may be manufactured and operated relatively independently, sequentially, or otherwise. In this document, "subarray" may also be considered as an array.

[0019] A conductor layer 16, comprising conductor material 17, is formed over the substrate 11. The conductor layer 16 may include portions of a control circuitry (e.g., peripheral array under-circuitry and / or common source line or board) for controlling read and write access to transistors and / or memory cells to be formed within the array 12. A stack 18 comprising vertically alternating insulating layers 20 and conductive layers 22 is formed over the conductor layer 16. In some embodiments, the conductive layer 22 is referred to as the first layer 22, and the insulating layer 20 as the second layer 20. An example method is described as gate-first, but alternatively, it may be gate-back (or other methods). Therefore, at this point in the process, the first / conductive layer 22 may not include conductive material, and the second / insulating layer 20 may not include insulating material or may not be insulating.

[0020] The thickness of each layer 20 and 22 is 22 to 60 nanometers. The uppermost layer 20 may be thicker / the thickest compared to one or more other layers 20 and / or 22. Only a small number of layers 20 and 22 are shown, while the stack 18 is more likely to include dozens, hundreds or more layers 20 and 22. Other circuitry, which may or may not be part of the peripheral and / or control circuitry, may be located between the conductor layer 16 and the stack 18. For example, multiple vertically alternating layers of conductive and insulating materials of such circuitry may be below the lowest conductive layer 22 and / or above the uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between the conductor layer 16 and the lowest conductive layer 22, and one or more select gate layers may be above the uppermost conductive layer 22 (not shown). Alternatively or additionally, at least one of the uppermost and lowest conductive layers 22 depicted may be a select gate layer. Example insulation layer 20 includes insulating material 24 (e.g., silicon dioxide and / or other materials that may have one or more components).

[0021] A channel opening 25 is formed by penetrating the insulating layer 20 and conductive layer 22 to the conductor layer 16 (e.g., by etching). The channel opening 25 may taper radially inward as it moves deeper within the stack 18 (not shown). In some embodiments, the channel opening 25 may enter the conductor material 17 of the conductor layer 16 as shown, or it may terminate at the top (not shown). Alternatively, as an example, the channel opening 25 may terminate at the top or inside of the lowest insulating layer 20. The reason for extending the channel opening 25 at least to the conductor material 17 of the conductor layer 16 is to ensure that the channel material is directly electrically coupled to the conductor layer 16 without using alternative processes and structures when such an connection is desired. An etch-stop material (not shown) may be present within or on top of the conductor material 17 of the conductor layer 16 to help stop the etching of the channel opening 25 relative to the conductor layer 16 when such a requirement is desired. Such an etch-stop material may be sacrificial or non-sacrificial. As an example and for simplicity only, the channel openings 25 are shown as arranged in groups or columns of staggered rows of four and five openings 25 per row, and arranged in laterally spaced memory blocks 58. In this document, "block" generally includes "sub-blocks". Memory blocks 58 may, for example, extend and be oriented longitudinally along direction 55. Any alternative existing or future-developed arrangements and constructions may be used.

[0022] Example memory block 58 is shown as being at least partially defined by horizontally elongated trenches 40 formed (e.g., by anisotropic etching) into stack 18. Trench 40 may have a corresponding bottom (as shown) directly abutting the conductive material 17 of conductive layer 16 (e.g., top or interior), or may have a corresponding bottom (not shown) above the conductive material 17 of conductive layer 16. Intermediate material 57 is in the trenches 40 in stack 18 and may provide lateral electrical isolation (insulation) between laterally adjacent memory blocks 58. This may include one or more of insulating, semiconductive, and conductive materials, and in any case, may facilitate shorting of conductive layers 22 relative to each other in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intermediate material 57 may include through-array vias (TAVs) and is not shown.

[0023] Transistor channel material can be formed vertically along the insulating and conductive layers in individual channel openings, thus including individual channel material strings directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally positioned between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge-transfer material. The storage material of the individual memory cell (e.g., a floating gate material, such as doped or undoped silicon, or a charge-trapping material, such as silicon nitride, metal dots, etc.) is vertically positioned along the individual charge-blocking region. The insulating charge-transfer material (e.g., a bandgap-engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide) is laterally positioned between the channel material and the storage material.

[0024] Figures 1 to 5 One embodiment is shown in which charge blocking material 30, storage material 32, and charge transport material 34 are formed vertically along insulating layer 20 and conductive layer 22 in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing corresponding thin layers of the transistor materials over stack 18 and within individual channel openings 25, and subsequently planarizing such backs at least to the top surface of stack 18, as shown.

[0025] Channel material 36 is also formed vertically along the insulating layer 20 and the conductive layer 22 in the channel opening 25, and in one embodiment includes individual operative channel material strings 53, which have memory cell materials (e.g., 30, 32, and 34) along their lengths, with material 24 in the insulating layer 20 horizontally positioned between adjacent channel material strings 53. Due to proportions, materials 30, 32, 34, and 36... Figure 1 and2 The material 37 is shown and designated only as material 37. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). The thickness of each of materials 30, 32, 34, and 36 is typically 25 to 100 angstroms. As shown, stamping etching can be performed to remove materials 30, 32, and 34 from the substrate of the channel opening 25 to expose the conductor layer 16, such that the channel material 36 directly abuts the conductor material 17 of the conductor layer 16. Such stamping etching can occur individually with respect to each of materials 30, 32, and 34 (as shown), or it can occur jointly with respect to all materials after the deposition of material 34 (not shown). Alternatively, and by way of example only, stamping etching may not be performed, and the channel material 36 may be directly electrically coupled to the conductor material 17 of the conductor layer 16 via separate conductive interconnects (not shown).

[0026] Example conductive layer 22 includes a conductive material 48 that is a portion of individual conductive lines 29 (e.g., word lines) that are also portions of vertically extending strings 49 of individual transistors and / or memory cells 56. A thin insulating liner (e.g., Al2O3, not shown) may be formed prior to the formation of the conductive material 48. The approximate locations of the transistors and / or memory cells 56 are... Figure 5 Parentheses are used to indicate this, and some are in Figures 1 to 4 The transistors and / or memory cells 56 are indicated by dashed outlines, where they are substantially annular or ring-shaped in the depicted example. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25, such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., in an individual conductive layer, multiple transistors and / or memory cells surround an individual channel opening, where there may be multiple word lines per channel opening in the individual conductive layer, and not shown). The conductive material 48 can be considered as having ends 50 corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. Figure 5 In the depicted embodiment, the control gate region 52 includes individual portions of the individual conductive lines 29. Materials 30, 32, and 34 can be considered as a memory structure 65 laterally located between the control gate region 52 and the channel material 36.

[0027] A charge blocking region (e.g., charge blocking material 30) is located between the storage material 32 and the individual control gate region 52. The charge blocking member in the memory cell may function to prevent charge carriers from flowing from the storage material (e.g., a floating gate material, a charge trapping material, etc.) to the control gate in program mode, and to prevent charge carriers from flowing from the control gate into the storage material in erase mode. Therefore, the charge blocking member can be used to block charge migration between the control gate region and the storage material of an individual memory cell. As shown in the example, the charge blocking region includes an insulating material 30. As another example, the charge blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), wherein such storage material is insulating (e.g., in the absence of any different compositional material between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, the junction between the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region even in the absence of any separately composed insulating material 30. Furthermore, the junction between the conductive material 48 and the insulating material 30 (if present) can together act as a charge-blocking region, and alternatively or additionally, can act as a lateral outer region of an insulating storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0028] In one embodiment and as shown, the channel material string 53 individually includes a cylindrical shell in which storage material (e.g., 32) is located radially outside such a cylindrical shell. Alternatively, and by way of example only, the channel material string may be a solid column (not shown) having a channel material that radially spans the entire length of the channel. In an exemplary embodiment, an insulating material 38 (e.g., spin-coated dielectric, silicon dioxide, and / or silicon nitride) has been deposited on top of the uppermost second layer 20 and radially deposited inside the cylindrical shell of the channel material string 53. Depending on the timing of the fabrication of the illustrated material, material 37 may be located on top of the uppermost layer 20 at this processing point (not shown), with the insulating material 38 on top of it (not shown). The cylindrical shell of the channel material string 53 may be considered to include a radially inner side 79 ( Figure 4 ).

[0029] refer to Figure 6 The insulating material 38 in the individual channel openings 25 is vertically recessed relative to the storage material 32 and relative to the channel material 36 (i.e., at least relative to such materials) (e.g., by wet or dry etching). In one embodiment, such vertical recessing causes the top 51 of the insulating material 38 to be lower than the uppermost first layer 22.

[0030] refer to Figure 7 and 8Conductor material 31 has been formed as part of structure 10, thereby forming conductor material contacts 41 in individual channel openings 25 radially inside the cylindrical shell of individual channel material strings 53 and directly abutting their radially inner sides 79, and on top of vertically recessed insulating material 38. In one embodiment, conductor material 31 comprises a conductively doped semiconducting material, such as conductively doped polysilicon, and in one embodiment, channel material 36 comprises undoped or channel-doped polysilicon, which may have an increased doping concentration therein due to diffusion from thereout at the contact of conductor material 31.

[0031] refer to Figure 9 and 10 The cylindrical housings of the conductor material contacts 41 and the individual channel material strings 53 are vertically recessed relative to the storage material 32 in the individual channel openings 25 (at least relative to the storage material) (e.g., by wet or dry etching). In one embodiment, and as shown, after the vertical recessing action, the conductor material contacts 41 in the individual channel openings 25 each have a top 44 above the uppermost first layer 22. In one embodiment, the vertical recessing of the conductor material contacts 41 and the vertical recessing of the cylindrical housings occur simultaneously. The cylindrical housings of the individual channel material strings include a top 39.

[0032] refer to Figure 11 and 12 Conductive material 42 (e.g., elemental tungsten on top of the TiN thin film) has been Figure 9 and 10 The structure 10 is formed on top, thereby forming a conductive via 43 by directly abutting the top 39 of the vertically recessed cylindrical shell of the channel material string 53 in the individual channel opening 25 and directly abutting the top 44 of the vertically recessed conductor material contact 41 in the individual channel opening 25. The conductive material 42 and the conductor material 31 may have the same composition relative to each other, or may include different compositions relative to each other. In any case, the conductive interface 44 ("conductive" when the materials 42 and 31 are conductive, and substantially the same as the top 44 indicated by the line) is between the conductive material 42 and the conductor material 31. For example, the conductive material 42 may be deposited to overfill. Figure 9 and 10 The remaining volume of the channel opening 25 in the middle is then flattened back at least to the top of the uppermost second layer 20.

[0033] refer to Figure 13 and 14An insulating layer 67, comprising insulating material 35, is formed directly above and abuts the insulating material 24 of the uppermost insulating layer 20. Insulating material 35 and insulating material 24 may have the same composition relative to each other, or may include different compositions relative to each other. In any case, an insulating interface 68 (“insulating” when materials 35 and 24 are insulating) lies between insulating material 24 and insulating material 35. Digital lines (not shown) may be formed within the insulating material 35 of the insulating layer 67, which is directly electrically coupled to one or more conductive vias 43. Alternatively, by way of example only, additional conductive vias (not shown) may be formed in the insulating material 35 of the insulating layer 67, which is individually directly electrically coupled to the conductive vias 43, and digital lines (not shown) may be formed thereon directly electrically coupled to one or more such additional vias (not shown). This is schematically and abstractly illustrated by a conductive schematic line 80 (e.g., a digital line or another conductive via) connected to node 81 (e.g., a digital line or a conductive connection to a digital line).

[0034] Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used in conjunction with the embodiments shown and described above.

[0035] In one embodiment, a method for forming a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) includes: forming a stack (e.g., 18) comprising vertically alternating first layers (e.g., 22) and second layers (e.g., 20). Strings of channel materials (e.g., 53) are located in individual channel openings (e.g., 25) within the vertically alternating first and second layers. Conductive material contacts (e.g., 41) directly abut against the channel material of the individual channel material strings within the individual channel openings. The conductive material contacts are vertically recessed within the individual channel openings. Conductive vias (e.g., 43) are formed directly against the vertically recessed conductive material contacts within the individual channel openings. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0036] Alternative embodiments may be constructed from the method embodiments described above or otherwise. In any case, embodiments of the invention cover memory arrays independent of manufacturing methods. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate having, forming, and / or having any of the properties described relative to the device embodiments.

[0037] In one embodiment, a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) includes laterally spaced memory blocks (e.g., 58), each memory block comprising a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). The uppermost insulating layer comprises an insulating material (e.g., 24). An insulating layer (e.g., 67) comprising an insulating material (e.g., 35) is directly above and abuts the insulating material of the uppermost insulating layer. An insulating interface (e.g., 68) lies between the insulating material and the insulating material. Strings (e.g., 53) of channel material for the memory cells (e.g., 56) are located within the insulating and conductive layers. Conductor material contacts (e.g., 41) abut directly against the channel material (e.g., 36) of the individual string of channel material (e.g., whether the string of channel material is entirely solid or comprises a cylindrical shell). The conductor material contacts have a top (e.g., 44) below the insulating interface. A conductive via (e.g., 43) is directly above and abuts against an individual conductive material contact. A conductive interface (e.g., 44) is located between the conductive material contact and the conductive via. The conductive via has a top (e.g., 73) at or below the insulating interface (“at”). Figure 13 and 14 (As shown in the diagram). In one embodiment, the conductive material contact has a bottom (e.g., 75) below the topmost conductive layer 22. In one embodiment, the conductive via has a topmost conductive layer 22 (e.g., 77). Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0038] Figure 15 An alternative construction 10a is shown, in which the top 73 of the conductive via is below the insulating interface 68. The same numbering from the embodiments described above has been used where appropriate, with the suffix "a" indicating some construction differences. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0039] In one embodiment, a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) includes laterally spaced memory blocks (e.g., 58), each memory block comprising a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). The uppermost insulating layer comprises an insulating material (e.g., 24). An insulating layer (e.g., 67) comprising an insulating material (e.g., 35) is directly above and abuts the insulating material of the uppermost insulating layer. An insulating interface (e.g., 68) is located between the insulating material and the insulating material. Strings of channel material (e.g., 53) of memory cells (e.g., 56) are located within the insulating and conductive layers. Storage material (e.g., 32) is radially outside the individual strings of channel material. The individual strings of channel material have a top (e.g., 39) below the insulating interface. The storage material has a top at or below the insulating interface. Conductor material contacts (e.g., 41) directly abut the channel material of the individual strings of channel material. A conductive via (e.g., 43) is directly above and abuts against an individual conductive material contact. A conductive interface (e.g., 44) is located between the conductive material contact and the conductive via. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0040] The above-described processing or construction can be viewed as relating to an array of components formed as a single stack or single group of such components above or as part of a base substrate (but the single stack / group may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed as part of the finished product construction at any location, and in some embodiments may be below the array (e.g., under-array CMOS). In any case, one or more additional such stacks / groups may be provided or fabricated above and / or below the stacks / groups shown in the figures or described above. Furthermore, arrays of components may be the same or different relative to each other in different stacks / groups, and different stacks / groups may have the same or different thicknesses relative to each other. Intermediate structures may be provided between vertically adjacent stacks / groups (e.g., additional circuitry and / or dielectric layers). Additionally, different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups may be fabricated individually and sequentially (e.g., one on top of another), or two or more stacks / groups may be fabricated substantially simultaneously.

[0041] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0042] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means a direction generally along the surface of the main substrate (i.e., within 10 degrees) and relative to which the substrate can be handled during manufacturing, and vertical is a direction generally orthogonal to it. The reference to “exactly horizontal” means a direction along the surface of the main substrate (i.e., not forming degrees with said surface) and relative to which the substrate can be handled during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” are directions generally perpendicular to each other and are independent of the substrate orientation in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to directions deviating at least 45° from exactly horizontal. Furthermore, relative to a field-effect transistor, “vertically extending,” “vertically extending,” “horizontally extending,” “horizontally extending,” and the like refer to the orientation of the transistor's channel length, along which current flows between the source / drain regions during operation. For a bipolar junction transistor, the orientation of “vertically extending,” “vertically extending,” “horizontally extending,” “horizontally extending,” and the like refers to the length of the substrate, and in operation, current flows between the emitter and collector along said orientation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10°.

[0043] Furthermore, "directly above," "directly below," and "directly below" require that the two stated areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Additionally, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above another stated area / material / component is vertically outside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "below" without the preceding "direct" only requires that a portion of the stated area / material / component below another stated area / material / component is vertically inside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0044] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event may be continuous or discontinuous over any material they cover. Where one or more example components are provided for any material, the material may comprise, consist primarily of, or consist of one or more of such components. Furthermore, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, wherein atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples.

[0045] Additionally, the term “thickness” (without a directional adjective) used alone is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, the thickness refers to the average thickness unless otherwise indicated, and such materials or regions will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, “different compositions” requires only that the portions of two stated materials or regions that can directly contact each other are chemically and / or physically different, for example, in cases where such materials or regions are not homogeneous. If two stated materials or regions are not directly contacting each other, then in cases where such materials or regions are not homogeneous, “different compositions” requires only that the portions of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, a material, region, or structure is “directly contacting” another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures. In contrast, the words "above," "up," "adjacent," "along," and "against" without the preceding "positive" encompass "direct contact" and constructions in which the intervening material, area, or structure causes the stated material, area, or structure to have no physical contact with each other.

[0046] In this text, if, during normal operation, current can flow continuously from one zone-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” relative to each other. Another electronic component may be electrically coupled between and to the zone-material-components. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intermediary electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0047] The terms "row" and "column" are used in this document for ease of distinguishing features of one series or orientation from features of another series or orientation, and for components that have been or may be formed along said "row" and "column". "Row" and "column" are used synonymously with any series of areas, components, and / or features, regardless of function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., except for straight angles).

[0048] The components of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconducting materials. “Metallic material” is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds.

[0049] In this document, any use of "selective" in relation to etching, removal, deposition, forming, and / or formation is an action in which a stated material is performed relative to another stated material at a volume ratio of at least 2:1. Furthermore, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of one material relative to one or more stated materials at a volume ratio of at least 2:1, reaching a deposition, growth, or formation of at least a first 75 angstroms.

[0050] Unless otherwise indicated, the use of "or" in this document covers either or both.

[0051] Summarize

[0052] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a stack comprising vertically alternating first and second layers. Strings of channel material are located in individual channel openings within the vertically alternating first and second layers. Conductive material contacts are located in the individual channel openings, directly abutting the channel material of the individual string of channel material. The conductive material contacts are vertically recessed into the individual channel openings. Conductive vias are formed directly abutting the vertically recessed conductive material contacts in the individual channel openings.

[0053] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a stack comprising vertically alternating first and second layers. A channel material string is formed in individual channel openings within the vertically alternating first and second layers. Each channel material string individually includes a cylindrical housing. An insulating material is radially inward of the cylindrical housing, and a storage material is radially outward of the cylindrical housing. The insulating material is vertically recessed in the individual channel opening relative to the storage material and relative to the channel material. Conductor material contacts are formed in the individual channel openings radially inward of the cylindrical housing of the channel material of the individual channel material string and directly abutting the radially inner side of the cylindrical housing, and on top of the vertically recessed insulating material. The conductor material contacts and the cylindrical housing of the individual channel material string are vertically recessed relative to the storage material in the individual channel opening. The conductive via directly abuts the top of the vertically recessed cylindrical shell of the channel material string and directly abuts the top of the vertically recessed conductor material contact located in the individual channel opening, which is formed in the individual channel opening.

[0054] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks, each memory block individually comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers. The uppermost insulating layer comprises an insulating material. An insulating layer comprising an insulating body material is directly above and abuts the insulating material of the uppermost insulating layer. An insulating interface is located between the insulating material and the insulating body material. Channel material strings of memory cells are formed within the insulating and conductive layers. Conductive material contacts directly abut the channel material of individual channel material strings. The conductor material contacts have a top that is below the insulating interface. Conductive vias are directly above and abut the individual conductor material contacts. A conductive interface is located between the conductor material contacts and the conductive vias. The conductive vias have a top that is at or below the insulating interface.

[0055] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks, each memory block individually comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers. The uppermost insulating layer comprises an insulating material. An insulating layer comprising an insulating material is directly above and abuts the insulating material of the insulating layer. An insulating interface is located between the insulating material and the insulating material. Channel material strings of memory cells are located within the insulating and conductive layers. Storage material is radially outside the individual channel material strings. Individual channel material strings have a top that is below the insulating interface. Storage material has a top that is at or below the insulating interface. Conductive material contacts directly abut the channel material of the individual channel material strings. Conductive vias are directly above and abut the individual conductor material contacts. A conductive interface is located between the conductor material contacts and the conductive vias.

[0056] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims have the full scope as stated literally and should be properly interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array comprising strings of memory cells, comprising: A stack comprising vertically alternating first and second layers is formed. In the completed construction, the first layer is conductive and the second layer is insulating. A string of channel material is located in individual channel openings in the vertically alternating first and second layers. Each string of channel material individually includes a cylindrical shell of channel material, with insulating material located radially inside the cylindrical shell of the channel material and storage material located radially outside the cylindrical shell of the channel material. The insulating material in the individual channel openings is vertically recessed relative to the storage material and relative to the channel material; Conductor material contacts are formed in the individual channel openings, the conductor material contacts being radially inside the cylindrical shell of the channel material in the individual channel material string and directly abutting the radially inside side of the cylindrical shell, and on the top of the vertically recessed insulating material, the bottom of the conductor material contacts being lower than the bottom of the uppermost layer of the first layer; The conductor material of the conductor material contact is etched vertically downwards so that the conductor material is vertically recessed relative to the storage material in the individual channel openings, and the channel material of the cylindrical shell of the individual channel material string is etched vertically downwards so that the cylindrical shell is vertically recessed relative to the storage material in the individual channel openings, and the conductor material has a flat uppermost surface after the etching. as well as Conductive vias are formed in the individual channel openings, the conductive vias directly abutting the top of the channel material of the vertically recessed cylindrical shell of the channel material string and directly abutting the entire flat uppermost surface of the vertically recessed conductor material contact in the individual channel openings.

2. The method of claim 1, wherein the uppermost second layer is thicker than the immediately following second layer.

3. The method of claim 1, wherein the uppermost layer of the stacked vertically alternating first and second layers is the second layer at the beginning of the vertical recess, the vertical recess positioning the top of the insulating material below the uppermost first layer.

4. The method of claim 1, further comprising forming the conductive via with a conductive material such that it extends laterally outward in a vertical cross-section beyond one side of the conductive material of the conductive material contact.

5. The method of claim 1, further comprising forming the conductive via with a conductive material such that it extends laterally outward in a vertical cross-section beyond two laterally opposite sides of the conductive material of the conductor material contact.

6. The method of claim 1, wherein the top of the conductor material contact is located above the top of the uppermost conductive layer.

7. The method according to claim 1, wherein the uppermost layer of the second layer comprises an insulating material, an insulating layer comprising the insulating material is directly above and directly abuts the insulating material of the uppermost second layer, an insulating interface is located between the insulating material and the insulating material, and the top of the conductive via is located at or below the insulating interface.

8. The method of claim 7, wherein the top of the conductive via is located at the insulating interface.

9. The method of claim 7, wherein the top of the conductive via is located below the insulating interface.

10. A method for forming a memory array comprising strings of memory cells, comprising: A stack comprising vertically alternating first and second layers is formed, with a string of channel material in an individual channel opening in the vertically alternating first and second layers, the string of channel material individually comprising a cylindrical shell of channel material, an insulating material radially inside the cylindrical shell of the channel material, and a storage material radially outside the cylindrical shell of the channel material; The insulating material in the individual channel openings is vertically recessed relative to the storage material and relative to the channel material; Conductor material contacts are formed in the individual channel openings, the conductor material contacts being radially inside the cylindrical shell of the channel material in the individual channel material string and directly abutting the radially inside side of the cylindrical shell, and on the top of the vertically recessed insulating material; The conductor material of the conductor material contact is etched vertically downwards so that the conductor material is vertically recessed relative to the storage material in the individual channel openings, and the channel material of the cylindrical shell of the individual channel material string is etched vertically downwards so that the cylindrical shell is vertically recessed relative to the storage material in the individual channel openings, and the conductor material has a flat uppermost surface after the etching. Conductive vias are formed in the individual channel openings, the conductive vias directly abutting the top of the channel material of the vertically recessed cylindrical shell of the channel material string and directly abutting the entire flat uppermost surface of the vertically recessed conductor material contact in the individual channel openings. as well as The etching of the conductor material of the conductor material contact and the etching of the channel material of the cylindrical housing occur simultaneously.

11. A method for forming a memory array comprising strings of memory cells, comprising: A stack comprising vertically alternating first and second layers is formed. In the completed construction, the first layer is conductive and the second layer is insulating. A string of channel material is located in individual channel openings in the vertically alternating first and second layers. The string of channel material individually includes a cylindrical shell, with insulating material located radially inside the cylindrical shell and storage material located radially outside the cylindrical shell. The insulating material in the individual channel openings is vertically recessed relative to the storage material and relative to the channel material; Conductor material contacts are formed in the individual channel openings, the conductor material contacts being radially inside the cylindrical shell of the channel material in the individual channel material string and directly abutting the radially inside side of the cylindrical shell, and on the top of the vertically recessed insulating material, the bottom of the conductor material contacts being lower than the bottom of the uppermost layer of the first layer; The cylindrical housing of the conductor material contact and the individual channel material string is vertically recessed relative to the storage material in the individual channel opening; as well as Conductive vias are formed in the individual channel openings, and the conductive vias directly abut against the top of the vertically recessed cylindrical shell of the channel material string and directly abut against the top of the vertically recessed conductor material contact in the individual channel openings.

12. The method of claim 11, wherein the uppermost layer of the second layer comprises an insulating material, an insulating layer comprising the insulating material is directly above and directly abuts the insulating material of the uppermost second layer, an insulating interface is located between the insulating material and the insulating material, and the top of the conductive via is located at or below the insulating interface.

13. The method of claim 12, wherein the top of the conductive via is located at the insulating interface.

14. The method of claim 12, wherein the top of the conductive via is located below the insulating interface.

15. A memory array comprising a string of memory cells, comprising: The memory blocks are spaced horizontally, each comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers, the uppermost insulating layer comprising an insulating material, an insulating layer comprising an insulating body material being directly above and abutting the insulating material of the uppermost insulating layer, and an insulating interface being between the insulating material and the insulating body material; A channel material string of a memory cell, which is located in the insulating layer and the conductive layer, wherein the storage material of the memory cell is located radially outside of an individual channel material string in the channel material string and has a top located at the insulating interface; A conductor material contact that directly abuts against the channel material of an individual channel material string in the channel material string, the conductor material contact having a top that is below the insulating interface; as well as A conductive via is located directly above and abutting against an individual conductor material contact in the conductor material contacts, with a conductive interface between the conductor material contact and the conductive via, the conductive via having a top located at or below the insulating interface.

16. The memory array of claim 15, wherein the channel material string individually includes a cylindrical housing, and the conductor material contacts are radially inside the cylindrical housing.

17. The memory array of claim 15, wherein the top of the conductive via is located at the insulating interface.

18. The memory array of claim 15, wherein the top of the conductive via is below the insulating interface.

19. The memory array of claim 15, wherein the conductor material contact has a bottom below the topmost conductive layer.

20. The memory array of claim 15, wherein the conductive via has a bottom higher than the topmost conductive layer.

21. The memory array of claim 15, wherein the uppermost insulating layer is thicker than the immediately following insulating layer.

22. The memory array of claim 15, wherein the conductor material contact comprises a conductively doped semiconducting material, and the conductive via comprises a metallic material.

23. A memory array comprising a string of memory cells, comprising: The memory blocks are spaced horizontally, each comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers, the uppermost insulating layer comprising an insulating material, an insulating layer comprising an insulating body material directly above and abutting the insulating material of the insulating layer, and an insulating interface between the insulating material and the insulating body material; A channel material string of a memory cell, which is in the insulating layer and the conductive layer, wherein the storage material is radially outside of an individual channel material string in the channel material string, the individual channel material string having a top below the insulating interface, and the storage material having a top at the insulating interface; A conductor material contact that directly abuts against the channel material of the individual channel material string; as well as A conductive via is located directly above and abutting against an individual conductor material contact in the conductor material contact, with a conductive interface situated between the conductor material contact and the conductive via.

24. The memory array of claim 23, wherein the channel material string individually includes a cylindrical housing, and the conductor material contact directly abuts the radially inner side of the cylindrical housing of the channel material in the individual channel material string.

25. The memory array of claim 24, comprising an insulating material inside the cylindrical housing.

26. The memory array of claim 23, wherein the conductor material contact has a top that is below the insulating interface.

27. The memory array of claim 23, wherein the conductive via has a top position at or below the insulating interface.

28. The memory array of claim 23, wherein the conductor material contact has a top below the insulating interface, and the conductive via has a top at or below the insulating interface.

Images