Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel includes a substrate; an oxide transistor located on one side of the substrate; the oxide transistor includes an active layer, which includes multiple stacked sub-layers, at least two of which have different indium ion concentrations. According to embodiments of the present application, the yield rate of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, users have increasingly higher requirements for the yield rate of display panels. Display panels contain a large number of transistors. If a transistor fails (NG) during the display panel manufacturing process, the display panel will become a defective product, affecting the yield rate of the display panel. Summary of the Invention

[0003] The present application provides a display panel and a display device, which can improve the yield rate of the display panel.

[0004] In a first aspect, an embodiment of the present application provides a display panel comprising: a substrate; an oxide transistor located on one side of the substrate, the oxide transistor comprising an active layer, the active layer comprising a plurality of stacked sub-film layers, at least two of the sub-film layers having different indium ion concentrations.

[0005] In a second aspect, based on the same inventive concept, an embodiment of the present application provides a display device, which includes a display panel according to the implementation of the first aspect of the present application.

[0006] The display panel and display device provided by the embodiments of the present application are no longer limited to setting the active layer of the oxide transistor as a single film layer containing only one indium ion concentration. Instead, the active layer of the oxide transistor is divided into multiple stacked sub-film layers, and at least two sub-film layers have different indium ion concentrations. Compared with a single film layer containing only one indium ion concentration, the overall thickness of the active layer can be increased while the total indium content of the active layer remains unchanged. In other words, while avoiding the active layer from being completely conductive and ensuring that the oxide transistor has a high mobility, by dividing the active layer into sub-film layers with different indium ion concentrations, the overall thickness of the active layer can be increased, and the via holes that overlap the source and drain electrodes with the active layer can be prevented from penetrating the active layer, thereby preventing the oxide transistor from having NGs and improving the yield rate of the display panel.

[0007] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0009] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present application is shown;

[0010] Figure 2 A schematic diagram showing a top view of a display panel provided by an embodiment of the present application is shown;

[0011] Figure 3 Show Figure 2 Schematic diagram of the cross-sectional structure along the AA direction;

[0012] Figure 4 A schematic structural diagram of a display panel provided in another embodiment of the present application is shown;

[0013] Figures 5 to 10 Schematic diagrams showing the structures of display panels provided in some other embodiments of the present application;

[0014] Figure 11 Show Figure 10 Enlarged schematic diagram of the middle Q region;

[0015] Figures 12 to 15 Schematic diagrams showing the structures of display panels provided in some other embodiments of the present application;

[0016] Figure 16 A schematic diagram showing a top view of a display panel provided in another embodiment of the present application is shown;

[0017] Figure 17 A schematic structural diagram of a display device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0019] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0020] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0021] Before describing the technical solutions provided by this application, in order to facilitate understanding of the embodiments of this application, this application first specifically describes the problems existing in the prior art:

[0022] Display panels typically include driver circuits, such as pixel driver circuits and gate driver circuits. The pixel driver circuits are used to drive the light-emitting elements of the display panel to emit light, while the gate driver circuits are used to generate gate control signals. These driver circuits include transistors, which include oxide transistors. With the advancement of display technology, there is a growing demand for high-mobility oxide transistors. However, the applicant has discovered that high-mobility oxide transistors are prone to having their active layers etched through during the source-drain overlap process, resulting in NG oxide transistors.

[0023] The inventors of this application first studied and analyzed the root causes of the above technical problems. The specific research and analysis process is as follows:

[0024] As the indium content of the active layer of the oxide transistor increases, the carrier concentration increases, thereby increasing the mobility of the oxide transistor. However, the higher the indium content of the active layer of the oxide transistor, the easier it is to make the active layer conductive. Conversely, the lower the indium content of the active layer, the easier it is to insulate the active layer. In order to ensure the semiconductor performance of the active layer of the oxide transistor (i.e., to prevent the active layer from being completely conductive or completely insulated), and in order to pursue high-mobility oxide transistors, it is necessary to avoid the indium content of the active layer being too high. Therefore, when the indium ion concentration of the active layer is constant, the thickness of the active layer of the oxide transistor needs to be set relatively thin. For example, the thickness of the active layer of the oxide transistor is less than 10nm. When using vias to overlap the source and drain electrodes with the active layer, based on current process capabilities, due to the thin thickness of the active layer, it is easy for the vias to pierce the active layer, thereby causing the oxide transistor to have NG, affecting the yield rate of the display panel.

[0025] In light of the applicant's research findings, the present invention provides a display panel and display device that address the problem of low display panel yield caused by the easy etching of the active layer of oxide transistors in related technologies. The display panel and display device provided by the present invention are described below with reference to the accompanying drawings.

[0026] The display panel provided in the embodiment of the present application can be an organic light-emitting diode (OLED) display panel. In other implementations of the present application, the display panel can also be a liquid crystal display panel, a micro light-emitting diode (Micro LED) display panel, a quantum dot display panel, etc., which is not limited in the present application. The display panel of the embodiment of the present application can be presented in various forms, some examples of which are described below.

[0027] like Figure 1 As shown, the display panel 100 may include a substrate 10 and an oxide transistor 20. The oxide transistor 20 is disposed on one side of the substrate 10.

[0028] The substrate 10 may be a flexible substrate, for example, a polyimide (PI) substrate, or a rigid substrate, for example, a glass substrate.

[0029] The oxide transistor 20 includes an active layer 21, and the active layer 21 includes a plurality of sub-film layers 210 stacked. It is understood that the plurality of sub-film layers 210 can be stacked in a direction away from the substrate 10. The number of sub-film layers 210 can be two or more. Figure 1 The number of sub-film layers 210 is shown as three, which is not intended to limit the present application. At least two sub-film layers 210 in the plurality of sub-film layers 210 have different indium (IN) ion concentrations. For example, Figure 1 The indium ion concentrations of the three sub-film layers 210 shown may be different, where the indium ion concentration may be understood as the number of indium ions per unit volume.

[0030] Continue to refer Figure 1 , the oxide transistor 20 may further include a gate 22, a source 23 and a drain 24. The display panel 100 may further include a gate insulating layer 31 and an interlayer insulating layer 32. The gate insulating layer 31 is located between the gate 22 and the active layer 21, the interlayer insulating layer 32 covers the gate 22, and the source 23 and the drain 24 are located on the side of the interlayer insulating layer 32 facing away from the substrate 10. The source 23 and the drain are each connected to the active layer 21 through a via 33. It can be understood that the orthographic projection of the gate 22 on the substrate 10 overlaps with the orthographic projection of the active layer 21 on the substrate 10. The source 23 and the drain 24 are overlapped with the active layer 21 through the via 33. In addition, Figure 1 The oxide transistor 20 is illustrated as a single-gate transistor. The oxide transistor 20 may also be a double-gate transistor, which is not limited in this application.

[0031] The display panel provided by the embodiments of the present application is no longer limited to setting the active layer of the oxide transistor as a single film layer containing only one indium ion concentration. Instead, the active layer of the oxide transistor is divided into multiple stacked sub-film layers, and at least two sub-film layers have different indium ion concentrations. Compared with a single film layer containing only one indium ion concentration, the overall thickness of the active layer can be increased while the total indium content of the active layer remains unchanged. In other words, while avoiding the active layer from being completely conductive and ensuring the high mobility of the oxide transistor, by dividing the active layer into sub-film layers with different indium ion concentrations, the overall thickness of the active layer can be increased, and the via holes that overlap the source and drain electrodes with the active layer can be prevented from penetrating the active layer, thereby preventing the oxide transistor from having NGs and improving the yield rate of the display panel.

[0032] To better understand the structure of the display panel provided by the embodiment, please refer to Figure 2 The display panel 100 provided in an embodiment of the present application may include a plurality of pixel driving circuits PX. The plurality of pixel driving circuits PX may be distributed in an array in the display area. For example, the plurality of pixel driving circuits PX may be distributed in an array in a first direction X and a second direction Y that intersect.

[0033] Exemplarily, the display panel 100 may further include a driver chip IC, a first gate driver circuit VSR1, a second gate driver circuit VSR2, a power signal line PVDD, a data signal line Data, a reference signal line Vref, a first scan signal line 051, a second scan signal line 052, a light emitting control signal line Emit, etc.

[0034] The first gate drive circuit VSR1 may include multiple cascaded shift registers. The first gate drive circuit VSR1 is connected to the pixel drive circuit PX via a first scan signal line O51 and a second scan signal line O52. The first gate drive circuit VSR1 is configured to provide scan signals to the pixel drive circuit PX. A driver chip IC provides a first start signal STV1 to the first gate drive circuit VSR1. Furthermore, the scan signals transmitted by the second scan signal line O52 of the current row and the first scan signal line O51 of the next row can be the same.

[0035] The second gate drive circuit VSR2 may include multiple cascaded shift registers. The second gate drive circuit VSR2 is connected to the pixel drive circuit PX via the emission control signal line Emit. The second gate drive circuit VSR2 is configured to provide an emission control signal to the pixel drive circuit PX. The driver chip IC provides a second start signal STV2 to the second gate drive circuit VSR2.

[0036] In addition, a clock signal line (not shown in the figure), a high-level signal line (VGH, not shown in the figure), and a low-level signal line (VGL, not shown in the figure) can be connected between the first gate drive circuit VSR1 and the drive chip IC, as well as between the second gate drive circuit VSR2 and the drive chip IC. The drive chip IC can also provide clock signals, high-level signals, and low-level signals to the first gate drive circuit VSR1 and the second gate drive circuit VSR2.

[0037] For example, a gate driving circuit capable of simultaneously generating a scanning signal and a light-emitting control signal may also be provided, but this application does not limit this.

[0038] The power signal line PVDD is used to provide a power voltage to the pixel driving circuit PX. The voltage on the power signal line PVDD can be a positive voltage. The reference signal line Vref is used to provide a reset voltage signal. The voltage on the reference signal line Vref can be a negative voltage.

[0039] like Figure 3 As shown, the display panel may include a display area AA and a non-display area NA, and the non-display area NA may include an ink area INK. For example, the display panel includes a substrate 10 and a driving device layer Array disposed on one side of the substrate 10. Taking the display panel as an OLED display panel as an example, Figure 3 Also shown are the planarization layer PLN, pixel definition layer PDL, light-emitting elements (including an anode RE, an organic light-emitting layer OM, and a cathode SE), support pillars PS, thin-film encapsulation layers (including a first inorganic layer CVD1, an organic layer IJP, and a second inorganic layer CVD2), an optical adhesive layer OCA, and a cover plate CG. The first and second gate drive circuits VSR1 and VSR2 can be located in the non-display area of ​​the driver device layer array, while the pixel drive circuit PX can be located in the display area of ​​the driver device layer array.

[0040] Exemplarily, the display panel may further include a multiplexer circuit (Demux circuit, not shown in the figure), an array substrate test circuit (AT circuit, not shown in the figure), a dot screen test circuit (CT circuit, not shown in the figure), etc.

[0041] At least one of the first gate driving circuit VSR1 , the second gate driving circuit VSR2 , the pixel driving circuit PX, the Demux circuit, the AT circuit, and the CT circuit may include the oxide transistor provided in the embodiment of the present application.

[0042] In some optional embodiments, the material of each sub-layer 210 of the active layer includes indium gallium zinc oxide. In other words, the oxide transistor 20 can be indium gallium zinc oxide (IGZO). Of course, the oxide transistor 20 can also be other types of transistors containing indium and oxygen.

[0043] For example, the sub-layers of the active layer can be formed using metal-organic chemical vapor deposition (MOCVD). For example, MOCVD can be used to adjust the gas composition and change the reaction products of each sub-layer, thereby ensuring film uniformity with a thickness of less than 30 angstroms. Of course, other film-forming technologies can also be used to form the sub-layers of the active layer. Here, 10 angstroms is equal to 1 nm.

[0044] Exemplarily, the number of sub-membrane layers 210 can be an odd number, such as 3, 5, 7, etc.; the number of sub-membrane layers 210 can also be an even number, such as 2, 4, 6, etc.

[0045] Exemplarily, the total thickness of the multiple sub-membrane layers 210 can be greater than or equal to 10 nm to avoid the overall thickness of the active layer 21 being too small, thereby minimizing the possibility of vias overlapping the source and drain electrodes with the active layer being etched through the active layer when the oxide transistor has high mobility.

[0046] In some optional embodiments, in the direction away from the substrate 10, multiple sub-film layers 210 can be arranged in a manner of alternating high and low indium ion concentration film layers, or, in the direction away from the substrate 10, multiple sub-film layers 210 can be arranged in a manner of alternating low and high indium ion concentration film layers.

[0047] For example, Figure 1 The relationship between the indium ion concentrations of the three sub-film layers 210 shown can be: the indium ion concentration of the sub-film layer 2112 located in the middle is greater than the indium ion concentrations of the sub-film layers 211 and 212 on both sides thereof. Figure 4 The relationship between the indium ion concentrations of the two sub-film layers 210 shown may be: the indium ion concentration of the sub-film layer 213 close to the substrate 10 is smaller than the indium ion concentration of the sub-film layer 214 far from the substrate 10 .

[0048] In the embodiment of the present application, by arranging the sub-film layers in an alternating manner of high and low indium ion concentration film layers or in an alternating manner of low and high indium ion concentration film layers, the sub-film layers of high and low indium ion concentrations can be better coordinated with each other, thereby better adjusting the performance of the oxide transistor.

[0049] The applicant also found that as time goes by, the indium in the active layer 21 will diffuse outward. For example, the indium in the active layer 21 will diffuse into the insulating layer adjacent to it, such as the gate insulating layer. Optionally, an insulating layer may also be provided between the active layer 21 and the substrate 10. In this way, in the thickness direction of the display panel, the indium in the active layer 21 will diffuse into the insulating layers on both sides thereof, and the indium will destroy the insulating properties of the insulating layer. The more indium diffuses into the insulating layer, the greater the destructive effect on the insulating properties of the insulating layer. If the insulating properties of the insulating layer are destroyed, its dielectric constant will also change, which will lead to the deterioration of the device performance of the oxide transistor 20, such as the deterioration of the threshold voltage and mobility of the oxide transistor 20, affecting the working stability of the oxide transistor 20.

[0050] In some optional embodiments, in order to minimize the amount of indium diffusion from the active layer 21 to the insulating layer, reduce damage to the insulating layer, and ensure the operating stability of the oxide transistor 20, when the active layer 21 includes an odd number of sub-film layers 210, the indium ion concentration of the two outermost sub-film layers 210 of the multiple sub-film layers 210 can be lower than the indium ion concentration of the adjacent sub-film layers 210. Figure 1 , still taking the example of the active layer 21 including three sub-film layers 210, and in the thickness direction of the display panel, the sub-film layer 210 closest to the substrate 10 is the first sub-film layer 211, and the sub-film layer farthest from the substrate 10 is the second sub-film layer 212. The first sub-film layer 211 and the second sub-film layer 212 are both adjacent to the middle sub-film layer 2112. The indium ion concentration of the first sub-film layer 211 is lower than that of the adjacent sub-film layer 2112, and the indium ion concentration of the second sub-film layer 212 is lower than that of the adjacent sub-film layer 2112. In other words, the indium ion concentration of the middle sub-film layer 2112 is the highest.

[0051] In the embodiment of the present application, since the indium ion concentration of the two outermost sub-film layers 210 is respectively lower than the indium ion concentration of the adjacent sub-film layers 210, the amount of indium diffused from the two outermost sub-film layers 210 to the adjacent insulating layer will be less, thereby reducing the amount of indium diffused from the active layer 21 to the insulating layer, reducing the destructiveness to the insulating layer, and thereby avoiding the deterioration of the device performance of the oxide transistor 20 and ensuring the operating stability of the oxide transistor 20.

[0052] It can be understood that the fewer sub-film layers the active layer contains, the fewer process steps are required. Therefore, while ensuring that the oxide transistor has high mobility and avoiding the vias that overlap the source and drain with the active layer and penetrate the active layer, the fewer sub-film layers the active layer contains, the more conducive it is to reducing costs and improving production efficiency.

[0053] The applicant has found through research that in some optional embodiments, the active layer may include two sub-layers while ensuring that the oxide transistor has high mobility and avoiding the via holes that overlap the source and drain electrodes with the active layer from penetrating the active layer. Figure 4 As shown, the active layer 21 includes two sub-film layers 210, which are a third sub-film layer 213 and a fourth sub-film layer 214; the fourth sub-film layer 214 is located on the side of the third sub-film layer 213 facing away from the substrate 10, and the indium ion concentration of the fourth sub-film layer 214 can be greater than the indium ion concentration of the third sub-film layer 213.

[0054] In the embodiment of the present application, on the one hand, only two sub-film layers are provided to ensure that the oxide transistor has high mobility and to avoid the via holes where the source and drain overlap with the active layer from penetrating the active layer; on the other hand, the indium ion concentration of the fourth sub-film layer 214 is greater than the indium ion concentration of the third sub-film layer 213, so the carrier concentration of the fourth sub-film layer 214 is also higher than the carrier concentration of the third sub-film layer 213. The fourth sub-film layer 214 with a high carrier concentration is located on the upper side, and the via holes where the source and drain overlap with the active layer must be in contact with the fourth sub-film layer 214, which can ensure that the source and drain have good conductivity.

[0055] As described above, the higher the indium content in the active layer, the easier it is to make the active layer conductive. Since the fourth sub-film layer 214 has a relatively high indium ion concentration, in order to prevent the fourth sub-film layer 214 from being completely conductive and losing its semiconductor properties, the indium content of the fourth sub-film layer 214 can be avoided to be relatively high. In some optional embodiments, the thickness of the fourth sub-film layer 214 can be less than the thickness of the third sub-film layer 213. In this way, even if the indium ion concentration of the fourth sub-film layer 214 is relatively high relative to the indium ion concentration of the third sub-film layer 213, the fourth sub-film layer 214 will not be completely conductive and lose its semiconductor properties due to the smaller thickness of the fourth sub-film layer 214. In addition, the larger thickness of the third sub-film layer 213 acts as a via etching barrier, which can prevent the via holes overlapping the source and drain electrodes with the active layer from penetrating the active layer.

[0056] In some optional embodiments, the thickness of the fourth sub-layer 214 may be less than 50 angstroms, and the thickness of the third sub-layer 213 may be less than 100 angstroms. For example, the total thickness of the fourth sub-layer 214 and the third sub-layer 213 may be greater than or equal to 10 nm.

[0057] As mentioned above, the indium in the active layer 21 will diffuse outward, and the indium ion concentrations of the two outermost sub-film layers 210 in the multiple sub-film layers 210 are respectively smaller than the indium ion concentrations of the adjacent sub-film layers 210, which can minimize the diffusion of indium from the active layer 21 to the insulating layer and reduce the damage to the insulating layer. In addition, while ensuring that the oxide transistor has high mobility and avoiding the via holes overlapping the source and drain with the active layer from penetrating the active layer, the fewer sub-film layers the active layer contains, the more conducive it is to reducing costs and improving production efficiency. In some optional embodiments, the active layer may include three sub-film layers. Figure 5 As shown, the three sub-film layers 210 are a fifth sub-film layer 215, a sixth sub-film layer 216, and a seventh sub-film layer 217. The sixth sub-film layer 216 is located on the side of the fifth sub-film layer 215 facing away from the substrate 10, and the seventh sub-film layer 217 is located on the side of the sixth sub-film layer 216 facing away from the substrate 10. The indium ion concentrations of the fifth sub-film layer 215 and the seventh sub-film layer 217 can both be lower than the indium ion concentration of the sixth sub-film layer 216. It can be understood that the indium ion concentrations of the fifth sub-film layer 215, the sixth sub-film layer 216, and the seventh sub-film layer 217 are in a low-high-low relationship.

[0058] In the embodiment of the present application, on the one hand, the three sub-film layers are arranged in a low-high-low indium ion concentration order, so that the indium ion concentration of the two sub-film layers located on the outer sides is relatively low, which can minimize the amount of indium diffusion from the active layer to the insulating layer and reduce the destructiveness to the insulating layer; on the other hand, the active layer only includes three sub-film layers, which can ensure that the oxide transistor has a high mobility and avoid the via holes overlapping the source and drain and the active layer from penetrating the active layer, while avoiding the active layer from having too many sub-film layers included, thereby reducing process costs and improving production efficiency.

[0059] In some optional embodiments, the thickness of the fifth sub-layer 215 and the thickness of the sixth sub-layer 216 may both be greater than the thickness of the seventh sub-layer 217. As described above, the lower the indium content of the active layer, the easier it is to insulate the active layer. Therefore, the thickness of the sixth sub-layer 216, which has a higher indium ion concentration, can be set to be greater than the thickness of the seventh sub-layer 217, thereby avoiding a low indium content in the active layer as a whole and preventing the active layer from being insulated. Furthermore, the greater thickness of the fifth sub-layer 215 acts as a via etching barrier, preventing the vias overlapping the source and drain electrodes with the active layer from penetrating the active layer.

[0060] In some optional embodiments, the thickness of the fifth sub-layer 215 may be less than 100 angstroms, the thickness of the sixth sub-layer 216 may be less than 50 angstroms, and the thickness of the seventh sub-layer 217 may be between 10 angstroms and 30 angstroms. For example, the total thickness of the fifth sub-layer 215, the sixth sub-layer 216, and the seventh sub-layer 217 may be greater than or equal to 10 nm.

[0061] In some optional embodiments, please continue to refer to Figure 5 , still taking the example of a display panel including a gate insulating layer 31 and an interlayer insulating layer 32, and an oxide transistor 20 also including a gate 22, a source 23, and a drain 24, the gate insulating layer 31 is located on the side of the active layer 21 facing away from the substrate 10, the gate 22 is located on the side of the gate insulating layer 31 facing away from the substrate 10, the interlayer insulating layer 32 covers the gate 22, and the source 23 and drain 24 are located on the side of the interlayer insulating layer 32 facing away from the substrate 10. The source 23 and drain 24 are each connected to the active layer 21 through a via 33. The via 33 can penetrate the seventh sub-layer 217 and the sixth sub-layer 216 and extend to the fifth sub-layer 215. In this way, the via 33 must be in contact with the sixth sub-layer 216, which has a higher indium ion concentration. Since a higher indium ion concentration leads to a higher carrier concentration, the contact between the via 33 and the sixth sub-layer 216 ensures that the source 23 and drain 24 have good conductivity. In addition, the via hole 33 does not penetrate the fifth sub-layer 215, which can ensure that the via hole does not penetrate the active layer, avoid NG of the oxide transistor, and thus improve the yield rate of the display panel.

[0062] Exemplarily, the via hole 33 may extend to the surface of the fifth sub-layer 215 facing away from the substrate 10 , or the via hole 33 may extend into the fifth sub-layer 215 , that is, the via hole 33 may have a certain depth inside the fifth sub-layer 215 .

[0063] In some optional embodiments, such as Figure 6 As shown, the sixth sub-film layer 216 may include a source-drain overlapping region 161 and a non-overlapping region 162, and the indium ion concentration of the source-drain overlapping region 161 may be greater than the indium ion concentration of the non-overlapping region 162. It is understandable that the source-drain overlapping region 161 overlaps with the source 23 and the drain 24, and the non-overlapping region 162 does not need to overlap with the source 23 and the drain 24. Exemplarily, the number of source-drain overlapping regions 161 may be two, one of which is connected to the source 23 through the via 33, and the other is connected to the drain 24 through the via 33. The orthographic projection of the via 33 on the substrate 10 overlaps with the orthographic projection of the source-drain overlapping region 161 on the substrate 10, and the orthographic projection of the via 33 on the substrate 10 does not overlap with the orthographic projection of the non-overlapping region 162 on the substrate 10.

[0064] The higher the indium ion concentration, the higher the carrier concentration. By dividing the sixth sub-film layer 216 into a source-drain overlapping area 161 with a high indium ion concentration and a non-overlapping area 162 with a low indium ion concentration, the source 23 and the drain 24 are overlapped with the source-drain overlapping area 161 with a high indium ion concentration, which can further ensure that the source 23 and the drain 24 have good conductivity.

[0065] In some optional embodiments, please refer to Figure 7 The display panel 100 may include a capacitor 40, and one electrode plate 41 of the capacitor 40 may be provided in the same layer and with the same material as the source-drain overlap region 161. Since the indium ion concentration in the source-drain overlap region 161 is relatively high, the carrier concentration in the source-drain overlap region 161 is relatively high, and the conductivity of the source-drain overlap region 161 is relatively good. In this way, while ensuring that one electrode plate 41 of the capacitor 40 has good conductivity, the one electrode plate 41 of the capacitor 40 and the source-drain overlap region 161 can be prepared using the same process, thereby simplifying the process steps.

[0066] For example, the other plate 42 of the capacitor 40 may be provided on the metal film layer of the display panel. Figure 7 As shown, the other plate 42 of the capacitor 40 is provided in the same layer and with the same material as the gate 22 . This is merely an example and is not intended to limit the present application.

[0067] In some optional embodiments, when the indium ion concentration of each sub-film layer is uniform, one plate of the capacitor and the sub-film layer with the high indium ion concentration among the at least two sub-film layers can be directly set to be in the same layer and made of the same material. Figure 8 As shown, taking the number of sub-film layers as three as an example, the indium ion concentration of the middle sub-film layer 2112 is the highest, and one electrode plate 41 of the capacitor 40 can be set to the same layer and the same material as the sub-film layer 2112. Similarly, the indium ion concentration of the sub-film layer 2112 is higher, and therefore the carrier concentration of the sub-film layer 2112 is higher, and the conductivity of the sub-film layer 2112 is better. In this way, while ensuring that the one electrode plate 41 of the capacitor 40 has good conductivity, the one electrode plate 41 of the capacitor 40 and the sub-film layer 2112 can be prepared using the same process, thereby simplifying the process steps.

[0068] For example, the other plate 42 of the capacitor 40 may be provided on the metal film layer of the display panel. Figure 8 As shown, the other plate 42 of the capacitor 40 is provided in the same layer and with the same material as the gate 22 . This is merely an example and is not intended to limit the present application.

[0069] In some optional embodiments, such as Figure 9 As shown, the display panel may include a first gate insulating layer 311 and an interlayer insulating layer 32, and the oxide transistor 20 further includes a first gate electrode 221, a source electrode 23, and a drain electrode 24. The first gate insulating layer 311 is located on the side of the active layer 21 facing away from the substrate 10, the first gate electrode 221 is located on the side of the first gate insulating layer 311 facing away from the substrate 10, the interlayer insulating layer 32 covers the first gate electrode 221, the source electrode 23 and the drain electrode 24 are located on the side of the interlayer insulating layer 32 facing away from the substrate 10; the source electrode 23 and the drain electrode 24 are each connected to the active layer 21 through a via 33. For example, Figure 9 As shown, the active layer 21 may include sub-film layers 215 , 216 , and 217 , wherein the indium ion concentrations of the sub-film layers 215 and 217 may be lower than the indium ion concentration of the sub-film layer 216 .

[0070] In order to prevent the via 33 from being over-engraved, that is, to prevent the via 33 from engraving through the entire active layer 21, the via 33 can be in surface contact with the active layer 21, that is, the contact surface between the via 33 and the active layer 21 can be set to be relatively large. The diameter of the via 33 is θ, where 2μm≤θ≤3μm. For example, θ can be equal to 2μm, 2.5μm, 3μm, etc. The via 33 can be a circular hole, and the via 33 has a certain depth, and the diameters corresponding to different depth positions can be different. For example, the minimum diameter of the via 33 can be greater than or equal to 2μm and less than or equal to 3μm.

[0071] Since 2 μm≤θ≤3 μm, the diameter of the via hole 33 is set to be relatively large, which can increase the contact area between the via hole 33 and the active layer 21. It can be understood that in the case of Figure 9 The arrangement order of low, high and low indium ion concentrations shown can also increase the contact area between the via 33 and the sub-membrane layer 216. On the one hand, it can prevent the via 33 from being over-engraved. On the other hand, it can increase the transmission area, reduce the transmission resistance, and improve the stability of signal transmission.

[0072] For example, the contact resistance between the via hole 33 and the active layer 21 may be less than or equal to 3000 ohms.

[0073] In the display panel provided by the embodiment of the present application, the oxide transistor 20 may be a dual-gate transistor. Figure 9 For example, the oxide transistor 20 may further include a second gate electrode 222, and the display panel may further include a second gate insulating layer 312. The second gate insulating layer 312 is located on a side of the active layer 21 facing away from the first gate insulating layer 311, and the second gate electrode 222 is located on a side of the second gate insulating layer 312 facing away from the active layer 21. In the case where the oxide transistor 20 may be a dual-gate transistor, Figure 9 The structure of each sub-layer of the active layer 21 is merely an example and is not intended to limit the specific structure of the oxide transistor 20 .

[0074] In some optional embodiments, in order to further increase the contact area between the via hole 33 and the active layer 21, as shown in FIG. Figure 10 and Figure 11 As shown, the side surface of the active layer 21 near the via hole 33 is the side surface 01, and the side surface 01 can be raised away from the via hole 33. The active layer 21 includes multiple sub-membrane layers 210. For example, the via hole 33 penetrates the sub-membrane layers 217 and 216, and the side surfaces 01 of the sub-membrane layers 217 and 216 can be raised away from the via hole 33.

[0075] In some optional embodiments, in order to further increase the contact area between the via hole 33 and the active layer 21, in some optional embodiments, please continue to refer to Figure 10 The surface of the active layer 21 facing the substrate 10 is the bottom surface 02. In the direction F from the active layer 21 toward the film layer where the source electrode 23 is located, the angle between the cut surface of the side surface 01 and the bottom surface 02 can gradually increase. For example, in the direction F from the active layer 21 toward the film layer where the source electrode 23 is located, the side surface 01 has cut surfaces 031 and 032. The angle a1 between the cut surface 031 and the bottom surface 02 can be smaller than the angle a2 between the cut surface 032 and the bottom surface 02. Because the angle between the cut surface of the side surface 01 and the bottom surface 02 gradually increases in the direction F from the active layer 21 toward the film layer where the source electrode 23 is located, it can be understood that the diameter of the via 33 gradually increases in the direction F from the active layer 21 toward the film layer where the source electrode 23 is located. Therefore, the contact area between the via 33 and the active layer also gradually increases, thereby further increasing the contact area between the via 33 and the active layer 21. Furthermore, this arrangement can reduce the difficulty of fabricating the via.

[0076] In some optional embodiments, still taking the example that the indium ion concentration of the fifth sub-film layer 215 and the indium ion concentration of the seventh sub-film layer 217 are both less than the indium ion concentration of the sixth sub-film layer 216, further, the indium ion concentration of the fifth sub-film layer 215 can be greater than the indium ion concentration of the seventh sub-film layer 217. Figure 12 As shown, the display panel 100 may include an oxide transistor 20 and a low-temperature polysilicon transistor 70 . The display panel 100 may also be referred to as a low-temperature polycrystalline oxide (LTPO) type display panel.

[0077] Specifically, the display panel 100 may further include a second gate insulating layer 312 located on the side of the active layer of the oxide transistor 20 facing the substrate 10, an interlayer dielectric layer 35 located on the side of the second gate insulating layer 312 facing the substrate 10, a second interlayer insulating layer 34 located on the side of the interlayer dielectric layer 35 facing the substrate 10, and a third gate insulating layer 313 located on the side of the second interlayer insulating layer 34 facing the substrate 10. The oxide transistor 20 may further include a second gate 222 located between the second gate insulating layer 312 and the interlayer dielectric layer 35. The low-temperature polysilicon transistor 70 may include an active layer 71, a gate 72, a source 73, and a drain 74. The active layer 71 is located between the substrate and the third gate insulating layer 313, the gate 72 is located between the third gate insulating layer 313 and the second interlayer insulating layer 34, the source 73 and the drain 74 are located on the side of the interlayer insulating layer 32 facing away from the substrate, and the source 73 and the drain 74 are each connected to the active layer 71 through a via.

[0078] The interlayer insulating layer 32 typically includes silicon oxide (SiOx), and the second interlayer insulating layer 34 typically includes silicon nitride (SiNx). The second interlayer insulating layer 34 contains hydrogen. If hydrogen diffuses into the active layer 20 of the oxide transistor, it will cause a short channel effect in the active layer 20, thereby affecting the stability of the oxide transistor 20. In order to minimize the diffusion of hydrogen in the second interlayer insulating layer 34 into the active layer 20 of the oxide transistor, the thickness of the second gate insulating layer 312 can be set to be greater than the thickness of the first gate insulating layer 311. However, since the thickness of the second gate insulating layer 312 is greater than the thickness of the first gate insulating layer 311, the carrier mobility of the second gate insulating layer 312 is relatively low. Therefore, the indium ion concentration of the fifth sub-film layer 215 can be increased, thereby improving or avoiding the problem of relatively low carrier mobility in the second gate insulating layer 312.

[0079] In some optional embodiments, such as Figures 13 to 15 As shown, still taking the example that the indium ion concentration of the fifth sub-film layer 215 and the indium ion concentration of the seventh sub-film layer 217 are both lower than the indium ion concentration of the sixth sub-film layer 216, further, the sixth sub-film layer 216 includes an upper surface 051 and a side surface 052, the upper surface 051 being the surface of the sixth sub-film layer 216 facing away from the substrate 10, the side surface 052 being connected to the upper surface 051, and the seventh sub-film layer 217 being in contact with the upper surface 051 and the side surface 052. In other words, the seventh sub-film layer 217 covers the sixth sub-film layer 216, and the sixth sub-film layer 216 is surrounded by the fifth sub-film layer 215 and the seventh sub-film layer 217, which have lower indium ion concentrations. This can better prevent the indium in the sixth sub-film layer 216 from diffusing into the insulating layer surrounding the active layer, thereby better preventing the insulating properties of the insulating layer from being destroyed.

[0080] It can be understood that the side surface 052 here faces away from the via hole 33 , and the side surface 01 mentioned above is in contact with the via hole 33 .

[0081] In addition, when the sixth sub-film layer 216 is further divided into the source-drain overlapping region 161 and the non-overlapping region 162, the seventh sub-film layer 217 covers the entire sixth sub-film layer 216. Figure 14 As shown, the source-drain overlapping region 161 may be located on both sides of the non-overlapping region 162; or, as shown in FIG. Figure 15 As shown, any source-drain overlapping region 161 may be surrounded by a non-overlapping region 162 .

[0082] The applicant has found that when hydrogen diffuses into a sub-film layer with a high indium ion concentration, a short channel effect will occur in the sub-film layer with a high indium ion concentration, thereby affecting the stability of the transistor. In some optional embodiments, still taking the example that the indium ion concentration of the fifth sub-film layer 215 and the indium ion concentration of the seventh sub-film layer 217 are both lower than the indium ion concentration of the sixth sub-film layer 216, the crystallinity of the fifth sub-film layer 215 and the crystallinity of the seventh sub-film layer 217 can both be greater than the crystallinity of the sixth sub-film layer 216. Since the crystallinity of the fifth sub-film layer 215 and the crystallinity of the seventh sub-film layer 217 are larger, there will be more oxygen ions in the fifth sub-film layer 215 and the seventh sub-film layer 217, and the oxygen ions will react chemically with the hydrogen ions to generate hydroxide ions, such as H + +O 2- →OH - , thus preventing hydrogen ions from damaging the sixth sub-film layer 216 .

[0083] In some optional embodiments, still taking the example where the indium ion concentrations of the fifth sub-layer 215 and the seventh sub-layer 217 are both lower than the indium ion concentration of the sixth sub-layer 216, the gallium content of the fifth sub-layer 215 can be the highest among the fifth sub-layer 215, the sixth sub-layer 216, and the seventh sub-layer 217. This can make electronic operation more stable and improve the operational stability of the oxide transistor 20.

[0084] In some optional embodiments, still taking the example where the indium ion concentration of the fifth sub-layer 215 and the indium ion concentration of the seventh sub-layer 217 are both lower than the indium ion concentration of the sixth sub-layer 216, the oxygen content of the sixth sub-layer 216 may be the lowest among the fifth sub-layer 215, the sixth sub-layer 216, and the seventh sub-layer 217. Since the sixth sub-layer 216 has the lowest oxygen content, it has more oxygen vacancies. More oxygen vacancies lead to a greater carrier concentration, which can increase the carrier concentration of the sixth sub-layer 216, thereby improving the driving capability of the oxide transistor 20.

[0085] In some optional embodiments, such as Figure 16As shown, the display panel 100 may include a first display area A1 and a second display area A2. The pixel density (PPI) of the first display area A1 is less than or equal to the pixel density of the second display area A2. For example, the first display area A1 may be at least partially surrounded by the second display area A2. A camera may be provided corresponding to the first display area A1, thereby forming a full-screen structure with an under-screen camera. Therefore, the transmittance of the first display area A1 needs to be higher than that of the second display area A2. The first display area A1 is provided with a first pixel driving circuit PX1, and the second display area A2 is provided with a second pixel driving circuit PX2. Since the oxide transistor 20 provided in the embodiment of the present application can increase the on-state current and driving capability, and the oxide transistor 20 has higher transparency than the low-temperature polysilicon (LTPS) transistor, the driving transistor in the first pixel driving circuit PX1 can be the oxide transistor provided in the embodiment of the present application, thereby improving the transmittance of the first display area and enhancing the light capture of the camera. Furthermore, all transistors in the first pixel driving circuit PX1 can be the oxide transistor provided in the embodiment of the present application. Compared with oxide transistors, low-temperature polysilicon transistors have higher mobility, so the driving transistors in the second pixel driving circuit PX can be low-temperature polysilicon transistors. Oxide transistors have lower leakage current, so at least some of the switching transistors in the second pixel driving circuit PX can be oxide transistors provided in the embodiment of the present application to ensure the driving capability and stability of the second pixel circuit.

[0086] This application also provides a display device, including the display panel provided by this application. Figure 17 , Figure 17 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Figure 17 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Figure 17 The embodiment only uses a mobile phone as an example to illustrate the display device 1000. It is understandable that the display device provided in the embodiment of the present application can be other display devices with display functions, such as a computer, a television, and an in-vehicle display device, and this application does not specifically limit this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the detailed description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0087] While the embodiments described above are not exhaustive, they do not limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: substrate; an oxide transistor located on one side of the substrate, the oxide transistor comprising an active layer, the active layer comprising a plurality of stacked sub-layers, at least two of the sub-layers having different indium ion concentrations; The active layer includes three sub-film layers, which are respectively a fifth sub-film layer, a sixth sub-film layer and a seventh sub-film layer; the sixth sub-film layer is located on the side of the fifth sub-film layer facing away from the substrate, and the seventh sub-film layer is located on the side of the sixth sub-film layer facing away from the substrate; the indium ion concentration of the fifth sub-film layer and the indium ion concentration of the seventh sub-film layer are both lower than the indium ion concentration of the sixth sub-film layer; the sixth sub-film layer includes a source-drain overlapping region and a non-overlapping region, and the indium ion concentration of the source-drain overlapping region is higher than the indium ion concentration of the non-overlapping region; The sixth sub-film layer includes an upper surface and a side surface, the upper surface is the surface of the sixth sub-film layer facing away from the substrate, the side surface of the sixth sub-film layer is connected to the upper surface, and the seventh sub-film layer is in contact with the upper surface and the side surface of the sixth sub-film layer; The display panel further includes a gate insulating layer and an interlayer insulating layer, and the oxide transistor further includes a gate, a source electrode, and a drain electrode; The gate insulating layer is located on a side of the active layer facing away from the substrate, the gate is located on a side of the gate insulating layer facing away from the substrate, the interlayer insulating layer covers the gate, and the source and drain are located on a side of the interlayer insulating layer facing away from the substrate; The source electrode and the drain electrode are each connected to the active layer through a via hole, and the via hole passes through the seventh sub-film layer and the sixth sub-film layer and extends to the fifth sub-film layer.

2. The display panel according to claim 1, wherein: The thickness of the fifth sub-film layer and the thickness of the sixth sub-film layer are both greater than the thickness of the seventh sub-film layer.

3. The display panel according to claim 1, wherein: The indium ion concentration of the fifth sub-film layer is greater than the indium ion concentration of the seventh sub-film layer.

4. The display panel according to claim 2, wherein: The thickness of the fifth sub-film layer is less than 100 angstroms, the thickness of the sixth sub-film layer is less than 50 angstroms, and the thickness of the seventh sub-film layer is between 10 angstroms and 30 angstroms.

5. The display panel according to claim 1, wherein: The crystallinity of the fifth sub-film layer and the crystallinity of the seventh sub-film layer are both greater than the crystallinity of the sixth sub-film layer.

6. The display panel according to claim 1, wherein: The diameter of the via hole is , where 2μm≤ ≤3μm.

7. The display panel according to claim 6, wherein: The surface of the active layer close to the via hole is the side surface of the active layer, and the side surface of the active layer is away from the via hole protrusion.

8. The display panel according to claim 7, wherein: In a direction from the active layer to the film layer where the source electrode is located, an angle between a cut surface of the side of the active layer and a surface of the active layer facing the substrate gradually increases.

9. The display panel according to claim 1, wherein: The display panel includes a capacitor, and one electrode plate of the capacitor and at least two sub-film layers with a high indium ion concentration are arranged in the same layer and made of the same material.

10. The display panel according to claim 9, wherein: The display panel includes a capacitor, and one plate of the capacitor and the source-drain overlapping region are provided in the same layer and made of the same material.

11. The display panel according to claim 1, wherein Among the fifth sub-film layer, the sixth sub-film layer and the seventh sub-film layer, the gallium content of the fifth sub-film layer is the largest.

12. The display panel according to claim 1, wherein Among the fifth sub-film layer, the sixth sub-film layer and the seventh sub-film layer, the sixth sub-film layer has the smallest oxygen content.

13. The display panel according to claim 1, wherein The display panel includes a first display area and a second display area, the pixel density of the first display area is less than or equal to the pixel density of the second display area, the first display area is provided with a first pixel circuit, and the second display area is provided with a second pixel circuit; The driving transistor in the first pixel circuit is the oxide transistor, the driving transistor in the second pixel circuit is a low-temperature polysilicon transistor, and at least part of the switching transistors in the second pixel circuit are the oxide transistor.

14. The display panel according to claim 1, wherein The material of the sub-film layer includes indium gallium zinc oxide.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 14.

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