Pixel and display device having the same

Abstract

The display device of the present application is provided with: a substrate including a display area in which a pixel circuit is positioned; a first active layer positioned on the substrate and including a first source area, a first active area positioned adjacent to the first source area, and a first drain area positioned adjacent to the first active area; a first gate layer positioned on a layer covering the first active layer and including a first gate electrode overlapping the first active area; a second gate layer positioned on a layer covering the first gate layer and extending in a first direction and including an initialization line having a fourth-1 gate electrode; a second active layer positioned on a layer covering the second gate layer and including a fourth active area overlapping the fourth-1 gate electrode; a third gate layer positioned on a layer covering the second active layer and including a fourth-2 gate electrode having an isolated shape and overlapping the fourth active area; and a first source-drain layer positioned on a layer covering the third gate layer and including a first connection wiring extending in the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a pixel and a display device having the same, and more specifically to an improved element characteristic and a defective pixel and a display device having the same. Background Technology

[0002] Among display devices, organic light-emitting diode (OLED) displays have the advantages of wide viewing angle, excellent contrast, and fast response speed, thus attracting attention as a new generation of display devices.

[0003] Typically, organic light-emitting display devices consist of thin-film transistors and organic light-emitting elements formed on a substrate, with the organic light-emitting elements emitting their own light to operate. Such organic light-emitting display devices are used as display units in small products such as mobile phones, as well as in large products such as televisions.

[0004] On the other hand, such a display device includes a thin-film transistor for driving and a capacitor. Here, the thin-film transistor may include: a semiconductor layer including an active region, a source region, and a drain region; and a gate electrode electrically insulated from the semiconductor layer by a gate insulating layer. Summary of the Invention

[0005] However, in this existing display device, due to structural problems with the pixel circuit, there is a possibility of defects arising as the characteristics of the components change.

[0006] Embodiments of the present invention are designed to solve various problems, including those described above, and are capable of providing improved element characteristics and defective pixels through structural improvements in pixel circuitry, as well as a display device incorporating such defects. However, these technical problems are exemplary, and the scope of the present invention is not limited thereto.

[0007] According to one aspect of the present invention, a display device is provided, comprising: a substrate including a display area with pixel circuitry positioned thereon; a first active layer located on the substrate and including a first source region, a first active region positioned adjacent to the first source region, and a first drain region positioned adjacent to the first active region; a first gate layer located on a layer covering the first active layer and including a first gate electrode overlapping the first active region; a second gate layer located on a layer covering the first gate layer, extending in a first direction and including an initialization line having a fourth-1st gate electrode; a second active layer located on a layer covering the second gate layer and including a fourth active region overlapping the fourth-1st gate electrode; a third gate layer located on a layer covering the second active layer and including a fourth-2nd gate electrode overlapping the fourth active region and having an isolated shape; and a first source-drain layer located on a layer covering the third gate layer and including a first connection wiring extending in the first direction.

[0008] According to this embodiment, the first connection wiring may not overlap with the 4-1 gate electrode and the 4-2 gate electrode.

[0009] According to this embodiment, the fourth-1 gate electrode and the fourth-2 gate electrode may be electrically connected through a first gate contact hole formed in a layer intervening between the second gate layer and the third gate layer.

[0010] According to this embodiment, the first gate contact hole may expose the top surface of the fourth-1 gate electrode and include an inner side surface that is inclined to the top surface of the fourth-1 gate electrode, and the fourth-2 gate electrode may cover the top surface of the fourth-1 gate electrode exposed through the first gate contact hole and the inner side surface.

[0011] According to this embodiment, the diameter of the upper part of the fourth-1 gate electrode exposed through the first gate contact hole may be smaller than the distance between the end of the fourth active region of the first gate contact hole and the end of the first gate contact hole of the fourth active region.

[0012] According to this embodiment, the cross-sectional area of ​​the first gate contact hole parallel to the upper surface of the 4-1 gate electrode may increase in the direction away from the 4-1 gate electrode.

[0013] According to this embodiment, the fourth-2 gate electrode may have a portion extending from a portion located within the first gate contact hole and located on a layer covering the second active layer.

[0014] According to this embodiment, the pixel circuit may include a first pixel circuit and a second pixel circuit, wherein the first pixel circuit and the second pixel circuit are symmetric with respect to an imaginary axis passing through the first pixel circuit and the second pixel circuit.

[0015] According to this embodiment, the 4-1 gate electrode of the first pixel circuit and the 4-1 gate electrode of the second pixel circuit may be integrated, the 4-2 gate electrode of the first pixel circuit and the 4-2 gate electrode of the second pixel circuit may be integrated, and the first gate contact hole may be located on the imaginary axis.

[0016] According to this embodiment, the third gate layer may further include a gate initialization voltage line extending in the first direction, and the first connection wiring overlaps with the gate initialization voltage line.

[0017] According to this embodiment, the gate initialization voltage line may be electrically connected to the second active layer through a second gate contact hole formed in the layer covering the second active layer.

[0018] According to this embodiment, the display device may further include: a second source-drain layer, located on a layer covering the first source-drain layer, and including a second connection wiring extending in a second direction intersecting the first direction and electrically connected to the first connection wiring.

[0019] According to this embodiment, the first active layer may comprise a silicon semiconductor, and the second active layer may comprise an oxide semiconductor.

[0020] According to another aspect of the present invention, a pixel is provided, comprising: an organic light-emitting diode; a first transistor including a first semiconductor layer comprising silicon semiconductor and a first gate electrode, wherein a current flowing to the organic light-emitting diode is controlled corresponding to a voltage applied to the first gate electrode; a fourth transistor electrically connected to the first transistor, and comprising: a fourth semiconductor layer comprising oxide semiconductor; a fourth-1 gate electrode located below the fourth semiconductor layer; and a fourth-2 gate electrode located above the fourth semiconductor layer and having an isolated shape; an initialization line including the fourth-2 gate electrode and extending in a first direction; and a first connection wiring extending in the first direction.

[0021] According to this embodiment, the first connection wiring may not overlap with the 4-1 gate electrode and the 4-2 gate electrode.

[0022] According to this embodiment, the fourth-1 gate electrode and the fourth-2 gate electrode may be electrically connected through a first gate contact hole, the first gate contact hole exposing the top surface of the fourth-1 gate electrode and including an inner side surface that is inclined to the top surface of the fourth-1 gate electrode, and the fourth-2 gate electrode covering the top surface of the fourth-1 gate electrode exposed through the first gate contact hole and the inner side surface.

[0023] According to this embodiment, the diameter of the upper part of the fourth-1 gate electrode exposed through the first gate contact hole may be smaller than the distance between the end of the fourth active region of the fourth semiconductor layer in the direction of the first gate contact hole and the end of the first gate contact hole in the direction of the fourth active region.

[0024] According to this embodiment, the cross-sectional area of ​​the first gate contact hole parallel to the upper surface of the 4-1 gate electrode may increase in the direction away from the upper surface of the 4-1 gate electrode.

[0025] According to this embodiment, the fourth-2 gate electrode may have a portion extending from a portion located within the first gate contact hole and located on a layer covering the fourth semiconductor layer.

[0026] According to this embodiment, the pixel may further include: a second connecting wire extending in a second direction intersecting the first direction and electrically connected to the first connecting wire.

[0027] Other aspects, features, and advantages beyond those described above will become clear from the following detailed description, claims, and drawings.

[0028] (Invention Effects)

[0029] According to one embodiment of the present invention configured as described above, by improving the structure of the pixel circuit, it is possible to achieve improved component characteristics and defective pixels, as well as a display device equipped with them. Of course, the scope of the present invention is not limited by such effects. Attached Figure Description

[0030] Figure 1 This is a conceptual diagram that schematically illustrates a display device according to an embodiment of the present invention.

[0031] Figure 2 yes Figure 1 The equivalent circuit diagram of any pixel in a display device.

[0032] Figure 3 It is a general overview Figure 1 A plan view of the pixel circuitry of the display device.

[0033] Figures 4 to 10 It is shown in a layered outline. Figure 3 A plan view of the pixel circuit.

[0034] Figure 11 Select only Figure 3 A partial floor plan shown.

[0035] Figure 12 It is along Figure 3 A cross-sectional view of the pixel circuit taken by the I-I' line.

[0036] Figure 13 It is along Figure 3 A cross-sectional view of the pixel circuit taken from line II-II'.

[0037] (Explanation of reference numerals in the attached diagram)

[0038] 81: First gate contact hole; 83: Second gate contact hole

[0039] 91: Connection wiring contact hole; 100: Substrate

[0040] 101: Buffer layer; 103: First gate insulating film

[0041] 105: Second gate insulating film; 107: Third gate insulating film

[0042] 109: Fourth gate insulating film; 111: First interlayer insulating film

[0043] 113: Second interlayer insulating film Detailed Implementation

[0044] This invention can be modified in various ways and can have various embodiments. Specific embodiments are illustrated in the accompanying drawings and described in detail in the accompanying description. Reference is made to the appended drawings. Figure 1 The effects and features of the invention, as well as the methods for implementing them, will become clear from the detailed embodiments described below. However, the invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, the same or corresponding constituent elements will be given the same reference numerals, and repeated descriptions of this will be omitted.

[0046] In the following embodiments, the terms "first," "second," etc., are not used in a limiting sense, but are used to distinguish one constituent element from other constituent elements.

[0047] In the following embodiments, unless the context clearly indicates otherwise, the singular expression includes the plural expression.

[0048] In the following embodiments, the terms "including" or "having" mean the presence of the features or constituent elements described in the specification, and do not preclude the possibility of adding more than one other feature or constituent element.

[0049] In the following embodiments, when referring to a part of a membrane, region, or constituent element being on or on other parts, it includes not only the case where it is directly on other parts, but also the case where other membranes, regions, or constituent elements are interposed in between.

[0050] In the accompanying drawings, the dimensions of the constituent elements may be enlarged or reduced for ease of explanation. For example, since the dimensions and thicknesses of the various structures shown in the drawings are arbitrarily depicted for ease of explanation, the present invention is not limited to the illustrations.

[0051] Where a particular embodiment can be implemented differently, the specific process sequence may also be performed differently than the described sequence. For example, two processes described consecutively may be performed substantially simultaneously, or in the reverse order of the description.

[0052] In this specification, "A and / or B" means A, or B, or A and B. Additionally, "at least one of A and B" means A, or B, or A and B.

[0053] In the following embodiments, when referring to the connection of membranes, regions, constituent elements, etc., it includes the case where the membranes, regions, constituent elements are directly connected, and / or the case where the membranes, regions, constituent elements are indirectly connected by intervening other membranes, regions, constituent elements. For example, in this specification, when referring to the electrical connection of membranes, regions, constituent elements, etc., it means the case where the membranes, regions, constituent elements, etc. are directly electrically connected, and / or the case where the membranes, regions, constituent elements, etc. are indirectly electrically connected by intervening other membranes, regions, constituent elements, etc.

[0054] In the following embodiments, "extending in the first or second direction" means not only extending in a straight line, but also extending in a zigzag or curved manner along the first or second direction.

[0055] In the following embodiments, "overlapping" of a first constituent element with respect to a second constituent element means that the first constituent element is located above or below the second constituent element.

[0056] Figure 1 This is a conceptual diagram that schematically illustrates a display device according to an embodiment of the present invention.

[0057] The organic light-emitting display device according to this embodiment can also be implemented as an electronic device such as a smartphone, mobile phone, navigation device, game console, television (TV), vehicle main control unit, laptop computer, tablet computer, personal media player (PMP), personal digital assistant (PDA), etc. Furthermore, the electronic device can be a flexible device.

[0058] Hereinafter, as a display device according to an embodiment of the present invention, an organic light-emitting display device including an organic light-emitting diode will be described as an example, but it is not limited thereto. The light-emitting diode of the display device may be an inorganic light-emitting diode containing inorganic materials. The inorganic light-emitting diode may include a PN diode containing a material comprising an inorganic semiconductor substrate. When a voltage is applied to the PN diode in the forward direction, holes and electrons are injected, and the energy generated by the recombination of the holes and electrons is converted into light energy, thereby emitting light of a predetermined hue. The aforementioned inorganic light-emitting diode may have a width of several micrometers to several hundred micrometers. In some embodiments, the inorganic light-emitting diode may be referred to as a micro LED.

[0059] like Figure 1 As shown, the display device according to this embodiment may include: a display area DA, including pixels PX; a scan driver SD; a data driver DD; and a timing controller TC for controlling the scan driver SD and the data driver DD.

[0060] The scan driver SD supplies scan signals GW[1]~GW[n], initialization signals GI[1]~GI[n], compensation control signals GC[1]~GC[n], and light emission control signals EM[1]~EM[n] to the scan lines extending in the first direction DR1, according to the control of the timing controller TC. For example, the scan driver SD supplies scan signals GW[1]~GW[n], initialization signals GI[1]~GI[n], compensation control signals GC[1]~GC[n], and light emission control signals EM[1]~EM[n] to the scan lines, initialization lines, compensation control lines, and light emission control lines, respectively.

[0061] The data driver DD supplies data signals D[1] to D[m] to the data lines extending in the second direction DR2 under the control of the timing controller TC. The data driver DD supplies data signals D[1] to D[m] in sync with the scan signals GW[1] to GW[n], thereby supplying data signals D[1] to D[m] to the pixel PX selected by the scan signals GW[1] to GW[n].

[0062] The timing controller TC controls the scan driver SD and the data driver DD in response to the synchronization signal supplied from the outside.

[0063] The pixel PX within the display area DA is supplied with a power supply voltage ELVDD and an electrode voltage ELVSS. The pixel PX receiving the power supply voltage ELVDD and the electrode voltage ELVSS controls the amount of current flowing from the driving voltage line through the organic light-emitting diode to the electrode power line, thereby generating light with brightness corresponding to the data signals D[1] to D[m]. The power supply voltage ELVDD is applied to the driving voltage line, and the electrode voltage ELVSS is applied to the electrode power line.

[0064] exist Figure 1 The illustration shows pixels PX arranged sequentially along a first direction DR1 and a second direction DR2 within the display area DA, but the invention is not limited thereto. For example, pixels PX can be configured in various forms such as stripe arrangement, five-grid arrangement, mosaic arrangement, etc. Furthermore, in Figure 1 The display area DA is shown as a rectangle on the plan view, but it is not limited to this. For example, the display area DA can have a polygonal shape such as a triangle, pentagon, or hexagon, or a circle, ellipse, or irregular shape.

[0065] Figure 2 yes Figure 1 The equivalent circuit diagram of any pixel in a display device.

[0066] Reference Figure 2 Pixel PX includes first transistors T1 to seventh transistors T7, storage capacitor Cst, organic light-emitting diode (OLED), gate initialization voltage line VIL1, positive electrode initialization voltage line VIL2, driving voltage line PL, and signal lines. Signal lines may include data line DL, scan line SL, initialization line IL, compensation control line CL, and light emission control line EL. Any one of the signal lines, gate initialization voltage line VIL1, positive electrode initialization voltage line VIL2, and / or driving voltage line PL can be shared in adjacent pixels.

[0067] The drive voltage line PL transmits the power supply voltage ELVDD to the first transistor T1. The gate initialization voltage line VIL1 transmits the first initialization voltage Vint1, which initializes the first transistor T1, to the pixel PX. The positive initialization voltage line VIL2 transmits the second initialization voltage Vint2, which initializes the organic light-emitting diode (OLED), to the pixel PX.

[0068] exist Figure 2The diagram shows that the third transistor T3 and the fourth transistor T4 of the first transistor T1 to the seventh transistor T7 are implemented as NMOS (n-channel metal-oxide-semiconductor field-effect transistor (MOSFET)), and the rest are implemented as PMOS (p-channel MOSFET), but are not limited thereto.

[0069] The first transistor T1 can be a driving transistor. The first transistor T1 is connected to the driving voltage line PL via the fifth transistor T5, and is electrically connected to the organic light-emitting diode (OLED) via the sixth transistor T6. It receives a data signal D[j] based on the voltage applied to the first gate electrode, and controls the driving current I flowing from the node connected to the driving voltage line PL through the OLED to the electrode power line. OLED The amount.

[0070] The second transistor T2 can be a switching transistor. The second transistor T2 is connected to the scan line SL and the data line DL, and is connected to the drive voltage line PL via the fifth transistor T5. The second transistor T2 in the i-th row of n rows is turned on according to the scan signal GW[i] received through the scan line SL, thereby performing a switching operation to transmit the data signal D[j] transmitted to the data line DL in the j-th column of m columns to the node connected to the first transistor T1. Here, i is a natural number greater than or equal to 1 and less than n, and j is a natural number greater than or equal to 1 and less than m.

[0071] The third transistor T3 can be a compensation control transistor. The third transistor T3 is connected to the compensation control line CL and is connected to the organic light-emitting diode (OLED) via the sixth transistor T6. The third transistor T3 is turned on according to the compensation control signal GC[i] received through the compensation control line CL, thereby connecting the first transistor T1 diode.

[0072] The fourth transistor T4 can be a gate initialization transistor. The fourth transistor T4 is connected to the initialization line IL and the gate initialization voltage line VIL1, and is turned on according to the initialization signal GI(i) received through the initialization line IL, thereby transmitting the first initialization voltage Vint1 from the gate initialization voltage line VIL1 to the first gate electrode of the first transistor T1 to initialize the voltage of the first gate electrode of the first transistor T1.

[0073] The fifth transistor T5 can be a control transistor, and the sixth transistor T6 can be a light-emitting control transistor. Both transistors T5 and T6 are connected to the light-emitting control line EL and are simultaneously turned on according to the light-emitting control signal EM[i] received through the light-emitting control line EL, thus forming a current path to drive the current I. OLED It can flow from the driving voltage line PL towards the organic light-emitting diode (OLED).

[0074] The seventh transistor T7 can be a positive initialization transistor. The seventh transistor T7 is connected to the light-emitting control line EL and the positive initialization voltage line VIL2, and is turned on according to the light-emitting control signal EM[n] received through the light-emitting control line EL, thereby transmitting the second initialization voltage Vint2 from the positive initialization voltage line VIL2 to the organic light-emitting diode OLED, thus initializing the OLED. The seventh transistor T7 can be omitted.

[0075] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 is connected to the first gate electrode of the first transistor T1, and the upper electrode CE2 is connected to the drive voltage line PL. In this case, the lower electrode CE1 can be integrated with the first gate electrode. By storing and maintaining the voltage corresponding to the voltage difference between the drive voltage line PL and the voltage across the first gate electrode of the first transistor T1, the storage capacitor Cst can maintain the voltage applied to the first gate electrode of the first transistor T1.

[0076] An organic light-emitting diode (OLED) has pixel electrodes, counter electrodes, and an intermediate layer between them that includes a light-emitting layer. In a plurality of pixels, an electrode voltage ELVSS is applied to the counter electrode, which is formed integrally. The OLED receives a drive current I from a first transistor T1. OLED The emission of light enables the display device to display images. For reference, the counter electrode extends outward from the display area and is connected to the electrode power line, and the electrode voltage ELVSS is applied to the electrode power line.

[0077] Figure 3 It is a general overview Figure 1 A plan view of the pixel circuitry of the display device.

[0078] exist Figure 3 The image shows a pair of pixel circuits arranged in the same row of adjacent columns. For reference, in Figure 3 For simplicity, the illustration of an organic light-emitting diode (OLED) is omitted. The pixel circuit can be configured to form a matrix along the first direction DR1 and the second direction DR2. Figure 3 The diagram shows a pair of pixel circuits PC1 and PC2 arranged in the same row of adjacent columns.

[0079] As an example, such as Figure 3 As shown, the first pixel circuit PC1 located on the left and the second pixel circuit PC2 located on the right can be a symmetrical structure. That is, the first pixel circuit PC1 and the second pixel circuit PC2 can be symmetric with respect to the imaginary axis AX passing through them.

[0080] The first pixel circuit PC1 and the second pixel circuit PC2 each include the aforementioned first transistor T1 to seventh transistor T7 and storage capacitor Cst.

[0081] The first transistor T1 to the seventh transistor T7 each include a semiconductor layer and a gate electrode overlapping the active region of the semiconductor layer. In addition, the semiconductor layer of the first transistor T1 to the seventh transistor T7 each includes a semiconductor layer having a source region, an active region located adjacent to the source region, and a drain region located adjacent to the active region.

[0082] As one embodiment, at least one of the first transistors T1 to the seventh transistor T7 includes a semiconductor layer comprising an oxide semiconductor, and the others include semiconductor layers comprising silicon semiconductors. For example, in the case of the first transistor T1, which directly affects the brightness of the display device, a semiconductor layer comprising polycrystalline silicon with high reliability is provided, thereby enabling a high-resolution display device.

[0083] On the other hand, because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even with long driving times. That is, in the case of thin-film transistors containing oxide semiconductors, even at low-frequency driving, the hue change of the image as the voltage drops is not significant. In the case of oxide semiconductors, there is an advantage of low leakage current. For example, by making at least one of the third transistor T3 and the fourth transistor T4 connected to the first gate electrode of the first transistor T1 contain oxide semiconductors, it is possible to reduce power consumption while preventing leakage current that may flow to the first gate electrode of the first transistor T1.

[0084] As a specific example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be configured as transistors containing silicon semiconductors. That is, the semiconductor layers of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are formed as part of a first active layer AL1 containing polycrystalline silicon semiconductors (see reference). Figure 4 They are arranged in the same layer and contain the same substance.

[0085] Furthermore, the third transistor T3 and the fourth transistor T4 can be configured as transistors comprising oxide semiconductors. The semiconductor layers of each of the third transistor T3 and the fourth transistor T4 are formed as components within a second active layer AL2 comprising oxide semiconductors (see reference). Figure 7 They are arranged in the same layer and contain the same substance.

[0086] First active layer AL1 (reference) Figure 4) and the second active layer AL2 (reference) Figure 7 The semiconductor layers included in an OLED can be interconnected and bent into various shapes. For example, a portion of the semiconductor layer can be bent into shapes such as "C", "Ω (Omega)", "S", "M", and "W" to form a long channel length within a narrow space. This results in an elongated active region for the transistor, thereby widening the driving range of the gate voltage applied to the gate electrode. Consequently, the color gradation of the light emitted from the OLED can be controlled more precisely, improving display quality. Of course, a portion of the semiconductor layer can also have a straight shape instead of a bent shape, depending on the requirements.

[0087] The first transistor T1 includes a first semiconductor layer and a first gate electrode G1. The first semiconductor layer includes a first active region A1, first source regions S1 on both sides of the first active region A1, and a first drain region D1. The first gate electrode G1 is formed with an island shape (isolated shape), thereby configuring the first gate insulating film 103 (refer to...) Figure 12 It is placed between and overlaps with the first active region A1.

[0088] The storage capacitor Cst can be positioned overlapping the first transistor T1. The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2. The first gate electrode G1 can function not only as the control electrode of the first transistor T1, but also as the lower electrode CE1 of the storage capacitor Cst. That is, the first gate electrode G1 and the lower electrode CE1 can be formed as a single unit. The upper electrode CE2 of the storage capacitor Cst is configured to have the second gate insulating film 105 (refer to...) Figure 12 The second gate insulating film 105 is placed between and overlaps with the lower electrode CE1. At this time, the second gate insulating film 105 can serve as the dielectric layer of the storage capacitor Cst.

[0089] The second transistor T2 includes a second semiconductor layer and a second gate electrode G2. The second semiconductor layer includes a second active region A2, second source regions S2 on both sides of the second active region A2, and a second drain region D2. The second source region S2 is electrically connected to the data line DL, and the second drain region D2 is connected to the first source region S1. The second gate electrode G2 may overlap with the second active region A2 and be configured as part of the scan line SL.

[0090] The fifth transistor T5 includes a fifth semiconductor layer and a fifth gate electrode G5. The fifth semiconductor layer includes a fifth active region A5, fifth source regions S5 on both sides of the fifth active region A5, and a fifth drain region D5. The fifth source region S5 may be electrically connected to the driving voltage line PL, and the fifth drain region D5 may be connected to the first source region S1. The fifth gate electrode G5 may overlap with the fifth active region A5 and be configured as part of the light-emitting control line EL.

[0091] The sixth transistor T6 includes a sixth semiconductor layer and a sixth gate electrode G6. The sixth semiconductor layer includes a sixth active region A6, sixth source regions S6 on both sides of the sixth active region A6, and a sixth drain region D6. Alternatively, the sixth source region S6 may be connected to the first drain region D1, and the sixth drain region D6 may be electrically connected to the pixel electrode of an organic light-emitting diode (OLED). The sixth gate electrode G6 may overlap with the sixth active region A6 and be configured as part of the light-emitting control line EL.

[0092] The seventh transistor T7 includes a seventh semiconductor layer and a seventh gate electrode G7. The seventh semiconductor layer includes a seventh active region A7, a seventh source region S7 on both sides of the seventh active region A7, and a seventh drain region D7. The seventh source region S7 can be electrically connected to the positive initialization voltage line VIL2, and the seventh drain region D7 can be connected to the sixth drain region D6. The seventh gate electrode G7 can overlap with the seventh active region A7 and be set as part of the initialization line IL.

[0093] It could be the second gate insulating film 105 (refer to...) Figure 12 The first transistor T1, the second transistor T2, the fifth transistor T5 to the seventh transistor T7, which contain silicon semiconductors, are located on the third transistor T3 and the fourth transistor T4, which are located on the second gate insulating film 105.

[0094] The semiconductor layers of the third transistor T3 and the fourth transistor T4 are each disposed on the same layer and contain the same material. For example, the semiconductor layers of the third transistor T3 and the fourth transistor T4 can be formed as included in a second active layer AL2 containing an oxide semiconductor (see reference). Figure 7 ).

[0095] The third transistor T3 includes a third semiconductor layer comprising an oxide semiconductor and a third gate electrode G3. The third semiconductor layer includes a third active region A3 and third source regions S3 and third drain regions D3 on both sides of the third active region A3. The third source region S3 can be bridged to the first gate electrode G1 via a bridge electrode. Additionally, the third source region S3 can be connected to a fourth drain region D4 disposed on the same layer. The third drain region D3 can be electrically connected to the first semiconductor layer of the first transistor T1 and the sixth semiconductor layer of the sixth transistor T6. Furthermore, the third transistor T3 can have a dual-gate structure with control electrodes located above and below the third semiconductor layer. Specifically, the third gate electrode G3 can include: a third-1 gate electrode G3-1, located on the first gate layer GL1 (see reference). Figure 5 On the layer covering the second active layer AL2, and configured as part of the compensation control line CL; and the third-second gate electrode G3-2, located on the layer covering the second active layer AL2, and configured as part of the positive initialization voltage line VIL2.

[0096] The fourth transistor T4 includes a fourth semiconductor layer comprising an oxide semiconductor and a fourth gate electrode G4. The fourth semiconductor layer includes a fourth active region A4, fourth source regions S4 on both sides of the fourth active region A4, and a fourth drain region D4. The fourth source region S4 can be electrically connected to the gate initialization voltage line VIL1, and the fourth drain region D4 can be bridged to the first gate electrode G1 via a bridge electrode. On the other hand, the fourth transistor T4 can have a dual-gate structure with control electrodes above and below the fourth semiconductor layer. Specifically, the fourth gate electrode G4 can include: a 4-1 gate electrode G4-1, located on the layer covering the first gate layer GL1 and configured as part of the initialization line IL; and a 4-2 gate electrode G4-2, located on the layer covering the second active layer AL2 (see reference). Figure 7 It is on the layer and has an island shape (isolated shape).

[0097] On the other hand, the 4-1 gate electrode G4-1 and the 4-2 gate electrode G4-2 can be formed in the second gate layer GL2 (reference). Figure 6 ) and the third gate layer GL3 (reference) Figure 8 The first gate contact hole 81 of the intervening layer is electrically connected. For a detailed description of the first gate contact hole 81, please refer to [link to documentation]. Figures 11 to 13 This will be discussed later.

[0098] The scan line SL, initialization line IL, compensation control line CL, light emission control line EL, gate initialization voltage line VIL1, positive electrode initialization voltage line VIL2, and first connection wiring BL1 can extend towards the first direction DR1 and are arranged spaced apart from each other in each row. The data line DL, drive voltage line PL, and second connection wiring BL2 can extend towards the second direction DR2, which intersects the first direction DR1, and are arranged spaced apart from each other in each column.

[0099] Figures 4 to 10 It is shown in a layered outline. Figure 3 A plan view of the pixel circuit.

[0100] like Figures 4 to 10 As shown in sequence, from the substrate 100 (refer to) Figure 12 From the location away from the substrate 100, there are arranged... Figure 4 The first active layer AL1, Figure 5 First gate layer GL1, Figure 6 The second gate layer GL2, Figure 7 The second active layer AL2, Figure 8 The third gate layer GL3, Figure 9 The first source and drain layer SDL1 and Figure 10 The second source-drain layer, SDL2.

[0101] Furthermore, an insulating film is inserted between these layers. Specifically, it can be... Figure 4 The first active layer AL1 and Figure 5 A first gate insulating film 103 is inserted between the first gate layers GL1 (see reference). Figure 12 ),exist Figure 5 The first gate layer GL1 and Figure 6 A second gate insulating film 105 is inserted between the second gate layer GL2 (see reference). Figure 12 ),exist Figure 6 The second gate layer GL2 and Figure 7 A third gate insulating film 107 is inserted between the second active layer AL2 (refer to...) Figure 12 ),exist Figure 7 The second active layer AL2 and Figure 8 A fourth gate insulating film 109 is inserted between the third gate layer GL3 (see reference). Figure 12 ),exist Figure 8 The third gate layer GL3 and Figure 9 A first interlayer insulating film 111 is inserted between the first source and drain layers SDL1 (refer to...). Figure 12 ),exist Figure 9 The first source and drain layers SDL1 and Figure 10 A second interlayer insulating film 113 is inserted between the second source and drain layers SDL2 (see reference). Figure 12 Such insulating films may comprise silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. Depending on the requirements, each insulating film may have a single-layer or multi-layer structure. Of course, components of different layers can be electrically connected to each other through contact holes formed in such insulating films.

[0102] Figure 4 The first active layer AL1 includes the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0103] As an example, Figure 4 The first active layer AL1 can be a semiconductor layer containing polysilicon semiconductor. The source and drain regions of the first active layer AL1 can be doped with impurities, which can include N-type or P-type impurities. The source and drain regions can respectively correspond to the source electrode and drain electrode. The source and drain regions can be interchanged depending on the characteristics of the transistor. Hereinafter, the terms source region and drain region will be used instead of source electrode or drain electrode. Figure 2 The equivalent circuit diagram shows that a specific portion of the first active layer AL1 is doped with P-type impurities, and the first transistor T1, the second transistor T2, and the fifth transistor T5 to the seventh transistor T7 are implemented as PMOS (p-channel MOSFET). Of course, other portions of the first active layer AL1 can also be doped with impurities, thereby serving as wiring to electrically connect transistors and / or capacitors, or as capacitor electrodes, etc.

[0104] Figure 4The first active layer AL1 is located on the substrate 100. The substrate 100 may contain glass, metal, or a polymer resin. If the substrate 100 has flexible or bendable properties, it may contain, for example, a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Of course, the substrate 100 may also have a multilayer structure including two layers, each containing such a polymer resin, and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) between these layers, allowing for various deformations.

[0105] Other layers may be interposed between the substrate 100 and the first active layer AL1. For example, a buffer layer 101 comprising one or more of the following layers may be interposed between the substrate 100 and the first active layer AL1: silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide (see reference). Figure 12 Such a buffer layer 101 can improve the smoothness of the substrate 100, or prevent or minimize the penetration of impurities from the substrate 100 into the first active layer AL1, etc. Depending on the needs, the buffer layer 101 can have a single-layer structure or a multi-layer structure. In the case of a multi-layer structure, some layers can also be referred to as barrier layers.

[0106] Figure 5 The first gate layer GL1 includes the gate electrodes of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. Additionally, the first gate layer GL1 includes a scan line SL extending in the first direction DR1 and a light emission control line EL. In this case, the scan line SL and the light emission control line EL are formed as a single unit in adjacent pixels. On the other hand, the lower electrode CE1 of the storage capacitor Cst can be formed as a single unit with the first gate electrode G1 of the first transistor T1.

[0107] Specifically, Figure 5The first gate layer GL1 includes an isolating shape first gate electrode G1, a second gate electrode G2 as part of a scan line SL, a seventh gate electrode G7, a fifth gate electrode G5 as part of a light emission control line EL, and a sixth gate electrode G6.

[0108] Figure 6 The second gate layer GL2 includes a 3-1 gate electrode G3-1 serving as the lower gate electrode of the third transistor T3, a 4-1 gate electrode G4-1 serving as the lower gate electrode of the fourth transistor T4, and an upper electrode CE2 for the storage capacitor Cst. Additionally, the second gate layer GL2 includes an initialization line IL extending in the first direction DR1 and a compensation control line CL. In this case, the initialization line IL and the compensation control line CL are formed as a single unit in adjacent pixels.

[0109] Specifically, Figure 6 The second gate layer GL2 includes a third-1 gate electrode G3-1 as part of the compensation control line CL, a fourth-1 gate electrode G4-1 as part of the initialization line IL, and an upper electrode CE2 with an opening SOP. The opening SOP can be formed by removing a portion of the upper electrode CE2, and has a closed shape. The contact hole formed on the second gate insulating film 105 to the fourth gate insulating film 109 and the first interlayer insulating film 111 to electrically connect the first gate electrode G1 to the layer above can be located within such an opening SOP. On the other hand, the upper electrode CE2 can be formed integrally in adjacent pixels, and for this purpose can have a bridge portion. In this case, the bridge portion refers to the portion that protrudes from the upper electrode CE2 in the first direction DR1.

[0110] Figure 5 First gate layer GL1, Figure 6 The second gate layer GL2 and the following description Figure 8 The third gate layer GL3 can each contain aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), etc. Of course, each of these layers can have a single-layer or multi-layer structure, and in the case of a multi-layer structure, it can contain a variety of materials. For example, Figure 5 First gate layer GL1, Figure 6 The second gate layer GL2 and Figure 8 Each of the third gate layers GL3 can have a two-layer structure of molybdenum layer / aluminum layer, or a three-layer structure of molybdenum layer / aluminum layer / molybdenum layer.

[0111] Figure 7The second active layer AL2 includes a semiconductor layer of a third transistor T3 and a semiconductor layer of a fourth transistor T4. In this case, the semiconductor layers of the third transistor T3 and the fourth transistor T4 can be formed as a single unit through adjacent pixels.

[0112] As an example, Figure 7 The second active layer AL2 can be a semiconductor layer containing an oxide. For example, the second active layer AL2 can contain a Zn oxide-based material, such as Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. Of course, various modifications are possible, and the second active layer AL2 can contain oxide semiconductors such as IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) containing metals such as indium (In) and gallium (Ga) or tin (Sn) in ZnO.

[0113] Figure 8 The third gate layer GL3 includes a 3-2 gate electrode G3-2 serving as the upper gate electrode of the third transistor T3, a 4-2 gate electrode G4-2 serving as the upper gate electrode of the fourth transistor T4, and a gate initialization voltage line VIL1. For reference, Figure 8 The contact holes shown, including the first gate contact hole 81 and the second gate contact hole 83, can be formed in at least one of the first gate insulating film 103 to the fourth gate insulating film 109, thereby allowing the... Figure 8 The layer shown is electrically connected to the layer located below it.

[0114] Specifically, Figure 8 The third gate layer GL3 includes a third-second gate electrode G3-2 extending in the first direction DR1, a fourth-second gate electrode G4-2 in an isolated shape, and a gate initialization voltage line VIL1 extending in the first direction DR1.

[0115] As one embodiment, the 4-1st gate electrode G4-1 and the 4-2nd gate electrode G4-2 can be integrated with adjacent pixels. Specifically, the 4-1st gate electrode G4-1 of the first pixel circuit PC1 and the 4-1st gate electrode G4-1 of the second pixel circuit PC2 can be integrated and formed into an isolated shape. Furthermore, the 4-2nd gate electrode G4-2 of the first pixel circuit PC1 and the 4-2nd gate electrode G4-2 of the second pixel circuit PC2 can be integrated and formed to extend in the first direction DR1.

[0116] On the other hand, such as Figure 8 As shown, the first gate contact hole 81 is formed in Figure 6 The second gate layer GL2 and Figure 8A layer is inserted between the third gate layer GL3. The first gate contact hole 81 electrically connects the 4-1 gate electrode G4-1 and the 4-2 gate electrode G4-2. In this way, in the case of limited design space, the 4-1 gate electrode G4-1, which is the lower gate electrode, can be formed in a wiring form, while the 4-2 gate electrode G4-2, which is the upper gate electrode, can be formed in an isolated shape that is not a wiring form. That is, by electrically connecting the 4-2 gate electrode G4-2 included in the third gate layer GL3 to the 4-1 gate electrode included in the first gate layer GL1 through the first gate contact hole 81, the wiring form of the 4-1 gate electrode G4-1 can be used as a control signal movement path.

[0117] As a specific example of a situation with limited design space, a first connection wiring BL1 extending in the first direction DR1 is added in the region adjacent to the fourth transistor T4. This results in a situation where there is limited space to form all the gate electrodes G4-1 and G4-2 of the fourth transistor T4 in the form of wiring. For a detailed explanation of the first connection wiring BL1, please refer to [link to relevant documentation]. Figure 9 This will be discussed later.

[0118] The gate initialization voltage line VIL1 can be electrically connected to the second active layer AL2 through a second gate contact hole 83 formed in the layer covering the second active layer AL2. Specifically, the second gate contact hole 83 can be formed in the layer intervening between the second active layer AL2 and the third gate layer GL3, thereby electrically connecting the gate initialization voltage line VIL1 included in the third gate layer GL3 and the fourth source region S4 of the semiconductor layer of the fourth transistor T4 included in the second active layer AL2. In this case, the second gate contact hole 83 may not be formed in each pixel, but shared in adjacent pixels. For example, the second gate contact hole 83 may be located on the imaginary axis AX passing through the first pixel circuit PC1 and the second pixel circuit PC2. Alternatively, the gate initialization voltage line VIL1 may extend in the first direction DR1 through the first pixel circuit PC1 and the second pixel circuit PC2 and be formed as one piece, and the fourth source region S4 of the first pixel circuit PC1 and the fourth source region S4 of the second pixel circuit PC2 may also be formed as one piece. In this case, the gate initialization voltage line VIL1 can be electrically connected to the fourth source region S4 of the first pixel circuit PC1 and the fourth source region S4 of the second pixel circuit PC2 through a second gate contact hole 83.

[0119] Figure 9 The first source-drain layer SDL1 includes a first connection wiring BL1 extending in a first direction DR1 and a positive initialization voltage line VIL2. For reference, including... Figure 9The contact holes of the connection wiring contact holes 91 shown are formed on the first gate insulating film 103 to the fourth gate insulating film 109 and / or the first interlayer insulating film 111, thereby connecting the contact holes. Figure 9 The layer shown is electrically connected to the layer located below it.

[0120] The first connection wiring BL1 can be positioned without overlapping with the 4-1 gate electrode G4-1 and the 4-2 gate electrode G4-2. That is, by positioning the first connection wiring BL1 separately from the gate electrode of the fourth transistor T4, the impact of the first connection wiring BL1 on the fourth transistor T4 can be minimized. As mentioned above, the reduced design space can be improved by forming the 4-2 gate electrode G4-2 into an isolated shape and electrically connecting the 4-1 gate electrode G4-1 and the 4-2 gate electrode G4-2 in wiring form through the first gate contact hole 81. In contrast, the first connection wiring BL1 can be positioned to overlap with components that are not significantly affected even if positioned to overlap with the first connection wiring BL1. For example, the first connection wiring BL1 can overlap with the gate initialization voltage line VIL1.

[0121] As one embodiment, the first connection wiring BL1 can be wiring added to reduce the area of ​​dead space. Specifically, the first connection wiring BL1 can be wiring connecting a data line DL and an input line (not shown). The data line DL extends from the non-display area into the display area DA. Additionally, the input line, used to input data signals to be applied to the data line DL, is positioned separately in the non-display area. Each input line is connected to a corresponding data line DL. In this case, the data lines DL are densely packed around the edge area of ​​the display panel to connect with the input lines, thereby forming dead space. To reduce the area of ​​this dead space, each input line can be positioned relatively centrally on the display panel, rather than near its corresponding data line DL. With this structure, the area of ​​dead space in the peripheral area of ​​the display area DA can be greatly reduced.

[0122] According to this embodiment, the first connection wiring BL1 extends in a first direction DR1, with one end electrically connected to the data line DL and passing over the adjacent data line DL and through the display area DA without contacting the adjacent data line DL. The other end is electrically connected to the second connection wiring BL2 through the connection wiring contact hole 91. Furthermore, the second connection wiring BL2 extends in a second direction DR2, intersecting the first direction DR1, and is electrically connected to the input line in the non-display area. Therefore, the data line DL can be connected to the input line via a path through the display area DA using both the first connection wiring BL1 and the second connection wiring BL2.

[0123] Figure 10The second source-drain layer SDL2 includes a drive voltage line PL, a data line DL, and a second connection wiring BL2. Specifically, the second source-drain layer SDL2 includes a drive voltage line PL, a data line DL, and a second connection wiring BL2 extending in a second direction DR2 that intersects the first direction DR1. For reference, Figure 10 The contact holes shown are formed in the second interlayer insulating film, thereby allowing Figure 10 The layer shown is electrically connected to the layer located below it.

[0124] The driving voltage line PL can be shared among adjacent pixels. For example, the driving voltage line PL can be located between the first pixel circuit PC1 and the second pixel circuit PC2, and electrically connected to the first pixel circuit PC1 and the second pixel circuit PC2 respectively to supply the power supply voltage ELVDD. In this case, the driving voltage line PL is electrically connected to a portion of the first source-drain layer SDL1 through a contact hole formed in the layer between the first source-drain layer SDL1 and the second source-drain layer SDL2. The portion of the first source-drain layer SDL1 connected to the driving voltage line PL is electrically connected to the fifth source region S5 of the fifth transistor T5 through a contact hole formed in the layer between the first source-drain layer SDL1 and the first active layer AL1. Thus, the driving voltage line PL and the fifth transistor T5 can finally be electrically connected.

[0125] The data line DL is electrically connected to a portion of the first source-drain layer SDL1 through a contact hole formed in the layer between the first source-drain layer SDL1 and the second source-drain layer SDL2. The portion of the first source-drain layer SDL1 connected to the data line DL is electrically connected to the second source region S2 of the second transistor T2 through a contact hole formed in the layer between the first source-drain layer SDL1 and the first active layer AL1. Thus, the data line DL and the second transistor T2 can be electrically connected.

[0126] The second connection wiring BL2 is electrically connected to the first connection wiring BL1 through a connection wiring contact hole 91 formed in the layer between the first source-drain layer SDL1 and the second source-drain layer SDL2, and is electrically connected to the input line in the non-display area.

[0127] Such Figure 9 The first source and drain layer SDL1 and Figure 10The second source and drain layers, SDL2, can each contain aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), etc. Of course, each of these layers can have a single-layer or multi-layer structure, and in the case of a multi-layer structure, it can contain a variety of materials. For example, Figure 9 The first source and drain layer SDL1 and Figure 10 The second source and drain layers SDL2 can each have a two-layer structure of titanium / aluminum layer or a three-layer structure of titanium / aluminum / titanium layer.

[0128] On the other hand, a planarization film (not shown) covering the second source / drain layer SDL2 can be located on the second source / drain layer SDL2. Contact holes (not shown) can be formed on the planarization film to electrically connect the pixel electrodes of the organic light-emitting diode (OLED) located on the planarization film to the second source / drain layer SDL2. The planarization film can contain organic materials such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Of course, the invention is not limited to this; as needed, the planarization film can also contain inorganic materials and can have a single-layer structure or a multi-layer structure.

[0129] The following is for reference Figures 11 to 13 The first gate contact hole 81 will be described in detail.

[0130] Figure 11 Select only Figure 3 A partial floor plan is shown. Figure 12 It is along Figure 3 A cross-sectional view of the pixel circuit taken by the I-I' line. Figure 13 It is along Figure 3 A cross-sectional view of the pixel circuit taken from line II-II'. Specifically, Figure 11 From Figure 3 Selection of floor plan Figure 6 The second gate layer GL2 and Figure 8 The third gate layer GL3 is shown in a plan view, with the outer layers omitted.

[0131] like Figures 11 to 13As shown, a first gate contact hole 81 is formed in a layer intervening between the 4-1 gate electrode G4-1 and the 4-2 gate electrode G4-2, thereby exposing a portion of the upper surface of the 4-1 gate electrode G4-1. Additionally, a second gate contact hole 83 includes an inner side surface that forms an incline with the exposed upper surface of the 4-1 gate electrode G4-1. The 4-2 gate electrode G4-2 is formed above the 4-1 gate electrode G4-1 to cover the upper surface of the 4-1 gate electrode G4-1 exposed through the first gate contact hole 81 and the inner side surface of the first gate contact hole 81. The 4-2 gate electrode G4-2 can contact and be electrically connected to the 4-1 gate electrode G4-1 in the exposed portion of the 4-1 gate electrode G4-1. Therefore, even if the 4-2 gate electrode G4-2 is not formed in the form of wiring extending in the first direction DR1 or the second direction DR2, but has an isolated shape, it can still receive control signals and perform control electrode functions using the wiring-formed 4-1 gate electrode G4-1. This allows for a reduction in the space occupied by the 4-2 gate electrode G4-2, thereby ensuring sufficient design space.

[0132] The first gate contact hole 81 may not be present in every pixel (or pixel circuit), but may be shared with adjacent pixels (or pixel circuits). For example, as Figure 11 As shown, the first gate contact hole 81 can be located on the imaginary axis AX passing between the first pixel circuit PC1 located in the first pixel and the second pixel circuit PC2 located in the second pixel. That is, the first gate contact hole 81 is located at the center of the isolating shape of the 4-1 gate electrode G4-1 and serves to electrically connect the 4-1 gate electrode G4-1 and the 4-2 gate electrode G4-2, which are formed as a single unit in the first pixel circuit PC1 and the second pixel circuit PC2, which are adjacent to each other.

[0133] As an embodiment, the diameter L1 of the upper surface of the fourth-1 gate electrode G4-1 exposed through the first gate contact hole 81 can be formed to be smaller than the distance L2 between the end of the fourth active region A4 of the fourth transistor T4 in the direction of the first gate contact hole 81 and the end of the fourth active region A4 of the fourth transistor T4 in the direction of the first gate contact hole 81. (Refer to...) Figure 11 as well as Figure 12The first gate contact hole 81 is positioned between the fourth active regions A4 of the fourth transistor T4. In this case, if the spacing between the first gate contact hole 81 and the fourth active region A4 is insufficient, a short circuit in the fourth transistor T4 may occur during the manufacturing or use of the display device, or malfunctions may occur due to changes in component characteristics such as increased circuit resistance. According to this embodiment, by forming the diameter L1 of the first gate contact hole 81 to be smaller than the distance from the first gate contact hole 81 to the fourth active region A4, it has the effect of improving component characteristics and preventing malfunctions that may occur during manufacturing or use.

[0134] For example, when the diameter L1 of the first gate contact hole 81 is less than 2.6 μm, and the distance L2 between the end of the fourth active region A4 of the fourth transistor T4 in the direction of the first gate contact hole 81 and the end of the fourth active region A4 of the fourth transistor T4 in the direction of the first gate contact hole 81 is more than 2.2 μm, L1 can be formed to be greater than L2.

[0135] In another embodiment, the cross-sectional area of ​​the first gate contact hole 81 parallel to the upper surface of the 4-1 gate electrode G4-1 can be formed to increase in the direction away from the 4-1 gate electrode G4-1. That is, as Figure 12 as well as Figure 13 As shown, the inner surface of the first gate contact hole 81 can be formed to slope outwards. Consequently, the fourth-second gate electrode G4-2, which covers the inner surface of the first gate contact hole 81, is also positioned to slope outwards from the first gate contact hole 81. This prevents, in advance, the introduction of hydrogen into the fourth active region A4 due to defects that may occur during the formation of the insulating film on the fourth-second gate electrode G4-2 (e.g., chemical vapor deposition seams) that could alter the device characteristics.

[0136] On the other hand, as a specific example of a method for adjusting the tilt angle of the inner side surface of the first gate contact hole 81, there are methods such as changing the outline of the photoresist pattern or the etching gas used in the etching process. For example, CF4 / O2 or CHF3 / Ar series etching gases can be used in the etching process to make the inner side surface of the first gate contact hole 81 tilt outward, but it is not limited to this.

[0137] In another embodiment, the 4-2 gate electrode G4-2 may include: a portion 81-1 covering the top surface of the 4-1 gate electrode G4-1 exposed through the first gate contact hole 81; a portion 81-2 covering the inner surface of the first gate contact hole 81; and a portion 81-3 extending within the portion located within the first gate contact hole 81 and situated on the layer covering the second active layer AL2. In this case, the portions 81-1, 81-2, and 81-3 of the 4-2 gate electrode G4-2 are integral. The 4-2 gate electrode G4-2 extends uninterruptedly from the end of the portion 81-2 covering the inner surface of the first gate contact hole 81, having a portion 81-3 situated on the layer covering the second active layer AL2, thereby enabling the formation of an insulating film on the 4-2 gate electrode G4-2 with superior quality. For example, the 4-2 gate electrode G4-2 may extend from the portion 81-2 covering the inner side of the first gate contact hole 81 in the second direction DR2, thereby being positioned to overlap the end of the 4-1 gate electrode G4-1 in the second direction DR2.

[0138] So far, only pixels and display devices equipped with them have been described, but the present invention is not limited thereto. For example, methods for manufacturing such pixels and display devices equipped with them are also within the scope of the present invention.

[0139] Although the invention has been described with reference to embodiments shown in the accompanying drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true scope of protection of the invention should be determined by the technical concept of the appended claims.

Claims

1. A display device, wherein, have: The substrate includes the display area where pixel circuitry is positioned; A first active layer is located on the substrate and includes a first source region, a first active region located adjacent to the first source region, and a first drain region located adjacent to the first active region. A first gate layer is located on a layer covering the first active layer and includes a first gate electrode that overlaps with the first active region. The second gate layer is located on the layer covering the first gate layer and extends in a first direction and includes an initialization line having a fourth gate electrode; The second active layer is located on the layer covering the second gate layer and includes a fourth active region that overlaps with the fourth-1 gate electrode; The third gate layer is located on the layer covering the second active layer and includes a fourth-2 gate electrode that overlaps with the fourth active region and has an island shape. A first source-drain layer is located on a layer covering the third gate layer and includes a first connection wiring extending in the first direction; as well as The second source-drain layer is located on the layer covering the first source-drain layer, and includes data lines extending in a second direction intersecting the first direction and second connection wiring. One end of the first connecting wire is electrically connected to the data line, and the other end of the first connecting wire is electrically connected to the second connecting wire.

2. The display device according to claim 1, wherein, The first connection wiring does not overlap with the 4-1 gate electrode and the 4-2 gate electrode.

3. The display device according to claim 1, wherein, The fourth-1 gate electrode and the fourth-2 gate electrode are electrically connected through a first gate contact hole formed in a layer interposed between the second gate layer and the third gate layer.

4. The display device according to claim 3, wherein, The first gate contact hole exposes the top surface of the 4-1 gate electrode and includes an inner side surface that forms an inclination with the top surface of the 4-1 gate electrode. The fourth-2 gate electrode covers the top surface and the inner side surface of the fourth-1 gate electrode exposed through the first gate contact hole.

5. The display device according to claim 4, wherein, The diameter of the upper part of the fourth-1 gate electrode exposed through the first gate contact hole is smaller than the distance between the end of the first gate contact hole in the direction of the fourth active region and the end of the fourth active region in the direction of the first gate contact hole.

6. The display device according to claim 4, wherein, The cross-sectional area of ​​the first gate contact hole, parallel to the top of the 4-1 gate electrode, increases in the direction away from the 4-1 gate electrode.

7. The display device according to claim 4, wherein, The fourth-2 gate electrode has a portion extending from the portion located within the first gate contact hole and located on the layer covering the second active layer.

8. The display device according to claim 4, wherein, The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit and the second pixel circuit are symmetrical with respect to an imaginary axis passing through the first pixel circuit and the second pixel circuit.

9. The display device according to claim 8, wherein, The 4-1 gate electrode of the first pixel circuit and the 4-1 gate electrode of the second pixel circuit are integrated. The fourth-2 gate electrode of the first pixel circuit and the fourth-2 gate electrode of the second pixel circuit are integrated. The first gate contact hole is located on the imaginary axis.

10. The display device according to claim 1, wherein, The third gate layer also includes a gate initialization voltage line extending in the first direction. The first connection wiring overlaps with the gate initialization voltage line.

11. The display device according to claim 10, wherein, The gate initialization voltage line is electrically connected to the second active layer through a second gate contact hole formed in the layer covering the second active layer.

12. The display device according to claim 1, wherein, The first active layer comprises a silicon semiconductor, and the second active layer comprises an oxide semiconductor.

13. A pixel, wherein, have: Organic light-emitting diode; The first transistor includes a first semiconductor layer comprising silicon semiconductor and a first gate electrode, and controls the current flowing to the organic light-emitting diode in accordance with the voltage applied to the first gate electrode; A fourth transistor, electrically connected to the first transistor, includes: a fourth semiconductor layer comprising an oxide semiconductor; a fourth-1 gate electrode located below the fourth semiconductor layer; and a fourth-2 gate electrode located above the fourth semiconductor layer and having an island shape. An initialization line, including the 4-1st gate electrode, extends in a first direction; A first connecting wire extends in the first direction; and The second connecting wire extends in a second direction intersecting the first direction and is electrically connected to the first connecting wire. One end of the first connection wire is electrically connected to the corresponding data line, and the other end of the first connection wire is electrically connected to the corresponding second connection wire.

14. The pixel according to claim 13, wherein, The first connection wiring does not overlap with the 4-1 gate electrode and the 4-2 gate electrode.

15. The pixel according to claim 13, wherein, The 4-1 gate electrode and the 4-2 gate electrode are electrically connected through the first gate contact hole. The first gate contact hole exposes the top surface of the 4-1 gate electrode and includes an inner side surface that forms an inclination with the top surface of the 4-1 gate electrode. The fourth-2 gate electrode covers the top surface and the inner side surface of the fourth-1 gate electrode exposed through the first gate contact hole.

16. The pixel according to claim 15, wherein, The diameter of the upper part of the fourth-1 gate electrode exposed through the first gate contact hole is smaller than the distance between the end of the fourth active region of the fourth semiconductor layer in the direction of the first gate contact hole and the end of the fourth active region in the direction of the first gate contact hole.

17. The pixel according to claim 15, wherein, The cross-sectional area of ​​the first gate contact hole parallel to the top of the 4-1 gate electrode increases in the direction away from the top of the 4-1 gate electrode.

18. The pixel according to claim 15, wherein, The fourth-2 gate electrode has a portion extending from the portion located within the first gate contact hole and located on the layer covering the fourth semiconductor layer.

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