Semiconductor device and method for forming the same

Abstract

The present disclosure relates to semiconductor devices and methods for forming the same. A method for forming a semiconductor device includes: forming a dummy gate on a fin, wherein the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, wherein replacing the dummy gate includes: forming a gate trench in the dielectric material, wherein forming the gate trench includes removing the dummy gate; forming a metal gate stack in the gate trench, wherein forming the metal gate stack includes sequentially forming a gate dielectric layer, a first work function layer, and a gap fill material in the gate trench; and expanding the volume of the gap fill material in the gate trench.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this improvement in integration density comes from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

[0003] Fin field effect transistor (FinFET) devices are becoming widely used in integrated circuits. FinFET devices have a three-dimensional structure that includes a semiconductor fin protruding from a substrate. A gate structure configured to control the flow of charge carriers within a conductive channel of the FinFET device surrounds the semiconductor fin. For example, in a tri-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, thereby forming a conductive channel on the three sides of the semiconductor fin. Summary of the invention

[0004] According to one aspect of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a dummy gate on a fin, wherein the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, wherein replacing the dummy gate comprises: forming a gate trench in the dielectric material, wherein forming the gate trench comprises removing the dummy gate; forming a metal gate stack in the gate trench, wherein forming the metal gate stack comprises sequentially forming a gate dielectric layer, a first work function layer, and a gap filling material in the gate trench; and expanding the volume of the gap filling material in the gate trench.

[0005] According to another aspect of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: surrounding a dummy gate disposed on a fin with a dielectric layer, wherein the fin protrudes above a substrate; removing the dummy gate to form a trench in the dielectric layer; lining the sidewalls and bottom of the trench with a gate dielectric layer; forming one or more work function layers on the gate dielectric layer; filling the trench with a conductive material, wherein after the trench is filled, a gap exists in the conductive material; and after filling the trench, processing the conductive material to expand the volume of the conductive material, wherein after the processing, the gap is removed.

[0006] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a fin protruding above the substrate; a metal gate structure located above the fin, wherein the metal gate structure comprises: a gate dielectric layer; a first work function layer located above the gate dielectric layer; a second work function layer located above the first work function layer; and a conductive material extending from an upper surface of the second work function layer into the second work function layer, wherein the conductive material comprises aluminum and fluorine; and a cap layer located above and in contact with the first work function layer, the second work function layer and the conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It is worth noting that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A perspective view of a fin field effect transistor (FinFET) device is shown in accordance with some embodiments.

[0009] Figure 2-Figure 6 , Figure 7A-7C as well as Figure 8-Figure 17 Cross-sectional views of a FinFET device at various stages of fabrication are shown in accordance with one embodiment.

[0010] Figure 18-Figure 20 Cross-sectional views of a FinFET device at various stages of fabrication are shown according to another embodiment.

[0011] Figure 21-23 Cross-sectional views of a FinFET device at various stages of fabrication are shown according to yet another embodiment.

[0012] Fig.24 A flow chart of a method of manufacturing a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0014] In addition, spatially related terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to easily describe the relationship of one element or feature shown in the figures relative to another (one or more) element or (one or more) feature. These spatially related terms are intended to cover different orientations of the device in use or operation other than the orientation shown in the figures. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may also be interpreted accordingly. Throughout the discussion herein, unless otherwise stated, the same or similar reference numerals in different figures represent the same or similar elements formed by the same or similar methods and using (one or more) the same or similar materials.

[0015] Embodiments of the present disclosure are discussed in the context of forming a FinFET device, and specifically, embodiments of the present disclosure are discussed in the context of forming a replacement gate (e.g., a metal gate) for a FinFET device. However, the concepts of the present invention are not limited to forming a metal gate in a FinFET device, and are applicable to many other applications in which filling a trench with (one or more) materials is performed. For example, the disclosed method can be used to perform trench filling in other types of devices, such as a planar FET device, a nanosheet FET device, or a nanowire FET device. In addition to forming a metal gate, the disclosed method can also be used to form other structures, such as a through-hole. In addition, the disclosed method can be used to fill trenches having shapes and / or sizes that are different from those disclosed herein. These and other variations are fully intended to be included within the scope of the present disclosure.

[0016] In some embodiments, a replacement gate process includes: forming a dummy gate on a fin, wherein the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, wherein replacing the dummy gate includes: forming a gate trench in the dielectric material by removing the dummy gate; forming a metal gate stack in the gate trench, wherein forming the metal gate stack includes sequentially forming a gate dielectric layer, a first work function layer, and a gap fill material in the gate trench; and expanding the volume of the gap fill material in the gate trench by treating the gap fill material with a fluorine treatment process. Due to the high aspect ratio of the gate trench in advanced semiconductor process nodes, there may be seams (or gaps) in the deposited gap fill material, which may cause seam-induced punch-through effects in a subsequent metal gate etch-back process. By treating the gap fill material with a fluorine treatment process, the seams can be removed, thereby preventing or reducing the seam-induced punch-through effects.

[0017] Figure 1An example of a FinFET 30 is shown in perspective view. The FinFET 30 includes a substrate 50 and a fin 64 protruding above the substrate 50. An isolation region 62 is formed on opposite sides of the fin 64, wherein the fin 64 protrudes above the isolation region 62. A gate dielectric 66 is along the sidewalls of the fin 64 and is located on the top surface of the fin 64, and a gate 68 is located on the gate dielectric 66. A source / drain region 80 is located in the fin 64 and is located on opposite sides of the gate dielectric 66 and the gate 68. Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section BB extends along the longitudinal axis of gate 68 of FinFET 30. Cross section AA is perpendicular to cross section BB and along the longitudinal axis of fin 64 and in the direction of current flow, for example, between source / drain regions 80. Cross section CC is parallel to cross section BB and spans source / drain regions 80. For clarity, subsequent figures refer to these reference cross sections.

[0018] Figure 2-Figure 6 , Figure 7A-7C as well as Figure 8-Figure 17 FIG. 1 shows a cross-sectional view of a FinFET device 100 at various stages of fabrication according to an embodiment. The FinFET device 100 is similar to Figure 1 The FinFET 30 in FIG. 1 is similar to the FinFET 30 in FIG. 1 , but has multiple fins and multiple gate structures. Figure 2-Figure 5 A cross-sectional view of the FinFET device 100 along cross-section BB is shown. Figure 6 , Fig. 7A and Figure 8-Figure 17 shows a cross-sectional view of the FinFET device 100 along the cross section AA, and Figure 7B and Figure 7C A cross-sectional view of the FinFET device 100 along cross section CC is shown.

[0019] Figure 2A cross-sectional view of a substrate 50 is shown. The substrate 50 may be a semiconductor substrate (e.g., a bulk semiconductor), a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, for example, a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0020] refer to Figure 3 , using techniques such as photolithography and etching to pattern Figure 2 5. For example, a mask layer, such as a pad oxide layer 52 and an overlying pad nitride layer 56, is formed over the substrate 50. The pad oxide layer 52 may be a thin film including silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer 52 may serve as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof, and may be formed using, for example, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0021] The mask layer may be patterned using photolithography techniques. Typically, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove portions of the photoresist material. The remaining photoresist material protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, as shown in FIG. Figure 3 shown.

[0022] The exposed portions of the substrate 50 are then patterned using the patterned mask 58 to form trenches 61, thereby defining semiconductor fins 64 between adjacent trenches 61, such as Figure 3As shown. In some embodiments, the semiconductor fin 64 is formed by etching a groove in the substrate 50 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. In some embodiments, the grooves 61 may be strips parallel to each other (as viewed from the top) and closely spaced from each other. In some embodiments, the grooves 61 may be continuous and surround the semiconductor fin 64. The semiconductor fin 64 may also be referred to as the fin 64 hereinafter.

[0023] The fin 64 may be patterned by any suitable method. For example, the fin 64 may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0024] Figure 4 An insulating material is shown formed between adjacent semiconductor fins 64 to form isolation regions 62. The insulating material may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material, e.g., an oxide), etc., or a combination thereof. Other insulating materials and / or other formation processes may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. A planarization process (e.g., chemical mechanical polishing (CMP)) may remove any excess insulating material and form coplanar top surfaces of the isolation regions 62 and the top surfaces of the semiconductor fins 64 (not shown). The patterned mask 58 (see Figure 3 ) can also be removed by planarization process.

[0025] In some embodiments, the isolation region 62 includes a liner, such as a liner oxide (not shown), at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the liner oxide.

[0026] Next, the isolation region 62 is recessed to form a shallow trench isolation (STI) region 62. The isolation region 62 is recessed so that the upper portion of the semiconductor fin 64 protrudes from between adjacent STI regions 62. The top surface of the STI region 62 may have a flat surface (as shown), a convex surface, a concave surface (e.g., recessed), or a combination thereof. By appropriate etching, the top surface of the STI region 62 may be formed to be flat, convex, and / or concave. The isolation region 62 may be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the isolation region 62. For example, dry etching or wet etching using diluted hydrofluoric acid (dHF) may be performed to recess the isolation region 62.

[0027] Figures 2 to 4 An embodiment of forming fins 64 is shown, but the fins can be formed in a variety of different processes. For example, the top portion of substrate 50 can be replaced with a suitable material (e.g., an epitaxial material suitable for the intended type of semiconductor device to be formed (e.g., N-type or P-type)). Thereafter, substrate 50 with the epitaxial material on top is patterned to form semiconductor fins 64 including the epitaxial material.

[0028] As another example, a dielectric layer may be formed over a top surface of the substrate; a trench may be etched through the dielectric layer; a homoepitaxial structure may be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin.

[0029] In further examples, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; a heteroepitaxial structure can be epitaxially grown in the trench using a different material than the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0030] In embodiments where epitaxial material(s) or epitaxial structures (e.g., heteroepitaxial structures or homoepitaxial structures) are grown, the grown material(s) or structures may be doped in situ during growth, which may avoid prior and subsequent implants, but may use both in situ and implant doping together. Additionally, it may be advantageous to epitaxially grow a different material in the NMOS region than in the PMOS region. In various embodiments, the fins 64 may include silicon germanium (Si x Ge 1-x , where x can be between about 0 and 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0031] Figure 5 The formation of a dummy gate structure 75 is shown. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate 68. A mask 70 may be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, multiple layers thereof, etc., and may be deposited or thermally grown.

[0032] A gate layer is formed on the dielectric layer, and a mask layer is formed on the gate layer. The gate layer may be deposited on the dielectric layer and then planarized, for example, by CMP. The mask layer may be deposited on the gate layer. The gate layer may be formed, for example, of polysilicon, but other materials may also be used. The mask layer may be formed, for example, of silicon nitride, etc.

[0033] After forming the layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer may be patterned using acceptable photolithography and etching techniques to form mask 70. Then, the pattern of mask 70 may be transferred to the gate layer and the dielectric layer by acceptable etching techniques to form gate 68 and gate dielectric 66, respectively. Gate 68 and gate dielectric 66 cover the corresponding channel regions of semiconductor fin 64. Gate 68 may also have a length direction substantially perpendicular to the length direction of the corresponding semiconductor fin 64.

[0034] exist Figure 5In the example of FIG. 5 , gate dielectric 66 is shown as being formed over fin 64 (e.g., over the top surface and sidewalls of fin 64) and over STI region 62. In other embodiments, gate dielectric 66 may be formed by, for example, thermal oxidation of the material of fin 64, and thus may be formed over fin 64 but not over STI region 62. These and other variations are fully intended to be included within the scope of the present disclosure.

[0035] Figure 6 , Fig. 7A and Figure 8-Figure 17 A further processed cross-sectional view of the FinFET device 100 along cross section AA (along the longitudinal axis of the fin 64 ) is shown. Figure 7B and Figure 7C Shown in Fig. 7A FIG. 1 is a cross-sectional view of two embodiments of the FinFET device 100 at the processing step of FIG. 1 but along the cross section CC. Figure 6-Figure 8 , three dummy gate structures 75A, 75B, and 75C are shown above the fin 64. For simplicity, the dummy gate structures 75A, 75B, and 75C may be collectively referred to as dummy gate structures 75. Those skilled in the art will appreciate that more or less than three gate structures may be formed above the fin 64, and these and other variations are fully intended to be included within the scope of the present disclosure.

[0036] like Figure 6 As shown, a lightly doped drain (LDD) region 65 is formed in the fin 64. The LDD region 65 may be formed by a plasma doping process. The plasma doping process may include forming and patterning a mask (e.g., a photoresist) to cover the FinFET region to be protected from the plasma doping process. The plasma doping process may implant N-type or P-type impurities in the fin 64 to form the LDD region 65. For example, a P-type impurity (e.g., boron) may be implanted in the fin 64 to form an LDD region 65 for a P-type device. As another example, an N-type impurity (e.g., phosphorus) may be implanted in the fin 64 to form an LDD region 65 for an N-type device. In some embodiments, the LDD region 65 is adjacent to the channel region of the FinFET device 100. Portions of the LDD region 65 may extend under the gate 68 and into the channel region of the FinFET device 100. Figure 6 A non-limiting example of an LDD region 65 is shown. Other configurations, shapes, and methods of forming the LDD region 65 are also possible and are fully intended to be included within the scope of the present disclosure. For example, the LDD region 65 may be formed after forming the gate spacers 87 / 85. In some embodiments, the LDD region 65 is omitted.

[0037] Still reference Figure 6, after forming the LDD region 65, a first gate spacer 85 is formed around the dummy gate structure 75 (e.g., along its sidewalls and in contact with its sidewalls), and a second gate spacer 87 is formed around the first gate spacer 85 (e.g., along its sidewalls and in contact with its sidewalls). For example, the first gate spacer 85 may be formed on the opposite sidewalls of the dummy gate structure 75. The second gate spacer 87 is formed on the first gate spacer 85. The first gate spacer 85 may be a low-k spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxynitride carbon, etc. The second gate spacer 87 may be formed of a nitride such as silicon nitride, silicon oxynitride, silicon carbon nitride, etc., or a combination thereof. The first gate spacer 85 and the second gate spacer 87 may be formed using any suitable deposition method such as thermal oxidation, chemical vapor deposition (CVD), etc. In the illustrated embodiment, the first gate spacer 85 and the second gate spacer 87 are formed of different materials to provide etching selectivity in subsequent processing. The first gate spacer 85 and the second gate spacer 87 may be collectively referred to as gate spacers 85 / 87 .

[0038] like Figure 6 The shapes and formation methods of the gate spacers (eg, 85 and 87) shown in are non-limiting examples only, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure.

[0039] Next, in Fig. 7A In the embodiment, a groove is formed in the fin 64 adjacent to the dummy gate structure 75, for example, between adjacent dummy gate structures 75 and / or immediately adjacent to the dummy gate structure 75, and a source / drain region 80 is formed in the groove. In some embodiments, the groove is formed by, for example, an anisotropic etching process using the dummy gate structure 75 as an etching mask, but any other suitable etching process may also be used.

[0040] The source / drain regions 80 are formed by epitaxially growing a semiconductor material in the recesses using an appropriate method (e.g., metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc., or a combination thereof).

[0041] like Fig. 7A As shown, the epitaxial source / drain regions 80 may have surfaces that are raised from the corresponding surfaces of the fins 64 (e.g., raised higher than the non-recessed portions of the fins 64) and may have facets. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80 (see Figure 7BIn some embodiments, the source / drain regions 80 of adjacent fins 64 are not merged together and remain as separate source / drain regions 80 (see Figure 7C ). In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain region 80 includes silicon carbide (SiC), silicon phosphorus (SiP), silicon carbon doped with phosphorus (SiCP), etc. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain region 80 includes SiGe and p-type impurities, such as boron or indium.

[0042] The epitaxial source / drain regions 80 may be implanted with dopants to form the source / drain regions 80, followed by an annealing process. The implantation process may include forming and patterning a mask (e.g., a photoresist) to cover the areas of the FinFET to be protected from the implantation process. The source / drain regions 80 may have a thickness of about 1E19 cm -3 to about 1E21 cm -3 The impurity (e.g., dopant) concentration may be within a range of . P-type impurities such as boron or indium may be implanted into the source / drain regions 80 of a P-type transistor. N-type impurities such as phosphorus or arsenic may be implanted into the source / drain regions 80 of an N-type transistor. In some embodiments, the epitaxial source / drain regions may be doped in situ during growth.

[0043] Next, if Figure 8 As shown, in Fig. 7A A contact etch stop layer (CESL) 83 is formed over the structure shown. The CESL 83 is used as an etch stop layer in a subsequent etching process and may include a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, etc., and may be formed by a suitable formation method such as CVD, PVD, a combination thereof, etc.

[0044] Next, an interlayer dielectric (ILD) 90 is formed over the CESL 83 and over the dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the ILD 90 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and may be deposited by any suitable method such as CVD, PECVD, or FCVD. After forming the ILD 90, a dielectric layer 91 is formed over the ILD 90. The dielectric layer 91 serves as a protective layer to prevent or reduce the loss of the ILD 90 in a subsequent etching process. The dielectric layer 91 may be formed of a suitable material such as silicon nitride, silicon carbonitride, etc. using a suitable method such as CVD, PECVD, or FCVD. After forming the dielectric layer 91, a planarization process such as a CMP process may be performed to achieve a flush upper surface of the dielectric layer 91. The CMP may also remove portions of mask 70 and CESL 83 disposed over gate 68. In some embodiments, after the planarization process, the upper surface of dielectric layer 91 is flush with the upper surface of gate 68.

[0045] An embodiment gate-last process (sometimes referred to as a replacement gate process) is then performed to replace the gate 68 and gate dielectric 66 of the dummy gate structure 75 with an effective gate (also referred to as a replacement gate or metal gate).

[0046] Next, in Fig. 9 , removing the dummy gate structures 75A, 75B and 75C (see Fig. 7A ) to form gate trenches 89A, 89B and 89C, respectively. Next, the upper portions of the gate trenches 89A, 89B and 89C are enlarged by removing the upper portions of the first gate spacers 85, so that each of the gate trenches 89A, 89B and 89C has an upper trench 89U and a lower trench 89L, wherein the upper trench 89U is wider than the lower trench 89L. The details of forming the gate trenches 89A, 89B and 89C are discussed below. For simplicity, the gate trenches 89A, 89B and 89C may be collectively referred to as gate trenches 89.

[0047] In some embodiments, to remove the dummy gate structure 75, one or more etching steps are performed to remove the gate 68 and the gate dielectric 66 directly below the gate 68, so that gate trenches 89 (which may also be referred to as recesses) are formed between the corresponding first gate spacers 85. Each gate trench 89 exposes a channel region of a corresponding fin 64. During the removal of the dummy gate, the gate dielectric 66 may be used as an etch stop layer when etching the gate 68. The gate dielectric 66 may then be removed after the gate 68 is removed.

[0048] Next, an anisotropic etching process, such as a dry etching process, is performed to remove the upper portion of the first gate spacer 85. In some embodiments, the anisotropic etching process is performed using an etchant that is selective to the material of the first gate spacer 85 (e.g., has a higher etching rate), so that the first gate spacer 85 is recessed (e.g., the upper portion is removed) without substantially corroding the second gate spacer 87, the dielectric layer 91, and the fin 64. After removing the upper portion of the first gate spacer 85, the upper sidewall 87SU of the second gate spacer 87 is exposed.

[0049] like Fig. 9 As shown, after removing the upper portion of the first gate spacer 85, each gate trench 89 has an upper trench 89U and a lower trench 89L. The lower trench 89L is between the remaining lower portions of the first gate spacer 85. The upper trench 89U is above the lower trench and is defined by (e.g., adjacent to) the upper sidewall 87SU of the second gate spacer 87. Fig. 9 An interface 86 between the upper trench 89U and the lower trench 89L is shown, which is flush with the upper surface 85U of the remaining lower portion of the first gate spacer 85. Each gate trench 89 has a wider upper trench 89U and a narrower lower trench 89L, similar to the letter "Y", and therefore, the gate trench 89 can be referred to as a Y-shaped gate trench. The Y-shaped gate trench is used as a non-limiting example. As will be readily appreciated by those skilled in the art, the trench filling method disclosed herein is applicable to trenches having other shapes and / or sizes.

[0050] In some embodiments, the upper trench 89U has a width W1 (e.g., the distance between the opposing upper sidewalls 87SU) and a depth H1 (e.g., the distance between the upper surface of the second gate spacer 87 and the interface 86). The lower trench 89L has a width W2 (e.g., the distance between the opposing sidewalls of the remaining lower portion of the first gate spacer 85) and a depth H2 (e.g., the distance between the bottom of the gate trench 89 and the interface 86). The widths W1 and W2 can be between about 1 nm and about 100 nm. The depth H2 can be between about 0 nm and about 300 nm, and the total trench depth H1+H2 can be between about 10 nm and about 300 nm. As will be described in subsequent processing, a metal gate 97 is formed in the lower trench 89L (e.g., see Fig.13 ). Therefore, in some embodiments, the size of the lower trench 89L determines the size of the metal gate.

[0051] Next, in Fig.10In the embodiment of the present invention, a gate dielectric layer 92, a work function layer 94, a work function layer 96 and a gap filling material 98 are sequentially formed in the gate trench 89. In the discussion herein, the gate dielectric layer 92, the work function layers 94 and 96 and the gap filling material 98 are collectively referred to as a gate stack 95. The gate stack 95 may also be referred to as a metal gate stack.

[0052] like Fig.10 As shown, the gate dielectric layer 92 is conformally deposited in the gate trench 89, for example, on the top surface and sidewalls of the fin 64, on the top surface and sidewalls of the gate spacer 85 / 87, and on the top surface of the dielectric layer 91. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multilayer thereof. In other embodiments, the gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0053] Next, a work function layer 94 is formed on (e.g., conformally) the gate dielectric layer 92, and a work function layer 96 is formed on (e.g., conformally) the work function layer 94. In the illustrated embodiment, the work function layer 94 is a P-type work function layer, and the work function layer 96 is an N-type work function layer. In the discussion herein, the work function layer may also be referred to as a work function metal. Although in Fig.10 Two work function layers are shown in FIG. 1 , but any suitable number of work function layers may be used, and each work function layer may be any suitable type (eg, N-type or P-type) of work function metal.

[0054] Example P-type work function metals that may be included in the gate structure include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Example N-type work function metals that may be included in the gate structure include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value so that the target threshold voltage Vt is achieved in the device to be formed. The (one or more) work function layers may be deposited by CVD, physical vapor deposition (PVD), ALD, or other suitable processes. In an example embodiment, the work function layer 94 (e.g., a P-type work function layer) is formed of TiN, TiSiN, TiAlN, WCN, etc., and the work function layer 96 (e.g., an N-type work function layer) is formed of TiAlC, etc.

[0055] Next, an optional capping layer (not shown) is formed over the work function layer 96 (e.g., conformally). The capping layer (if formed) protects the underlying work function layer 96 from oxidation. The capping layer may include elements such as Ti, N, Si, C, O, Al, or combinations thereof. In some embodiments, the capping layer is a silicon-containing layer, such as a silicon layer, a silicon oxide layer, or a silicon nitride layer formed by a suitable method such as ALD, MBD, CVD, etc. In some embodiments, the capping layer is omitted.

[0056] Next, a gap filling material 98 (which may also be referred to as a gap filling film or gap filling layer) is formed over the work function layer 96 (or the cap layer of the work function layer 96, if formed) to fill the gate trench 89. In some embodiments, the gap filling material 98 is a conductive material. In an exemplary embodiment, the gap filling material 98 is formed of an aluminum-containing material, such as titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), aluminum nitride (AlN), or aluminum oxide (Al2O3) using a suitable deposition method such as CVD, PVD, ALD, etc. The temperature of the deposition process may be between about 250°C and about 450°C. The thickness of the deposited gap filling material 98 may be between about 5 angstroms and about 100 angstroms.

[0057] As feature sizes continue to shrink in advanced semiconductor manufacturing processes, filling trenches with high aspect ratios becomes increasingly difficult. Fig.10In the example of , since it is difficult to fill the gate trench 89, a seam 81 (also referred to as a gap or cavity) is formed in the gap filling material 98 in the gate trench 89. In the example shown, the seam 81 is a closed space in the gap filling material 98. In other embodiments, the seam 81 may be a gap extending to the gap filling material 98 away from the upper surface of the substrate 50. If the seam 81 is not processed, the gap filling material 98 may be over-etched in the area below the seam 81 in the subsequent metal gate etch back process. The seam-induced over-etching may be referred to as a seam-induced punch-through effect, or simply a punch-through effect. The present disclosure removes the seam 81 by treating the gap filling material 98 with a fluorine-containing chemical, details of which are disclosed below.

[0058] Figure 11-Figure 17 Additional processing steps to form the FinFET device 100 are shown. For simplicity, Figure 11-Figure 16 Each shows only a portion of the FinFET device 100. Specifically, Figure 11-Figure 16 Each shows Fig.10 An enlarged view of region 88 in FIG. Fig.11 After forming the gap filling material 98, Fig.10 Area 88. Fig.11 The seam 81 is shown in the gap filling material 98 in FIG.

[0059] Next reference Fig.12 , the gap filling material 98 is treated (e.g., doped) with a fluorine-containing chemical to close (e.g., remove) the seam 81. In the illustrated embodiment, the volume of the gap filling material 98 is increased by the treatment using the fluorine-containing chemical (also referred to as fluorine treatment). In other words, the gap filling material 98 is expanded after being treated with the fluorine-containing chemical, and the expansion of the gap filling material 98 causes the gap filling material 98 to fill (e.g., occupy) the space of the seam 81, thereby removing the seam 81. After the fluorine treatment, the gap filling material 98 completely fills the gate trench 89, and the seam 81 no longer exists in the gap filling material 98. In the discussion herein, the fluorine-treated gap filling material 98 may also be referred to as a fluorine-containing filling material 99 or a fluorine-doped filling material 99.

[0060] In some embodiments, the fluorine treatment of the gap fill material 98 is a thermal process performed using a fluorine-containing gas such as nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), or fluorine (F2). Depending on the intensity of fluorination to be achieved, a carrier gas (e.g., Ar, He, etc.) may or may not be used. For example, the FinFET device 100 is placed in a processing chamber, and a fluorine-containing gas (e.g., NF3, CF4, F2) is then supplied to the processing chamber so that the gap fill material 98 is in contact with the fluorine-containing gas. The flow rate of the fluorine-containing gas can be between about 100 standard cubic centimeters (sccm) and about 8000 sccm per minute. The ratio of the flow rate of the fluorine-containing gas to the carrier gas can be between about 0.01:1 and 1:0. The temperature of the fluorine treatment thermal process can be between about 25°C and about 600°C. In the embodiment shown, the fluorine in the fluorine-containing gas diffuses into the gap fill material 98 and reacts (e.g., combines or chemically reacts) with the aluminum in the gap fill material 98 to form aluminum fluoride (e.g., AlF x ).

[0061] In some embodiments, the fluorine treatment of the gap filling material 98 is a plasma process performed using a fluorine-containing gas such as NF3, CF4, or F2. For example, a fluorine-containing gas (e.g., NF3, CF4, F2) is ignited into a plasma, and the fluorine-containing plasma is supplied to a processing chamber in which the FinFET device 100 is placed. Therefore, the gap filling material 98 is treated by a fluorine-containing plasma. Depending on the fluorination intensity to be achieved, a carrier gas (e.g., Ar, He, etc.) may or may not be used. The flow rate of the fluorine-containing gas used for the plasma process may be between about 100 sccm and about 8000 sccm. The ratio of the flow rate of the fluorine-containing gas to the carrier gas may be between about 0.01:1 and 1:0. The temperature of the plasma process may be between about 25°C and about 500°C. The pressure of the plasma process may be between about 0.1 Torr and about 50 Torr, and the RF power of the plasma process may be between about 50W and about 5000W. In some embodiments, the fluorine-containing plasma diffuses into the gap-fill material 98 and reacts (eg, combines or chemically reacts) with the aluminum in the gap-fill material 98 to form aluminum fluoride (eg, AlF x ).

[0062] exist Fig.12 In the illustrated embodiment, by appropriately adjusting the fluorine treatment intensity and due to the strong affinity between fluorine (F) and aluminum (Al), the diffusion of fluorine (F) from the fluorine-containing gas or fluorine-containing plasma is confined to the gap filling material 98, and other materials of the gate structure (e.g., 96, 94, 92) are not affected by the fluorine treatment and are therefore substantially free of fluorine.

[0063] Next, in Fig.13In, a metal gate etch back process is performed to remove the upper portion of the gate stack 95 (for example, the upper portion of the gate dielectric layer 92, the upper portion of the work function layer 94 / 96, and the upper portion of the fluorine-containing filling material 99). After the metal gate etch back process, a groove 84 is formed between the second gate spacers 87. A suitable etching process such as dry etching, wet etching, or a combination thereof can be performed as the metal gate etch back process. The etchant used for the etching process can be a halide (for example, CCl4), an oxidizer (for example, O2), an acid (for example, HF), a base (for example, NH3), an inert gas (for example, Ar), a combination thereof, and the like. In Fig.13 In the example of , since the etchant has etching selectivity between different materials (e.g., 92, 94, 96, 99), after the etching process, the upper surface of the remaining portion of the gate dielectric layer 92 is flush with the upper surface 85U of the first gate spacer 85, and the upper surface 97U of the remaining portion of the work function layer 94 / 96 and the fluorine-containing filling material 99 is lower than the upper surface 85U (e.g., closer to the substrate 50). In other embodiments, the upper surface of the remaining portion of the gate dielectric layer 92 is flush with the upper surface 97U. The upper surface 97U of the remaining portion of the work function layer 94 / 96 and the fluorine-containing filling material 99 may extend from about 2 angstroms to about 20 angstroms above the top surface of the fin 64. After the metal gate etch back process, the remaining portion of the gate dielectric layer 92, the remaining portion of the work function layer 94 / 96, and the remaining portion of the fluorine-containing filling material 99 form a metal gate 97 (also referred to as a metal gate structure or a replacement gate structure).

[0064] Next, in Fig.14 In the embodiment, a capping layer 101 is formed over the work function layer 94 / 96 and the remaining portion of the fluorine-containing fill material 99. The capping layer 101 is formed of a conductive material such as tungsten using a suitable deposition method such as ALD, CVD, PVD, etc. Fig.14 In the example of FIG. 1 , the cap layer 101 is selectively formed over the work function layer 94 / 96 and the remaining portion of the fluorine-containing fill material 99 , but non-selective formation methods may also be used.

[0065] Note that due to the fluorine treatment of the gap filling material 98, the seam 81 in the gap filling material 98 is removed. As a result, after the metal gate etch back process, the seam-induced punch-through effect is avoided. Without the fluorine treatment of the gap filling material 98, the seam-induced punch-through effect may produce a divot (e.g., a groove or hole) in the upper surface 97U of the work function layer 94 / 96 and the remaining portion of the gap filling material 98, and the cap layer 101 may not be properly formed in or around the divot. Failure to grow the cap layer 101 in or around the divot may reduce device performance due to, for example, higher resistance. In addition, the punch-through effect may damage the top of the fin 64. By avoiding or reducing the punch-through effect, the present disclosure improves yield and achieves better device performance.

[0066] like Fig.14 As shown, the cap layer 101 completely covers the upper surface 97U of the work function layer 94 / 96 and the remaining portion of the fluorine-containing fill material 99. In other words, the cap layer 101 completely covers (eg, extends along and physically contacts) the upper surface 97U. Fig.14 In the embodiment, the capping layer 101 continuously extends from a first inner sidewall of the gate dielectric layer 92 (e.g., a sidewall facing the fluorine-containing filling material 99) to an opposite second inner sidewall of the gate dielectric layer 92. In some embodiments, the capping layer 101 has a uniform thickness. In some embodiments, the lower surface of the capping layer 101 facing the substrate 50 is substantially parallel to the main upper surface of the substrate 50. Fig.14 In the example, the upper surface of the cap layer 101 away from the substrate 50 is flush with the upper surface 85U of the first gate spacer 85. In some embodiments, the fluorine-containing filling material 99 is disposed below the cap layer 101 and has a height H3 between about 5 angstroms and about 300 angstroms.

[0067] Next, in Fig.15 In the embodiment of the present invention, a semiconductor material 111 such as silicon is formed in the groove 84 using a suitable formation method such as PVD, CVD, etc. Next, a gate contact 102 is formed in the semiconductor material 111 to be electrically coupled to the cap layer 101. In order to form the gate contact 102 (also referred to as a contact plug), a contact opening is formed in the semiconductor material 111 using, for example, photolithography and etching to expose the cap layer 101. Once the contact opening is formed, a barrier layer 104, a seed layer 109, and a filling metal 110 are sequentially formed in the contact opening to form the gate contact 102.

[0068] In some embodiments, barrier layer 104 includes a conductive material (e.g., titanium nitride), but other materials (e.g., tantalum nitride, titanium, tantalum, etc.) may be used instead. Barrier layer 104 may be formed using a CVD process (e.g., PECVD). However, other alternative processes may be used instead, such as sputtering, metal organic chemical vapor deposition (MOCVD), or ALD.

[0069] Next, a seed layer 109 is formed on the barrier layer 104. The seed layer 109 may include copper, titanium, tantalum, titanium nitride, tantalum nitride, etc., or a combination thereof, and may be deposited by ALD, sputtering, PVD, etc. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. For example, the seed layer 109 may include a titanium layer and a copper layer located on the titanium layer.

[0070] Next, a fill metal 110 is deposited on the seed layer 109 and fills the remaining portion of the contact opening. The fill metal 110 may be a metal-containing material (e.g., Cu, Al, W, etc., a combination thereof, or a multilayer thereof), and may be formed by, for example, electroplating, electroless plating, or other appropriate methods. After forming the fill metal 110, a planarization process such as CMP may be performed to remove excess portions of the barrier layer 104, the seed layer 109, and the fill metal 110 that are above the upper surface of the dielectric layer 91 (see FIG. 1 ). Fig.10 ) and the upper surface of the second gate spacer 87. The resulting remaining portions of the barrier layer 104, the seed layer 109, and the fill metal 110 thus form the gate contact 102.

[0071] Next, in Fig.16 In the embodiment of the present invention, the semiconductor material 111 is replaced by the dielectric material 113. The semiconductor material 111 may be removed by an etching process using an etchant that is selective to the semiconductor material 111. After the semiconductor material 111 is removed, a dielectric material 113 (e.g., silicon oxide, silicon nitride, a low-K dielectric material, etc.) is formed to fill the space previously occupied by the semiconductor material 111.

[0072] Fig.17 FIG. 1 shows a cross-sectional view of the FinFET device 100 after the dielectric material 113 replaces the semiconductor material 111. Fig.17 As shown, metal gates 97A, 97B, and 97C that replace dummy gate structures 75A, 75B, and 75C, respectively, are formed over fin 64. Those skilled in the art will appreciate that additional processing may be performed to complete the fabrication of FinFET device 100, such as forming source / drain contacts and forming metallization layers over dielectric layer 91. For the sake of brevity, the details are not discussed herein.

[0073] Figure 18-Figure 20 A cross-sectional view of a FinFET device 100A at various stages of fabrication is shown in accordance with another embodiment. The FinFET device 100A is similar to the FinFET device 100 , but has a different level (eg, a higher level) of fluorination during the fluorine treatment of the gap fill material 98 .

[0074] Fig.18 The processing follows Figure 1-Figure 11 In other words, Figure 1-Figure 11 and Figure 18-Figure 20 The processing steps of the FinFET device 100A are shown. Fig.18 In, through a method similar to Fig.12 The gap filling material 98 is treated with a fluorine treatment process (eg, a thermal process or a plasma process) to remove the seam 81, but the fluorination strength is higher than Fig.12 The intensity of fluorination can be enhanced by, for example, increasing the processing temperature, increasing the plasma power of the plasma process, increasing the flow rate of the fluorine-containing gas, and / or increasing the processing pressure. In addition, changing the gas used as the fluorine-containing gas can also change the intensity of fluorination. Due to the intensity of the higher fluorine treatment process, fluorine diffuses into the gap filling material 98 and the portion of the work function layer 96 that contacts the gap filling material 98. Fig.18 FIG. 1 shows a fluorine-doped region 99 ′ of the metal gate stack after the fluorine treatment, wherein the fluorine-doped region 99 ′ includes the gap fill material 98 and a portion of the work function layer 96 that is in contact with the gap fill material 98 . Fig.12 In the embodiment, the diffusion of fluorine is confined within the gap filling material 98, so Fig.12 The fluorine-doped filling material 99 has the same boundary as the gap filling material 98, while Fig.18 The fluorine-doped region 99' in FIG. 1 extends beyond the boundary of the gap-fill material 98. Note that in addition to the intensity level of the fluorine treatment process, other factors (e.g., material selection of the metal gate stack, stacking sequence of different layers of the metal gate stack) may also affect the boundary of the fluorine-doped region 99'.

[0075] Next, in Fig.19 In the implementation and Fig.13 A metal gate etch back process identical or similar to the metal gate etch back process of the FinFET device 100A is used to remove the upper portion of the gate dielectric layer 92, the upper portion of the work function layer 94 / 96, and the upper portion of the fluorine-doped region 99'. A recess 84 is formed between the second gate spacers 87. The remaining portion of the gate dielectric layer 92, the remaining portion of the work function layer 94 / 96, and the remaining portion of the fluorine-doped region 99' form the metal gate structure 97 of the FinFET device 100A. Next, the metal gate etch back process of the FinFET device 100A is removed using the same method as the metal gate etch back process of the FinFET device 100A. Fig.14The cap layer 101 is formed on the remaining portion of the work function layer 94 / 96 and the remaining portion of the fluorine-doped region 99' by a deposition process that is the same as or similar to the deposition process of the above-mentioned embodiment. Note that due to the higher intensity of the fluorine treatment, the fluorine-doped region 99' disposed below the cap layer 101 has a height H4 that is greater than Fig.14 The height H3 of the fluorine-doped filling material 99 is as follows.

[0076] Next, execute Fig.15 and Fig.16 For example, semiconductor material 111 is formed in recess 84, and gate contact 102 is formed in semiconductor material 111 and electrically coupled to cap layer 101. Next, semiconductor material 111 is replaced with dielectric material 113. Fig. 20 FIG. 4 shows a cross-sectional view of the FinFET device 100A after the dielectric material 113 replaces the semiconductor material 111. Fig. 20 As shown, metal gates 97A, 97B, and 97C that replace the dummy gate structures 75A, 75B, and 75C, respectively, are formed over the fin 64. Those skilled in the art will appreciate that additional processing may be performed to complete the fabrication of the FinFET device 100A, such as forming source / drain contacts and forming metallization layers over the dielectric layer 91. For the sake of brevity, the details are not discussed herein.

[0077] Figure 21-23 A cross-sectional view of a FinFET device 100B at various stages of fabrication is shown in accordance with yet another embodiment. The FinFET device 100B is similar to the FinFET device 100A, but has a higher level of fluorination during the fluorine treatment of the gap fill material 98 .

[0078] Fig.21 The processing follows Figure 1-Figure 11 In other words, Figure 1-Figure 11 and Figure 21-23 The processing steps of the FinFET device 100B are shown. Fig.21 In, through a method similar to Fig.12 The gap filling material 98 is treated with a fluorine treatment process (e.g., a thermal process or a plasma process) to remove the seam 81, but at a higher intensity (e.g., a longer duration, a higher temperature, and / or a higher fluorine-containing gas flow rate) to diffuse the fluorine into the gap filling material 98 and the work function layers 96 and 94. Fig.21 A fluorine-doped region 99 ″ of the metal gate stack after the fluorine treatment process is shown, wherein the fluorine-doped region 99 ″ includes all of the gap-fill material 98 , the work function layers 96 and 94 .

[0079] Next, in Fig. 22 In the implementation and Fig.13 A metal gate etch back process that is the same as or similar to the metal gate etch back process of the FinFET device 100B is used to remove the upper portion of the gate dielectric layer 92, the upper portion of the work function layer 94 / 96, and the upper portion of the fluorine-doped region 99″. A recess 84 is formed between the second gate spacers 87. The remaining portion of the gate dielectric layer 92, the remaining portion of the work function layer 94 / 96, and the remaining portion of the fluorine-doped region 99″ form a metal gate structure 97 of the FinFET device 100B. Next, the same as Fig.14 A cap layer 101 is formed on the remaining portion of the work function layer 94 / 96 and the remaining portion of the fluorine-doped region 99" by a deposition process that is the same as or similar to the deposition process of the fluorine-doped region 99".

[0080] Next, execute Fig.15 and Fig.16 For example, semiconductor material 111 is formed in recess 84, and gate contact 102 is formed in semiconductor material 111 and electrically coupled to cap layer 101. Next, semiconductor material 111 is replaced with dielectric material 113. Fig.23 FIG. 4 shows a cross-sectional view of the FinFET device 100B after the dielectric material 113 replaces the semiconductor material 111. Fig.23 As shown, metal gates 97A, 97B, and 97C that replace the dummy gate structures 75A, 75B, and 75C, respectively, are formed over the fin 64. Those skilled in the art will appreciate that additional processing may be performed to complete the fabrication of the FinFET device 100B, such as forming source / drain contacts and forming metallization layers over the dielectric layer 91. For the sake of brevity, the details are not discussed herein.

[0081] Embodiments can achieve advantages. For example, the fluorine treatment process removes the seam 81, thereby preventing or reducing the punch-through effect caused by the seam. As a result, the cap layer 101 is prevented from not growing, and damage to the top of the fin 64 is avoided, which improves device performance and yield. As the semiconductor manufacturing process continues to advance, the distance (e.g., spacing) between adjacent metal gates 97 is getting closer. For advanced processing nodes such as 5nm or more advanced, the small spacing between the metal gates 97 may cause metal gate leakage, which reduces the reliability of the formed device. Compared to a reference design in which a metal gate 97 is formed between the second gate spacers 87 (e.g., the first gate spacer 85 is completely removed and the metal gate 97 fills the space between the second gate spacers 87), the current disclosure increases the spacing between the metal gates 97 by forming a metal gate 97 between the recessed first gate spacers 85, thereby reducing metal gate leakage and increasing device reliability. The increased spacing between adjacent metal gates 97 may also increase the spacing between adjacent gate contacts 102 , which, combined with the fact that the gate contacts 102 are surrounded by the second gate spacers 87 , prevents or reduces the likelihood of electrical shorts between adjacent gate contacts 102 .

[0082] Variations and modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. Fig.17 , Fig. 20 and Fig.23 In the embodiment, all metal gates 97 (e.g., 97A, 97B, and 97C) have the same structure (e.g., the same film scheme in the metal gate). In other embodiments, the metal gate 97 may have different structures. For example, each metal gate 97A, 97B, and 97C may have different (one or more) work function layers to achieve different threshold voltages, and / or form metal gates in different regions of the FinFET device (e.g., N-type device regions or P-type device regions). As another example, the fluorination level of each metal gate 97A, 97B, and 97C may be different, so that the metal gate 97A may have a structure such as Fig.17 The fluorine-doped filling material 99 shown in FIG. 1 and the metal gate 97B may have a Fig. 20 The fluorine-doped region 99' shown in FIG. 1 and the metal gate 97C may have a Fig.23 The fluorine-doped region 99" is shown.

[0083] Fig.24 1 shows a flow chart of a method for manufacturing a semiconductor device according to some embodiments. It should be understood that Fig.24 The embodiment methods shown in are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, and repeated. Fig.24 The various steps shown.

[0084] refer to Fig.24 At block 1010, a dummy gate is formed on the fin, wherein the fin protrudes above the substrate. At block 1020, the dummy gate is surrounded by a dielectric material. At block 1030, the dummy gate is replaced with a replacement gate structure, wherein replacing the dummy gate includes: forming a gate trench in the dielectric material, wherein forming the gate trench includes removing the dummy gate; forming a metal gate stack in the gate trench, wherein forming the metal gate stack includes sequentially forming a gate dielectric layer, a first work function layer, and a gap fill material in the gate trench; and increasing the volume of the gap fill material in the gate trench.

[0085] In an embodiment, a method of forming a semiconductor device includes: forming a dummy gate on a fin, wherein the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, wherein replacing the dummy gate includes: forming a gate trench in the dielectric material, wherein forming the gate trench includes removing the dummy gate; forming a metal gate stack in the gate trench, wherein forming the metal gate stack includes sequentially forming a gate dielectric layer, a first work function layer, and a gap fill material in the gate trench; and expanding the volume of the gap fill material in the gate trench. In an embodiment, after forming the metal gate stack and before expanding, there is a cavity in the gap fill material. In an embodiment, after expanding, the cavity is filled with the expanded gap fill material. In an embodiment, the gap fill material is formed of an aluminum-containing material, and wherein expanding the volume includes treating the gap fill material with a fluorine-containing chemical. In an embodiment, the gap fill material is formed of titanium aluminum nitride, titanium aluminum carbide, aluminum nitride, or aluminum oxide. In an embodiment, the fluorine-containing chemical is nitrogen trifluoride, carbon tetrafluoride, or fluorine. In an embodiment, processing the gap filling material includes processing the gap filling material with a fluorine-containing gas in a thermal process. In an embodiment, processing the gap filling material includes processing the gap filling material with a plasma of a fluorine-containing gas. In an embodiment, the method further includes: etching the metal gate stack so that the metal gate stack is recessed relative to the upper surface of the dielectric material; forming a cap layer on the recessed metal gate stack; and forming a gate contact on the cap layer. In an embodiment, the cap layer extends along the upper surface of the gap filling material and contacts the upper surface of the gap filling material. In an embodiment, the cap layer is formed of tungsten. In an embodiment, the lower surface of the cap layer in contact with the gap filling material extends substantially parallel to the main upper surface of the substrate.

[0086] In an embodiment, a method of forming a semiconductor device includes: surrounding a dummy gate disposed on a fin with a dielectric layer, wherein the fin protrudes above a substrate; removing the dummy gate to form a trench in the dielectric layer; lining the sidewalls and bottom of the trench with a gate dielectric layer; forming one or more work function layers on the gate dielectric layer; filling the trench with a conductive material, wherein after filling the trench, there is a gap in the conductive material; and after filling the trench, treating the conductive material to expand the volume of the conductive material, wherein after the treatment, the gap is removed. In an embodiment, the conductive material is an aluminum-containing material, and treating the conductive material includes treating the conductive material with a fluorine-containing chemical. In an embodiment, treating the conductive material includes supplying a fluorine-containing gas to the conductive material. In an embodiment, treating the conductive material includes treating the conductive material with a plasma of a fluorine-containing gas. In an embodiment, the method further includes: after processing the conductive material, recessing the gate dielectric layer, one or more work function layers, and the conductive material using an etching process; forming a cap layer on the one or more work function layers and the conductive material; and forming a contact plug on the cap layer, and the contact plug is electrically coupled to the cap layer.

[0087] In an embodiment, a semiconductor device includes: a substrate; a fin protruding above the substrate; a metal gate structure located above the fin, wherein the metal gate structure includes: a gate dielectric layer; a first work function layer located above the gate dielectric layer; a second work function layer located above the first work function layer; and a conductive material extending from an upper surface of the second work function layer into the second work function layer, wherein the conductive material includes aluminum and fluorine; and a cap layer located above and in contact with the first work function layer, the second work function layer and the conductive material. In an embodiment, the cap layer extends continuously between the opposite inner sidewalls of the gate dielectric layer facing the conductive material, wherein the upper surface of the cap layer away from the substrate is flush with the upper surface of the gate dielectric layer away from the substrate. In an embodiment, the semiconductor device also includes: a first gate spacer along the sidewall of the metal gate structure; and a second gate spacer along the sidewall of the first gate spacer, wherein the second gate spacer extends farther from the substrate than the first gate spacer.

[0088] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. It should be understood by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. It should also be recognized by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0089] Example 1. A method for forming a semiconductor device, the method comprising: forming a dummy gate above a fin, wherein the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, wherein replacing the dummy gate comprises: forming a gate trench in the dielectric material, wherein forming the gate trench comprises removing the dummy gate; forming a metal gate stack in the gate trench, wherein forming the metal gate stack comprises sequentially forming a gate dielectric layer, a first work function layer, and a gap filling material in the gate trench; and expanding the volume of the gap filling material in the gate trench.

[0090] Example 2. The method of Example 1, wherein a cavity exists in the gap fill material after forming the metal gate stack and before the enlarging.

[0091] Example 3. The method of Example 2, wherein after the expanding, the cavity is filled with an expanded gap-filling material.

[0092] Example 4. The method of Example 3, wherein the gap filling material is formed of an aluminum-containing material, and wherein expanding the volume includes treating the gap filling material with a fluorine-containing chemical.

[0093] Example 5. The method of Example 4, wherein the gap filling material is formed of titanium aluminum nitride, titanium aluminum carbide, aluminum nitride, or aluminum oxide.

[0094] Example 6. The method of Example 5, wherein the fluorine-containing chemical is nitrogen trifluoride, carbon tetrafluoride, or fluorine.

[0095] Example 7. The method of Example 4, wherein treating the gap fill material comprises treating the gap fill material with a fluorine-containing gas in a thermal process.

[0096] Example 8. The method of Example 4, wherein treating the gap fill material comprises treating the gap fill material with a plasma of a fluorine-containing gas.

[0097] Example 9. The method according to Example 1 further includes: etching the metal gate stack so that the metal gate stack is recessed relative to the upper surface of the dielectric material; forming a cap layer on the recessed metal gate stack; and forming a gate contact on the cap layer.

[0098] Example 10. The method of Example 9, wherein the capping layer extends along and contacts an upper surface of the gap filling material.

[0099] Example 11. The method of Example 10, wherein the cap layer is formed of tungsten.

[0100] Example 12. The method of Example 10, wherein a lower surface of the capping layer in contact with the gap-filling material extends substantially parallel to a major upper surface of the substrate.

[0101] Example 13. A method for forming a semiconductor device, the method comprising: surrounding a dummy gate disposed on a fin with a dielectric layer, wherein the fin protrudes above a substrate; removing the dummy gate to form a trench in the dielectric layer; lining the sidewalls and bottom of the trench with a gate dielectric layer; forming one or more work function layers above the gate dielectric layer; filling the trench with a conductive material, wherein after the trench is filled, a gap exists in the conductive material; and after filling the trench, processing the conductive material to expand the volume of the conductive material, wherein after the processing, the gap is removed.

[0102] Example 14. The method of Example 13, wherein the conductive material is an aluminum-containing material, and treating the conductive material includes treating the conductive material with a fluorine-containing chemical.

[0103] Example 15. The method of Example 14, wherein processing the conductive material comprises supplying a fluorine-containing gas to the conductive material.

[0104] Example 16. The method of Example 14, wherein treating the conductive material comprises treating the conductive material with a plasma of a fluorine-containing gas.

[0105] Example 17. The method according to Example 13 further includes: after processing the conductive material, using an etching process to recess the gate dielectric layer, the one or more work function layers and the conductive material; forming a cap layer on the one or more work function layers and the conductive material; and forming a contact plug on the cap layer, and the contact plug is electrically coupled to the cap layer.

[0106] Example 18. A semiconductor device, comprising: a substrate; a fin protruding above the substrate; a metal gate structure located above the fin, wherein the metal gate structure comprises: a gate dielectric layer; a first work function layer located above the gate dielectric layer; a second work function layer located above the first work function layer; and a conductive material extending from the upper surface of the second work function layer into the second work function layer, wherein the conductive material comprises aluminum and fluorine; and a cap layer located above and in contact with the first work function layer, the second work function layer and the conductive material.

[0107] Example 19. A semiconductor device according to Example 18, wherein the cap layer extends continuously between relative inner side walls of the gate dielectric layer facing the conductive material, wherein an upper surface of the cap layer away from the substrate is flush with an upper surface of the gate dielectric layer away from the substrate.

[0108] Example 20. The semiconductor device of Example 19 further includes: a first gate spacer along a sidewall of the metal gate structure; and a second gate spacer along a sidewall of the first gate spacer, wherein the second gate spacer extends farther from the substrate than the first gate spacer.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a dummy gate on the fin, wherein the fin protrudes above the substrate; surrounding the dummy gate with a dielectric material; and Replacing the dummy gate with a replacement gate structure, wherein replacing the dummy gate comprises: forming a gate trench in the dielectric material, wherein forming the gate trench comprises removing the dummy gate; forming a metal gate stack in the gate trench, wherein forming the metal gate stack comprises sequentially forming a gate dielectric layer, a first work function layer, and a gap filling material in the gate trench; and increasing the volume of the gap-fill material in the gate trench; Wherein the gap filling material is formed of an aluminum-containing material, and wherein enlarging the volume comprises treating the gap filling material with a fluorine-containing chemical.

2. The method according to claim 1, wherein: After forming the metal gate stack and before the enlarging, a cavity exists in the gap fill material.

3. The method according to claim 2, wherein: After the expanding, the cavity is filled with the expanded gap-filling material.

4. The method according to claim 1, wherein: The gap filling material is formed of titanium aluminum nitride, titanium aluminum carbide, aluminum nitride or aluminum oxide.

5. The method according to claim 4, wherein: The fluorine-containing chemical is nitrogen trifluoride, carbon tetrafluoride or fluorine.

6. The method according to claim 1, wherein: Treating the gap-fill material includes treating the gap-fill material with a fluorine-containing gas in a thermal process.

7. The method according to claim 1, wherein: Treating the gap-fill material includes treating the gap-fill material with a plasma of a fluorine-containing gas.

8. The method according to claim 1, further comprising: etching the metal gate stack so that the metal gate stack is recessed relative to an upper surface of the dielectric material; forming a capping layer over the recessed metal gate stack; as well as A gate contact is formed over the capping layer.

9. The method according to claim 8, wherein: The capping layer extends along an upper surface of the gap-filling material and contacts an upper surface of the gap-filling material.

10. The method according to claim 9, wherein: The capping layer is formed of tungsten.

11. The method according to claim 9, wherein: A lower surface of the capping layer in contact with the gap-filling material extends substantially parallel to the main upper surface of the substrate.

12. A method for forming a semiconductor device, the method comprising: Surrounding a dummy gate disposed on a fin with a dielectric layer, wherein the fin protrudes above a substrate; removing the dummy gate to form a trench in the dielectric layer; lining the sidewalls and bottom of the trench with a gate dielectric layer; forming one or more work function layers over the gate dielectric layer; filling the trench with a conductive material, wherein after the trench is filled, a gap exists in the conductive material; and After filling the trench, processing the conductive material to expand the volume of the conductive material, wherein after the processing, the gap is removed; Wherein, the conductive material is an aluminum-containing material, and treating the conductive material includes treating the conductive material with a fluorine-containing chemical.

13. The method according to claim 12, wherein: Processing the conductive material includes supplying a fluorine-containing gas to the conductive material.

14. The method according to claim 12, wherein: Treating the conductive material includes treating the conductive material with a plasma of a fluorine-containing gas.

15. The method according to claim 12, further comprising: After processing the conductive material, recessing the gate dielectric layer, the one or more work function layers, and the conductive material using an etching process; forming a capping layer over the one or more work function layers and the conductive material; as well as A contact plug is formed over the capping layer and is electrically coupled to the capping layer.

16. A semiconductor device comprising: substrate; A fin protruding above the substrate; A metal gate structure is located on the fin, wherein the metal gate structure comprises: a gate dielectric layer; A first work function layer, located on the gate dielectric layer; a second work function layer, located on the first work function layer; and a conductive material extending from an upper surface of the second work function layer into the second work function layer, wherein the conductive material comprises aluminum and fluorine; and a capping layer, located on the first work function layer, the second work function layer and the conductive material and in contact with the first work function layer, the second work function layer and the conductive material; a first gate spacer along a sidewall of the metal gate structure; and A second gate spacer is provided along a sidewall of the first gate spacer, wherein the second gate spacer extends further from the substrate than the first gate spacer.

17. The semiconductor device according to claim 16, wherein: The capping layer continuously extends between opposite inner sidewalls of the gate dielectric layer facing the conductive material, wherein an upper surface of the capping layer remote from the substrate is flush with an upper surface of the gate dielectric layer remote from the substrate.

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