Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the display device are provided. The method for manufacturing the display device includes forming a first hole extending into a substrate using a first wet etching process with a first etchant and forming a second hole further extending into the substrate from the first hole using a second etchant. The second etchant has a pH different from that of the first etchant.

Description

Technical Field

[0001] Exemplary embodiments of this disclosure generally relate to display devices and methods for manufacturing display devices. Background Technology

[0002] Display devices are typically divided into a display area and a non-display area surrounding the display area. A display device includes: a substrate that overlaps with the display area and the non-display area; a display panel disposed on the surface of the substrate and overlapping the display area; and a driver disposed on the surface of the substrate and overlapping the non-display area. The driver provides signals or voltages to the display panel, and the display panel displays an image. The non-display area is typically the bezel of the display device. Summary of the Invention

[0003] Some implementations provide methods for manufacturing display devices with reduced bezels.

[0004] Some implementations provide display devices manufactured using this method.

[0005] A method for manufacturing a display device includes forming a first hole extending into a substrate using a first wet etching process with a first etchant and forming a second hole extending further into the substrate using a second wet etching process with a second etchant, wherein the second etchant has a pH different from that of the first etchant.

[0006] According to an embodiment, the method may further include: forming an etch stop layer on a substrate, wherein the surface of the etch stop layer contacts the substrate.

[0007] According to the embodiment, the first hole and the second hole penetrate the substrate, and the surface of the etch stop layer is exposed by the second hole.

[0008] According to an embodiment, the method may further include: forming a filler metal that fills the interior of the first hole and the second hole.

[0009] According to an embodiment, the method may further include: irradiating the substrate with a laser before forming a first hole that exposes the interior of the substrate.

[0010] According to the embodiments, the pH of the first etchant may be alkaline, and the pH of the second etchant may be acidic.

[0011] According to an embodiment, the first etchant may include potassium hydroxide, and the second etchant may include hydrofluoric acid.

[0012] According to an embodiment, the etch stop layer may include an organic material.

[0013] According to an embodiment, the method may further include: forming a third hole extending further into the substrate from the second hole using a third wet etching process with a third etchant having an alkaline pH.

[0014] According to the implementation method, the third etchant may be the same as the first etchant.

[0015] According to the implementation, the first hole, the second hole, and the third hole can penetrate the substrate together, and the surface of the etch stop layer can be exposed by the third hole.

[0016] According to an embodiment, the etch stop layer may include one of a metal and an inorganic material.

[0017] According to the embodiments, the pH of the first etchant may be acidic, and the pH of the second etchant may be alkaline.

[0018] According to an embodiment, the second etchant comprises potassium hydroxide, and the first etchant comprises hydrofluoric acid.

[0019] According to an embodiment, the etch stop layer may include one of a metal and an inorganic material.

[0020] According to an embodiment, the method may further include: forming a third hole extending further into the substrate from the second hole using a third wet etching process with a third etchant having an acidic pH.

[0021] According to an embodiment, the etch stop layer may include an organic material.

[0022] A display device according to an embodiment includes: a substrate including a hole penetrating the substrate; and a filler metal disposed on a first surface of the substrate and filling the interior of the hole. The hole may include a first hole and a second hole, and a first cone angle formed by the upper surface and side surface of the first hole and a second cone angle formed by a plane parallel to the first surface of the substrate and the side surface of the second hole may be different from each other.

[0023] According to an embodiment, the display device may further include: an etch stop layer disposed on a second surface of the substrate opposite to the first surface and overlapping the hole.

[0024] According to one embodiment, the display device may further include: a display panel disposed on a second surface of a substrate opposite to the first surface. A filler metal may be electrically connected to the display panel.

[0025] According to an embodiment, the hole may further include a third hole connected to the second hole, wherein the third hole extends further from the second hole into the substrate.

[0026] A method for manufacturing a display device includes: irradiating a substrate with a laser; forming an etch stop layer on the substrate, wherein the surface of the etch stop layer contacts the substrate; and forming a hole in the substrate at a point irradiated by the laser. The hole includes a first hole and a second hole, the first hole extending into the substrate and formed by a first wet etching process using a first etchant, and the second hole extending further into the substrate from the first hole and formed by a second wet etching process using a second etchant. The second etchant has a pH different from that of the first etchant, and the hole penetrates the substrate, exposing the surface of the etch stop layer.

[0027] In a method for manufacturing a display device according to an embodiment, a first hole is formed in a substrate using a first wet etching process with a first etchant, and a second hole connected to the first hole is formed using a second wet etching process with a second etchant having a pH different from that of the first etchant. The substrate is penetrated by the holes including the first and second holes. Since the holes are formed differently depending on the pH of the etchant, holes with desired shapes can be formed using etchants with different pH values. For example, holes with desired taper angles and desired widths can be formed. Accordingly, filler metal can be easily formed inside the holes, and the spacing between holes can be reduced. Therefore, since the display device may include a display panel disposed on a first surface of the substrate and a driving member disposed on a second surface of the substrate, the bezel of the display device can be reduced. Attached Figure Description

[0028] Figure 1 This is a block diagram of a display device according to an example embodiment.

[0029] Figure 2 yes Figure 1 A plan view of the display device.

[0030] Figure 3 yes Figure 1 A cross-sectional view of the display device.

[0031] Figure 4 yes Figure 3 A magnified view of an example of region A.

[0032] Figure 5 yes Figure 3 A magnified view of another example of region A.

[0033] Figure 6 It is a cross-sectional view of the holes formed based on the pH of the etchant.

[0034] Figures 7 to 16 It shows the manufacturing process. Figure 4 A cross-sectional view of a method for displaying a device.

[0035] Figure 17 yes Figure 3 A magnified view of another example of region A.

[0036] Figures 18 to 27 It shows the manufacturing process. Figure 17 A cross-sectional view of a method for displaying a device. Detailed Implementation

[0037] The illustrative and non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0038] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0039] Reference Figure 1 The display device 1000 according to the embodiment includes a display panel 200, a gate driver GDV, a data driver DDV, and a timing controller CON.

[0040] According to one embodiment, a plurality of pixels PX are disposed on the display panel 200. For example, each of the pixels PX receives a gate signal GS and a data voltage DS from a gate driver GDV and a data driver DDV, respectively. Each of the pixels PX emits light based on the gate signal GS and the data voltage DS. For example, the light can be any of red, green, and blue.

[0041] According to the implementation, the timing controller CON generates a gate control signal GCTRL, a data control signal DCTRL, and output image data ODAT based on the control signal CTRL received from an external device and the input image data IDAT. For example, the control signal CTRL includes a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc., and the input image data IDAT can be RGB data including red image data, green image data, and blue image data.

[0042] According to the implementation, the gate driver GDV generates the gate signal GS based on the gate control signal GCTRL received from the timing controller CON. For example, the gate control signal GCTRL includes a vertical start signal and a clock signal.

[0043] According to the embodiment, the gate driver GDV is electrically connected to the display panel 200 and sequentially outputs the gate signal GS. Each pixel PX receives the data voltage DS under the control of the gate signal GS.

[0044] According to the implementation, the data driver DDV generates the data voltage DS based on the data control signal DCTRL received from the timing controller CON and the output image data ODAT. For example, the data control signal DCTRL includes an output data enable signal, a level start signal, and a load signal.

[0045] According to one embodiment, the data driver DDV is electrically connected to the display panel 200 and outputs a data voltage DS. Each pixel PX emits light with a brightness corresponding to the data voltage DS.

[0046] Figure 2 yes Figure 1 A plan view of the display device. Figure 3 yes Figure 1 A cross-sectional view of the display device. For example, Figure 3 It is along Figure 2 The cross-sectional view taken from line I-I'.

[0047] Reference Figure 1 , Figure 2 and Figure 3 According to an embodiment, the display device 1000 includes a first substrate 100, a display panel 200, a gate driver GDV, a data driving circuit D-IC, a sealing member SEAL, a second substrate 900, and a window WIN. The display panel 200 includes a transistor layer 210 and an emitter layer 220.

[0048] According to embodiments, the first substrate 100 may include glass, quartz, or plastic, etc. The first substrate 100 is the lower substrate supporting the display panel 200. In one embodiment, the first substrate 100 is a glass substrate including glass. In this case, the display device 1000 is a rigid display device or a large display device. In another embodiment, the first substrate 100 is a plastic substrate including plastic. In this case, the display device 1000 is a flexible display device or a small-to-medium-sized display device. Hereinafter, the case where the first substrate 100 is a glass substrate will be mainly described, but embodiments of the first substrate 100 are not limited to this.

[0049] According to one embodiment, a transistor layer 210 is disposed on a first surface S1 of a first substrate 100. In another embodiment, the transistor layer 210 includes multiple lines and multiple electrodes. For example, the lines and electrodes constitute multiple transistors. The lines and electrodes receive a gate signal GS and a data voltage DS. The transistor layer 210 generates a drive current corresponding to the data voltage DS. The transistor layer 210 transmits the drive current to the emitter layer 220 in response to the gate signal GS.

[0050] According to one embodiment, an emitter layer 220 is disposed on a transistor layer 210. In one embodiment, the emitter layer 220 includes a first electrode electrically connected to the transistor, a pixel defining layer including an opening exposing the upper surface of the first electrode, an organic emitter layer disposed on the first electrode, and a second electrode disposed on the organic emitter layer. For example, the first electrode, the organic emitter layer, and the second electrode constitute an organic light-emitting diode (OLED). The organic emitter layer emits light with a brightness corresponding to the driving current. In another embodiment, the emitter layer 220 includes a first electrode electrically connected to the transistor, liquid crystal disposed on the first electrode, and a second electrode disposed on the liquid crystal.

[0051] According to one embodiment, a driving member is disposed on a second surface S2 of the first substrate 100 opposite to the first surface S1. The driving member overlaps with the display panel 200 and passes through... Figure 4 The filler metal FM shown is electrically connected to the display panel 200. For example, the filler metal FM is disposed inside a hole penetrating the first substrate 100.

[0052] For example, according to an embodiment, the driving component transmits signals or voltages to the display panel 200. The driving component includes a data driver (DDV), a gate driver (GDV), etc. Figure 2 and Figure 3 As shown, the data driver DDV is implemented using multiple data driver circuits D-IC. The data driver circuits D-IC overlap with the display panel 200 and are disposed on the second surface S2. Additionally, the gate driver GDV overlaps with the display panel 200 and is disposed on the second surface S2.

[0053] The driving component is not limited to the embodiments described above. For example, the driving component can be any component electrically connected to the display panel 200 via a filler metal FM. In one embodiment, the display device 1000 has a back-side bonding structure, wherein the display panel 200 and the driving component are disposed between a first substrate 100.

[0054] According to an embodiment, a sealing member SEAL is disposed between the first substrate 100 and the second substrate 900. For example, the upper surface of the sealing member SEAL directly contacts the lower surface of the second substrate 900, and the lower surface of the sealing member SEAL directly contacts the first surface S1 of the first substrate 100. Furthermore, the sealing member SEAL surrounds the display panel 200 in a plan view. The sealing member SEAL prevents foreign matter from penetrating into the display device 1000 and protects the display panel 200 from the influence of foreign matter.

[0055] According to one embodiment, a second substrate 900 faces the first substrate 100 and is disposed on the display panel 200 and the sealing member SEAL. In another embodiment, the second substrate 900 is a color filter substrate. For example, the second substrate 900 includes a plurality of color filters.

[0056] According to the embodiment, the window WIN is disposed on the second substrate 900. The window WIN absorbs external impacts and protects the display panel 200 from external impacts.

[0057] According to an embodiment, the display device 1000 also includes various functional layers. For example, the display device 1000 also includes a polarizing plate for polarizing external light to improve display quality, a transparent adhesive layer for transmitting light and including an adhesive material, a sensing layer for sensing the proximity and touch of a user, and an encapsulation layer for preventing moisture and oxygen penetration.

[0058] Figure 4 yes Figure 3 A magnified view of an example of region A. Figure 5 yes Figure 3 A magnified view of another example of region A.

[0059] Reference Figure 4 According to an embodiment, a hole 300 penetrating the first substrate 100 is formed in the first substrate 100. A fill metal FM is disposed inside the hole 300. An etch stop layer EST is disposed on the first surface S1 of the first substrate 100 and is in contact with the fill metal FM. The transistor layer 210 includes a buffer layer BFR, an active pattern ACT, a gate insulating layer GI, an interlayer insulating layer ILD, a source electrode SE, a drain electrode DE, a gate electrode GAT, a connection line CL, and a via insulating layer VIA. The emitter layer 220 includes a first electrode 221, a pixel defining layer PDL, an organic emitter layer 222, and a second electrode 223.

[0060] According to an embodiment, an etch stop layer EST is disposed on a first surface S1 of the first substrate 100. The etch stop layer EST protects the transistor layer 210 from damage during the wet etching process for forming the via 300. Accordingly, the etch stop layer EST comprises a material resistant to the etchant used in the wet etching process. Furthermore, the etch stop layer EST overlaps with the via 300. In an embodiment, as... Figure 4 As shown, the etch stop layer EST comprises metal and overlaps with the hole 300. In another embodiment, as... Figure 5 As shown, the etch stop layer EST1 comprises an inorganic material and overlaps with the hole 300. For example, the inorganic material is silicon oxide ("SiO2"). x ), silicon nitride ("SiN") x Silicon nitride oxide ("SiON"), aluminum oxide ("AlO") x ), titanium oxide ("TiO2") x ), tantalum oxide ("TaO") x Hafnium oxide ("HfO") x ”) and zinc oxide (“ZnO”)x One or more of the following: In this case, a hole penetrating the etch stop layer EST1 is further formed in the etch stop layer EST1.

[0061] Refer again Figure 4 According to an embodiment, a buffer layer BFR covers the etch stop layer EST and is disposed on the first surface S1 of the first substrate 100. The buffer layer BFR prevents metal atoms or impurities from diffusing from the first substrate 100 to the active pattern ACT. In addition, since the buffer layer BFR controls the heating rate during the crystallization process of forming the active pattern ACT, the active pattern ACT can be formed uniformly.

[0062] According to an embodiment, an active pattern ACT is disposed on a buffer layer BFR. For example, the active pattern ACT includes silicon semiconductor or oxide semiconductor, etc. The silicon semiconductor includes amorphous silicon or polycrystalline silicon, etc. Ions are selectively implanted into the active pattern ACT. Accordingly, the active pattern ACT is divided into a source region where ions are implanted, a drain region where ions are implanted, and a channel region between the source region and the drain region.

[0063] According to an embodiment, a gate insulating layer GI covers the active pattern ACT and is disposed on the first surface S1 of the first substrate 100. The gate insulating layer GI comprises an insulating material. For example, the gate insulating layer GI comprises silicon oxide ("SiO2"). x ), silicon nitride ("SiN") x ), titanium oxide ("TiO2") x ”) and tantalum oxide (“TaO”) x One or more of the following: ")

[0064] According to an embodiment, the gate electrode GAT overlaps with the channel region of the active pattern ACT and is disposed on the gate insulating layer GI. The gate electrode GAT comprises a conductive material. For example, the gate electrode GAT may comprise a metal, an alloy, a conductive metal oxide, or a transparent conductive material. Specifically, the gate electrode GAT comprises one or more of the following: silver (“Ag”), silver-containing alloys, molybdenum (“Mo”), molybdenum-containing alloys, aluminum (“Al”), aluminum-containing alloys, aluminum nitride (“AlN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), and indium zinc oxide (“IZO”).

[0065] According to one embodiment, an interlayer insulating layer (ILD) covers the gate electrode (GAT) and is disposed on the gate insulating layer (GI). The interlayer insulating layer (ILD) comprises an insulating material.

[0066] According to one embodiment, a source electrode SE and a drain electrode DE are disposed on an interlayer insulating layer ILD. The source electrode SE contacts the source region of the active pattern ACT through a first contact hole formed in the gate insulating layer GI and the interlayer insulating layer ILD. The drain electrode DE contacts the drain region of the active pattern ACT through a second contact hole formed in the gate insulating layer GI and the interlayer insulating layer ILD.

[0067] According to the implementation method, the active pattern ACT, the gate electrode GAT, the source electrode SE, and the drain electrode DE constitute a thin-film transistor (TFT).

[0068] According to one embodiment, the connection line CL is connected to the source electrode SE and disposed on the interlayer insulating layer ILD. For example, the connection line CL and the source electrode SE are a single metal pattern. The connection line CL contacts the etch stop layer EST through a third contact hole formed in the buffer layer BFR, the gate insulating layer GI, and the interlayer insulating layer ILD.

[0069] According to an embodiment, the through-hole insulating layer VIA covers the connection line CL, the source electrode SE, and the drain electrode DE, and is disposed on the interlayer insulating layer ILD. The through-hole insulating layer VIA comprises an organic insulating material. For example, the through-hole insulating layer VIA comprises one or more of photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, and epoxy resin. The through-hole insulating layer VIA has a substantially flat upper surface.

[0070] According to an embodiment, a driving member is disposed on the second surface S2 of the first substrate 100. As described above, the driving member is electrically connected to any component of the display panel 200 via a filler metal FM. In an embodiment, as... Figure 4 As shown, the driving component is a data driving circuit (D-IC). In another embodiment, the driving component is a gate driver (GDV).

[0071] As described above, according to the embodiment, a hole 300 penetrating the first substrate 100 is formed, and a filler metal FM is disposed inside the hole 300. The filler metal FM electrically connects the etch stop layer EST and the data drive circuit D-IC.

[0072] According to an embodiment, a first electrode 221 is disposed on a through-hole insulating layer VIA. The first electrode 221 contacts the drain electrode DE through a contact hole formed in the through-hole insulating layer VIA. The first electrode 221 is formed of a conductive material. For example, the first electrode 221 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc.

[0073] According to one embodiment, a pixel defining layer (PDL) is disposed on a via insulating layer (VIA). An opening is formed in the pixel defining layer (PDL), and a first electrode 221 and an organic emitting layer 222 are disposed in the opening.

[0074] According to an embodiment, an organic emitting layer 222 is disposed on the first electrode 221. The organic emitting layer 222 includes a light-emitting material that emits at least one of red light, green light, and blue light.

[0075] According to an embodiment, the second electrode 223 is disposed on the organic emission layer 222. The second electrode 223 comprises a conductive material. For example, the second electrode 223 comprises a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0076] Figure 6 It is a cross-sectional view of the holes formed based on the pH of the etchant.

[0077] Reference Figure 6 The holes penetrating the first substrate 100 are formed by a wet etching process. The wet etching process uses an etchant that reacts chemically with the object to be etched, such as the first substrate 100, to pattern the object to be etched. The etchant may be a liquid or a gas, and when the etchant is an acidic etchant, the pH of the etchant is less than 7, or when the etchant is an alkaline etchant, the pH of the etchant is greater than 7.

[0078] exist Figure 6 In one embodiment, the first hole H1 is formed by a first wet etching process using an acidic etchant AEC with a pH of less than 7, and the second hole H2 is formed by a second wet etching process using an alkaline etchant BEC with a pH of greater than 7.

[0079] In the case of the first wet etching process, according to the embodiment, the acidic etchant AEC has strong isotropy. In other words, the acidic etchant AEC etches the first substrate 100 in the depth direction D3 and the width direction D2 perpendicular to the depth direction D3. Accordingly, the upper surface of the first hole H1 has a large first width W1 and a small first cone angle θ1. The cone angle is formed between the upper surface of the hole and the side surface of the hole.

[0080] In the second wet etching process, according to the embodiment, the alkaline etchant BEC has weak isotropy. In other words, the alkaline etchant BEC etches the first substrate 100 in the thickness direction D3. Accordingly, the upper surface of the second hole H2 has a smaller second width W2 and a larger second cone angle θ2.

[0081] In the case of the first hole H1, according to the embodiment, since the first cone angle θ1 is small, the filler metal is easily formed inside the first hole H1. On the other hand, since the first width W1 is large, the distance to the other adjacent first hole is large.

[0082] In the case of the second hole H2, according to the embodiment, since the second width W2 is small, the distance between the second hole H2 and another adjacent second hole is short. On the other hand, since the second cone angle θ2 is large, filler metal may not form in the second hole H2.

[0083] In a method for manufacturing a display device 1000 according to an exemplary embodiment, a first etchant and a second etchant with different pH values ​​are used to form holes 300 in a first substrate 100. In other words, in the method according to the embodiment, a first wet etching process and a second wet etching process are performed sequentially. The order in which the first wet etching process and the second wet etching process are performed can be changed as needed. Accordingly, filler metal is easily formed in the holes 300 and is close to another adjacent hole. The method according to the embodiment will be described in detail below.

[0084] Figures 7 to 16 It shows the manufacturing process. Figure 4 A cross-sectional view of a method for displaying a device.

[0085] Reference Figure 4 and Figure 7 According to the embodiment, laser L is irradiated onto a first substrate 100. Specifically, laser L is irradiated onto the region where the hole 300 will be formed. Laser L selectively weakens the intermolecular bonding forces in the irradiated region of the first substrate 100. Accordingly, the hole 300 can be formed smoothly. Therefore, in the method according to the embodiment, a mask is not required when performing the wet etching process.

[0086] Reference Figure 4 and Figure 8 According to an embodiment, an etch stop layer EST is formed on the first surface S1 of the first substrate 100. In an embodiment, as... Figure 8 As shown, the etch stop layer EST is patterned to overlap with the irradiation area of ​​the first substrate 100.

[0087] Reference Figure 4 and Figure 9According to an embodiment, a first wet etching process using a first etchant BEC1 is performed. In this embodiment, the pH of the first etchant BEC1 is greater than 7. In other words, the first etchant BEC1 is an alkaline etchant. For example, the first etchant BEC1 comprises potassium hydroxide (“KOH”). When the first etchant BEC1 reacts with the first substrate 100, a first hole 310' extending into the first substrate 100 and exposing the interior of the first substrate 100 is formed at the point irradiated by the laser L. After the first hole 310' is formed, the first substrate 100 is cleaned using a cleaning solution. Accordingly, any first etchant BEC1 remaining on the first substrate 100 can be removed.

[0088] Reference Figure 4 and Figure 10 According to an embodiment, a second wet etching process using a second etchant AEC2 is performed. In this embodiment, the pH of the second etchant AEC2 is less than 7. In other words, the second etchant AEC2 is an acidic etchant. For example, the second etchant AEC2 includes hydrofluoric acid (“HF”). When the second etchant AEC2 reacts with the first substrate 100, the first hole 310' is widened to a first hole 310”, and the taper angle of the first hole 310” is reduced. Additionally, a second hole 320' is formed connected to the first hole 310”. The second hole 320' extends further into the first substrate 100 from the first hole 310”. After the second hole 320' is formed, the first substrate 100 is cleaned using a cleaning solution. Accordingly, any second etchant AEC2 remaining on the first substrate 100 can be removed.

[0089] Reference Figure 4 and Figure 11 According to an embodiment, a third wet etching process is performed using a third etchant, BEC3. In this embodiment, the pH of the third etchant, BEC3, is greater than 7. For example, the third etchant, BEC3, is the same as the first etchant, BEC1. When the third etchant, BEC3, reacts with the first substrate 100, a first hole 310, a second hole 320, and a third hole 330 are formed from a first hole 310” and a second hole 320’. The third hole 330 is connected to the second hole 320 and extends further into the first substrate 100 from the second hole 320.

[0090] In this embodiment, the first substrate 100 is penetrated through the first hole 310, the second hole 320, and the third hole 330. In other words, the upper surface of the first hole 310 coincides with the second surface S2 of the first substrate 100, the lower surface of the first hole 310 coincides with the upper surface of the second hole 320, the lower surface of the second hole 320 coincides with the upper surface of the third hole 330, and the lower surface of the third hole 330 coincides with the first surface S1 of the first substrate 100. In this case, the surfaces of the etch stop layer EST that contact the first substrate 100 (such as the surface that contacts the first surface S1) are exposed by the third hole 330.

[0091] In this embodiment, the first cone angle θ1 formed between the upper surface and the side surface of the first hole 310 is different from the second cone angle θ2 formed between the plane parallel to the second surface S2 or the first surface S1 of the first substrate 100 and the side surface of the second hole 320. Furthermore, the second cone angle θ2 and the third cone angle θ3 formed between the plane parallel to the second surface S2 or the first surface S1 of the first substrate 100 and the side surface of the third hole 330 are different from each other. In other words, the side surfaces of the first hole 310, the second hole 320, and the third hole 330 have different inclinations.

[0092] Reference Figure 4 and Figure 12 According to the embodiment, a buffer layer BFR and an active pattern ACT are formed on the first surface S1 of the first substrate 100.

[0093] Reference Figure 4 and Figure 13 According to the embodiment, a gate insulating layer GI is formed on a buffer layer BFR, a gate electrode GAT is formed on the gate insulating layer GI, and an interlayer insulating layer ILD is formed on the gate insulating layer GI and covers the gate electrode GAT.

[0094] Reference Figure 4 and Figure 14 According to an embodiment, after the first to third contact holes are formed in the buffer layer BFR, the gate insulating layer GI, and the interlayer insulating layer ILD, the source electrode SE, the drain electrode DE, and the interconnect CL are formed. Accordingly, the source electrode SE contacts the source region of the active pattern ACT, the drain electrode DE contacts the drain region of the active pattern ACT, and the interconnect CL contacts the etch stop layer EST and connects the etch stop layer EST to the source electrode SE.

[0095] Reference Figure 4 and Figure 15 According to the embodiment, a via insulating layer VIA is formed covering the connection line CL, the source electrode SE, and the drain electrode DE. In other words, a transistor layer 210 is formed.

[0096] Reference Figure 4 and Figure 16 According to the embodiment, a filler metal FM is formed inside the hole 300. For example, the filler metal FM can be formed by methods such as low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, or vacuum deposition. The filler metal FM fills the interior of the hole 300 and contacts the etch stop layer EST.

[0097] According to the implementation method, although Figure 4 Hole 300 is shown as including a first hole 310, a second hole 320, and a third hole 330, but embodiments of this disclosure are not limited thereto. For example, hole 300 may not include the third hole 330.

[0098] In detail, according to the embodiment, the hole 300 includes only a first hole 310 and a second hole 320. For example, the first substrate 100 is penetrated through the first hole 310 and the second hole 320. In other words, the upper surface of the first hole 310 coincides with the second surface S2 of the first substrate 100, the lower surface of the first hole 310 coincides with the upper surface of the second hole 320, and the lower surface of the second hole 320 coincides with the first surface S1 of the first substrate 100. In this case, the surface of the etch stop layer EST that contacts the first substrate 100 is exposed by the second hole 320. Furthermore, in order to form the first hole 310 and the second hole 320, only a first wet etching process using a first etchant BEC1 and a second wet etching process using a second etchant AEC2 are performed.

[0099] According to the implementation, the third wet etching process for forming the third hole 330 can be omitted depending on the process conditions. For example, the third wet etching process can be omitted depending on the material of the etching stop layer. Specifically, when the etching stop layer includes a material resistant to acidic etchants (such as an organic material), the third wet etching process is omitted.

[0100] Furthermore, according to the implementation method, the order of the method steps is not limited to the above. For example, refer to... Figures 11 to 15 After forming via 300, transistor layer 210 is formed. In another example, via 300 is formed after transistor layer 210 is formed. (See reference...) Figures 7 to 16 The order described is merely an example of various processes that can be performed according to the method of the implementation, and those skilled in the art can appropriately change the order.

[0101] Figure 17 It is shown Figure 3 A magnified view of another example of region A.

[0102] Reference Figure 3 and Figure 17According to an embodiment, a hole 400 penetrating the first substrate 100 is formed in the first substrate 100. A filler metal FM is disposed inside the hole 400. An etch stop layer EST2 is disposed on the first surface S1 of the first substrate 100. The transistor layer 210 includes a buffer layer BFR, an active pattern ACT, a gate insulating layer GI, an interlayer insulating layer ILD, a gate electrode GAT, a source electrode SE, a drain electrode DE, a connection line CL, and a via insulating layer VIA. The emitter layer 220 includes a first electrode 221, a pixel defining layer PDL, an organic emitter layer 222, and a second electrode 223. However, since the remaining structure, except for the hole 400 and the etch stop layer EST2, is similar to the reference... Figure 4 The constructions described are essentially the same, so the following will describe hole 400 and etch stop layer EST2.

[0103] According to an embodiment, an etch stop layer EST2 is disposed on a first surface S1 of the first substrate 100. The etch stop layer EST2 protects the transistor layer 210 so as not to damage the transistor layer 210 during a wet etching process to form the via 400. Accordingly, the etch stop layer EST2 comprises a material resistant to the etchant used in the wet etching process. Furthermore, the etch stop layer EST2 overlaps with the via 400. In an embodiment, as... Figure 17 As shown, the etch stop layer EST2 comprises an organic material and is disposed on the entire first substrate 100. For example, the organic material is one or more of photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, and epoxy resin. In this case, a hole penetrating the etch stop layer EST2 is further formed.

[0104] Figures 18 to 27 It shows the manufacturing process. Figure 17 A cross-sectional view of a method for displaying a device.

[0105] Reference Figure 17 and Figure 18 According to an embodiment, a laser L is irradiated onto a first substrate 100. Specifically, the laser L is irradiated onto the region where the hole 400 will be formed. The laser L selectively weakens the intermolecular bonding forces in the irradiated region of the first substrate 100. Accordingly, the hole 400 is formed smoothly. Therefore, in the method according to the embodiment, a mask is not required when performing the wet etching process.

[0106] Reference Figure 17 and Figure 19 According to an embodiment, an etch stop layer EST2 is formed on the first surface S1 of the first substrate 100. In the embodiment, as... Figure 19 As shown, the etch stop layer EST2 is deposited on the first substrate 100 and completely overlaps with the first substrate 100.

[0107] Reference Figure 17 and Figure 20 According to an embodiment, a first wet etching process using a first etchant AEC1 is performed. In this embodiment, the pH of the first etchant AEC1 is less than 7. In other words, the first etchant AEC1 is an acidic etchant. When the first etchant AEC1 reacts with the first substrate 100, a first hole 410' extending into the first substrate 100 and exposing the interior of the first substrate 100 is formed at the point irradiated by the laser L. After the first hole 410' is formed, the first substrate 100 is cleaned using a cleaning solution. Accordingly, any first etchant AEC1 remaining on the first substrate 100 can be removed.

[0108] Reference Figure 17 and Figure 21 According to an embodiment, a second wet etching process using a second etchant, BEC2, is performed. In this embodiment, the pH of the second etchant, BEC2, is greater than 7. In other words, the second etchant, BEC2, is an alkaline etchant. When the second etchant, BEC2, reacts with the first substrate 100, the first hole 410' is widened to a first hole 410"", and a second hole 420' is formed connected to the first hole 410"". The second hole 420' extends further into the first substrate 100 from the first hole 410"". After the second hole 420' is formed, the first substrate 100 is cleaned using a cleaning solution. Accordingly, any second etchant, BEC2, remaining on the first substrate 100 can be removed.

[0109] Reference Figure 17 and Figure 22 According to an embodiment, a third wet etching process is performed using a third etchant AEC3. In this embodiment, the pH of the third etchant AEC3 is less than 7. For example, the third etchant AEC3 is the same as the first etchant AEC1. When the third etchant AEC3 reacts with the first substrate 100, a first hole 410, a second hole 420, and a third hole 430 are formed. The third hole 430 extends further from the second hole 420 into the first substrate 100 and exposes the interior of the first substrate 100.

[0110] In this embodiment, the first substrate 100 is penetrated through the first hole 410, the second hole 420, and the third hole 430. In other words, the upper surface of the first hole 410 coincides with the second surface S2 of the first substrate 100, the lower surface of the first hole 410 coincides with the upper surface of the second hole 420, the lower surface of the second hole 420 coincides with the upper surface of the third hole 430, and the lower surface of the third hole 430 coincides with the first surface S1 of the first substrate 100. In this case, the surface of the etch stop layer EST2 that contacts the first substrate 100 is exposed by the third hole 430.

[0111] In this embodiment, the first cone angle θ1 formed between the upper surface and the side surface of the first hole 410 is different from the second cone angle θ2 formed between the plane parallel to the second surface S2 or the first surface S1 of the first substrate 100 and the side surface of the second hole 420. Furthermore, the second cone angle θ2 is different from the third cone angle θ3 formed between the plane parallel to the second surface S2 or the first surface S1 of the first substrate 100 and the side surface of the third hole 430. In other words, the side surfaces of the first hole 410, the second hole 420, and the third hole 430 have different inclinations.

[0112] Reference Figure 17 and Figure 23 According to the embodiment, a buffer layer BFR and an active pattern ACT are formed on the surface of an etch stop layer EST2 opposite to the first surface S1 of the first substrate 100.

[0113] Reference Figure 17 and Figure 24 According to the embodiment, a gate insulating layer GI is formed on a buffer layer BFR and an active pattern ACT, a gate electrode GAT is formed on the gate insulating layer GI, and an interlayer insulating layer ILD is formed on the gate insulating layer GI and covers the gate electrode GAT.

[0114] Reference Figure 17 and Figure 25 According to an embodiment, after the first to third contact holes are formed in the etch stop layer EST2, the buffer layer BFR, the gate insulating layer GI, and the interlayer insulating layer ILD, the source electrode SE, the drain electrode DE, and the connection line CL are formed. Accordingly, the source electrode SE contacts the source region of the active pattern ACT, the drain electrode DE contacts the drain region of the active pattern ACT, and the connection line CL contacts the first surface S1 of the first substrate 100 and is connected to the source electrode SE.

[0115] Reference Figure 17 and Figure 26 According to the embodiment, a via insulating layer VIA is formed on the interlayer insulating layer ILD and covers the interconnect CL, the source electrode SE, and the drain electrode DE. In other words, a transistor layer 210 is formed.

[0116] Reference Figure 17 and Figure 27 According to the embodiment, a filler metal FM is formed inside the aperture 400. For example, the filler metal FM can be formed by methods such as low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, or vacuum deposition. The filler metal FM fills the interior of the aperture 400 and contacts the connecting line CL.

[0117] According to the implementation method, although Figure 17 Hole 400 is shown as including a first hole 410, a second hole 420, and a third hole 430, but embodiments of this disclosure are not limited thereto. For example, hole 400 may not include the third hole 430.

[0118] In detail, according to the embodiment, the hole 400 includes only a first hole 410 and a second hole 420. For example, the first substrate 100 is penetrated through the first hole 410 and the second hole 420. In other words, the upper surface of the first hole 410 coincides with the second surface S2 of the first substrate 100, the lower surface of the first hole 410 coincides with the upper surface of the second hole 420, and the lower surface of the second hole 420 coincides with the first surface S1 of the first substrate 100. In addition, in order to form the first hole 410 and the second hole 420, only a first wet etching process using a first etchant AEC1 and a second wet etching process using a second etchant BEC2 are performed.

[0119] According to the implementation, the third wet etching process for forming the third hole 430 can be omitted depending on the process conditions. For example, the third wet etching process can be omitted depending on the material of the etch stop layer. Specifically, when the etch stop layer includes a material resistant to alkaline etchants (such as metals or inorganic materials), the third wet etching process using the third etchant AEC3 is omitted.

[0120] Furthermore, according to the implementation method, the order of the method steps is not limited to the above. For example, refer to... Figures 22 to 26 After forming via 400, transistor layer 210 is formed. In another example, via 400 is formed after transistor layer 210 is formed. (See reference...) Figures 18 to 27 The order described is merely an example of various processes that can be performed according to the method of the implementation, and those skilled in the art can appropriately change the order.

[0121] In the method for manufacturing a display device 1000 according to an embodiment of the present disclosure, a first hole is formed in a substrate using a first wet etching process with a first etchant, and a second hole connected to the first hole is formed using a second wet etching process with a second etchant having a pH different from that of the first etchant. The substrate is penetrated through the hole including the first hole and the second hole. Since the holes are formed differently according to the pH of the etchant, etchants with different pH can be used to form holes with desired shapes. For example, holes with desired taper angles and desired widths can be formed. Accordingly, filler metal is easily formed inside the holes, and the spacing between holes can be reduced. Therefore, since the display device 1000 includes a display panel disposed on a first surface of the substrate and a driving member disposed on a second surface of the substrate, the bezel of the display device 1000 can be reduced.

[0122] Although certain exemplary embodiments have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the embodiments of the inventive concept are not limited to such embodiments, but are limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A method for manufacturing a display device, the method comprising: A first hole extending from a first surface of a substrate into the substrate is formed by using a first wet etching process with a first etchant. as well as A second hole extending further into the substrate from the first hole is formed using a second wet etching process employing a second etchant, wherein the second etchant has a different pH than the first etchant. The method further includes forming an etch stop layer on a second surface of the substrate opposite to the first surface. The surface of the etch stop layer contacts the substrate and the etch stop layer overlaps with the first hole and the second hole.

2. The method according to claim 1, wherein, The first hole and the second hole penetrate the substrate, and the surface of the etch stop layer is exposed by the second hole.

3. The method according to claim 1, further comprising: A filler metal is formed to fill the interior of the first hole and the second hole.

4. The method according to claim 1, further comprising: Before forming the first hole in the substrate, the substrate is irradiated with a laser.

5. The method according to claim 1, wherein, The pH of the first etchant is alkaline, and the pH of the second etchant is acidic.

6. The method according to claim 5, wherein, The first etchant comprises potassium hydroxide, and the second etchant comprises hydrofluoric acid.

7. The method according to claim 5, wherein, The etch stop layer comprises an organic material.

8. The method according to claim 5, further comprising: A third hole is formed by using a third wet etching process with a third etchant having an alkaline pH, extending further into the substrate from the second hole.

9. The method according to claim 8, wherein, The third etchant is the same as the first etchant.

10. The method according to claim 8, wherein, The first hole, the second hole, and the third hole together penetrate the substrate, and the surface of the etch stop layer is exposed by the third hole.

11. The method according to claim 8, wherein, The etch stop layer comprises one of a metal and an inorganic material.

12. A method for manufacturing a display device, the method comprising: A first hole extending from a first surface of a substrate into the substrate is formed by using a first wet etching process with a first etchant. A second hole is formed by using a second wet etching process with a second etchant, extending further into the substrate from the first hole, wherein the pH of the first etchant is less than 7 and the pH of the second etchant is greater than 7; as well as A third hole is formed by using a third wet etching process with a third etchant having an acidic pH, extending further into the substrate from the second hole.

13. The method according to claim 12, wherein, The second etchant comprises potassium hydroxide, and the first etchant comprises hydrofluoric acid.

14. The method of claim 12, further comprising forming an etch stop layer on a second surface of the substrate opposite to the first surface, wherein, The etch stop layer overlaps with the first hole, the second hole, and the third hole. The etch stop layer comprises one of a metal and an inorganic material.

15. The method according to claim 12, wherein, The third etchant is the same as the first etchant.

16. The method of claim 14, wherein, The first hole, the second hole, and the third hole together penetrate the substrate, and the surface of the etch stop layer is exposed by the third hole.

17. The method according to claim 14, wherein, The etch stop layer comprises an organic material.

18. A display device, comprising: A substrate, including a hole penetrating the substrate; as well as A filler metal is disposed on the first surface of the substrate and fills the interior of the hole. The hole includes a first hole and a second hole, and The first cone angle formed by the upper surface and the side surface of the first hole is different from the second cone angle formed by the plane parallel to the first surface of the substrate and the side surface of the second hole. The display device further includes: An etch stop layer is disposed on a second surface of the substrate opposite to the first surface and overlaps with the hole.

19. The display device according to claim 18, further comprising: A display panel is disposed on the second surface of the substrate opposite to the first surface. The filler metal is electrically connected to the display panel.

20. A display device, comprising: A substrate, including a hole penetrating the substrate; as well as A filler metal is disposed on the first surface of the substrate and fills the interior of the hole. The hole includes a first hole and a second hole, and The first cone angle formed by the upper surface and the side surface of the first hole is different from the second cone angle formed by the plane parallel to the first surface of the substrate and the side surface of the second hole. The hole further includes a third hole connected to the second hole, wherein the third hole extends further from the second hole into the substrate.

21. A method for manufacturing a display device, the method comprising: The substrate is irradiated with a laser; An etch stop layer is formed on the substrate, wherein the surface of the etch stop layer contacts the substrate; and At the point in the substrate irradiated by the laser, a hole is formed in the substrate, wherein the hole includes a first hole and a second hole, the first hole extending from a first surface of the substrate into the substrate and formed by a first wet etching process using a first etchant, and the second hole further extending from the first hole into the substrate and formed by a second wet etching process using a second etchant, wherein the second etchant has a pH different from that of the first etchant. The etch stop layer is disposed on the second surface of the substrate opposite to the first surface and overlaps with the hole. The hole penetrates the substrate and the surface of the etch stop layer is exposed by the hole.

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