Voltage multiplier circuit for generating positive and negative voltages

Abstract

Embodiments of the present disclosure relate to a voltage multiplier circuit for generating positive and negative voltages. A voltage multiplier circuit supports operation in both a positive voltage boost mode to positively boost a voltage from a first node to a second node, and a negative voltage boost mode to negatively boost a voltage from a second node to the first node. The voltage multiplier circuit is formed from transistors of the same conductivity type that share a common body, the common body not being connected to the source of any of the voltage multiplier circuit transistors. A bias generator circuit is coupled to receive a first voltage from a first node and a second voltage from a second node. The bias generator circuit operates to apply the lower of the first and second voltages to the common body.

Description

[0001] This application is a divisional application of the invention patent application with the application date of October 22, 2018, application number 201811231003.0, and invention name “Voltage multiplier circuit for generating positive voltage and negative voltage”.

[0002] Priority claim

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 575,692, filed October 23, 2017, the disclosure of which is incorporated herein by reference. Technical Field

[0004] The present invention relates to voltage multiplying (eg, doubling) circuits configured to generate positive and negative voltages. Background Art

[0005] refer to Figure 1 , which shows a circuit diagram of a voltage multiplier circuit 100. Circuit 100 includes an n-channel MOS transistor MN1 (having a source terminal coupled to node A and a drain terminal coupled to node NA1) and an n-channel MOS transistor MN2 (having a source terminal coupled to node A and a drain terminal coupled to node NA2). Transistor MN1 and transistor MN2 are cross-coupled, wherein the gate terminal of transistor MN1 is coupled to the drain terminal of transistor MN2 at node NA2, and the gate terminal of transistor MN2 is coupled to the drain terminal of transistor MN1 at node NA1.

[0006] Circuit 100 also includes an n-channel MOS transistor MN3 (having a source terminal coupled to node NA1 and a drain terminal coupled to node NB1) and an n-channel MOS transistor MN4 (having a source terminal coupled to node NA2 and a drain terminal coupled to node NB2). Transistor MN3 and transistor MN4 are cross-coupled, wherein the gate terminal of transistor MN3 is coupled to the source terminal of transistor MN4 at node NA2, and the gate terminal of transistor MN4 is coupled to the source terminal of transistor MN3 at node NA1.

[0007] Circuit 100 also includes an n-channel MOS transistor MN5 (having a drain terminal coupled to node B and a source terminal coupled to node NA1) and an n-channel MOS transistor MN6 (having a drain terminal coupled to node B and a source terminal coupled to node NA2). The gate terminal of transistor MN5 is coupled to node NB1, and the gate terminal of transistor MN6 is coupled to node NB2.

[0008] Capacitor C1 has one terminal coupled to node NA1 and another terminal coupled to receive clock signal CK. Capacitor C2 has one terminal coupled to node NA2 and another terminal coupled to receive clock signal CKN (which is the logical inversion of clock signal CK). Bootstrap capacitor Cbs1 has one terminal coupled to node NB1 and another terminal coupled to receive clock signal CKH. Bootstrap capacitor Cbs2 has one terminal coupled to node NB2 and another terminal coupled to receive clock signal CKHN (which is the logical inversion of clock signal CKH).

[0009] Use in Figure 2 The clock voltage boost circuit 110 shown in FIG generates clock signals CKH and CKHN from clock signals CK and CKN. Circuit 110 includes an n-channel MOS transistor 112 (having a source terminal coupled to a positive power supply voltage node VDD and a drain terminal coupled to a node 114) and an n-channel MOS transistor 116 (having a source terminal coupled to the VDD node and a drain terminal coupled to a node 118). Transistor 112 and transistor 116 are cross-coupled, wherein the gate terminal of transistor 112 is coupled to the drain terminal of transistor 116 at node 118, and the gate terminal of transistor 116 is coupled to the drain terminal of transistor 112 at node 114.

[0010] Capacitor C1' has one terminal coupled to node 114 and another terminal coupled to receive clock signal CK. Capacitor C2' has one terminal coupled to node 118 and another terminal coupled to receive clock signal CKN.

[0011] CMOS inverter 120 has an input coupled to the VDD node and an output generating a clock signal CKH. The source terminal of the p-channel MOS transistor in inverter 120 is coupled to node 114, and the source terminal of the n-channel MOS transistor in inverter 120 is coupled to receive the clock signal CK.

[0012] CMOS inverter 122 has an input coupled to the VDD node and an output generating a clock signal CKHN. The source terminal of the p-channel MOS transistor in inverter 122 is coupled to node 118, and the source terminal of the n-channel MOS transistor in inverter 122 is coupled to receive the clock signal CKN.

[0013] The clock voltage boost circuit 110 is used to level-shift the clock signals CK and CKN to generate clock signals CKH and CKHN. Figure 3A The waveforms of the clock signals CK and CKN are shown. Figure 3B1 shows the waveforms of the clock signals CKH and CKHN. It should be noted that the clock voltage boost circuit 110 is used to boost the high voltage level of the clock signals CKH and CKHN to 2*VDD, where the high voltage level of the clock signals CK and CKN is VDD. The clock signals CKH and CKHN have the same phase as the clock signals CK and CKN, respectively.

[0014] Figure 1 The voltage multiplier circuit 100 is operable to generate a positive voltage or a negative voltage. When the voltage multiplier circuit 100 is used as a positive voltage multiplier circuit (i.e., operating in a high positive voltage mode), an input voltage such as the power supply voltage VDD is connected to node A and an output voltage such as a high positive voltage of 2*VDD is generated at node B. Conversely, when the voltage multiplier circuit 100 is used as a negative voltage multiplier circuit (i.e., operating in a high negative voltage mode), an input voltage such as the ground power supply voltage GND is connected to node B and an output voltage such as a high negative voltage of -VDD is generated at node A.

[0015] The voltage multiplier circuit 100 advantageously operates based on only two clocks (CK / CKH and CKN / CKHN).

[0016] In the high positive voltage mode, the voltage multiplier circuit 100 operates as follows:

[0017] First, assume there is no clock. In this case, nodes NA1 and NA2 will be charged to a voltage level of VDD-Vt, where Vt is the threshold voltage of n-channel MOS transistors MN1 and MN2. Now, assume a clock signal is applied. If clock signal CK is at a voltage level of VDD and clock signal CKN is at a voltage level of 0 (ground GND), then clock signal CKH is at a voltage level of 2*VDD and clock signal CKHN is at a voltage level of 0. In this configuration, node NA1 will shift to a voltage level of 2VDD-Vt, and node NA2 will shift to a voltage level of VDD. Due to the cross-coupling between transistors MN3 and MN4, node NB1 will be charged to a voltage level of 3*VDD, and node NB2 will be charged to a voltage level of VDD. When node NB1 is at a voltage level of 3*VDD and node NA1 is at a voltage level of 2*VDD, n-channel MOS transistor MN5 has sufficient Vgs (gate-to-source voltage) to pass the 2*VDD voltage from node NA1 to node B. In this way, a high positive voltage is generated (higher than the input supply voltage VDD) and passed to the output. Thus, during high positive voltage mode operation, voltage VDD is applied to node A, and a voltage of 2*VDD is generated at node B. During opposite phases of the clock, nodes NA1 and NA2 switch between the VDD voltage level and the 2*VDD voltage level. Similarly, nodes NB1 and NB2 switch between the VDD voltage level and the 3*VDD voltage level.

[0018] In the high negative voltage mode, the voltage multiplier circuit 100 operates as follows:

[0019] When the ground reference voltage GND is applied to node B, when the clock signal CKH transitions to a 2*VDD voltage level, the clock signal CK is simultaneously at the VDD voltage level, and n-channel MOS transistor MN5 turns on, charging node NA1 to a 0 (GND) voltage level. During the next clock cycle, the clock signal CKH switches from a 2*VDD voltage level to a 0 voltage level, with the clock signal CK changing from a VDD voltage level to a 0 voltage level. Consequently, node NA1 transitions from a 0 voltage level to a -VDD voltage level. Furthermore, node NB1 discharges to a -VDD voltage level due to the turning off of transistors MN3 and MN5. In this manner, node NA1 also reaches a -VDD voltage level. Due to the influence of clock signals CKN and CKHN, node NA2 is charged to a 0 (GND) voltage level via transistor MN6. When NA2 is at a 0 voltage level and NA1 is at a -VDD voltage level, this configuration causes transistor MN1 to turn on and pass the -VDD voltage level voltage to node A. In the negative high voltage operation mode, the nodes NA1 and NA2 switch between a 0 voltage level and a -VDD voltage level, and vice versa. Similarly, the nodes NB1 and NB2 switch between a VDD voltage level and a -VDD voltage level, and vice versa.

[0020] It should be noted that the aforementioned voltage levels in the positive and negative operating modes are mentioned under ideal operating conditions assuming no current load at the output and no charge loss.

[0021] Implementation of circuit 100 as an integrated circuit utilizes three different isolated P-type wells (PWELLs) for the bodies (bulks) of the transistors. Those PWELLs include: a first PWELL associated with node A for the bodies of transistors MN1 and MN2, a second PWELL associated with node NA1 for the bodies of transistors MN3 and MN5, and a third PWELL associated with node NA2 for the bodies of transistors MN4 and MN6. Those skilled in the art will recognize that providing three different isolated PWELL structures would take up a significant amount of integrated circuit area. Furthermore, because the isolated bodies are locally connected to the transistor source terminals, the bodies become capacitive due to the associated capacitance on the source nodes (this is particularly a problem at nodes NA1 and NA2 due to the large capacitance provided by capacitors C1 and C2).

[0022] There is a need in the art to address the aforementioned problems. Summary of the Invention

[0023] In one embodiment, a circuit includes a voltage multiplier circuit, the voltage multiplier circuit including a first node configured to receive a first voltage when the voltage multiplier circuit is configured to operate in a positive voltage boost mode and configured to output a negative voltage when the circuit is configured to operate in a negative voltage boost mode; a second node configured to output a positive voltage exceeding the first voltage when the voltage multiplier circuit is configured to operate in the positive voltage boost mode and configured to receive a second voltage exceeding the negative voltage when the circuit is configured to operate in the negative voltage boost mode; and a plurality of transistors of the same conductivity type and sharing a common body, the common body not connected to the source of any of the plurality of transistors; and a bias generator circuit coupled to receive the first voltage from the first node and the second voltage from the second node, the bias generator circuit configured to apply the lower of the first and second voltages to the common body.

[0024] In one embodiment, a circuit includes: a first node; a second node; a first transistor and a second transistor connected in a cross-coupling configuration, wherein the first transistor is coupled between the first node and a first intermediate node, and the second transistor is coupled between the first node and the second intermediate node; a third transistor and a fourth transistor connected in a cross-coupling configuration, wherein the third transistor is coupled between the first intermediate node and the third intermediate node, and the fourth transistor is coupled between the second intermediate node and the fourth intermediate node; a fifth transistor coupled between the first intermediate node and the second node and having a control terminal coupled to the third intermediate node; a sixth transistor coupled between the second intermediate node and the second node and having a control terminal coupled to the fourth intermediate node; wherein the first to sixth transistors share a common body that is not connected to a source of any of the first to sixth transistors; and a bias generator circuit coupled to receive a first voltage from the first node and a second voltage from the second node, the bias generator circuit being configured to apply a lower voltage of the first and second voltages to the common body; wherein the first and second intermediate nodes are capacitively coupled to receive opposite phases of a first clock signal, respectively; and wherein the third and fourth intermediate nodes are capacitively coupled to receive opposite phases of a second clock signal, respectively.

[0025] In one embodiment, a circuit includes: a first node; a second node; a first transistor and a second transistor, wherein the first transistor is coupled between the first node and a first intermediate node, and wherein the second transistor is coupled between the first node and the second intermediate node; a third transistor and a fourth transistor, wherein the third transistor is coupled between the first intermediate node and the third intermediate node, and wherein the fourth transistor is coupled between the second intermediate node and the fourth intermediate node, wherein gates of the first and fourth transistors are coupled to the third intermediate node and wherein gates of the second and third transistors are coupled to the fourth intermediate node; a fifth transistor coupled between the first intermediate node and the second node and having a control terminal coupled to the fourth intermediate node; a sixth transistor a transistor coupled between a second intermediate node and a second node and having a control terminal coupled to a third intermediate node; wherein the first to sixth transistors share a common body that is not connected to a source of any of the first to sixth transistors; and a bias generator circuit coupled to receive a first voltage from the first node and a second voltage from the second node, the bias generator circuit being configured to apply a lower voltage of the first and second voltages to the common body; wherein the first and second intermediate nodes are capacitively coupled to receive opposite phases of a first clock signal, respectively; and wherein the third and fourth intermediate nodes are capacitively coupled to receive opposite phases of a second clock signal, respectively.

[0026] In one embodiment, a circuit includes: a first node; a second node; a first transistor and a second transistor, wherein the first transistor is coupled between the first node and a first intermediate node, and wherein the second transistor is coupled between the first node and the second intermediate node; a third transistor and a fourth transistor, wherein the third transistor is coupled between the first intermediate node and the third intermediate node, and wherein the fourth transistor is coupled between the second intermediate node and the fourth intermediate node, gates of the first and fourth transistors are coupled to the third intermediate node, and gates of the second and third transistors are coupled to the fourth intermediate node; a fifth transistor coupled between the first intermediate node and the second node and having a control terminal coupled to the fourth intermediate node; a sixth transistor coupled between the second intermediate node and the second node and having a control terminal coupled to the third intermediate node; wherein the first intermediate node and the second intermediate node are capacitively coupled to receive opposite phases of a first clock signal, respectively; and wherein the third intermediate node and the fourth intermediate node are capacitively coupled to receive opposite phases of a second clock signal, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0028] Figure 1is a circuit diagram of a voltage multiplier according to the prior art;

[0029] Figure 2 This is the circuit diagram of the clock voltage boost circuit;

[0030] Figure 3A and Figure 3B shows the clock signal waveform;

[0031] Figure 4 is a circuit diagram of a voltage multiplier according to a first embodiment of the present invention;

[0032] Figure 5 yes Figure 4 Cross-sectional view of the triple-well technology implementation of the circuit;

[0033] Figure 6 is a circuit diagram of a voltage multiplier according to a second embodiment of the present invention; and

[0034] Figure 7 is a circuit diagram of a voltage multiplier according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0035] Now refer to Figure 4 , which shows a circuit diagram of the voltage multiplier circuit 200. The same reference numerals denote Figure 1 . Voltage multiplier circuit 200 differs from voltage multiplier circuit 100 in that each of n-channel transistors MN1-MN6 of circuit 200 is formed to share a common body (body) 202. Another difference is that the source terminals of n-channel MOS transistors MN1-MN6 are not connected to common body 202. However, common body 202 is not a floating node. Yet another difference is that circuit 200 further includes circuit 204 for biasing common body 202.

[0036] Bias circuit 204 is formed by a pair of n-channel MOS transistors MN7 and MN8, whose source-drain paths are connected in series between nodes A and B. More specifically, the drain of transistor MN7 is connected to node A, and the drain of transistor MN8 is connected to node B. The sources of transistors MN7 and MN8 are connected to each other and output a body bias voltage applied to the common body 202. The gate of transistor MN7 is connected to the drain of transistor MN8 at node B, and the gate of transistor MN8 is connected to the drain of transistor MN7 at node A. Transistors MN7 and MN8 thus have a cross-coupled circuit configuration.

[0037] The effect of the cross-coupling circuit configuration of transistors MN7 and MN8 between nodes A and B is that the output body bias voltage applied to common body 202 will always remain at the lower of the voltages present at nodes A and B, regardless of whether circuit 200 is operating in a high positive voltage mode or a high negative voltage mode. This ensures that there is no forward biased common body 202 in the static case. Thus, in the case of high positive voltage mode operation (e.g., VDD applied to node A and 2*VDD output from node B), the voltage at node A is lower than the voltage at node B, and bias circuit 204 biases common body 202 at the VDD voltage at node A. In the case of high negative voltage mode operation (e.g., GND applied to node B and -VDD output from node A), the voltage at node A is lower than the voltage at node B, and bias circuit 204 biases common body 202 at the voltage at node A.

[0038] Now refer to Figure 5 Circuit 200 can be fabricated using triple-well technology, wherein circuit 200 is fabricated using an isolated p-type substrate 210. An n-type well 212 is formed within p-type substrate 210. A p-type common body 202 is then formed via a p-type well 214 within n-type well 212. The n-type source and drain regions (generally referred to as 216) of transistors MN1-MN6 are then formed within the p-type well 214 of common body 202. The sources of transistors MN1-MN6 are not connected to the p-type well 214 of common body 202. Transistors MN7 and MN8 of bias circuit 204 are also formed within the p-type well 214 of common body 202 and differ from the structures of transistors MN1-MN6 in that the sources 218 of transistors MN7 and MN8 are connected to their bodies in p-type substrate 210 via a highly doped p-type region 220.

[0039] The triple-well technology structure forms two parasitic diodes 230 and 232. The first parasitic diode 230 is formed between the isolated p-type well 214 and n-type well 212. The second parasitic diode 232 is formed between the p-type substrate 210 and the n-type well 212. In this embodiment, the p-type substrate 210 is biased at ground voltage, and the bodies of all transistors MN1-MN8 are at the same potential. To ensure that neither parasitic diode 230 nor 232 becomes forward biased, the bias signal 226 for the n-type well 212 applies the maximum positive voltage of the integrated circuit through the highly doped n-type region 228 (of course, considering the safe operating area of the integrated circuit).

[0040] Implementations of circuit 200 address Figure 1This solves the problem of circuit 100. Because all transistors MN1-MN8 use a single, isolated PWELL, the occupied area is reduced. Because common body 202 is not connected to any capacitors associated with nodes NA1 or NA2, common body 202 is less capacitive, thus eliminating parasitic capacitance. As a result, the body charges / discharges first, which reduces the probability of body current flow under all operating conditions.

[0041] refer to Figure 6 , which shows a circuit diagram of a voltage multiplier circuit 300. Circuit 300 includes an n-channel MOS transistor MN11 (having a source terminal coupled to node A and a drain terminal coupled to node NA11) and an n-channel MOS transistor MN12 (having a source terminal coupled to node A and a drain terminal coupled to node NA12). The gate terminal of transistor MN11 is coupled to node NB12, and the gate terminal of transistor MN12 is coupled to node NB11.

[0042] Circuit 300 also includes an n-channel MOS transistor MN13 (having a source terminal coupled to node NA11 and a drain terminal coupled to node NB12) and an n-channel MOS transistor MN14 (having a source terminal coupled to node NA12 and a drain terminal coupled to node NB11). The gate terminal of transistor MN13 is coupled to node NB11, and the gate terminal of transistor MN14 is coupled to node NB12.

[0043] Circuit 300 also includes an n-channel MOS transistor MN15 (having a drain terminal coupled to node B and a source terminal coupled to node NA11) and an n-channel MOS transistor MN16 (having a drain terminal coupled to node B and a source terminal coupled to node NA12). The gate terminal of transistor MN15 is coupled to node NB11, and the gate terminal of transistor MN16 is coupled to node NB12.

[0044] Capacitor C11 has one terminal coupled to node NA11 and another terminal coupled to receive clock signal CK. Capacitor C2 has one terminal coupled to node NA12 and another terminal coupled to receive clock signal CKN (which is the logical inversion of clock signal CK). Bootstrap capacitor Cbs11 has one terminal coupled to node NB12 and another terminal coupled to receive clock signal CKHN. Bootstrap capacitor Cbs12 has one terminal coupled to node NB11 and another terminal coupled to receive clock signal CKH (which is the logical inversion of clock signal CKHN).

[0045] use Figure 2The clock voltage boosting circuit 110 shown in FIG. 1 generates clock signals CKH and CKHN from clock signals CK and CKN.

[0046] Figure 6 The voltage multiplier circuit 300 is operable to generate a positive voltage or a negative voltage. When the voltage multiplier circuit 300 is used as a positive voltage multiplier circuit (i.e., operating in a high positive voltage mode), an input voltage such as the power supply voltage VDD is connected to node A and an output voltage such as a high positive voltage of 2*VDD is generated at node B. Conversely, when the voltage multiplier circuit 200 is used as a negative voltage multiplier circuit (i.e., operating in a high negative voltage mode), an input voltage such as the ground power supply voltage GND is connected to node B and an output voltage such as a high negative voltage of -VDD is generated at node A.

[0047] The voltage multiplier circuit 300 advantageously operates based on only two clocks (CK / CKH and CKN / CKHN).

[0048] The voltage multiplier circuit 300 operates in the high positive voltage mode as follows:

[0049] When the circuit is used to generate a positive voltage, the power supply voltage VDD is applied to the "A" node and in the absence of a clock, nodes NA11 and NA12 will be charged to a voltage level of "VDD-Vtn". When the clock is enabled, assume that CK is "VDD", CKN is "0", CKH is "2*VDD" and CKHN is "0". With this configuration, node NA11 will be charged to "2*VDD-Vtn" and NA12 will be charged to "VDD". Due to the cross-coupling MN13 and MN14, NB11 and NB12 will be charged to "3*VDD" and "VDD", respectively. Since NB11 is at "3*VDD" and NA11 is at "2*VDD", NMOS MN15 has sufficient Vgs to pass the 2*VDD voltage from node NA1 to "B". In this way, a positive voltage (higher than the input power supply voltage) is generated and passed to the output node to drive capacitive loads and current loads. During different clock cycles, nodes NA11 and NA12 switch between "VDD" and "2*VDD." Similarly, NB11 and NB12 switch between "VDD" and "3*VDD" voltage levels.

[0050] The voltage multiplier circuit 300 operates in the high negative voltage mode as follows:

[0051] When the same circuit is used as a negative voltage generator, the clock configuration remains unchanged, but the input is applied to the "B" node and the output is taken from the "A" node. During the negative voltage configuration, the "B" node is connected to "GND" and, in the absence of a clock, NA11 and NA12 will be charged to the voltage level of "Vtn". When CKH becomes "2*VDD" (CK is "VDD" at this time), it turns on NMOS MN15 and charges node NA11 to "0". During the next clock cycle, when CKH switches from "2*VDD" to "0" and CK changes state from "VDD" to "0", node NA11 moves from "0" to "-VDD". Node NB11 also discharges to "-VDD" via transistor MN14 and turns off transistor MN15. In this way, node NA11 reaches the -VDD voltage level. Due to the influence of CKN and CKHN, node NA12 is charged to "0" via MN16. Since NA11 is at -VDD and NB12 is at VDD, this configuration turns on transistor MN11 and passes the -VDD voltage to node A. In this way, a negative voltage is generated and passed to node A. During the negative voltage configuration, nodes NA11 and NA12 switch between 0 and -VDD, and vice versa. Similarly, nodes NB11 and NB12 switch between VDD and -VDD, and vice versa.

[0052] It should be noted that the aforementioned voltage levels for the positive and negative modes of operation are mentioned under ideal operating conditions assuming no current load at the output and no charge loss.

[0053] In one embodiment, circuit 300 is implemented as an integrated circuit utilizing three different isolated P-type wells (PWELLs) for the bodies (bulks) of the transistors. Those PWELLs include: a first PWELL associated with node A for the bodies of transistors MN11 and MN12; a second PWELL associated with node NA11 for the bodies of transistors MN13 and MN15; and a third PWELL associated with node NA12 for the bodies of transistors MN14 and MN16. In this embodiment, the sources of the various transistors MN11-MN16 are connected to their respective bodies.

[0054] In an alternative embodiment, as Figure 7As shown in FIG, circuit 300′ differs from voltage multiplier circuit 300 in that each of n-channel transistors MN11-MN16 of circuit 300′ is formed to share a common body (bulk) 202. Another difference is that the source terminals of n-channel MOS transistors MN11-MN16 are not connected to common body 202. However, common body 202 is not a floating node. Yet another difference is that circuit 200′ further includes circuit 204 for biasing common body 202.

[0055] Bias circuit 204 is formed by a pair of n-channel MOS transistors MN7 and MN8, whose source-drain paths are connected in series between node A and node B. More specifically, the drain of transistor MN7 is connected to node A, and the drain of transistor MN8 is connected to node B. The sources of transistors MN7 and MN8 are connected to each other and output a body bias voltage applied to the common body 202. The gate of transistor MN7 is connected to the drain of MN8 at node B, and the gate of transistor MN8 is connected to the drain of MN7 at node A. Thus, transistors MN7 and MN8 have a cross-coupled circuit configuration.

[0056] The effect of the cross-coupling circuit configuration of transistors MN7 and MN8 between nodes A and B is that the output body bias voltage applied to common body 202 will always remain at the lower of the voltages present at nodes A and B, regardless of whether circuit 300 is operating in a high positive voltage mode or a high negative voltage mode. This ensures that common body 202 is not forward biased in the static case. Thus, in the case of operating in a high positive voltage mode (e.g., VDD is applied to node A and 2*VDD is output from node B), the voltage at node A is lower than the voltage at node B, and bias circuit 204 biases common body 202 at the VDD voltage at node A. In the case of operating in a high negative voltage mode (e.g., where GND is applied to node B and -VDD is output from node A), the voltage at node A is lower than the voltage at node B, and bias circuit 204 biases common body 202 at the voltage at node A.

[0057] The circuit 300' can be manufactured using Figure 5 The triple-well technology shown in and described previously.

[0058] The foregoing description has provided by way of exemplary and non-limiting examples a complete and informative description of the exemplary embodiments of the present invention. However, various modifications and adaptations will become apparent to those skilled in the art in view of the foregoing description when read in conjunction with the accompanying drawings and the appended claims. Nevertheless, all such and similar modifications of the teachings of this invention will still fall within the scope of the invention as defined in the appended claims.

Claims

1. A circuit comprising: A voltage multiplier circuit comprising: A first intermediate node and a second intermediate node are capacitively coupled to receive first clock signals of opposite phases, respectively; and a first transistor and a second transistor, the first transistor and the second transistor being connected in a cross-coupled configuration, wherein a first conduction terminal of the first transistor and a gate terminal of the second transistor are connected to the first intermediate node, and wherein a first conduction terminal of the second transistor and the gate terminal of the first transistor are connected to the second intermediate node; wherein the first transistor and the second transistor have the same conductivity type and share a common body, the common body not being connected to a source of either the first transistor or the second transistor; and A bias generator circuit is configured to apply a bias voltage to a common body of the first transistor and the second transistor.

2. The circuit according to claim 1, wherein The bias generator circuit receives a first voltage from a first node and a second voltage from a second node, the bias generator circuit being configured to apply a lower voltage of the first voltage and the second voltage to the common body.

3. The circuit according to claim 2, wherein Each of the first transistor and the second transistor has a source-drain path coupled between the first node and the second node.

4. The circuit according to claim 3, wherein Sources of the first transistor and the second transistor are connected to the first node.

5. The circuit according to claim 2, wherein The bias generator circuit includes a first bias transistor and a second bias transistor having source-drain paths coupled in series between the first node and the second node at a common source connected to the common body, and wherein gates of the first bias transistor and the second bias transistor are cross-coupled to drains of the second bias transistor and the first bias transistor, respectively. 6 . The circuit of claim 5 , wherein the first bias transistor and the second bias transistor have the same conductivity type as the first transistor and the second transistor of the voltage multiplier circuit.

7. The circuit of claim 6 , wherein the first bias transistor and the second bias transistor have sources and drains formed in the common body, and wherein the first transistor and the second transistor of the voltage multiplier circuit have sources and drains formed in the common body.

8. The circuit of claim 1 , wherein the first transistor and the second transistor are implemented in triple-well technology, the triple-well technology including a p-type region, an isolated n-type well in the p-type region, and a p-type well forming the common body in the isolated n-type well.

9. The circuit of claim 8, further comprising an additional bias for biasing the isolated n-type well at a voltage level at least as high as a voltage at the p-type region and a voltage at the common body.

10. The circuit of claim 1 , wherein the voltage multiplier circuit further comprises: A third intermediate node and a fourth intermediate node are capacitively coupled to receive second clock signals with opposite phases, respectively; as well as a third transistor and a fourth transistor connected in a cross-coupled configuration, wherein a first conduction terminal of the third transistor and a gate terminal of the fourth transistor are connected to the first intermediate node, and wherein a first conduction terminal of the fourth transistor and a gate terminal of the third transistor are connected to the second intermediate node; The third transistor and the fourth transistor are of the same type and share a common body, the common body not being connected to a source of either the third transistor or the fourth transistor.

11. The circuit of claim 10 , wherein the first to fourth transistors are implemented in triple-well technology, the triple-well technology including a p-type region, an isolated n-type well in the p-type region, and a p-type well forming the common body in the isolated n-type well.

12. The circuit of claim 11, further comprising an additional bias for biasing the isolated n-type well at a voltage level at least as high as a voltage of the p-type region and a voltage of the common body.

13. The circuit according to claim 10, wherein The first clock signal and the second clock signal have aligned phases.

14. The circuit of claim 1, wherein: The voltage multiplier circuit further includes: a first node configured to receive a first voltage when the voltage multiplier circuit is configured to operate in a positive voltage boost mode, and configured to output a negative voltage when the voltage multiplier circuit is configured to operate in a negative voltage boost mode; and a second node configured to output a positive voltage exceeding the first voltage when the voltage multiplier circuit is configured to operate in the positive voltage boost mode, and configured to receive a second voltage exceeding the negative voltage when the voltage multiplier circuit is configured to operate in the negative voltage boost mode; The source-drain paths of the first transistor and the second transistor are coupled between the first node and the second node.

15. The circuit of claim 14, wherein: The bias generator circuit is coupled to receive the first voltage from the first node and the second voltage from the second node, the bias generator circuit being configured to apply a lower voltage of the first voltage and the second voltage to the common body.

16. The circuit of claim 14 , wherein the bias generator circuit comprises: a first bias transistor and a second bias transistor, the first bias transistor and the second bias transistor having source-drain paths coupled in series between the first node and the second node at a common source, and wherein gates of the first bias transistor and the second bias transistor are cross-coupled to drains of the second bias transistor and the first bias transistor, respectively.

17. The circuit of claim 16, wherein: The first bias transistor and the second bias transistor have the same conductivity type as the first transistor and the second transistor of the voltage multiplier circuit.

18. The circuit of claim 17, wherein: The first bias transistor and the second bias transistor have sources and drains formed in a common body with sources and drains of the first transistor and the second transistor of the voltage multiplier circuit.

19. A circuit comprising: First node; Second node; a first transistor and a second transistor connected in a cross-coupled configuration, wherein the first transistor is coupled between the first node and a first intermediate node, and the second transistor is coupled between the first node and the second intermediate node; wherein the first intermediate node and the second intermediate node are capacitively coupled to respectively receive first clock signals of opposite phases; a third transistor coupled between the first intermediate node and the second node; a fourth transistor coupled between the second intermediate node and the second node; wherein the first to fourth transistors share a common body that is not connected to a source of any of the first to fourth transistors; as well as A bias generator circuit is coupled to receive a first voltage from the first node and a second voltage from the second node, the bias generator circuit being configured to apply a lower voltage of the first voltage and the second voltage to a common body.

20. The circuit of claim 19, wherein The first to fourth transistors are all n-channel MOS transistors.

21. The circuit of claim 20, wherein: The first to fourth transistors are implemented in a triple-well technology including a p-type region, an isolated n-type well in the p-type region, and a p-type well forming the common body in the isolated n-type well.

22. The circuit of claim 21, further comprising an additional bias for biasing the isolated n-type well at a voltage level at least as high as a voltage of the p-type region and a voltage of the common body.

23. The circuit of claim 19, wherein: The bias generator circuit includes a first bias transistor and a second bias transistor, the first bias transistor and the second bias transistor having source-drain paths coupled in series at a common source electrically coupled to the common body, and wherein gates of the first bias transistor and the second bias transistor are cross-coupled to drains of the second bias transistor and the first bias transistor, respectively.

24. The circuit of claim 23, wherein: The first bias transistor and the second bias transistor have the same conductivity type as the first to fourth transistors.

25. The circuit of claim 24, wherein: The first bias transistor and the second bias transistor have sources and drains formed in the common body with sources and drains of the first to fourth transistors.

26. The circuit of claim 23, wherein: The first bias transistor and the second bias transistor have sources and drains formed in the common body with sources and drains of the first to fourth transistors.

27. A circuit comprising: A voltage multiplier circuit comprising: A first intermediate node and a second intermediate node are capacitively coupled to receive first clock signals of opposite phases, respectively; a first transistor having a first conduction terminal connected to the first intermediate node; a second transistor having a first conduction terminal connected to the second intermediate node; and a third transistor and a fourth transistor connected in a cross-coupled configuration, wherein a first conduction terminal of the third transistor is connected to the gate terminal of the first transistor and the gate terminal of the fourth transistor, and wherein a first conduction terminal of the fourth transistor is connected to the gate terminal of the second transistor and the gate terminal of the third transistor; wherein the third transistor and the fourth transistor have the same conductivity type and share a common body that is not connected to sources of the third transistor and the fourth transistor; and A bias generator circuit is configured to apply a bias voltage to a common body of the third transistor and the fourth transistor.

28. The circuit of claim 27, wherein the second conduction terminal of the third transistor is connected to the first intermediate node, and wherein the second conduction terminal of the fourth transistor is connected to the second intermediate node.

29. The circuit of claim 27, wherein: The bias generator circuit receives a first voltage from a first node and a second voltage from a second node, the bias generator circuit being configured to apply a lower voltage of the first voltage and the second voltage to a common body.

30. The circuit of claim 29, wherein: Each of the first transistor and the second transistor has a source-drain path coupled between the first node and the second node.

31. The circuit of claim 30, wherein: Sources of the first transistor and the second transistor are connected to the first node.

32. The circuit of claim 29, wherein: The bias generator circuit includes: a first bias transistor and a second bias transistor, the first bias transistor and the second bias transistor having source-drain paths coupled in series between the first node and the second node at a common source connected to the common body, and wherein the gates of the first bias transistor and the second bias transistor are cross-coupled to the drains of the second bias transistor and the first bias transistor, respectively.

33. The circuit of claim 32, wherein: The first bias transistor and the second bias transistor have the same conductivity type as the first transistor, the second transistor, the third transistor, and the fourth transistor of the voltage multiplier circuit.

34. The circuit of claim 33, wherein the first bias transistor and the second bias transistor have sources and drains formed in the common body, and wherein the third transistor and the fourth transistor of the voltage multiplier circuit have sources and drains formed in the common body.

35. The circuit of claim 27, wherein: The first transistor and the second transistor have the same conductivity type and share the common body that is not connected to sources of the first transistor and the second transistor.

36. The circuit of claim 27 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are implemented in triple-well technology, the triple-well technology including a p-type region, an isolated n-type well in the p-type region, and a p-type well forming the common body in the isolated n-type well.

37. The circuit of claim 36, further comprising an additional bias for biasing the isolated n-type well at a voltage level at least as high as a voltage of the p-type region and a voltage of the common body.

38. The circuit of claim 27, wherein: The voltage multiplier circuit further comprises: A third intermediate node and a fourth intermediate node are capacitively coupled to receive second clock signals with opposite phases, respectively; wherein the third intermediate node is connected to a first conduction terminal of the third transistor, and wherein the fourth intermediate node is connected to a first conduction terminal of the fourth transistor.

39. The circuit of claim 38, wherein The first clock signal and the second clock signal have aligned phases.

40. The circuit of claim 27, wherein: The voltage multiplier circuit further comprises: a first node configured to receive a first voltage when the voltage multiplier circuit is configured to operate in a positive voltage boost mode and configured to output a negative voltage when the voltage multiplier circuit is configured to operate in a negative voltage boost mode; and a second node configured to output a positive voltage exceeding the first voltage when the voltage multiplier circuit is configured to operate in a positive voltage boost mode, and configured to receive a second voltage exceeding the negative voltage when the voltage multiplier circuit is configured to operate in a negative voltage boost mode; The source-drain paths of the first transistor and the second transistor are coupled between the first node and the second node.

41. The circuit of claim 40, wherein The bias generator circuit is coupled to receive a first voltage from the first node and a second voltage from the second node, the bias generator circuit being configured to apply a lower voltage of the first and second voltages to the common body.

42. The circuit of claim 40, wherein: The bias generator circuit includes: a first bias transistor and a second bias transistor having source-drain paths coupled in series between the first node and the second node at a common source, and wherein gates of the first bias transistor and the second bias transistor are cross-coupled to drains of the second bias transistor and the first bias transistor, respectively.

43. The circuit of claim 42, wherein: The first bias transistor and the second bias transistor have the same conductivity type as the first transistor, the second transistor, the third transistor, and the fourth transistor of the voltage multiplier circuit.

44. The circuit of claim 43, wherein: The first bias transistor and the second bias transistor have sources and drains formed in the common body with sources and drains of the first transistor and the second transistor of the voltage multiplier circuit.

45. A circuit comprising: A voltage multiplier circuit comprising: A first intermediate node and a second intermediate node are capacitively coupled to receive first clock signals of opposite phases, respectively; A third intermediate node and a fourth intermediate node are capacitively coupled to receive second clock signals with opposite phases, respectively; a first transistor and a second transistor connected in a cross-coupled configuration, wherein: a first conduction terminal of the first transistor connected to the first intermediate node, and wherein the second conduction terminal of the first transistor is connected to the gate terminal of the second transistor and to the third intermediate node; and a first conduction terminal of the second transistor connected to the second intermediate node, and wherein the second conduction terminal of the second transistor is connected to the gate terminal of the first transistor and to a fourth intermediate node; wherein the first transistor and the second transistor have the same conductivity type and share a common body that is not connected to sources of the first transistor and the second transistor; and A bias generator circuit is configured to apply a bias voltage to a common body of the first transistor and the second transistor.

46. The circuit of claim 45, wherein The first clock signal and the second clock signal have aligned phases.

47. The circuit of claim 45, further comprising: a third transistor having a source-drain path coupled between the first node and the second node, wherein a gate terminal of the third transistor is connected to a third intermediate node; and A fourth transistor has a source-drain path coupled between the first node and the second node, wherein a gate terminal of the fourth transistor is connected to a fourth intermediate node.

48. The circuit of claim 47, wherein The third and fourth transistors have the same conductivity type and share the common body that is not connected to sources of the third and fourth transistors.

49. The circuit of claim 48, wherein the first to fourth transistors are implemented in triple-well technology, the triple-well technology comprising a p-type region, an isolated n-type well in the p-type region, and a p-type well forming the common body in the isolated n-type well.

50. The circuit of claim 49, further comprising an additional bias for biasing the isolated n-type well at a voltage level at least as high as a voltage of the p-type region and a voltage of the common body.

51. The circuit of claim 47, wherein: The bias generator circuit receives a first voltage from the first node and a second voltage from the second node, the bias generator circuit being configured to apply a lower voltage of the first voltage and the second voltage to the common body.

52. The circuit of claim 51 , wherein: Sources of the third and fourth transistors are connected to the first node.

53. The circuit of claim 47, wherein: The bias generator circuit includes: first and second bias transistors having source-drain paths coupled in series between a first node and a second node at a common source connected to the common body, and wherein gates of the first and second bias transistors are cross-coupled to drains of the second bias transistor and the first bias transistor, respectively.

54. The circuit of claim 53, wherein: The first bias transistor and the second bias transistor have the same conductivity type as the first transistor, the second transistor, the third transistor, and the fourth transistor of the voltage multiplier circuit.

55. The circuit of claim 54, wherein the first bias transistor and the second bias transistor have sources and drains formed in the common body, and wherein the third transistor and the fourth transistor of the voltage multiplier circuit have sources and drains formed in the common body.

56. The circuit of claim 47, wherein: The first node is configured to receive a first voltage when the voltage multiplier circuit is configured to operate in a positive voltage boost mode, and is configured to output a negative voltage when the voltage multiplier circuit is configured to operate in a negative voltage boost mode; and The second node is configured to output a positive voltage exceeding the first voltage when the voltage multiplier circuit is configured to operate in a positive voltage boost mode, and is configured to receive a second voltage exceeding the negative voltage when the voltage multiplier circuit is configured to operate in a negative voltage boost mode.

57. The circuit of claim 56, wherein: The bias generator circuit is coupled to receive a first voltage from a first node and a second voltage from a second node, the bias generator circuit being configured to apply a lower voltage of the first voltage and the second voltage to the common body.

58. The circuit of claim 56, wherein the bias generator circuit comprises: A first bias transistor and a second bias transistor having source-drain paths coupled in series between the first node and the second node at a common source, and wherein gates of the first bias transistor and the second bias transistor are cross-coupled to drains of the second bias transistor and the first bias transistor, respectively.

59. The circuit of claim 58, wherein The first bias transistor and the second bias transistor have the same conductivity type as the first transistor and the second transistor of the voltage multiplier circuit.

60. The circuit of claim 58, wherein The first and second bias transistors have sources and drains formed in a common body with sources and drains of the first and second transistors of the voltage multiplier circuit.

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