Driver circuit, corresponding device and operation method

Abstract

Disclosed are a driver circuit, corresponding device, and operating method. The circuit includes first and second input power supply nodes that receive a power supply voltage therebetween. The circuit includes a high-side driver circuit coupled to a high-side switch and generating a first signal between a first high-side output node and a second high-side output node. The circuit includes a low-side driver circuit coupled to a low-side switch and generating a second signal between a first low-side output node and a second low-side output node. The circuit includes: a floating node that receives a floating voltage applied between the floating node and the second high-side output node; a bootstrap diode located between the first input power supply node and an intermediate node; and a current limiter circuit located between the intermediate node and the floating node that senses the floating voltage and offsets current flowing from the intermediate node to the floating node due to the floating voltage reaching a threshold.

Description

Technical Field

[0001] This specification relates to a half-bridge switching circuit with a high-side bootstrap architecture. Background Art

[0002] High voltage (HV) half-bridge switching circuits known in the art may be used in various applications, such as motor drive devices, electronic ballasts for fluorescent lamps, power supply devices, and other devices.

[0003] Gallium nitride (GaN) power transistors are increasingly being used in half-bridge switching circuits to replace traditional power transistors, such as conventional silicon MOS field-effect transistors or insulated gate bipolar transistors (IGBTs), with the goal of improving the overall efficiency of the switching circuits. For example, GaN power transistors offer lower gate capacitance and higher switching speeds.

[0004] Known circuit arrangements for driving GaN power transistors in half-bridge switching circuits may not provide satisfactory performance in terms of efficiency and / or robustness. Summary of the Invention

[0005] It is an object of one or more embodiments to provide a driver circuit for a half-bridge switching circuit with improved efficiency and / or robustness.

[0006] For example, such circuitry may be fully integrated in a monolithic integrated circuit (IC) or chip.

[0007] One or more embodiments may be directed to corresponding devices (eg, an active clamp flyback converter, or a resonant LLC converter).

[0008] One or more embodiments may be directed to a corresponding method of operating the circuit or device.

[0009] According to one or more embodiments, a circuit may include a first input power node and a second input power node configured to receive a first power supply voltage applied between the first input power node and the second input power node, a first input control node configured to receive a first input control signal, and a second input control node configured to receive a second input control signal. The circuit may include a high-side driver circuit configured to couple to a high-side switch of a half-bridge circuit, the high-side driver circuit configured to receive the first input control signal and generate a first output control signal between a first high-side output node and a second high-side output node for controlling the high-side switch. The circuit may include a low-side driver circuit configured to couple to a low-side switch of the half-bridge circuit, the low-side driver circuit configured to receive a second input control signal and generate a second output control signal between the first low-side output node and the second low-side output node for controlling the low-side switch. The circuit may include a floating power supply node configured to receive a floating power supply voltage applied between the floating power supply node and the second high-side output node. The high-side driver circuit may be electrically coupled between the floating power supply node and the second high-side output node to receive the floating power supply voltage. The circuit may include a bootstrap diode having an anode coupled to the first input power supply node and a cathode coupled to the intermediate power supply node; and a current limiter circuit coupled between the intermediate power supply node and the floating power supply node. The current limiter circuit may be configured to sense a floating power supply voltage and offset a current flowing from the intermediate power supply node to the floating power supply node due to the floating power supply voltage reaching a threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings.

[0011] Figure 1 is an exemplary circuit block diagram of a half-bridge switching circuit including a high-side bootstrap architecture and a related driving circuit device,

[0012] Figure 2A 、 3A 4A are exemplary circuit block diagrams of various bootstrap architectures for half-bridge switching circuits,

[0013] Figure 2B 、 3B and 4B respectively Figure 2A 、 3A Examples of possible waveforms for signals in the circuits shown in 4A,

[0014] Figure 5A is an exemplary circuit block diagram of a bootstrap architecture for a half-bridge switching circuit according to one or more embodiments,

[0015] Figure 5B Yes Figure 5A Examples of possible waveforms of signals in one or more of the illustrated embodiments,

[0016] Figure 6 is an exemplary circuit block diagram of a half-bridge switching circuit including a high-side bootstrap architecture and a related driving circuit device according to one or more embodiments.

[0017] Figure 7 is an exemplary circuit block diagram of implementation details of one or more embodiments,

[0018] Figure 8 is an example of a possible waveform of a signal in one or more embodiments,

[0019] Figure 9 is an exemplary circuit block diagram of implementation details of one or more embodiments,

[0020] Figure 10 is an exemplary circuit block diagram of a level shifter circuit, and

[0021] Figure 11 is an exemplary circuit block diagram of a level shifter circuit according to one or more embodiments. DETAILED DESCRIPTION

[0022] In the following description, one or more specific details are shown to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not described or illustrated in detail so that some aspects of the embodiments are not obscured.

[0023] References to "an embodiment" or "one embodiment" throughout this specification are intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification are not necessarily referring to one and the same embodiment. Furthermore, particular configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0024] Throughout the drawings appended hereto, the same parts or elements are denoted by the same reference numerals / numbers, and the corresponding descriptions will not be repeated for the sake of brevity.

[0025] As an introduction to the detailed description of the exemplary embodiments, reference may first be made to Figure 1 .

[0026] Figure 1is an exemplary circuit block diagram of a half-bridge switching circuit and associated driving circuitry, wherein the driving circuitry relies on a conventional high-side bootstrap architecture.

[0027] like Figure 1 As shown, the half-bridge switching circuit 10 includes a high-side power transistor HS and a low-side power transistor LS having a node 102 a located intermediate the high-side power transistor HS and the low-side power transistor LS.

[0028] The high-side transistor HS is configured to provide a DC voltage V BUS A current flow line is provided between the DC high voltage supply rail 108 and the intermediate node 102a (eg, the drain terminal of the high-side transistor HS may be coupled to the positive DC high voltage rail 108, and the source terminal of the high-side transistor HS may be coupled to the node 102a).

[0029] The low-side transistor LS is configured to provide a current flow line between the intermediate node 102a and a reference voltage node 102b, for example, coupled to ground GND (e.g., the drain terminal of the low-side transistor LS can be coupled to the node 102a and the source terminal of the low-side transistor LS can be coupled to the reference GND of the DC high voltage rail).

[0030] According to different applications of the embodiment, the DC voltage V BUS The value of can be chosen in a wide range of values, for example, between 20 V and 1 kV. Purely as a non-limiting example, the DC voltage V BUS The value of can be around 190V.

[0031] Therefore, the pair of nodes 102a, 102b may be configured to provide an output voltage V to an (external) load L that may be coupled therebetween. OUT (For example, transistors HS, LS may be arranged according to a so-called totem pole configuration.) Figure 1 As shown, the load L can be an inductive load.

[0032] Note that a load L coupled between nodes 102a, 102b is shown purely by way of non-limiting example. According to various embodiments, the circuit may be applied to a variety of load topologies.

[0033] Note that the high-side transistor HS and the low-side transistor LS may include corresponding drain-body diodes, such as Figure 1 The high-side transistor HS and the low-side transistor LS may include gallium nitride (GaN) power transistors, and optionally, enhanced GaN power transistors.

[0034] The half-bridge switching circuit 10 may include a pair of input terminals 100a, 100b configured to receive a power supply voltage V between them from a power supply PS coupled thereto. CC The (negative) input terminal 100b may be coupled to the same reference voltage node GND described previously. Thus, the input terminals 100a, 100b may provide a DC low voltage supply rail.

[0035] Power supply voltage V CC The half-bridge driver circuit HBD may be powered and configured to control the switching activity of the transistors HS, LS. In particular, the half-bridge driver circuit HBD may receive an input control signal IN HS and IN LS , for controlling the switching activities of transistors HS and LS, respectively. In one or more embodiments, the driver circuit HBD may be fully integrated in a monolithic integrated circuit (IC).

[0036] According to different applications of the embodiment, the power supply voltage V CC The value of can be selected within a range of values, for example, between 5 V and 24 V. In particular, in the specific case of a driver circuit HBD driving an enhanced GaN power transistor, the supply voltage V CC It can be around 5V.

[0037] like Figure 1 As shown, the half-bridge drive circuit HBD may include a high-side gate driver circuit 12a (e.g., a buffer stage) that provides a control signal for the high-side transistor HS at an output node 120a and a low-side gate driver circuit 12b (e.g., a buffer stage) that provides a control signal for the low-side transistor LS at an output node 120b.

[0038] Input control signal IN LS Can be propagated (directly) to the low-side gate driver circuit 12b. Input control signal IN HS The input control signal IN may be propagated to the high-side gate driver circuit 12a by means of the level shifter circuit 14, which is configured to HS From the low voltage portion (V CC to GND) is transferred to the floating portion FS (V BOOT To V OUT ).

[0039] like Figure 1 As shown, the bootstrap architecture can be used to generate a DC voltage source V between nodes 104 and 102a. CB , where the DC voltage source V CBRelative to the DC low voltage supply rail V CC is floating so as to provide a floating portion FS of the half-bridge switching circuit 10. Therefore, the DC voltage supply V CB This can be achieved, for example, by providing a high voltage diode DB from the DC low voltage supply rail V CC The high voltage diode DB is coupled to the DC low voltage supply rail V CC The anode of the positive terminal 100 a and the cathode are coupled to the floating supply voltage node 104 .

[0040] like Figure 1 As shown, a bootstrap capacitor C is provided between the (positive) output terminal 102a and the floating supply voltage node 104. B A capacitor (e.g., mounted external to circuit 10) may be configured to store charge (during a bootstrap "recharge" phase) in order to provide a DC voltage supply V CB , used to power the high-side gate driver circuit 12a (during the bootstrap "power" phase), as described below.

[0041] Bootstrap capacitor C B The value of can be selected based on a set of parameters, such as the gate-source capacitance of the power transistors HS and LS, the output frequency and the duty cycle. B The value of can be selected within a wide range of values, for example, within a few tens of nF (1nF = 10 -9 F) and several μF (1 μF = 10 -6 F). As a non-limiting example only, the bootstrap capacitor C B The value can be around 100nF.

[0042] As a result of the low-side transistor LS being turned on (bootstrap recharging phase), the (positive) output terminal 102a is coupled to the reference voltage node GND (e.g., 0V), and the diode DB allows current to flow from the DC low-voltage supply rail V CC The positive terminal 100a flows to the bootstrap capacitor C B , thereby the bootstrap capacitor C B Charge to approximately V CC Since the low-side transistor LS is turned off and the high-side transistor HS is turned on (bootstrap supply phase), the voltage at the (positive) output terminal 102a is approximately equal to V BUS This causes diode DB to become reverse biased (as long as node 104 exhibits a voltage level approximately equal to V CC +V BUS The voltage value V BOOT ), and offset the bootstrap capacitor C BAs a result of the diode DB remaining reverse biased, the current flowing to the node 100a is stored in the bootstrap capacitor C B The charge stored in the bootstrap capacitor C B The finite amount of charge in the bootstrap capacitor C can provide a finite amount of time for the high-side gate driver circuit 12a. In the subsequent switching cycle, when the high-side transistor HS is turned off and the low-side transistor LS is turned on again, the bootstrap capacitor C B The charge in can be restored.

[0043] Therefore, in Figure 1 In the half-bridge switching circuit 10 shown, the gate-source voltage of the high-side transistor HS can be controlled by the bootstrap capacitor C that supplies power to the gate driver circuit 12a. B Note that the gate-source voltage of the enhanced GaN power transistor can advantageously be limited to less than 6V, for example, to meet certain technical requirements. Therefore, an improved solution may aim to reduce the bootstrap capacitor C B The voltage across the two ends V CB limited to a value below an upper threshold (e.g., 6V).

[0044] It should also be noted that in order to improve the power efficiency of the high-side transistor HS, the bootstrap capacitor C B can benefit from as much charging as possible (within the limits discussed above), for example, to achieve a bootstrap voltage V above a lower threshold (e.g. 4V) CB .

[0045] Therefore, an improved solution may aim to maintain the voltage applied to the gate of the high-side transistor HS within a range of values (e.g., 4V to 6V). An applied gate voltage above this range may stress the high-side transistor, while an applied gate voltage below this range may reduce system efficiency. An improved solution may aim to keep the gate voltage of the high-side transistor HS below an upper threshold to protect it from electrical stress, while keeping the gate voltage as close to the upper threshold as possible to improve efficiency.

[0046] Figure 2A Yes Figure 1 The exemplary circuit block diagram of the bootstrap circuit of the illustrated half-bridge switching circuit does not show certain components of the circuit 10 that are not directly related to the bootstrap function. Figure 1 The bootstrap circuit includes a low voltage DC power rail V CC A bootstrap diode DB is coupled between the positive terminal 100a and the floating supply voltage node 104, and a bootstrap capacitor C is coupled between the floating supply voltage node 104 and the (positive) output terminal 102a. BThe (positive) output terminal 102a is selectively coupled to a voltage reference node 102b via a switch (e.g., a low-side transistor LS) or to a DC high voltage positive rail V (e.g., via a high-side transistor HS). BUS .

[0047] Figure 2B yes Figure 2A The schematic circuit of the bootstrap capacitor C B The bootstrap voltage V CB Examples of possible waveforms during the supply phase T1 and the recharge phase T2. Voltage V TH,H is the bootstrap voltage V CB For example, the upper threshold value (eg, 6V) is TH,L is the bootstrap voltage V CB Example of a lower threshold value (eg, 4V). Voltage V D is the bootstrap voltage V CB Examples of expected values, for example, below V TH,H But sufficiently close to V TH,H To provide the bootstrap capacitor C B A satisfactory efficiency value to be achieved during the "recharging" phase.

[0048] Note that depending on the voltage level of the "floating ground" of the floating portion FS (ie, the output terminal 102a), as shown Figure 2A The illustrated circuit may provide unsatisfactory behavior.

[0049] For example, if the voltage level of the floating ground 102a is (largely) lower than the voltage level of the reference node GND during the recharging phase T2, the bootstrap voltage V CB Can overcome the upper threshold V TH,H ,like Figure 2B. Note that as a result of the current of the inductive load recirculating in the low-side power transistor LS, for example, when the load current flows out of the half-bridge output node 102a and flows from the GND reference into the source terminal of the low-side power transistor LS, the voltage of the floating ground 102a can be lower than the reference GND. A higher recirculating current can result in a lower voltage at node 102a. Note that in the case of a MOS power transistor, the voltage difference between node 102a and the reference GND can be limited by the drain-source diode (also called a freewheeling diode) of the low-side power transistor, which is directly biased and therefore keeps the voltage difference in the range of about 1V to 2V depending on the current intensity. In the case of a GaN transistor without a freewheeling diode, the voltage difference can reach higher values (e.g., in the range of 4V to 8V) as long as the voltage drop can be maintained by the channel of the GaN transistor in reverse conduction. The worst-case scenario can be represented by the gate of the GaN transistor being biased to the reference node GND and the current flowing into the GaN transistor being at its maximum, for example, during the half-bridge dead time. In this case, the voltage drop is determined by the sum of the threshold voltage of the conduction channel, the voltage drop along the channel, and the parasitic resistance in series with the power transistor.

[0050] On the other hand, if the voltage level of the floating ground 102a is close to or higher than the voltage level of the reference node GND during the recharging phase T2, the bootstrap voltage V CB Can be kept (well) below the desired value V D (For example, due to the voltage drop V across the bootstrap diode DB L ),like Figure 2B As shown by the dashed line in FIG. When the current in the load is zero, the voltage of the floating ground can be near GND. Note that during the recharging phase T2, the voltage level of the floating ground 102a can increase above the reference GND due to the current of the inductive load flowing into the half-bridge output pin 102a and flowing from the drain terminal of the low-side power transistor LS into the GND reference.

[0051] This may occur, for example, when the low-side power transistor LS is on and the voltage difference between the node 102 a and GND is determined by the on-resistance of the low-side power transistor LS multiplied by the current flowing in the low-side power transistor.

[0052] For example, the above-described situation may occur in which the second terminal of the inductive load L (which, in the presently considered example, is coupled to the node 102b by way of example only) may be connected to the voltage V BUS This situation may arise when two half-bridge circuits are used in a full-bridge configuration to drive the inductance of a brushless DC motor stator.

[0053] Solutions exist (for example according to documents such as US 8593211 B2) that aim to prevent the bootstrap voltage V CB During the bootstrap recharge phase T2, the upper threshold V TH,H .

[0054] For example, by providing a current limiter circuit coupled in series to a bootstrap diode DB in a low voltage portion of a half-bridge switching circuit, such as Figure 3A As shown, this can be facilitated.

[0055] The current limiter circuit may include a MOS transistor Q1 (e.g., a p-type transistor with a corresponding drain-body diode D1) coupled between node 100a and the anode of the bootstrap diode DB. The current limiter circuit may include a voltage sensing circuit 30 and a level shifter circuit 32 configured to sense the bootstrap voltage V CB And the control signal is transmitted from the floating portion FS to the control (gate) terminal of the MOS transistor Q1 in the low voltage portion.

[0056] In such Figure 3A In the illustrated circuit, the current limiter circuit can be configured to respond to the bootstrap voltage V CB Reaching the upper threshold V TH,H And offset the current flowing through the bootstrap diode DB. Therefore, the bootstrap capacitor C B The bootstrap voltage V CB may be limited to an upper threshold V TH,H The following, such as Figure 3B However, due to the threshold of the bootstrap diode DB (such as Figure 3B As shown by the dotted line in Figure 3A The circuit shown may not be able to reduce the voltage loss V L .

[0057] There are other solutions (for example according to documents such as US 7215189 B2, US 7456658 B2 or US 7538583 B2) which aim to reduce the voltage drop V due to the threshold of the bootstrap diode DB. L .

[0058] For example, Figure 4A As shown, this can be conveniently achieved by replacing the bootstrap diode DB with an active diode circuit in the low voltage portion of the half-bridge switching circuit.

[0059] The active diode circuit may include a MOS transistor Q3 (eg, an n-type transistor with a corresponding drain-body diode D3) coupled between node 100a and a floating supply voltage node 104. The active diode circuit may include a MOS transistor Q3 (eg, an n-type transistor with a corresponding drain-body diode D3) coupled between node 100a and a floating supply voltage node 104. CCA respective driver circuit 40 is powered and coupled via a capacitive component C5 (eg, a capacitor) to the control (gate) terminal of the MOS transistor Q3.

[0060] In such Figure 4A In the illustrated circuit, the active diode circuit can be configured to reduce the voltage drop between the power supply node 100a and the floating power supply voltage node 104 during the bootstrap recharging phase T2. B The bootstrap voltage V CB May approach (or reach) the expected value V D ,like Figure 4B However, as Figure 4A The circuit shown may not be able to bootstrap the voltage V CB Limited to the upper threshold V TH,H The following, such as Figure 4B As shown by the solid line in .

[0061] Thus, one or more embodiments may involve including Figure 5A and Figure 6 The illustrated half-bridge switching circuit 10 ′ of the high-side bootstrap circuit device.

[0062] One or more embodiments are primarily directed to a driver circuit HBD for a half-bridge circuit. It will also be understood that, although intended to cooperate with such a half-bridge circuit, a driver circuit according to one or more embodiments may be implemented as a different element than the half-bridge circuit driven thereby.

[0063] like Figure 5A As shown, one or more embodiments may include a current limiter circuit implemented (entirely) in the floating portion FS of the half-bridge switching circuit 10', the current limiter circuit being located between the bootstrap diode and the floating supply voltage node 104, and having associated control circuitry. For example, the current limiter circuit may include a MOS transistor Q1' (e.g., a p-type transistor with a corresponding drain-body diode D1') coupled to the cathode of the bootstrap diode (at Figure 5A and Figure 6 and the voltage sensing circuit 50 is configured to sense the bootstrap voltage V CB and transmits the corresponding control signal to the control (gate) terminal of the MOS transistor Q1′.

[0064] In one or more embodiments, the bootstrap diode may be a diode, or alternatively an active diode circuit, such as Figure 5A and Figure 6 exemplified in .

[0065] In such Figure 5A and Figure 6In the circuit shown, the bootstrap voltage V CB can be limited to an upper threshold V TH,H The following, such as Figure 5B As illustrated by the solid line in the figure, it can approach (or reach) the expected value V D ,like Figure 5B As illustrated by the dot-dash line in , this depends on the voltage level of the floating ground of the floating portion FS (ie, the output terminal 102 a ).

[0066] Specifically, Figure 6 1 is an exemplary illustration of one or more embodiments of a half-bridge switching circuit 10′ including an active diode circuit (e.g., including a transistor Q3 having a drain-body diode D3) and its corresponding control circuit 60, and a current limiting circuit implemented in a floating portion FS (e.g., including a transistor Q1′ having a drain-body diode D1′) and its corresponding control circuit 62. Thus, the control circuit 62 can be powered and driven in the floating portion FS of the half-bridge driver circuit HBD to drive the gate-source voltage of the transistor Q1′ as desired.

[0067] like Figure 7 As illustrated in FIG and explained below, control circuit 62 may be connected and powered by nodes 106 and 104 acting as positive power supply nodes to facilitate proper operation of control circuit 62. Node 102a acts as a reference or negative power supply node for circuit 62.

[0068] As previously mentioned, and now with reference to Figure 6 , note that the switching operation of the half-bridge circuits HS, LS also results in a bootstrap recharging phase (during which HS is off and LS is on) and a bootstrap supply phase (during which HS is on and LS is off).

[0069] During the recharge phase, the voltage V at the floating supply voltage node 104 is BOOT Can be lower than V CC , the current flowing through the bootstrap diode (such as Q3, D3) and the current limiter (such as Q1') can provide the bootstrap capacitor C B Charging (C B It may include capacitors mounted outside the circuit 10'). The bootstrap voltage V CB The value reached during the recharging phase may depend on the amount of current flowing into the low-side transistor LS during the recharging phase.

[0070] As mentioned previously, the following situations may occur:

[0071] i) With negligible current recycling on the low-side transistor LS, the bootstrap voltage V CBTherefore, the bootstrap diode (eg, active diode Q3, D3) can be turned on (eg, by the corresponding control circuit 60) to increase the current flow, thereby promoting the bootstrap voltage V at the end of the recharging phase T2 CB A higher final value of ; and

[0072] ii) In case of current recycling on the low-side transistor LS (especially at high currents), the bootstrap voltage V CB can rise (much) above V CC voltage level, and thus can overcome the upper threshold V TH,H (e.g., equal to 6V); therefore, due to the bootstrap voltage V CB Reach the expected value V D (e.g., equal to 5.4V), the voltage detection circuit in the control circuit 62 can send a control signal to the logic circuit to turn off the current limiting circuit (e.g., transistor Q1′) to avoid the bootstrap capacitor C B Further charging.

[0073] In the above case (ii), when the voltage drop due to the recirculating current is so high as to reduce the voltage V BOOT When the voltage is pulled down to a level close to or lower than the reference voltage GND (for example, during the dead time), the Figure 6 The circuit of one or more embodiments illustrated in FIG. 1 can advantageously provide a supply voltage V at node 106 for the level shifter circuit 14. S , thereby facilitating operation of the level shifter circuit 14 independent of the voltage at the floating supply voltage node 104 .

[0074] like Figure 5A and Figure 6 As shown, a current limiting transistor Q1′ is provided in the floating portion FS to provide a new node 106 in the bootstrap path between the node 100a and the node 104. The current limiting transistor Q1′ may have a corresponding drain-body diode D1′. BOOT <V CC To counteract the current flowing from node 100a to node 104, the drain-body diode D1′ and the bootstrap diode (BD or D3) are arranged “back to back”, allowing current to flow from node 104 to node 106 (but not vice versa).

[0075] Therefore, in one or more embodiments, node 106 may be arranged in the middle of two back-to-back diodes so that its voltage may be limited (eg, by design) to be greater than or equal to V CC and V BOOT The maximum value between them minus the allowable voltage drop of a diode.

[0076] It should be noted that the combination of the above two properties, namely (i) even when the voltage V BOOT A voltage lower than the reference node GND (e.g., at node 104) can also cancel the voltage from V CC (e.g., node 100a) to the floating side (e.g., node 104), and (ii) the ability to BOOT A voltage lower than the reference node GND (e.g., at node 104) can also be used to convert the switching signal (e.g., IN HS ) from the low voltage side of the half bridge to the floating side FS, resulting in the floating power supply node 104 (e.g., voltage V BOOT ) as a common operating mode, the half-bridge circuit can be correctly switched even when the floating power supply node 104 is biased far below the reference or ground level (e.g., even tens of volts) at a large percentage of the duty cycle without increasing the power consumption within the half-bridge driver integrated circuit HBD. The maximum achievable negative voltage of the floating power supply node 104 (e.g., voltage V BOOT ) is related only to the maximum voltage drop that transistor Q1' can sustain when it is in the off state.

[0077] Figure 7 is an exemplary circuit block diagram of a possible implementation of a current limiter circuit and associated control circuitry in one or more embodiments.

[0078] It should be understood that while in one or more embodiments such a current limiter circuit may be advantageously used in combination with an active bootstrap diode (and therefore, reference will be made hereinafter to such an active diode), certain embodiments may involve such a current limiter circuit being used in combination with a conventional passive bootstrap diode BD.

[0079] like Figure 7 As shown, one or more embodiments may include a current limiting transistor Q1′ coupled between nodes 106 and 104 and having a corresponding drain-body diode D1′. To align the drain-body diode D1′ in the desired direction (i.e., with the cathode coupled to node 106 and the anode coupled to node 104), the current limiting transistor Q1′ may include a P-channel high-voltage MOS transistor with its source and body terminals connected to node 106. In this example, the gate-source voltage (which drives the transistor Q1′ to switch the channel on or off) may be lower than V S .

[0080] Alternatively, the current limiting transistor may comprise an N-channel high voltage MOS transistor having a source terminal connected to node 104. In this exemplary case, the gate-source voltage that drives such a transistor to turn the channel on and off may be higher than V BOOT, and may be generated by a circuit such as a charge pump circuit, not visible in the figures accompanying this document.

[0081] In one or more embodiments, the voltage at node 104 can be increased from a low value (eg, approximately V CC ) switches to a high value (e.g., much higher than V CC ), and then returns to a low value at a very high speed. For example, the voltage V BOOT The change in time interval can exceed 100V / ns (1ns=10 -9 s), such as Figure 8 shown.

[0082] like Figure 8 As shown, due to the voltage V BOOT Switching to a high value (entering the “bootstrap supply phase” T1), node 106 may be pulled up to (almost) equal to V by the current flowing in the drain-body diode D1 of the current limiter transistor Q1. BOOT Because the drain-body diode D1 is forward biased. This current can charge the parasitic capacitance between node 106 and the low voltage node. In particular, this current can charge the parasitic capacitance C3 at the cathode of the active diode Q3 (see Figure 9 ).

[0083] During the “bootstrap power supply phase” T1, when the voltage V BOOT In the high voltage range, node 106 can still be pulled up by the drain-body diode D1′ of the current limiting transistor. The current limiting transistor Q1′ can be set to be conductive to reduce the voltage drop between node 106 and node 104, and is turned on at the beginning of the falling phase, such as when entering the "bootstrap recharging phase" T2.

[0084] Since the voltage V BOOT Switching back to a low value (entering the “bootstrap recharging phase” T2), the drain-body diodes D3 and D1′ of the active diode circuit and the current limiter circuit may both be reverse biased and the node 106 may remain floating at a high voltage, risking overcoming the breakdown voltage of the circuit devices connected between the node 106 and the nodes 104, 102a.

[0085] To cope with such an overvoltage event, node 106 can be discharged to node 104 with a current sufficient to limit the voltage difference between nodes 106 and 104 to within the breakdown voltage of the circuit device. Thus, node 106 can be discharged by keeping current limiting transistor Q1′ turned on, thereby providing a conductive path between node 106 and node 104.

[0086] It should be noted that even if the voltage V BOOTThe conduction during the falling phase may remain, but its conductivity may not be sufficient to allow a high enough peak current to discharge the node 106 at a sufficient speed (eg, considering the worst case), ie, at a very fast falling rate.

[0087] Therefore, one or more embodiments may optionally include a "fast discharge" transistor Q2 (e.g., Figure 7 ) and associated circuitry. For example, the fast discharge transistor may include an N-channel MOS transistor Q2 having a source terminal coupled to node 104 and a drain terminal coupled to node 106. The fast discharge transistor Q2 may include a corresponding drain-body diode D2 in parallel with diode D1′. Associated circuitry may include a resistive element R4 (e.g., a resistor) coupled between the source and gate of transistor Q2, and a capacitive element C4 (e.g., a capacitor) coupled between the drain and gate of transistor Q2.

[0088] The fast discharge circuit arrangement Q2, R4, and C4 can help to sink current from the parasitic capacitance at node 106 so as to discharge node 106 at a higher rate (e.g., up to 200V / ns). Transistor Q2 can be normally turned off as long as no current flows through resistor R4, keeping the gate-source voltage of transistor Q2 close to 0V. Since the voltage V BOOT With respect to the voltage V at node 106 S If the voltage drops rapidly (e.g., with a fast or sharp edge), capacitor C4 can provide a current path for current to flow into resistor R4, thereby turning on the channel of transistor Q2. This can provide an additional current path in parallel with transistor Q1', which helps to keep the voltage difference between node 106 and node 104 within the threshold. The fast discharge transistor Q2 can be turned off after a (short) time interval until the voltage V BOOT The duration of this time interval can be adjusted based on the values of resistor R4 and capacitor C4. As a non-limiting example only, resistor R4 can have a value of approximately 300Ω and capacitor C4 can have a value of approximately 10pF (1pF=10 -12 F), so that the time interval can have a value of about 3 ns (1 ns = 10 - 9 s).

[0089] At voltage V BOOT At the end of the falling phase, the voltage at node 104 may drop to V CC below, and the active diode Q3 can start to bootstrap capacitor C BSince resistor R4 discharges the gate-source capacitance of transistor Q2, the fast discharge current path can be opened quickly and the on / off state of the current limiting transistor Q1′ can be controlled to avoid the bootstrap capacitor C B Overcharge.

[0090] When the voltage V at the node 104 BOOT Lower than V CC When the bootstrap capacitor C B The voltage V CB can be increased, and one or more embodiments as illustrated herein can provide a voltage V at the end of the charging phase T2. CB For example, the active diode Q3 can reduce the voltage drop between node 100a and node 104 to increase the bootstrap capacitance C B The amount of charge that can be stored in the current limiting transistor Q1′ can prevent the corresponding bootstrap voltage V CB The bootstrap capacitor C B Further charging.

[0091] like Figure 7 As shown, the driving circuit device for driving the current limiting transistor Q1′ may include a detector circuit DT1 (eg, a comparator circuit), DT1 being configured to compare the voltage V CC and voltage V OUT (e.g. by receiving a voltage V CC and receives a voltage V at the negative input OUT ). When the voltage V OUT Higher than the voltage V CC When the half-bridge circuit is considered to be in the high state, the signal HBlow at the output of the detector circuit DT1 is low and the current limiting transistor Q1′ is turned on. As mentioned above, this condition can be BOOT The rising phase, high level phase and falling phase of the node 104 are maintained. BOOT When low, the voltage V OUT Lower than V CC , signal HBlow is high, the state of the current limiting transistor Q1′ can be controlled by a signal VBOov provided at the output of another detector circuit DT2 (e.g., a comparator circuit). The detector circuit DT2 can be configured to convert the reference voltage V REF (For example, the reference voltage V OUT ) and according to the voltage V BOOT and V OUT The generated signal V R For example, the signal V REF It can be generated by a circuit VG2 acting as a voltage generator coupled to node 102a. For example, the signal V RThe voltage difference V BOOT -V OUT part of the voltage difference V R Higher than the reference voltage V REF , the signal VBOov can be switched to a high state, the signal Q1off can rise to a high state, and the current limiting transistor Q1′ can be turned off to prevent the bootstrap capacitor C B The voltage across the two ends V CB Further increase.

[0092] like Figure 7 As shown, logic signal Q1off can be generated at the output of AND gate 70, which receives logic signals HBlow and VBOov as inputs. Table 1, appended at the end of the specification, summarizes the logic for driving current limiting transistor Q1′ according to the example currently considered. The symbol “X” in the “Input” column indicates a “don’t care” condition.

[0093] In one or more embodiments as illustrated herein, the voltage V at node 106 S Can be in V BOOT During the falling phase, the voltage V BOOT , as previously discussed, and the voltage at node 104 drops (deeply) below the voltage V CC Therefore, if Figure 7 One or more of the illustrated embodiments may include a circuit SW configured to convert the logic signal Q1off to an appropriate voltage level to drive the gate-source voltage of the current limiting transistor Q1'.

[0094] Therefore, in one or more embodiments, the level shifter circuit LVS may be used to shift the logic signal Q1off from the floating power domain (at V BOOT and V OUT ) propagates to the power domain of node 106 to drive switch S1. Switch S1 can selectively connect the gate terminal of transistor Q1′ to the source terminal of transistor Q1′ (i.e., node 106) or to the supply voltage V R3 Another node. Figure 7 As shown, the voltage V R3 It can be generated by circuit VG3, which acts as a voltage generator and provides a voltage lower than V to another node. S The voltage V R3 , suitable for turning on the current limiting transistor Q1′.

[0095] In one or more embodiments, the voltage V CBA value close to 0V (such as might occur when the device is powered on) may represent a critical condition, as in this case the logic value of the signal Q1off may be invalid and, if not driven correctly, the current limiting transistor Q1′ may remain off, thereby preventing the bootstrap capacitor C B charging, so that the voltage V CB Keep it at 0V.

[0096] Therefore, one or more embodiments may optionally include a resistive connection R0 between the propagation path of the signal Q1off and the node 102a, which can advantageously keep the signal Q1off at a low value under the above-described conditions. The resistance of the resistive path R0 can be selected to be high to limit static power consumption. For example, the resistor R0 can be approximately 30 kΩ. Considering that the internal power supply voltage of the logic circuit is 3.3 V, the static power consumption when the node Q1off is at a high level can be limited to approximately 10 μA. In one or more embodiments, the internal power supply voltage of this detail of the logic circuit can be different, and the value of R0 can be selected accordingly.

[0097] Note that after the device is powered on, CB ~0V bootstrap capacitor C B At the first charging event of , node 102a can be shorted to reference node GND (eg, ground) by turning on low-side transistor LS. Thus, circuit SW can operate at voltage V at node 106. S (It can be compared to V CC low approximately the diode threshold voltage drop) and the voltage V OUT (which can be approximately equal to the reference voltage of node GND). Therefore, circuit SW can be sufficiently overdriven to generate voltage V R3 and propagates the signal Q1off to the switch S1, which turns on the current limiting transistor Q1′, allowing current to flow through the active diode Q3 to supply the bootstrap capacitor C B For example, the last row of Table I illustrates this condition.

[0098] Figure 9 is an exemplary circuit block diagram of a possible implementation of an active diode circuit and associated control circuitry in one or more embodiments.

[0099] like Figure 9As shown, the active diode circuit may include a transistor Q3 (e.g., a large, high-voltage N-channel transistor) whose drain-body diode D3 operates as a conventional bootstrap diode, with the body of transistor Q3 shorted to its corresponding source terminal, and the source terminal coupled to node 100a. When the voltage drop between the anode and cathode of the drain-body diode D3 reaches the diode threshold voltage, the channel of transistor Q3 may turn on to increase the current flowing from node 100a to node 104 (via node 106). Therefore, compared to other solutions for implementing a passive bootstrap diode DB (e.g., see Figure 3A ) compared to the bootstrap capacitor C B Can be charged to a higher voltage V CB .

[0100] In one or more embodiments, the voltage at the gate terminal of (N-channel) transistor Q3 may be provided to be higher than the voltage connected to V CC The level of the voltage at the source terminal of transistor Q3 is increased to turn on the channel of transistor Q3. Therefore, a boost circuit can be used to drive the gate terminal of transistor Q3. Figure 9 As shown, the boost circuit may include a boost capacitor C5 , which is driven by a driver circuit B5 , and the driver circuit B5 is controlled by a control signal S5 generated by a logic circuit LOG2 .

[0101] In one or more embodiments, the gate terminal of (N-channel) transistor Q3 may be connected to V CC (e.g., connected to node 100a) to turn off the channel of transistor Q3. Due to the voltage V BOOT and V S Rapidly rises to a high voltage value V CC +V BUS , the drain-gate capacitance of transistor Q3 can increase the gate voltage and turn on transistor Q3. Therefore, transistor Q3 can be turned off by activating the low resistance switch S6, which is connected to the transistor Q3 with a voltage V CC The gate terminal of transistor Q3 is coupled to node 100a. Switch S6 may be driven by a control signal generated by logic circuit LOG2.

[0102] In one or more embodiments, if V CC If V is below a threshold (e.g., 2 V measured relative to a reference voltage at node GND), the logic circuit LOG2 may not provide sufficient drive capability to properly activate switch S6, and the path coupling the gate terminal of transistor Q3 to node 100a may exhibit a high resistance. CCWhen the voltage at nodes 104 and 106 rises rapidly, the channel of transistor Q3 may be turned on, thereby allowing an undesired current to flow from node 104 to node 100a. Therefore, one or more embodiments may include a detector circuit DT3 configured to detect the voltage at nodes 104 and 106 by turning on V CC With voltage reference V REF,CC Compare and generate the corresponding output signal PWRok to detect the power supply voltage V CC Is it lower than the threshold V REF,CC (eg, approximately 2.5V above GND). As a result of the signal PWRok being low (eg, indicating that the power supply voltage VCC is below the threshold V REF,CC ), another switch S7 can be activated to pull the gate terminal of transistor Q3 down to the voltage V CC Following (eg by coupling the gate terminal of the transistor Q3 to the ground level GND), so as to generate a negative gate-source voltage of the transistor Q3 and (almost) switch off its channel.

[0103] In one or more embodiments, since the power supply voltage V CC In the correct operating range (for example, above V REF,CC ), the signal PWRok may be high, and the conductivity of the channel of the transistor Q3 may be controlled according to two control signals LOn and VCgtBT. The control signal LOn may correspond to the low-side control signal IN of the half-bridge circuit. LS The control signal VCgtBT may be generated at the output of the detector circuit DT4, which is configured to convert the voltage V BOOT With voltage V CC For example, the control signal VCgtBT is low, which indicates the voltage V CC Higher than the voltage V BOOT .

[0104] Table II summarizes the values of the input and output signals of the logic circuit LOG2 according to the presently considered example, and the corresponding state of the transistor Q3. The symbol "X" in the "Input" column indicates a "don't care" condition.

[0105] In one or more embodiments, transistor Q3 can be responsive to voltage V BOOT Increase to voltage V CC (e.g., as detected by the detector circuit DT4) above and is turned off so that at the voltage V BOOT Higher than the voltage V CC , behaves similarly to a junction bootstrap diode and cancels the current flow. However, the detector circuit DT4 may have some response delay and may therefore (only) be BOOTEffective when the voltage changes slowly. BOOT The fast rising edge of (due to the half-bridge output node switching) is preceded by the deactivation (i.e., turn-off) of the low-side power transistor LS. Therefore, the logic signal LOn, which goes low when the low-side transistor LS turns off, can also be used to turn off transistor Q3 just before the half-bridge output node commutates.

[0106] Note that one or more embodiments may advantageously address another issue related to the driving of enhancement-mode GaN power transistors. In fact, both the low-side power transistor LS and the high-side power transistor HS may remain off for a (short) time, called the dead time, before switching to the on state, to avoid cross-conduction between the power supplies. During the dead time, if the load current circulates inside the low-side power transistor LS, the output node 102a of the half-bridge circuit may exhibit a voltage much lower than the reference voltage of the node GND (e.g., even more than 4V lower than the reference voltage GND) due to the reverse conduction characteristics of the enhancement-mode GaN transistor. In this case, even if the bootstrap capacitor C B Charged to the maximum limit V D (e.g., 5.4V), the voltage at node 104 V BOOT It may also be only about 1V higher than the reference voltage at node GND. In this case, if Figure 10 The logic signal IN is shown as HS A conventional level shifter 14 that transfers voltage from a low voltage input buffer to the high voltage floating portion FS of the half-bridge circuit may not operate correctly, for example because the dynamic range of the level shifter circuit is not extended enough.

[0107] As previously mentioned, in one or more embodiments, the voltage V at node 106 is S Can not be reduced to V CC -1V or less. Power supply voltage V for driving enhancement mode GaN transistors CC The preferred value of may be around 5V, and 4V may be the minimum value. Therefore, the voltage V at node 106 S Can not be lower than 3V, and the voltage V S can be used as a power supply node for level shifters driven from the GND supply domain. For similar reasons, the voltage between nodes 106 and 102a (i.e., V S and voltage V OUT The voltage drop between the two terminals can (always) be higher than 3V.

[0108] Therefore, in one or more embodiments, the level shifter circuit 14 may include Figure 11 Two stages are shown. You can S drives the first stage between V S and V OUTbetween driving the second stage.

[0109] For example, the first stage may include an n-type transistor N1 configured to receive an input signal IN at a corresponding gate terminal. HS , the current path of transistor N1 is arranged between the reference terminal GND and the intermediate node 110. The first stage may also include a transistor arranged between the intermediate node 110 and a transistor at a voltage V S The second stage may include a p-type transistor P1 having a respective gate terminal coupled to the intermediate node 110 of the first stage, the transistor P1 having a gate terminal arranged at a voltage V S The second stage may also include a current path between the node 106 and the intermediate node 112. OUT and a resistor R12 between the nodes 102a and 102b.

[0110] like Figure 11 The illustrated level shifter circuit 14 may be capable of shifting the input logic signal IN HS Transfer from GND voltage domain to V OUT voltage domain, and the voltage V at node 104 BOOT The value of CC , lower than V CC , even lower than GND).

[0111] It is noted that one or more embodiments may include diodes D3 and D1', which advantageously provide node 106 for operation of level shifter circuit 14. Alternatively, level shifter circuit 14 may be standalone, ie, it may include diodes D3 and D1'.

[0112] In one or more embodiments, the Figure 11 The two examples of level shifter circuit 14 shown are differential level shifter circuits.

[0113] Thus, as illustrated herein, one or more embodiments of a driver circuit for a half-bridge circuit may include a current limiter circuit in the floating portion of the system and a bootstrap diode (optionally, an active diode circuit) in the low-voltage portion. Both circuits may be driven by respective control circuitry implemented in the respective portions.

[0114] Advantageously, one or more embodiments may also provide a positive internal voltage V at node 106 that is always positive. S , the internal voltage V S A level shifter circuit 14 is adapted to be provided for the high-side transistor HS.

[0115] One or more embodiments can be fully integrated into a single-chip HBD, for example, including active diode circuits, current limiter circuits, and associated driver circuitry. One or more embodiments can be used to drive a variety of different devices, such as active clamp flyback converters, resonant LLC converters, and the like.

[0116] As illustrated herein, a circuit (e.g., an HBD) may include:

[0117] The first input power supply node (eg, 100a) and the second input power supply node (eg, 100b) are configured to receive a first power supply voltage (eg, V CC );

[0118] A first input control node and a second input control node, the first input control node being configured to receive a first input control signal (eg, IN HS ), the second input control node is configured to receive a second input control signal (eg, IN LS ),

[0119] a high-side driver circuit (e.g., 12 a ) configured to be coupled to a high-side switch (e.g., HS) of the half-bridge circuit, the high-side driver circuit being configured to receive (e.g., 14 ) the first input control signal and generate a first output control signal between a first high-side output node (e.g., 120 a ) and a second high-side output node (e.g., 102 a ) to control the high-side switch,

[0120] a low-side driver circuit (e.g., 12 b) configured to be coupled to a low-side switch (e.g., LS) of the half-bridge circuit, the low-side driver circuit configured to receive the second input control signal and generate a second output control signal for controlling the low-side switch between a first low-side output node (e.g., 120 b) and a second low-side output node (e.g., 102 b),

[0121] A floating power supply node (eg, 104) is configured to receive a floating power supply voltage (eg, V CB 、C B ), wherein a high-side driver circuit is electrically coupled between the floating supply node and the second high-side output node to receive the floating supply voltage,

[0122] a bootstrap diode (e.g., D3) having an anode coupled to the first input power supply node and a cathode coupled to an intermediate power supply node (e.g., 106), and

[0123] A current limiter circuit (eg, Q1 ′, D1 ′, 62 ) is coupled between the intermediate power supply node and the floating power supply node.

[0124] As illustrated herein, the current limiter circuit can be configured to sense (e.g., 50) the floating supply voltage and offset current flowing from the intermediate supply node to the floating supply node due to the floating supply voltage reaching a threshold (e.g., approximately equal to 5.4V).

[0125] As illustrated herein, the current limiter circuit may include a first field effect transistor (e.g., Q1′) having a corresponding first drain-body diode (e.g., D1′) having an anode coupled to the floating power supply node and a cathode coupled to the intermediate power supply node.

[0126] As illustrated herein, a current limiter circuit may include:

[0127] a second field effect transistor (e.g., Q2) having a corresponding second drain-body diode (e.g., D2) having an anode coupled to the floating power supply node and a cathode coupled to the intermediate power supply node,

[0128] a capacitor (e.g., C4) coupled between the intermediate power supply node and the gate terminal of the second field effect transistor, and

[0129] A resistor (eg, R4) is coupled between the floating power supply node and the gate terminal of the second field effect transistor.

[0130] As illustrated herein, the current limiter circuit may include a state comparator circuit (e.g., DT1) configured to compare the first supply voltage with a switching voltage (e.g., V OUT The current limiter circuit may be configured to switch the first field effect transistor to an on state in response to the switching voltage being higher than the first power supply voltage.

[0131] As illustrated herein, the current limiter circuit may include an overvoltage comparator circuit (eg, DT2) configured to convert a signal indicative of the floating supply voltage (eg, V R ) and a reference signal (such as V REF The current limiter circuit may be configured to switch the first field effect transistor to a non-conductive state in response to the signal indicating that the floating supply voltage is higher than the reference signal.

[0132] As illustrated herein, the current limiter circuit may include a logic gate (e.g., 70) configured to generate an output logic signal (e.g., Q1off) based on an output signal (e.g., HBlow) from the state comparator circuit and an output signal (e.g., VBOov) from the overvoltage comparator circuit. The first field effect transistor may switch to a non-conductive state in response to the output logic signal having a high value, and switch to a conductive state in response to the output logic signal having a low value. The circuit may include a resistive current flow path (e.g., R0) between the output node of the logic gate and the second high-side output node.

[0133] As illustrated herein, the current limiter circuit may include a switch (eg, S1) configured to selectively couple the gate terminal of the first field effect transistor to the intermediate power supply node to receive a positive voltage (eg, V S ), or coupled to another voltage node. The other voltage node may be configured to provide a voltage lower than the positive voltage (eg, V R3 ).

[0134] As illustrated herein, the bootstrap diode may include a bootstrap field effect transistor (e.g., Q3) having a corresponding drain-body diode (e.g., D3) having an anode coupled to the first input power supply node and a cathode coupled to the intermediate power supply node.

[0135] As illustrated herein, the circuit may include a power supply comparator circuit (eg, DT3) configured to compare the first power supply voltage with a threshold power supply voltage (eg, V REF,CC , optionally equal to approximately 2.5V) for comparison; and a logic circuit (eg, LOG2) configured to switch the bootstrap field effect transistor to a non-conducting state in response to the first power supply voltage being lower than the threshold power supply voltage.

[0136] As illustrated herein, the circuit may include a bootstrap comparator circuit (e.g., DT4) configured to sense a voltage (e.g., V at the floating power supply node) (e.g., sensed between the floating power supply node and the second input power supply node) to a voltage (e.g., V BOOT ) is compared with the first power supply voltage; and a logic circuit configured to switch the bootstrap field effect transistor to a non-conducting state in response to the voltage at the floating power supply node being higher than the first power supply voltage.

[0137] As illustrated herein, the circuit may include a logic circuit that is sensitive to a control signal (e.g., LSON) indicating whether the low-side switch is in a conducting state or a non-conducting state. The logic circuit may be configured to switch the bootstrap field effect transistor to a non-conducting state in response to the control signal indicating that the low-side switch is in a non-conducting state.

[0138] As illustrated herein, the circuit may include a level shifter circuit (e.g., 14) configured to propagate the first input control signal from the first input control node to the high-side driver circuit. The level shifter circuit may be powered between the intermediate power supply node and the second input power supply node.

[0139] As illustrated herein, a level shifter circuit may include:

[0140] a first current flow line between the intermediate power supply node and the second input power supply node, the first current flow line comprising a first transistor (e.g., N1) having a source terminal coupled to the second input power supply node, and a first resistor (e.g., R11) coupled between a drain terminal (e.g., 110) of the first transistor and the intermediate power supply node, the first transistor having a respective control terminal configured to receive the first input control signal, and

[0141] a second current flow line between the intermediate power supply node and the second high-side output node, the second current flow line comprising a second transistor (e.g., P1) having a source terminal coupled to the intermediate power supply node, and a second resistor (e.g., R12) coupled between a drain terminal (e.g., 112) of the second transistor and the second high-side output node, the second transistor having a corresponding control terminal coupled to the drain terminal of the first transistor.

[0142] As exemplified herein, the circuit may further include:

[0143] The high-side switch is configured to provide a current flow line between a third input power supply node (eg, 108) and a second high-side output node, wherein the third input power supply node is configured to receive a second power supply voltage (eg, V BUS ),as well as

[0144] The low-side switch is configured to provide a current flow line between the second high-side output node and the second low-side output node.

[0145] As illustrated herein, the second high-side output node and the second low-side output node may be configured to provide the switching voltage therebetween.

[0146] As illustrated herein, the high-side switch and the low-side switch may include gallium nitride power transistors.

[0147] As exemplified herein, a device may include:

[0148] According to one or more embodiments of the circuit,

[0149] The bootstrap capacitor (e.g. C B ), coupled between the floating power supply node and the second high-side output node of the circuit, and

[0150] An inductive load (eg, L) is coupled between the second high-side output node and the second low-side output node of the circuit to receive the switching voltage.

[0151] As illustrated herein, a method of operating a circuit or device according to one or more embodiments may include:

[0152] receiving a first supply voltage between the first input supply node and the second input supply node,

[0153] receiving a first input control signal at the first input control node and receiving a second input control signal at the second input control node;

[0154] generating a first output control signal between the first high-side output node and the second high-side output node for controlling a high-side switch of a half-bridge circuit;

[0155] generating a second output control signal for controlling a low-side switch of the half-bridge circuit between the first low-side output node and the second low-side output node;

[0156] receiving a floating supply voltage applied between the floating supply node and the second high-side output node to power the high-side driver circuit; and

[0157] The floating power supply voltage is sensed, and a current flowing from the intermediate power supply node to the floating power supply node due to the floating power supply voltage reaching a threshold is canceled.

[0158] Table I

[0159]

[0160] Table II

[0161]

[0162]

[0163] A circuit (HBD) can be summarized as comprising: a first input power supply node (100a) and a second input power supply node (100b) configured to receive a first power supply voltage (V CC ); a first input control node and a second input control node, the first input control node being configured to receive a first input control signal (IN HS ), the second input control node is configured to receive a second input control signal (IN LS ); a high-side driver circuit (12a) configured to be coupled to a high-side switch (HS) of the half-bridge circuit, the high-side driver circuit (12a) being configured to receive (14) the first input control signal (IN HS ) and generates a first output control signal between a first high-side output node (120a) and a second high-side output node (102a) to control the high-side switch (HS); a low-side driver circuit (12b) configured to be coupled to the low-side switch (LS) of the half-bridge circuit, the low-side driver circuit (12b) configured to receive the second input control signal (IN LS ) and generates a second output control signal between the first low-side output node (120b) and the second low-side output node (102b) to control the low-side switch (LS); a floating power supply node (104) configured to receive a floating power supply voltage (V CB 、C B ), wherein the high-side driver circuit (12a) is electrically coupled between the floating power supply node (104) and the second high-side output node (102a) to receive the floating power supply voltage (V CB ); a bootstrap diode (D3) having an anode coupled to the first input power supply node (100a) and a cathode coupled to an intermediate power supply node (106); and a current limiter circuit (Q1′, D1′, 62) coupled between the intermediate power supply node (106) and the floating power supply node (104), wherein the current limiter circuit (Q1′, D1′, 62) is configured to sense (50) the floating power supply voltage and due to the floating power supply voltage (V CB ) reaches a threshold value to offset the current flowing from the intermediate power supply node (106) to the floating power supply node (104).

[0164] The current limiting circuit may include a first field effect transistor (Q1') having a corresponding first drain-body diode (D1') having an anode coupled to the floating power supply node (104) and a cathode coupled to the intermediate power supply node (106).

[0165] The current limiting circuit may include a second field effect transistor (Q2) having a corresponding second drain-body diode (D2), the corresponding second drain-body diode (D2) having an anode coupled to the floating power supply node (104) and a cathode coupled to the intermediate power supply node (106), a capacitor (C4) coupled between the intermediate power supply node (106) and a gate terminal of the second field effect transistor (Q2), and a resistor (R4) coupled between the floating power supply node (104) and the gate terminal of the second field effect transistor (Q2).

[0166] The current limiter circuit may include a state comparator circuit (DT1) configured to convert the first power supply voltage (V CC ) and a switching voltage (V OUT ) is compared, and wherein the current limiter circuit is configured to respond to the switching voltage (V OUT ) is higher than the first power supply voltage (V CC ) and switches the first field effect transistor (Q1′) to an on state.

[0167] The current limiter circuit may include an overvoltage comparator circuit (DT2) configured to convert a current indicating the floating supply voltage (V CB ) signal (V R ) and the reference signal (V REF ) is compared, and wherein the current limiter circuit is configured to respond to an indication that the floating supply voltage (V CB ) exceeds the reference signal (V REF ) signal (V R ) so that the first field effect transistor (Q1′) operates in a non-conducting state.

[0168] The current limiter circuit may include a logic gate (70) configured to generate an output logic signal (Q1off) based on an output signal (HBlow) from the state comparator circuit (DT1) and an output signal (VBOov) from the overvoltage comparator circuit (DT2), wherein the first field effect transistor (Q1′) switches to a non-conducting state in response to the output logic signal (Q1off) having a high value and switches to a conducting state in response to the output logic signal (Q1off) having a low value, and wherein the circuit (HBD) includes a resistive current flow path (R0) between an output node of the logic gate (70) and the second high-side output node (102a).

[0169] The current limiter circuit may include a switch (S1) configured to selectively couple the gate terminal of the first field effect transistor (Q1′) to the intermediate power supply node (106) to receive a positive voltage (V S ) or coupled to another voltage node, wherein the other voltage node is configured (VG3) to provide a voltage lower than the positive voltage (V S ) voltage (V R3 ).

[0170] The bootstrap diode may include a bootstrap field effect transistor (Q3) having a corresponding drain-body diode (D3) having an anode coupled to the first input power supply node (100a) and a cathode coupled to the intermediate power supply node (106).

[0171] The circuit (HBD) may include a power supply comparator circuit (DT3) configured to convert the first power supply voltage (V CC ) and the threshold supply voltage (V REF,CC ) for comparison; and a logic circuit (LOG2) configured to respond to the first power supply voltage (V CC ) is below the threshold supply voltage (V REF,CC ) and switches the bootstrap field effect transistor (Q3) to a non-conducting state.

[0172] The circuit (HBD) may include a bootstrap comparator circuit (DT4) configured to convert the voltage (V BOOT ) and the first power supply voltage (V CC ) for comparison; and a logic circuit (LOG2) configured to respond to the voltage (V BOOT ) is higher than the first power supply voltage (V CC ) and switches the bootstrap field effect transistor (Q3) to a non-conducting state.

[0173] The circuit (HBD) may include a logic circuit (LOG2) that is sensitive to a control signal (LSon) indicating whether the low-side switch (LS) is in a conducting state or a non-conducting state, wherein the logic circuit (LOG2) is configured to switch the bootstrap field effect transistor (Q3) to a non-conducting state in response to the control signal (LSon) indicating that the low-side switch (LS) is in a non-conducting state.

[0174] The circuit (HBD) may include a level shifter circuit (14) configured to shift the first input control signal (IN HS) propagates from the first input control node to the high-side driver circuit (12a), wherein the level shifter circuit (14) is electrically powered between the intermediate power supply node (106) and the second input power supply node (100b).

[0175] The level shifter circuit (14) may include a first current flow line between the intermediate power supply node (106) and the second input power supply node (100b), the first current flow line including a first transistor (N1), the first transistor (N1) having a source terminal coupled to the second input power supply node (100b) and a first resistor (R11) coupled between a drain terminal (110) of the first transistor (N1) and the intermediate power supply node (106), the first transistor (N1) having a corresponding control terminal, the control terminal being configured to receive the first input control signal (IN HS ), and a second current flow line between the intermediate power supply node (106) and the second high-side output node (102a), the second current flow line comprising a second transistor (P1) having a source terminal coupled to the intermediate power supply node (106) and a second resistor (R12) coupled between a drain terminal (112) of the second transistor (P1) and the second high-side output node (102a), the second transistor (P1) having a corresponding control terminal coupled to the drain terminal (110) of the first transistor (N1).

[0176] The circuit (10') may further include the high-side switch (HS) configured to provide a current flow line between a third input power supply node (108) and a second high-side output node (102a), wherein the third input power supply node (108) is configured to receive a voltage higher than the first power supply voltage (V CC ) of the second power supply voltage (V BUS ), and the low-side switch (LS) is configured to provide a current flow line between the second high-side output node (102a) and the second low-side output node (102B), wherein the second high-side output node (102a) and the second low-side output node (102B) are configured to provide the switching voltage (V OUT ).

[0177] The high-side switch (HS) and the low-side switch (LS) may include gallium nitride power transistors.

[0178] A device can be summarized as comprising a circuit (10') according to claim 14 or 15, a bootstrap capacitor (C) coupled between a floating power supply node (104) of the circuit (10') and the second high-side output node (102A)B ), and coupled between the second high-side output node (102a) and the second low-side output node (102b) of the circuit (10') to receive the switching voltage (V OUT ) of inductive load (L).

[0179] A method of operating a circuit (HBD, 10') can be summarized as comprising receiving a first supply voltage (V CC ), receiving a first input control signal (IN HS ) and receiving a second input control signal (IN LS ), generating (12a) a first output control signal between the first high-side output node (120a) and the second high-side output node (102a) for controlling a high-side switch (HS) of a half-bridge circuit, generating a second output control signal (12b) between the first low-side output node (120b) and the second low-side output node (102b) for controlling a low-side switch (LS) of the half-bridge circuit, receiving a floating power supply voltage (V CB 、C B ) to power the high-side driver circuit (12a), sensing (50) the floating supply voltage (V CB ), and since the floating supply voltage (V CB ) reaches a threshold value to offset the current flowing from the intermediate power supply node (106) to the floating power supply node (104).

[0180] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full range of equivalents to which the claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. A circuit comprising: a first input power supply node and a second input power supply node, the first input power supply node and the second input power supply node being configured to: receive a first power supply voltage differentially applied between the first input power supply node and the second input power supply node; a first input control node and a second input control node, the first input control node being configured to receive a first input control signal, the second input control node being configured to receive a second input control signal; a high-side driver circuit configured to be coupled to a high-side switch of the half-bridge circuit, the high-side driver circuit configured to receive the first input control signal and differentially generate a first output control signal between a first high-side output node and a second high-side output node for controlling the high-side switch; a low-side driver circuit configured to be coupled to a low-side switch of the half-bridge circuit, the low-side driver circuit configured to receive the second input control signal and differentially generate a second output control signal between a first low-side output node and a second low-side output node for controlling the low-side switch; a floating supply node configured to receive a floating supply voltage differentially applied between the floating supply node and the second high-side output node, wherein the high-side driver circuit is electrically coupled between the floating supply node and the second high-side output node to receive the floating supply voltage; Intermediate power node; a bootstrap diode having an anode and a cathode, the anode being coupled to the first input power supply node and the cathode being coupled to the intermediate power supply node; as well as a current limiter circuit coupled between the intermediate power supply node and the floating power supply node, The current limiter circuit is configured to sense the floating power supply voltage and, in response to the floating power supply voltage reaching a threshold, offset current flowing from the intermediate power supply node to the floating power supply node.

2. The circuit of claim 1 , wherein the current limiter circuit comprises: a first field effect transistor having a corresponding first drain-body diode having: an anode coupled to the floating power supply node; and a cathode coupled to the intermediate power supply node.

3. The circuit of claim 2 , wherein the current limiter circuit comprises: a second field effect transistor having a corresponding second drain-body diode having: an anode coupled to the floating power supply node; and a cathode coupled to the intermediate power supply node; a capacitor coupled between the intermediate power supply node and the gate terminal of the second field effect transistor; as well as A resistor is coupled between the floating power supply node and the gate terminal of the second field effect transistor.

4. The circuit of claim 2 , wherein the current limiter circuit comprises a state comparator circuit configured to compare the first power supply voltage with a switching voltage, the switching voltage being differentially sensed between the second high-side output node and the second low-side output node, and wherein the current limiter circuit is configured to operate the first field effect transistor in a conductive state in response to the switching voltage exceeding the first power supply voltage.

5. The circuit of claim 2 , wherein the current limiter circuit comprises an overvoltage comparator circuit configured to compare a signal representing the floating supply voltage with a reference signal, and wherein the current limiter circuit is configured to operate the first field effect transistor in a non-conducting state in response to a signal indicating that the floating supply voltage exceeds the reference signal.

6. The circuit of claim 4 , wherein the current limiter circuit comprises a logic gate and an overvoltage comparator circuit, the overvoltage comparator circuit being configured to compare a signal representing the floating supply voltage with a reference signal, the logic gate being configured to generate an output logic signal based on an output signal of the state comparator circuit and an output signal of the overvoltage comparator circuit, wherein the first field effect transistor operates in a non-conducting state in response to the output logic signal having a first state and operates in a conducting state in response to the output logic signal having a second state, and wherein the circuit comprises a resistive current flow path between an output node of the logic gate and the second high-side output node.

7. The circuit of claim 2 , wherein the current limiter circuit comprises a switch configured to selectively couple a gate terminal of the first field effect transistor to the intermediate power supply node to receive a positive voltage or to another voltage node configured to provide a voltage lower than the positive voltage.

8. The circuit of claim 1 , wherein the bootstrap diode comprises a bootstrap field effect transistor having a corresponding drain-body diode having an anode coupled to the first input power supply node and a cathode coupled to the intermediate power supply node.

9. The circuit according to claim 8, comprising: a power supply comparator circuit configured to compare the first power supply voltage to a threshold power supply voltage; as well as The logic circuit is configured to operate the bootstrap field effect transistor in a non-conductive state in response to the first power supply voltage being lower than the threshold power supply voltage.

10. The circuit according to claim 8, comprising: a bootstrap comparator circuit configured to compare the voltage at the floating power supply node with the first power supply voltage; as well as A logic circuit is configured to switch to operate the bootstrap field effect transistor in a non-conducting state in response to the voltage at the floating power supply node exceeding a first power supply voltage.

11. The circuit according to claim 8, comprising: The logic circuit is configured as follows: receiving a control signal indicating whether the low-side switch is in a conducting state or a non-conducting state; as well as In response to the control signal indicating that the low-side switch is in a non-conducting state, the bootstrap field effect transistor is operated in a non-conducting state.

12. The circuit according to claim 1, comprising: A level shifter circuit is configured to propagate the first input control signal from the first input control node to the high-side driver circuit, wherein the level shifter circuit is electrically coupled to the intermediate power supply node and the second input power supply node.

13. The circuit of claim 12 , wherein the level shifter circuit comprises: A first circuit is coupled between the intermediate power supply node and the second input power supply node, the first circuit comprising: a first transistor having a first conductive terminal and a second conductive terminal, the first conductive terminal being coupled to the second input power supply node, the second conductive terminal being configured to receive the first input control signal, the first transistor having a control terminal; and a first resistor coupled between the second conduction terminal of the first transistor and the intermediate power supply node; and A second circuit is coupled between the intermediate power supply node and the second high-side output node, the second circuit comprising: a second transistor having a first conduction terminal coupled to the intermediate power supply node and a control terminal coupled to the second conduction terminal of the first transistor, the second transistor having a second conduction terminal; and A second resistor is coupled between the second conduction terminal of the second transistor and the second high-side output node.

14. The circuit of claim 4, further comprising: the high-side switch configured to provide a current flow line between a third input power supply node and the second high-side output node, wherein the third input power supply node is configured to receive a second power supply voltage higher than the first power supply voltage; as well as The low-side switch is configured to provide a current flow line between the second high-side output node and the second low-side output node, The second high-side output node and the second low-side output node are configured to provide the switching voltage between the second high-side output node and the second low-side output node.

15. The circuit of claim 14, wherein the high-side switch and the low-side switch comprise gallium nitride power transistors.

16. A circuit device comprising: Circuit, including: a first input power supply node and a second input power supply node, the first input power supply node and the second input power supply node being configured to: receive a first power supply voltage differentially applied between the first input power supply node and the second input power supply node; a first input control node and a second input control node, the first input control node being configured to receive a first input control signal, the second input control node being configured to receive a second input control signal; a high-side driver circuit configured to be coupled to a high-side switch of the half-bridge circuit, the high-side driver circuit configured to receive the first input control signal and differentially generate a first output control signal between a first high-side output node and a second high-side output node for controlling the high-side switch; a low-side driver circuit configured to be coupled to a low-side switch of the half-bridge circuit, the low-side driver circuit configured to receive the second input control signal and differentially generate a second output control signal between a first low-side output node and a second low-side output node for controlling the low-side switch; a floating supply node configured to receive a floating supply voltage differentially applied between the floating supply node and the second high-side output node, wherein the high-side driver circuit is electrically coupled between the floating supply node and the second high-side output node to receive the floating supply voltage; Intermediate power node; a bootstrap diode having an anode coupled to the first input power supply node and a cathode coupled to the intermediate power supply node; and a current limiter circuit coupled between the intermediate power supply node and the floating power supply node, wherein the current limiter circuit is configured to sense the floating power supply voltage and, in response to the floating power supply voltage reaching a threshold, offset current flowing from the intermediate power supply node to the floating power supply node; a bootstrap capacitor coupled between the floating power supply node and the second high-side output node; and An inductive load is coupled between the second high-side output node and the second low-side output node and is configured to receive a switching voltage.

17. The apparatus of claim 16, wherein the current limiter circuit comprises: a first field effect transistor having a corresponding first drain-body diode having: an anode coupled to the floating power supply node; and a cathode coupled to the intermediate power supply node.

18. The apparatus of claim 16, wherein the bootstrap diode comprises: a bootstrap field effect transistor having a corresponding drain-body diode having: an anode coupled to the first input power supply node; and a cathode coupled to the intermediate power supply node.

19. A method for a circuit, comprising: receiving a first supply voltage differentially between a first input supply node and a second input supply node; receiving a first input control signal at the first input control node and receiving a second input control signal at the second input control node; differentially generating a first output control signal between a first high-side output node and a second high-side output node for controlling a high-side switch of the half-bridge circuit; differentially generating a second output control signal between the first low-side output node and the second low-side output node for controlling the low-side switch of the half-bridge circuit; receiving a floating supply voltage differentially applied between a floating supply node and the second high-side output node to power a high-side driver circuit; sensing the floating supply voltage; as well as In response to the floating power supply voltage reaching a threshold, current flowing from the intermediate power supply node to the floating power supply node is offset.

20. The method according to claim 19, comprising: comparing the first supply voltage to a switched voltage, the switched voltage being differentially sensed between the second high-side output node and the second low-side output node; as well as In response to the switching voltage exceeding the first power supply voltage, a switch coupled between the floating power supply node and the intermediate power supply node is operated in an on state.

21. The method according to claim 19, comprising: comparing a signal representing the floating supply voltage with a reference signal; as well as A switch coupled between the floating power supply node and the intermediate power supply node is operated in a non-conducting state in response to a signal indicating that the floating power supply voltage exceeds the reference signal.

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