Inverse quantization flip-chip structure for a quantitative computing device

Abstract

A quantum computing device is formed using a first chip (302) and a second chip (306). The first chip has a first substrate (303), a first set of pads (312A, B), and a set of Josephson junctions (304) disposed on the first substrate. The second chip has a second substrate (307), a second set of pads (308) disposed on the second substrate opposite the first set of pads, and a second layer (310) formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency conflicts between qubits in a set of qubits. Qubits are formed using Josephson junctions in the subset of Josephson junctions and another Josephson junction not in the subset that is caused to be unavailable for forming qubits.

Description

Technical Field

[0001] The present invention generally relates to a superconducting quantum device. More specifically, the present invention relates to a structure fabricated in a transmons qubit flip-chip configuration for a quantum computing device. Background Art

[0002] Hereinafter, unless explicitly distinguished in use, the prefix "Q" in a word or phrase indicates a reference to that word or phrase in the context of quantum computing.

[0003] Molecules and subatomic particles follow the laws of quantum mechanics, which is a branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave in strange ways, simultaneously presenting more than one state and interacting with other particles that are very far away. Quantum computing utilizes these quantum phenomena to process information.

[0004] The computers we use now are called classical computers (also referred to herein as "classical" computers or classical nodes, or "CN"). Classical computers use classical processors, semiconductor memories, and magnetic or solid-state storage devices fabricated by using semiconductor materials and technologies, which is called the von Neumann architecture. In particular, the processors in classical computers are binary processors, that is, they operate on binary data represented by 1s and 0s.

[0005] A quantum processor (q-processor) uses the odd properties of entangled qubit devices (compactly referred to herein as "qubits", plural "qubits") to perform computational tasks. In a particular domain where quantum mechanics works, matter particles can exist in multiple states, such as an "on" state, an "off" state, and an "on" and "off" state simultaneously. While binary calculations using semiconductor processors are limited to using only the on and off states (equivalent to 1 and 0 in binary code), quantum processors utilize these quantum states of matter to output signals that can be used for data calculations.

[0006] Conventional computers encode information in bits. Each bit can take a value of 1 or 0, and these 1s and 0s are used as on / off switches that ultimately drive the functions of the computer. On the other hand, quantum computers are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent 1 and 0 simultaneously. Entanglement means that qubits in superposition can be related to each other in a non-classical way; that is, the state of one (whether it is 1 or 0 or both) can depend on the state of the other, and more information about the two qubits can be determined when the two qubits are entangled than when they are processed separately.

[0007] Using these two principles, qubits operate as more complex information processors, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers. Quantum processors using superconducting qubits have been successfully built and their operability demonstrated (IBM is a registered trademark of International Business Machines Corporation in the United States and other countries).

[0008] A superconducting qubit includes a Josephson junction (Josephson junction). A Josephson junction is a superconducting tunnel junction formed by separating two thin film superconducting metal layers with a non-superconducting material. When the metal in the superconducting layer becomes superconducting, for example by reducing the temperature of the metal to a specific low temperature, electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. There are other ways to form a Josephson junction and this description is not meant to be limiting. In a qubit, the Josephson junction, which acts as a dispersive nonlinear inductor, is electrically coupled in parallel with one or more capacitive devices that form a nonlinear microwave oscillator. The oscillator has a resonant / transition frequency determined by the values of the inductance and capacitance in the qubit circuit. Any reference to the term "qubit" is a reference to a superconducting qubit circuit employing a Josephson junction, unless explicitly distinguished when used.

[0009] In the superconducting state, the material first offers no resistance to the passage of an electric current. When the resistance drops to zero, an electric current can circulate within the material without any energy dissipation. Second, the material exhibits the Meissner effect, i.e., as long as they are weak enough, external magnetic fields do not penetrate the superconductor but remain at its surface. When the material no longer exhibits one or both of these properties, the material is said to be in the normal state and is no longer superconducting.

[0010] The critical temperature of a superconducting material is the temperature at which the material begins to exhibit superconducting characteristics. Superconducting materials exhibit very low or zero electrical resistivity to an electric current. The critical magnetic field is the highest magnetic field for which the material remains superconducting for a given temperature.

[0011] Superconductors are generally classified into one of two types. Type I superconductors exhibit a single transition at the critical magnetic field. When the critical magnetic field is reached, a Type I superconductor transitions from a non-superconducting state to a superconducting state. Type II superconductors include two critical magnetic fields and two transitions. When at or below the lower critical magnetic field, a Type II superconductor exhibits a superconducting state. When above the upper critical magnetic field, a Type II superconductor does not exhibit superconductivity. Between this upper critical magnetic field and the lower critical magnetic field, a Type II superconductor exhibits a mixed state. In the mixed state, a Type II superconductor exhibits an incomplete Meissner effect, i.e., the external magnetic field penetrates the superconducting material in quantized packets at specific locations.

[0012] The information processed by qubits is carried or transmitted in the form of microwave signals / photons in the microwave frequency range. The microwave signals are captured, processed, and analyzed in order to decrypt the quantum information encoded therein. A readout circuit is a circuit coupled to the qubit for capturing, reading, and measuring the quantum state of the qubit. The output of the readout circuit is information that can be used by a q-processor to perform calculations.

[0013] Superconducting qubits have two quantum states — |0> and |1>. These two states can be two energy states of an atom, e.g., the ground state (|g>) and the first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of a nuclear or electron spin, two positions of a crystal defect, and two states of a quantum dot. Since the system has quantum properties, any combination of the two states is allowed and valid.

[0014] In known semiconductor manufacturing technologies, superconducting devices such as qubits are fabricated using superconducting and semiconductor materials. Superconducting devices typically use one or more layers of different materials to achieve the performance and functionality of the device. The material layers can be superconducting, conductive, semiconductive, insulating, resistive, inductive, capacitive, or have any number of other properties. Depending on the nature of the materials, the shape, size, or arrangement of the materials, other materials adjacent to the materials, and many other considerations, different methods may have to be used to form the different material layers.

[0015] Software tools for designing semiconductor and superconducting devices fabricate, operate, or otherwise work with electrical layouts and device components on a very small scale. Some of the components that can be manipulated by such tools may measure only a few nanometers in width when formed in a suitable substrate.

[0016] The layout includes shapes, the shapes and positions of which are selected in the tool according to the objectives of the device. Once the design layout (also simply referred to as the layout) has been completed for a device or a group of devices, the design is converted into a set of masks or reticles. A set of masks or reticles is one or more masks or reticles. During manufacturing, a semiconductor wafer is exposed to light or radiation through the masks to form microscopic components including the structures. This process is called lithography. The mask plates can be used to fabricate or print the content of the mask onto the wafer. During the lithography printing process, the radiation is focused through the mask at a specific desired radiation intensity. This intensity of the radiation in combination with any material deposited by the radiation is generally referred to as the “dose”. The focusing and dose of the radiation are controlled to achieve the desired shape and electrical properties of the structures on the wafer.

[0017] Manufacturing processes for semiconductor or superconducting devices include not only dosing but also other methods of depositing and / or removing materials with various electrical and / or mechanical properties. For example, an ion beam of a conductive material can be used to deposit the material; a chemical substance can be used to dissolve or mechanical planarization can be used to erode a hard insulator. Examples of operations in these manufacturing processes are not restrictive. Based on the present disclosure, a person of ordinary skill in the art will be able to conceive of many other operations in the manufacturing processes that can be used to manufacture devices according to the illustrative embodiments, and these operations can be envisioned within the scope of the illustrative embodiments.

[0018] Superconducting devices are typically planar, i.e., where the superconducting structures are fabricated on a plane. Non-planar devices are three-dimensional (3D) devices where some structures are formed above or below a given fabrication plane.

[0019] Some qubits are fabricated using a flip-chip geometry. In a flip-chip geometry, a qubit chip (also referred to as a "Qchip") is fabricated to have a plurality of individual qubits on a substrate, and one or more connected interposer chips are fabricated on a separate substrate. Solder bumps are deposited onto chip pads on a first surface of the qubit chip and / or the interposer chip, and the qubit chip or the interposer chip is flipped so that its first side faces downward. The qubit chip and the interposer chip are aligned and bump-bonded such that the solder of the solder bumps completes the electrical connection between the qubit chip and the interposer chip.

[0020] Therefore, there is a need in the art to solve the above problems. Summary of the Invention

[0021] In a first aspect, the present invention provides a quantum computing device, comprising: a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate; and a second chip having a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer being configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collisions between qubits in a set of qubits, and one qubit in the set of qubits is generated by one Josephson junction in the subset of the Josephson junctions.

[0022] From another aspect, the present invention provides a quantum data processing system, comprising: a quantum processor including a set of qubits, at least one qubit in the set of qubits being formed in a flip-chip configuration including a pair of chips, the pair of chips including: a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate; and a second chip having a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer being configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collisions between qubits in the set of qubits, and one qubit in the set of qubits is generated by one Josephson junction in the subset of the Josephson junctions.

[0023] From a further aspect, the present invention provides a quantum processor, comprising: a set of qubits, at least one qubit in the set of qubits being formed in a flip-chip configuration including a pair of chips, the pair of chips including: a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate; and a second chip having a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer being configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collisions between qubits in the set of qubits, and the qubits in the set of qubits are generated by the Josephson junctions in the subset of the Josephson junctions.

[0024] From a further aspect, the present invention provides a quantum processor.

[0025] Exemplary embodiments provide a quantum computing device. The embodiment includes a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The embodiment further includes a second chip having a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency conflicts between qubits in a set of qubits, the qubits in the set of qubits being generated by Josephson junctions in a subset of the set of Josephson junctions. Thus, the embodiment provides a quantum computing device in a flip-chip configuration, where a number of Josephson junctions on a J-chip are made with manufacturing variations in multiple characteristics, and only some of the Josephson junctions are selected to form qubits with desired frequency conflict avoidance characteristics.

[0026] Another embodiment further includes an unavailable Josephson junction in the set of Josephson junctions, wherein in response to a first Josephson junction in the set of Josephson junctions being excluded from a subset of the set of Josephson junctions, the first Josephson junction is modified to become the unavailable Josephson junction. Thus, the embodiment provides a quantum computing device in a flip-chip configuration, where other Josephson junctions on the J-chip are made unavailable for the quantum computing device.

[0027] Another embodiment also includes a disconnected pad in the first set of pads, wherein the first set of pads includes a first pad electrically coupled to a first Josephson junction, and wherein the first pad is electrically disconnected from the first Josephson junction to form the disconnected pad, the disconnected pad rendering the first Josephson junction unavailable. Thus, the embodiment provides a hardware change to render a Josephson junction on a J-chip unavailable for the quantum computing device.

[0028] In another embodiment, the electrical characteristics of the first Josephson junction are modified such that the first Josephson junction no longer operates as a Josephson junction. Thus, the embodiment provides another hardware change to render a Josephson junction on a J-chip unavailable for the quantum computing device.

[0029] In another embodiment, a subset is selected based on measurements of parameters associated with each Josephson junction in a set of Josephson junctions. Thus, the embodiment provides characteristics of Josephson junctions on a J-chip based on which the junctions can be selected for the quantum computing device.

[0030] In another embodiment, the resonance frequency associated with a particular qubit is a member selected from the set of (i) a predicted resonance frequency calculated based on a measured parameter, and (ii) an actually measured resonance frequency of the particular qubit. Thus, this embodiment provides a predicted characteristic of qubits formed using Josephson junctions on a J-chip, based on which the junction can be selected for use in the quantum computing device.

[0031] In another embodiment, the parameter includes the resistance associated with the Josephson junction in the set of Josephson junctions. Thus, this embodiment provides a particular characteristic of the Josephson junctions on the J-chip, based on which the junction can be selected for use in the quantum computing device.

[0032] In another embodiment, the resistance is the normal state resistance of the Josephson junction. Thus, this embodiment provides a particular characteristic of the Josephson junctions on the J-chip, based on which the junction can be selected for use in the quantum computing device.

[0033] Another embodiment further includes a first set of protrusions formed on the first wafer. This embodiment also includes a set of bumps formed on the first layer of the second chip, the set of bumps being formed of a material having a ductility higher than a threshold at room temperature ranges, wherein the set of bumps is configured to cold weld to the first set of protrusions. Thus, the embodiment provides a device for detachably configuring two chips in a flip-chip configuration.

[0034] In another embodiment, the first set of protrusions is at least one member selected from the group including gold and platinum. Thus, the embodiment provides materials for a device for detachably configuring two chips in a flip-chip configuration.

[0035] In another embodiment, the set of bumps is at least one member selected from the group including indium, tin, lead, and bismuth. Thus, the embodiment provides a device for joining two chips into a flip-chip configuration.

[0036] Another embodiment further includes a flip-chip assembly including a first chip detachably attached to a second chip using cold welding, wherein the parameters of the Josephson junctions inside the flip-chip assembly are tunable by decomposing the flip-chip assembly at the cold weld. Thus, this embodiment provides a detachable configuration of two chips in a flip-chip configuration or tuning the characteristics of the Josephson junctions.

[0037] One embodiment provides a quantum data processing system that uses a quantum processor comprising structures in a flip-chip configuration of transmission qubit devices. The embodiment includes a first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The embodiment further includes a second chip having a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer being configured to bond the first chip to the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency conflicts between qubits in a set of qubits, the qubits in the set of qubits being generated by Josephson junctions in a subset of the set of Josephson junctions. Thus, the embodiment provides a quantum computing device in a flip-chip configuration, where a number of Josephson junctions on a J-chip are made with manufacturing variations in a plurality of characteristics, and only some of the Josephson junctions are selected to form qubits with desired frequency conflict avoidance characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The novel features believed to be characteristic of the invention are set forth in the appended claims. However, the invention itself, as well as its preferred mode of use, further objects and advantages, will best be understood by reference to the following detailed description of illustrative embodiments in conjunction with the accompanying drawings, where:

[0039] Figure 1 A block diagram of a network of a data processing system in which illustrative embodiments can be implemented is described;

[0040] Figure 2 A qubit for use in a quantum processor is depicted;

[0041] Figure 3 An example cross-sectional view of a flip-chip quantum computing device is depicted, which illustrates problems that can be solved using illustrative embodiments;

[0042] Figure 4 A block diagram of an example J-chip configuration according to an illustrative embodiment is described;

[0043] Figure 5 A block diagram of an example configuration achieved in the manufacture of a flip-chip device according to an illustrative embodiment is shown;

[0044] Figure 6 A block diagram of an example configuration achieved in the manufacture of a flip-chip device according to an illustrative embodiment is shown;

[0045] Figure 7 An exemplary graph depicting the predicted frequency of a qubit calculated based on measured junction resistance according to an illustrative embodiment is depicted;

[0046] Figure 8 A block diagram showing an example configuration achieved in the manufacture of a flip-chip device according to an illustrative embodiment;

[0047] Figure 9 A block diagram showing an example configuration achieved in the manufacture of a flip-chip device according to an illustrative embodiment;

[0048] Figure 10 A block diagram showing an example flip-chip configuration achieved in the manufacture of a flip-chip device according to an illustrative embodiment;

[0049] Figure 11 A top-down schematic view of an example J-chip configuration according to an illustrative embodiment;

[0050] Figure 12 A block diagram depicting an alternative example configuration according to an illustrative embodiment;

[0051] Figure 13 A block diagram depicting an example J-chip assembly according to an illustrative embodiment;

[0052] Figure 14 A block diagram describing an example J-chip configuration according to an illustrative embodiment;

[0053] Figure 15 A block diagram depicting an example detachable configuration according to an illustrative embodiment;

[0054] Figure 16 A block diagram depicting an example detachable conductive coupling configuration according to an illustrative embodiment; and

[0055] Figure 17 A block diagram depicting another example configuration of a detachable conductive coupling according to an illustrative embodiment. Detailed Description

[0056] According to the illustrative embodiments described herein, a flip-chip geometry can combine an interposer chip with other chips that contain components with qubits rather than full qubits. For example, a junction chip (also referred to as a "J chip") is a chip on which multiple individual Josephson junctions are fabricated according to an illustrative embodiment. When the interposer is combined with the J chip in a flip-chip configuration as described herein, the Josephson junctions from the multiple Josephson junctions can be used to form qubits. According to an exemplary embodiment, an interposer chip with one or more connections is fabricated on a separate substrate. Bumps of a suitable material are deposited onto chip pads on a first surface of the J chip and / or the interposer chip, the suitable material being, for example, a solder material that has the required electrical, thermal, ductility, and malleability properties at low temperatures and other operating conditions described herein. Generally, any reference to solder bumps should be interpreted to include bumps made of materials that meet these requirements. The J chip or the interposer chip is flipped such that the first face of the flipped chip faces the first face of the non-flipped chips from both chips. The J chip and the interposer chip are aligned and bump-bonded such that the material of the bumps completes the electrical connection between the J chip and the interposer chip.

[0057] Readout circuits typically use resonators to couple to qubits via electromagnetic resonance (typically microwave or radio frequency resonance). The resonators in the readout circuits include inductive elements and capacitive elements. Some qubits are fixed-frequency qubits, i.e., their resonance frequencies are unalterable. Other qubits are frequency-tunable qubits. A q-processor can employ fixed-frequency qubits, frequency-tunable qubits, or a combination thereof.

[0058] Illustrative embodiments recognize that fixed-frequency qubits are designed to be fixed in frequency to improve resilience to noise. Illustrative embodiments recognize that negative effects such as crosstalk, quantum decoherence, energy decay, generation of mixed states, unintentional information transfer, quantum state leakage, etc. can occur when the resonance frequencies of two coupled qubits on a chip are the same or within a threshold frequency band, or when their higher transition frequencies are in resonance or near resonance. Illustrative embodiments also recognize that such qubits can also negatively impact the performance or utility of certain quantum gates, such as cross-resonance gates that have strict requirements on the frequency spectrum of the resonance frequencies of the qubits on which the gate operates. Illustrative embodiments further recognize that one challenge in a quantum processor based on fixed-frequency qubits is frequency crowding or frequency conflict between adjacent qubits.

[0059] Exemplary embodiments recognize that another challenge in quantum processors based on fixed-frequency qubits is the low on / off ratio between the interaction of coupled qubits when microwave signals are turned on (turning on the interaction strength) and when these signals are disabled (turning off the interaction strength). Exemplary embodiments further recognize that yet another challenge in quantum processors based on fixed-frequency qubits is enabling the gates of interest without creating unwanted interactions at other sites. Exemplary embodiments also recognize that defects in manufacturing and the materials used in the manufacturing methods of currently available fixed-frequency qubits result in deviations from the expected resonant frequencies.

[0060] Exemplary embodiments further recognize that in some cases, the Josephson junctions of qubits can be tuned to adjust the resonant frequency of the qubit. However, exemplary embodiments recognize that once a flip-chip assembly is formed, the Josephson junctions on the qubit chip or J-chip become physically inaccessible for operations such as laser annealing, through which the impedance of the Josephson junction can be modified or tuned. In such cases, the flip-chip assembly becomes fixed to the qubit structure, where the Josephson junction has an undesired impedance. Thus, exemplary embodiments recognize the need for a flip-chip configuration in which qubits can be formed at the desired resonant frequency even after the interposer has been flipped onto the J-chip.

[0061] Exemplary embodiments for describing the present invention generally address and meet the above problems or needs, as well as other related problems or needs, by providing a transmons qubit flip-chip structure for forming a flip-chip quantum computing device. Exemplary embodiments also provide a quantum processor formed using the described transmons qubit flip-chip structure.

[0062] Referring to the accompanying drawings, and specifically referring to Figure 1 , these drawings are example diagrams of a data processing environment in which exemplary embodiments can be implemented. Figure 1 These are merely examples and are not intended to assert or imply any limitations on the environments in which different embodiments can be implemented. Many modifications to the depicted environments can be made based on the following description for a particular implementation.

[0063] Figure 1 A block diagram of a network of a data processing system in which exemplary embodiments can be implemented is described. The data processing environment 100 is a computer network in which exemplary embodiments can be implemented. The data processing environment 100 includes a network 102. The network 102 is a medium for providing a communication link between various devices and computers connected together within the data processing environment 100. The network 102 can include connections such as wired, wireless communication links, or fiber optic cables.

[0064] A client or server is merely an example role of certain data processing systems connected to network 102 and is not intended to exclude other configurations or roles of these data processing systems. Server 104 and server 106 are coupled to network 102 along with storage unit 108. Software applications can be executed on any computer in data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. Data processing systems such as server 104 or 106 or clients 110, 112, or 114 can contain data and can have software applications or software tools executing thereon.

[0065] Device 132 is an example of a mobile computing device. For example, device 132 can take the form of a smart phone, a tablet computer, a laptop computer, a client 110 in fixed or portable form, a wearable computing device, or any other suitable device. Any software application described as executing in another data processing system in Figure 1 can be configured to execute in device 132 in a similar manner. Any data or information stored or generated in another data processing system in Figure 1 can be configured to be stored or generated in device 132 in a similar manner.

[0066] Application 105 implements the embodiments described herein. Fabrication system 107 is a software component of any suitable system for fabricating quantum devices such as Josephson junctions, qubits, and other superconducting structures used in quantum computing devices. Generally, fabrication systems for fabricating superconducting devices and their corresponding software components are known, the superconducting devices including devices for quantum computing purposes. Application 105 provides instructions to such known fabrication systems via fabrication application 107 for assembling the novel flip-chip quantum devices contemplated in the illustrative embodiments in the manner described herein.

[0067] Referring to Figure 2 , the figure depicts qubits in a quantum processor. Qubit 200 includes capacitor structure 202 and Josephson junction 204. Josephson junction 204 is formed by separating two thin film superconducting metal layers with a non-superconducting material. When the metal in the superconducting layer becomes superconducting, for example by reducing the temperature of the metal to a specific cryogenic temperature, electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In superconducting qubit 200, Josephson junction 204 (with a small inductance) is electrically coupled in parallel with capacitor structure 202, forming a nonlinear resonator.

[0068] Referring to Figure 3, which depicts an example cross-sectional view of a flip-chip quantum computing device, illustrating problems that can be solved using the illustrative embodiments. The flip-chip quantum computing device 300 includes a J-chip 302 having a substrate 303. The substrate 303 is selected as a suitable material on which Josephson junctions can be formed, and ultimately the material is suitable for forming qubits using Josephson junctions. The substrate 303 includes Josephson junctions 304 formed on a first surface of the substrate 303. In this embodiment, the Josephson junctions 304 have an associated impedance that helps set a qubit resonance frequency for the qubits in which the Josephson junctions 304 can be used, as described herein.

[0069] The substrate 303 includes a material that exhibits a residual resistance ratio (RRR) of at least 100 and a thermal conductivity greater than 1 W / (cm×K) at 4 Kelvin when operated within a cryogenic temperature range. The RRR is the ratio of the resistivity of the material at room temperature and 0K, and since 0K cannot be achieved in practice, an approximation at 4K is used. For example, the substrate 303 can be formed using sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, or diamond to operate within a temperature range of 77K to 0.01K. These examples of substrate materials are not limiting. Those of ordinary skill in the art will be able to think of many other materials suitable for forming the substrate 303 in accordance with the present disclosure, and such materials can be envisioned within the scope of the illustrative embodiments.

[0070] The flip-chip quantum computing device 300 further includes an interposer chip 306 that includes an interposer substrate 307. The interposer substrate 307 includes a material that exhibits an RRR of at least 100 and a thermal conductivity greater than 1 W / (cm*K) at 4 Kelvin. For example, the interposer substrate 307 can be made of materials such as sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, or diamond to operate within a temperature range of 77K to 0.01K. These examples of substrate materials are not limiting. Those of ordinary skill in the art will be able to think of many other materials suitable for forming the substrate 307 in accordance with the present disclosure, and such materials can be envisioned within the scope of the illustrative embodiments. In a particular embodiment, one or more of the substrate 303 and the interposer substrate 307 are formed of silicon or another suitable substrate material.

[0071] The interposer chip 306 includes a conventional ground plane 308 formed on a first surface of the interposer substrate 307. In a particular embodiment, the ground plane 308 is formed of a superconducting material, a plurality of superconducting materials, a metallic material, or a combination thereof.

[0072] The J-chip 302 includes a first bonding pad 312A and a second bonding pad 312B formed on a first surface of a substrate 303. The first bonding pad 312A and the second bonding pad 312B are part of a ground plane (not shown) on the J-chip 302. In certain embodiments, the bonding pads 312A-B are formed of a superconducting material, a plurality of superconducting materials, a metallic material, or a combination thereof.

[0073] The ground plane 308 of the interposer chip 306 is bonded to the J-chip 302 via a first bump bond 310A and a second bump bond 310B. In some embodiments, a single bump bond or more than two bump bonds may also be used to bond the ground plane 308 of the interposer 306 to the J-chip 302. In such embodiments, the J-chip 302 may be formed with an appropriate number of bonding pads to achieve the desired number of ground plane bonds.

[0074] An electrical connection between the interposer chip 306 and the J-chip 302 is formed through the first bump bond 310A and the first bonding pad 312A, and through the second bump bond 310B and the second bonding pad 312B. In an embodiment, at least one of aluminum, niobium, titanium, titanium nitride, palladium, gold, silver, copper, or platinum is used to form the ground plane 308, the first bonding pad 312A, and the second bonding pad 312B for operation in a temperature range from 77K to 0.01K. In one embodiment, indium, tin, and bismuth alloys are used to form the bump bonds 310A, 310B for operation in a temperature range from 77K to 0.01K. These examples of ground plane, bump bond material, and bonding pad material are not intended to be limiting. Those of ordinary skill in the art will be able to think of many other materials suitable for forming the first layer and these materials can be envisioned within the scope of the exemplary embodiments in accordance with the present disclosure.

[0075] The qubit resonance frequency is difficult to control due to variations in the Josephson junction inductance during fabrication. Josephson junctions fabricated by shadow evaporation, e.g., by the Dolan bridge technique, naturally exhibit variations in their Josephson inductance. For single-junction transmon qubits of the same design and fabrication / processing, each qubit can naturally have a different resonance frequency (e.g., with a variation of 100 MHz - 200 MHz). This situation can lead to frequency conflicts for fixed-frequency qubits using cross-resonance entanglement gates, e.g., a frequency conflict between a qubit using the Josephson junction 304 and a second coupled qubit using another Josephson junction on the J-chip 302.

[0076] Exemplary embodiments recognize that preventing frequency conflicts is a challenging problem for fixed-frequency superconducting qubits, and it is difficult to change or modify qubit frequencies using conventional methods after chip fabrication. The frequency of a qubit is inversely proportional to the square root of the product of the Josephson inductance and the total capacitance across the Josephson junction. Thus, methods for resolving frequency conflicts include changing the frequency of a single-junction transmon qubit by modifying the junction inductance or the total capacitance across the junction (e.g., in parallel with the junction).

[0077] Several methods have been proposed to adjust the junction inductance in order to tune the resonant frequency, but each method has limitations and drawbacks. For example, it is difficult to precisely perform the inductance change. Alternatively, frequency tuning can be performed by changing the capacitance, e.g., by etching the substrate (e.g., a silicon (Si) substrate) in the gap of a planar capacitor to change the effective dielectric constant. However, such etching exposes the Josephson junction to significantly more fabrication processes. In addition, the etching and associated processes may introduce additional loss mechanisms. Further, the etching and associated processes are typically only available for reducing capacitance and increasing qubit frequency, but not for increasing capacitance and correspondingly reducing qubit frequency.

[0078] One embodiment provides a flip-chip geometry that includes a J-chip and an interposer chip, and the flip-chip geometry can be used to form qubits in a quantum processor. The J-chip includes a plurality of Josephson junctions defined on a substrate.

[0079] One embodiment provides a novel design of a quantum computing device with a flip-chip geometry. In this embodiment, a design / fabrication system uses known processes for fabricating Josephson junctions to design and fabricate a J-chip with a plurality of Josephson junctions. The design / fabrication system also designs and fabricates the interposer chip.

[0080] Each fabricated Josephson junction has a normal-state resistance, e.g., which can be measured by electrically probing the Josephson junction resistance at a temperature above the superconducting transition temperature. The resonant frequency of a qubit using a particular Josephson junction can be predicted based on the measured Josephson junction resistance of that particular Josephson junction. One specific embodiment uses a fitting curve that relates the Josephson junction resistance to frequency to calculate the predicted frequency of such a qubit. Although various embodiments describe the measurement of the resistance of the Josephson junction, in other embodiments the measurement of the impedance or inductance of the Josephson junction can be used to predict the resonant frequency of a qubit using the Josephson junction.

[0081] In one embodiment, the design / manufacturing system determines possible frequency conflicts based on predicted resonance frequencies generated by a set of more than one Josephson junction fabricated on the J-chip 302. Specifically, this embodiment determines the predicted resonance frequencies of possible qubits that may use the Josephson junctions from the set of Josephson junctions. Based on a set of possible qubits, this embodiment determines a first subset of possible qubits (which uses a corresponding first subset of Josephson junctions from the set of Josephson junctions) that satisfies a frequency conflict separation threshold. Accordingly and optionally, from the set of possible qubits, this embodiment determines a second subset of possible qubits (which uses a corresponding second subset of Josephson junctions from the set of Josephson junctions) that does not satisfy the frequency conflict separation threshold.

[0082] In an embodiment where the qubit resonance frequency is a function of the separation gap distance between the interpolator chip and the J-chip, the design / manufacturing system also determines a suitable separation gap distance between the interpolator chip and the J-chip based on a desired frequency adjustment, a frequency tuning range, and a sensitivity, which will result in an acceptable number of qubits in the first subset. In this embodiment, the design / manufacturing system joins the interpolator chip and the J-chip at the separation gap distance to achieve a desired qubit frequency and qubit number in a flip-chip arrangement.

[0083] In a particular embodiment, the design / manufacturing system joins the interpolator chip and the J-chip. In one embodiment, the joining is performed using a bump bonding process. In other particular embodiments, other suitable methods may be used to join the interpolator chip and the J-chip.

[0084] The manufacturing method for fabricating a flip-chip quantum computing device of the embodiment can be implemented as a software application. The application implementing the manufacturing method can be configured to operate in conjunction with an existing superconducting manufacturing system (such as a lithography system).

[0085] For clarity of description and without implying any limitation thereto, illustrative embodiments are described using an example number of Josephson junctions in a set of Josephson junctions disposed on a substrate or the number of qubits using a subset of the set of Josephson junctions. Within the scope of the illustrative embodiments, one embodiment can be implemented with a different number of Josephson junctions in the set of Josephson junctions, a different number of Josephson junctions in the subset to form qubits, different arrangements, superconducting devices different from the qubits formed using the Josephson junctions in the subset, various types of quantum computing devices not based on cryogenic superconductors, or some combination thereof.

[0086] In addition, simplified diagrams of exemplary flip-chip geometries are used in the drawings and illustrative embodiments. When actually fabricating a flip-chip, additional structures that are not shown or described herein, or structures different from those shown and described herein, may exist without departing from the scope of the illustrative embodiments. Similarly, within the scope of the illustrative embodiments, the structures shown or described in the exemplary flip-chip may be fabricated differently to yield similar operations or results as described herein.

[0087] As described herein, the different shaded portions in the two-dimensional diagrams of the exemplary structures, layers, and formations are intended to represent different structures, layers, materials, and formations in the exemplary fabrication. The different structures, layers, materials, and configurations may be fabricated using suitable materials known to those of ordinary skill in the art.

[0088] The specific shapes, positions, orientations, or dimensions of the shapes described herein are not intended to limit the exemplary embodiments, unless such features are explicitly described as features of an embodiment. The selection of a shape, position, dimension, quantity, or some combination thereof is for clarity of the drawings and description only, and may have been exaggerated, minimized, or otherwise altered relative to the actual shapes, positions, or dimensions that may be used in actual lithography to achieve the objectives in accordance with the illustrative embodiments.

[0089] In addition, by way of example only, the illustrative embodiments are described with respect to specific actual or hypothetical superconducting devices, such as currently viable qubits. The steps described by the various illustrative embodiments may be adapted to fabricate various quantum computing devices in a similar manner, and such adaptations are contemplated within the scope of the illustrative embodiments.

[0090] When implemented in an application, the embodiments cause a manufacturing process to perform certain steps as described herein. The steps of the manufacturing process are described in several of the drawings. Not all steps are required in a particular manufacturing process. Some manufacturing processes may implement the steps in a different order, combine certain steps, remove or replace certain steps, or perform some combination of these and other step operations without departing from the scope of the illustrative embodiments.

[0091] By way of example only, the illustrative embodiments are described with respect to certain types of materials, electrical properties, thermal properties, structures, formations, shapes, layer orientations, directions, steps, operations, planes, dimensions, quantities, data processing systems, environments, components, and applications. Any particular manifestations of these and other similar artificial factors are not intended to limit the invention. Any suitable manifestations of these and other similar products may be selected within the scope of the exemplary embodiments.

[0092] Illustrative embodiments are described using specific designs, architectures, layouts, diagrams, and tools, which are only examples and not limitations of the illustrative embodiments. The illustrative embodiments can be used in combination with other equivalent or similar-purpose designs, architectures, layouts, diagrams, and tools.

[0093] An advantage that embodiments can provide is that no additional processing on the J chip is required after manufacturing, which does not pose a risk of junction damage or failure.

[0094] The examples in this disclosure are only for clear description and not limitations of the illustrative embodiments. Any advantages listed herein are only examples and are not intended to limit the illustrative embodiments. Additional or different advantages can be achieved through specific illustrative embodiments. Moreover, a specific illustrative embodiment may have some, all, or none of the advantages listed above.

[0095] Reference Figure 4 , which depicts a block diagram of an example J chip configuration in accordance with an illustrative embodiment. Figure 1 The application 105 in Figure 3 interacts with the manufacturing system 107 to produce or manipulate the configuration 400 as described herein. The substrate 402 is

[0096] One embodiment causes the manufacturing system to deposit the material 404 to form a set of pads 408. For example, a mask can be designed to include the layout of one or more pads 408. The manufacturing system operating in conjunction with the embodiment uses the mask to pattern the material 404 on (or within) the substrate 402 in the shape of the pads 408 via the previously described lithography process. The pattern corresponding to the pads 408 etched in the hard mask layer can also allow the lithography process to deposit the material 404 in the shape of the pads 408. These and other possible ways of forming the pads 408 by the lithography process can be envisioned within the scope of the exemplary embodiments.

[0097] The set of pads 408 includes a material 404 that has high electrical conductivity and high thermal conductivity (above a threshold RRR and above a threshold thermal conductivity) in a low-temperature range. In one embodiment, at least one of aluminum, niobium, titanium, titanium nitride, palladium, gold, silver, copper, or platinum is used to form the set of pads 408 for operation in a temperature range from 77K to 0.01K. These examples of layer materials are not restrictive. Those of ordinary skill in the art will be able to think of many other materials suitable for forming the set of pads in accordance with the present disclosure, and these materials can be envisioned within the scope of the exemplary embodiments.

[0098] In one embodiment, a set of pads 408 is deposited on one side, e.g., the side of substrate 402 that will face the interposer in a flip-chip configuration. For example, a set of pads 408 can be a thin film deposition of particles 406 on substrate 402. Thin film deposition techniques in lithography can be used to deposit particles 406. This example of a deposition method is not limiting. Those of ordinary skill in the art will be able to conceive of many other methods and processes suitable for forming the set of pads in accordance with the present disclosure, and such methods and processes are considered to be within the scope of the exemplary embodiments. In one embodiment, particles 406 are materials that can be used to electrically isolate an under-bump metal (UBM) layer (described at least in Figure 5 from substrate 402. In one embodiment, pads 408 are optional, e.g., when the substrate or underlying structure (e.g., a ground plane formed in some other way) has the electrical characteristics required to fabricate the UBM layer on top of such structure, the UBM layer can be formed directly on the substrate or underlying structure to the desired height.

[0099] Refer to Figure 5 , which depicts a block diagram of an example configuration achieved in the fabrication of a flip-chip device according to an illustrative embodiment. Figure 1 The application 105 in Figure 4 interacts with the manufacturing system 107 to produce or manipulate configuration 500 as described herein. Substrate 502 is an example of substrate 402 in Figure 3 or substrate 302 in Figure 4 , and pads 504 are examples of pads 408 in

[0100] and can be optional for the reasons described previously.

[0101] Configuration 500 is an optionally reachable configuration from configuration 400 in Figure 4 using a properly configured mask in a lithography process. Alternatively, when pads 408 of Figure 4 are not used, structure 500 can be reached from structure 300 in Figure 3 , and the UBM structure depicted in the figure can be formed directly on the substrate or another structure to the desired height in a lithography process using a properly configured mask in the manner described previously herein.

[0102] The description of the mask and the lithography techniques should not be construed as a limitation on the manner of forming the structures described herein. The depicted masks and the manner of depicting the deposited materials are merely simplified and generalized examples. The described structures can be lithographed in many ways. For example, currently, the lithography of the described structures is achieved by patterning a resist with lithography (light) or electron beam lithography (electron beam), developing the resist, and then subtracting the deposited material from the openings in the resist or depositing material in the openings in the resist. Finally, the resist is removed. The pads, resonators, and ground planes are typically made by subtraction, and the junctions and UBMs are typically made by addition (and subsequent lift-off processes) using currently available manufacturing facilities. The manufacturing processes and techniques are constantly changing, and other methods of forming the described structures are within the contemplation of the illustrative embodiments, as long as the resulting structures have the electrical, mechanical, thermal, and operational characteristics described herein.

[0103] In one embodiment, a first layer 510 is patterned using a mask on a pad 504 by a lithography process, such as using a deposition method, to form a UBM. In another embodiment, as depicted in configuration 550, a first layer 552 is patterned on a substrate 502 in the manner described herein via a lithography process up to a desired height to form a UBM. As a non-limiting example, the first layer 510 can be patterned using thin film deposition techniques in lithography to deposit particles 508. As another example, the first layer 510 can be patterned using sputtering techniques known in lithography. These examples of methods of forming a UBM are not intended to be limiting. According to the present disclosure, one of ordinary skill in the art will be able to conceive of many other methods and processes suitable for forming a UBM, and these methods and processes are considered to be within the scope of the exemplary embodiments. The further description of using the UBM 510 of configuration 500 is for clarity of description only and does not imply any limitation on any embodiment. Without departing from the scope of the illustrative embodiments, a configuration shown using the UBM 510 or its equivalent can be implemented using the UBM 552 or its equivalent.

[0104] Reference Figure 6 , which depicts a block diagram of an example configuration achieved in the manufacture of a flip-chip device according to an illustrative embodiment. Figure 1 The application 105 in interacts with the manufacturing system 107 to generate or manipulate a configuration 600 as described herein. The substrate 602 is Figure 5 an example of the substrate 502 in the configuration 500 or 550, the pad 604 is a UBM, configured in the manner of the combination of the structure 504 and the first layer 510 or in the manner of the layer 552 in Figure 5 , embodiments enable a manufacturing system configured to manufacture a quantum computing device or components therefor, as regarding Figure 1As described, material 606 is patterned into Josephson junction 610 on J-chip substrate 602. As a non-limiting example, Josephson junction 610 can be patterned using lithography with a suitably designed mask.

[0105] Reference Figure 7 , which depicts an exemplary graph for calculating the predicted frequency of a qubit based on a measured junction resistance, according to an illustrative embodiment. Figure 7 A graph 700 showing the relationship between the predicted qubit frequency f01 and the Josephson junction resistance R includes curve 702 and curve 704. According to one embodiment, the resistance of the Josephson junction is measured (e.g., by electrical probing) to obtain the resistance R. Based on the measured resistance R, the predicted resonant frequency of the qubit using the Josephson junction can be determined by reading the corresponding values on the Y-axis of curves 702 and 704 in graph 700.

[0106] Reference Figure 8 , which depicts a block diagram of an example configuration achieved in the fabrication of a flip-chip device, according to an illustrative embodiment. Figure 1 Application 105 in [reference] interacts with fabrication system 107 to produce or manipulate configuration 800 as described herein. Configuration 800 includes an interposer substrate 802, a set of pads 804 formed on the front side of interposer substrate 802, and a set of resonator signal lines 806. In one embodiment, pads 804 and resonator signal lines 806 are formed of a material exhibiting electrothermal characteristics similar to those of the Figure 3 ground plane 308 in [reference], and in another embodiment, pads 804 and resonator signal lines 806 are formed of the same material as the Figure 3 ground plane 308 in [reference]. In one embodiment, pads 804 and resonator signal lines 806 are patterned in the same lithography step in which the Figure 3 ground plane 308 in [reference] is patterned, and in another embodiment, pads 804 and resonator signal lines 806 are patterned separately and are patterned after the lithography step in which the Figure 3 ground plane 308 in [reference] is patterned.

[0107] One embodiment causes fabrication system to deposit material 810, e.g., patterned using a deposition process 808 in lithography, to form a first layer 812 on a set of pads 804. In one embodiment, first layer 812 is patterned using a material and lithography process functionally similar to those Figure 5 used to pattern first layer 510 on pads 504 in [reference], and first layer 812 forms a UBM layer on corresponding pads 804.

[0108] Reference Figure 9 , which depicts a block diagram of an example configuration achieved in the fabrication of a flip-chip device, according to an illustrative embodiment.Figure 1 The application 105 in interacts with the manufacturing system 107 to generate or manipulate the configuration 900 as described herein. The configuration 900 is Figure 8 a further development of the configuration 800 in, and the reference numerals 802, 804, 806, and 812 indicate structures that are the same as or similar to those Figure 8 depicted and described with respect to.

[0109] One embodiment causes the manufacturing system to perform an appropriate lithography operation 910 to deposit the material 912, thereby forming a second layer 914 on the first layer 812. In one embodiment, the second layer 914 is deposited on the first layer 812 only on a subset of a set of pad UBM structures 804 - 812. In one embodiment, the subset of the set of pad - UBM structures 804 - 812 corresponds to a selected subset of a set of Josephson junctions. As described herein, not all of the Josephson junctions in a set of Josephson junctions may meet the requirements for forming qubits, and a subset of the Josephson junctions may be selected. The subset of the set of pad - UBM structures 804 - 812 corresponding to the selected subset of the Josephson junctions is those that accommodate the second layer 914. In effect, the embodiment causes a lithography mask to be formed such that only the selected subset of the pad UBM structures 804 - 812 receives the deposition of the material 912 to form the second layer 914. Other methods, such as but not limited to hard mask formation instead of a lithography mask, may also be used for a similar purpose, and the same purpose can be expected within the scope of the exemplary embodiments.

[0110] In one embodiment, the second layer 914 is a set of solder bumps. In one embodiment, an example of the second layer 914 is bumps formed using indium, tin, and bismuth or some combination thereof, for operation in the temperature range from 77K to 0.01K. These examples of the second layer material are not restrictive. Those of ordinary skill in the art will be able to think of many other materials suitable for forming the second layer in accordance with the present disclosure, and these materials can be envisioned within the scope of the exemplary embodiments.

[0111] In an embodiment, the second layer 914 is deposited on the first layer 906. For example, the second layer 914 is an injection - molded solder (IMS) deposition of particles 912 on the first layer 812. In some implementations, the layer 812 may not be present, and the particles 912 may be deposited onto the pads 804 to form the bumps 914. In some other implementations, the pads 804 may not be present, and the bumps 914 may be formed on the UBM layer 812. In some other embodiments, the pad - UBM layer combination 804 - 812 may be formed in an alternative manner using alternative materials, but for a similar purpose, such that electrical connection from points in the interposer chip to the Josephson junctions is enabled. In such a case, the bumps 914 may be formed at or above the alternative structure without departing from the scope of the exemplary embodiments.

[0112] Reference Figure 10 , which depicts a block diagram of an example flip-chip configuration achieved in the fabrication of a flip-chip device according to an illustrative embodiment. Figure 1 Application 105 in interacts with fabrication system 107 to produce or manipulate configuration 1000 as described herein.

[0113] One embodiment causes the fabrication system to orient an interposer chip 802 having its corresponding structure relative to a J-chip 602 such that their corresponding structures are oriented relative to each other such that their respective structures face each other to form a flip-chip configuration. For example, the interposer chip is shown flip-chip on the J-chip such that Figure 9 the bumps 914 described in Figure 6 make physical and electrical contact with the structure 604 on the J-chip 602 of

[0114] Reference Figure 11 , which depicts a top-down schematic view of an example J-chip configuration according to an illustrative embodiment. Figure 1 Application 105 in Figure 6 interacts with fabrication system 107 to produce or manipulate configuration 1100, thereby forming configuration 1101 as described herein. In configuration 1100, it is assumed that the J-chip substrate 602 of Figure 5 is configured with three non-limiting example Josephson junctions 610. Each Josephson junction 610 is electrically coupled to a corresponding pair of pads 504, and the pair of pads 504 has a UBM layer 510 fabricated in the manner described in Figure 5

[0115] For clarity, only three Josephson junctions and their corresponding connection structures are shown, rather than implying that the illustrative embodiment is limited to a configuration having three or fewer Josephson junctions on the J-chip under consideration. Embodiments can be implemented and practiced using J-chips including any number of Josephson junctions and their corresponding connection structures, without any limitation imposed by the illustrative embodiment and limited only by the state of the art at any given time.

[0116] ​In an embodiment, application 105 determines that a subset of a set of Josephson junctions 610 is to be removed to avoid frequency conflicts. One embodiment causes the fabrication system to disable a subset of the set of Josephson junctions 610, thereby forming configuration 1101. The disabled Josephson junctions are represented as Josephson junctions 1112 in configuration 1101. The Josephson junctions can be disabled in various ways, including but not limited to physically damaging or altering the Josephson junctions, electrically damaging or altering the electrical characteristics of the Josephson junctions, disconnecting the Josephson junctions from one or both of their corresponding pads, physically damaging or altering one or both of the pads of the Josephson junctions, electrically damaging or altering the electrical characteristics of one or both of the pads of the Josephson junctions, physically damaging or altering the UBM layer on one or both of the pads of the Josephson junctions, electrically damaging or altering the electrical characteristics of the UBM layer on one or both of the pads of the Josephson junctions, covering one or both of the pads or one or both of the UBMs of the Josephson junctions by fabricating an insulating layer, or some combination of these ways with many other possible ways of rendering the Josephson junctions unavailable.

[0117] For example, in one embodiment, the fabrication system ablates a subset of the set of Josephson junctions 1112 from the surface of the J-chip substrate 602. For example, the fabrication system can use laser ablation to remove a subset of the set of Josephson junctions 1112. As another example, the fabrication system can use a focused ion beam (FIB) to remove a subset of the set of Josephson junctions 1112. In another embodiment, the fabrication system disrupts a subset of the set of Josephson junctions 1112 by disconnecting the electrical connectors 1108 and 1110 that couple the Josephson junctions 1112 to their corresponding pad pairs 504. The disconnection of connectors 1108 and 1110 can also be performed by ablation, FIB, or other suitable methods.

[0118] Refer to Figure 12 , which depicts a block diagram of an alternative example configuration in accordance with an illustrative embodiment. Figure 1 The application 105 in Figure 8 interacts with the fabrication system 107 to produce or manipulate configuration 1200 as described herein. Configuration 1200 is an example of configuration 800 in

[0119] By simply not connecting to a Josephson junction, the Josephson junction can be disabled or made unavailable for use in a quantum computing device. For example, by simply not forming a bump at the location of the UBM layer corresponding to the Josephson junction on the interposer chip, the unwanted Josephson junction, along with the connection pads and UBM layer of the Josephson junction, can be kept unconnected. Without the bump, the pad on the interposer at that location will not make electrical contact with the UBM layer of the Josephson junction, rendering the Josephson junction unavailable.

[0120] An embodiment causes the mask to be configured such that certain interposer pads are blocked from receiving material 1212 deposited using process 1210 in the fabrication system. Thus, from the example results of such selective deposition, it can be seen that the second layer 904 is formed only on some pad-UBM combinations 804-812 and not on other pad-UBM combinations. For example, a single pad-UBM combination 804-812 in the region labeled 1202 does not have a second layer-bump. As another example, a pair of pad-UBM combinations 804-812 in the region labeled 1204 does not have a bump.

[0121] Reference Figure 13 , which depicts a block diagram of an example J-chip assembly according to an illustrative embodiment. As a non-limiting example, assembly 1300 shows an interposer chip flip-chip mounted on a J-chip, where some of the Josephson junctions from the J-chip are connected to circuits and components on the interposer chip, while other Josephson junctions are at least disconnected and preferably made unavailable for use.

[0122] Reference Figure 14 , which depicts a block diagram of an example detachable J-chip configuration according to an illustrative embodiment. Figure 1 The application 105 in Figure 5 interacts with the fabrication system 107 to produce or manipulate a configuration 1400 as described herein. Configuration 1400 is an example of the configuration 500 in

[0123] Structure 1400 includes a J-chip substrate 1402, similar to the substrate 502 in Figure 5 , pads 1404 similar to the pads 504 in Figure 5 , and a first layer 1406 similar to the first layer 510 in Figure 5 .

[0124] One embodiment causes the fabrication system (e.g., Figure 1In the manufacturing system 107), a set of protrusions 1412 is formed on the first layer 1406 of a set of pads 1404 of the substrate 1402. For example, an embodiment may cause the mask 1408 in the manufacturing system to deposit the material 1410 to form a set of protrusions 1412. In one embodiment, the manufacturing system 107 includes a wire bonder to deposit the material 1410 and form the protrusions 1412. For example, the wire bonder may form the first half of the ball bond before pulling up to deposit the remainder of the protrusion. In one embodiment, the protrusions 1412 are columns. For example, the protrusions 1412 may have a conical, triangular, cylindrical, or rectangular cross-section.

[0125] In one embodiment, the protrusions 1412 include a material 1410 having a predetermined ductility (above a threshold) in the room temperature range. In one embodiment, the protrusions 1412 are formed using a material that exhibits at least twenty percent elongation at break at room temperature. For example, the protrusions 1412 may be formed using gold, platinum, or a gold-coated superconducting material. These examples of protrusion materials, qubit substrate materials, protrusion shapes, and deposition methods are not intended to be limiting. Those of ordinary skill in the art will be able to envision many other materials and methods suitable for forming substrates, J-chips, and protrusions in accordance with the present disclosure, and they may be envisioned within the scope of the illustrative embodiments.

[0126] Reference Figure 15 , which depicts a block diagram of an example detachable configuration in accordance with an illustrative embodiment. Figure 1 The application 105 in interacts with the manufacturing system 107 to produce or manipulate a configuration 1500 as described herein.

[0127] The configuration 1500 includes an interposer chip configuration constructed on the substrate 802 in a Figure 9 manner, and the configuration 1550 further includes a J-chip configuration constructed on the substrate 602 in a Figure 6 manner and further transformed in a Figure 14 manner.

[0128] One embodiment causes the manufacturing system to couple the J-chip configuration with the interposer chip configuration such that the protrusions 1412 on the J-chip are separably but conductively coupled to corresponding bumps 914 on the interposer chip. Note that the protrusions 1412 may be formed and interfaced with the bumps on the interposer even when the corresponding Josephson junctions are disabled in the manner described herein.

[0129] In one embodiment, a separable conductive coupling between the protrusions 1412 and the bumps 914 is achieved by causing the manufacturing system 107 to cold weld the protrusions 1412 to the solder bumps 914. For example, the protrusions 1412 penetrate the corresponding solder bumps 914. Cold welding is a welding process in which a joint occurs at the interface of two components to be welded, where the interface is in the room temperature range. In cold welding, the interface is in the solid state. In this way, a set of protrusions is separably but conductively coupled to a corresponding set of bumps.

[0130] Reference Figure 16 , which depicts a block diagram of an example detachable conductive coupling configuration in accordance with an illustrative embodiment. Structure 1600 is Figure 15 an example of a cold weld connection between a set of protrusions and a set of solder bumps, and structure 1600 includes pads 804 and UBM layer 812 on an interposer chip as in Figure 8 , bumps 914 as in Figure 9 , pads 504 and UBM layer 510 on a J chip as in Figure 5 , and protrusions 1412 as in Figure 14 .

[0131] In one embodiment, the bumps 914 include a material having a predetermined ductility (above a threshold) at room temperature. In one embodiment, the bumps 914 are formed using a material that exhibits at least twenty percent elongation at break at room temperature. For example, the bumps 914 are formed using at least one of indium, tin, lead, bismuth, and any combination thereof. In one embodiment, the bumps 914 include a material that exhibits superconductivity in a low temperature range. In one embodiment, the bumps 914 contact the UBM layers on the interposer chip and the J chip. In other words, the bumps 914 fully extend and provide a complete conductive path between the UBM layers 812 and 510 as shown.

[0132] Reference Figure 17 , which depicts a block diagram of another example configuration of a detachable conductive coupling in accordance with an illustrative embodiment. Configuration 1700 is Figure 15 an example of a cold weld connection between a set of protrusions and a set of solder bumps, and configuration 1700 is Figure 8 the pads 804 and UBM layer 812 on an interposer chip as in Figure 9 , the bumps 914 as in Figure 5 , the pads 504 and UBM layer 510 on a J chip as in Figure 14 , and the protrusions 1412 as in

[0133] In one embodiment, the bumps 914 include a material having a predetermined ductility (above a threshold) at room temperature. In one embodiment, the bumps 914 are formed using reference Figure 16Formed of the materials described, in one embodiment, bump 914 contacts the UBM layer on only one chip and not the other. For example, as shown, bump 914 contacts the UBM layer 812 on the interposer chip and does not contact the UBM layer 510 on the J chip. In other words, bump 914 extends partially and provides a complete conductive path between UBM layers 812 and 510 only when pierced by protrusion 1412, as shown. In one embodiment, the capacitance of the electrical connection is determined by the distance between the first pad 804 and the second pad 504. For example, the capacitance is inversely proportional to the distance or gap height between the first pad 804 and the second pad 504. In one embodiment, protrusion 1412 has a height corresponding to the desired capacitance of the electrical connection. In one embodiment, the gap height is a function of the height of protrusion 1412 and the compressive force during cold welding. For example, the gap height can have an inverse relationship with the amount of compressive force during cold welding. As another example, the gap height can have a direct relationship with the height of protrusion 1412.

[0134] These examples of substrate materials, bump materials, deposition methods, and pad materials are not intended to be limiting. Those of ordinary skill in the art will be able to think of many other materials and deposition methods suitable for forming the components of the device in accordance with the present disclosure, and these can be envisioned within the scope of the exemplary embodiments. In one embodiment, between a set of protrusions formed on a surface, the heights of corresponding protrusions are different. For example, the heights of the protrusions can be different to accommodate warping of the substrate.

[0135] Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be designed without departing from the scope of the present invention. Although various connection and positional relationships between elements (e.g., top, bottom, above, below, adjacent, etc.) are set forth in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functions are maintained even with a change in orientation. Unless otherwise stated, these connections and / or positional relationships can be direct or indirect, and the present invention is not intended to be limited in this regard. Thus, the coupling of entities can refer to direct or indirect coupling, and the positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, the formation of layer "A" on layer "B" as referred to in this specification includes the case where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", provided that the relevant characteristics and functions of layer "A" and layer "B" are not substantially altered by the intermediate layer.

[0136] The following definitions and abbreviations are used to explain the claims and the specification. As used herein, the terms "comprising," "including," "having," "containing," or any other variation thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a series of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0137] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as more preferred or advantageous than other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" shall be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include indirect "connection" and direct "connection."

[0138] References in the specification to "one embodiment," "example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but each embodiment may or may not include that particular feature, structure, or characteristic. Moreover, these phrases are not necessarily referring to the same embodiment. Further, when an embodiment describes a particular feature, structure, or characteristic, it is contemplated that it is within the knowledge of one of ordinary skill in the art to effect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0139] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with a measurement of a particular quantity based upon the equipment available at the time of filing the present application. For example, "about" may include a range of ±8% or 5% or 2% of a given value.

[0140] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or a technical improvement over technologies found in the marketplace, or to enable other one of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A quantum computing device, comprising: A first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate; And A second chip having a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads, the second layer being configured to bond the first chip and the second chip, wherein the subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency conflicts between qubits in a set of qubits, the qubits in the set of qubits being generated by Josephson junctions in a subset of the set of Josephson junctions.

2. The quantum computing device according to claim 1, further comprising: An unavailable Josephson junction in the set of the set of Josephson junctions, wherein in response to a first Josephson junction being excluded from the subset of the set of Josephson junctions, the first Josephson junction in the set of the set of Josephson junctions is modified to become the unavailable Josephson junction.

3. The quantum computing device according to claim 2, further comprising: A disconnected pad in the first set of pads, wherein the first set of pads includes a first pad electrically coupled to the first Josephson junction, and wherein the first pad is electrically disconnected from the first Josephson junction to form the disconnected pad, the disconnected pad rendering the first Josephson junction unavailable.

4. The quantum computing device according to any one of claims 2 or 3, wherein the electrical characteristics of the first Josephson junction are modified such that the first Josephson junction no longer operates as a Josephson junction.

5. The quantum computing device according to claim 1, wherein the subset is selected based on measurements of parameters associated with each of the set of Josephson junctions.

6. The quantum computing device according to claim 5, wherein the resonant frequency associated with a particular qubit is a member selected from the set of (i) a predicted resonant frequency calculated based on the measured parameters and (ii) an actually measured resonant frequency of the particular qubit.

7. The quantum computing device according to claim 5, wherein the parameters include the resistance associated with the Josephson junctions in the set of Josephson junctions.

8. The quantum computing device according to claim 7, wherein the resistance is the normal state resistance of the Josephson junction.

9. The quantum computing device according to claim 1, further comprising: A first set of protrusions formed on the first chip; And A set of bumps formed on the second layer of the second chip, the set of bumps being formed of a material having a ductility higher than a threshold at room temperature ranges, wherein the set of bumps is configured to cold weld to the first set of protrusions.

10. The quantum computing device according to claim 9, wherein the first set of protrusions is at least one member selected from the group including gold and platinum.

11. The quantum computing device according to claim 9, wherein the set of bumps is at least one member selected from the group including indium, tin, lead, and bismuth.

12. The quantum computing device according to claim 9, further comprising: A flip chip assembly, wherein the flip chip assembly includes the first chip detachably attached to the second chip using cold welding, and parameters of Josephson junctions inside the flip chip assembly can be tuned by detaching the flip chip assembly at the cold weld.

13. A quantum processor, comprising: A set of qubits, at least one qubit in the set of qubits being formed in a flip chip configuration including a quantum processor, the quantum processor including a set of qubits, at least one qubit in the set of qubits being formed in a flip chip configuration including the quantum computing device according to any one of claims 1 to 12.

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